From c.aeschlimann at acn-group.ch Thu Jul 1 01:52:50 2010 From: c.aeschlimann at acn-group.ch (Christophe Aeschlimann) Date: Thu, 01 Jul 2010 08:52:50 +0200 Subject: GPIO in userspace In-Reply-To: References: <70E876B0EA86DD4BAF101844BC814DFE08E0856234@Cloud.RL.local> <4C2AF220.3070605@acn-group.ch> <201006302029.56161.caglarakyuz@gmail.com> Message-ID: <4C2C3B42.5090801@acn-group.ch> Hi Nicolas, On 30.06.2010 20:10, Nicolas Luna wrote: > Ok so finally I found it.. I changed > > echo 1 > /sys/class/gpio/gpio142/direction > > to > > echo "high" > /sys/class/gpio/gpio142/direction > > I think it is also possible to use "out". > > Thank you guys, > > Regards, > > Nicolas You should read : http://lxr.linux.no/#linux+v2.6.34/Documentation/gpio.txt Especially : "Sysfs Interface for Userspace (OPTIONAL)" Regards, -- Christophe Aeschlimann Embedded Software Engineer Advanced Communications Networks S.A. Rue du Puits-Godet 8a 2000 Neuch?tel, Switzerland T?l. +41 32 724 74 31 c.aeschlimann at acn-group.ch From c.aeschlimann at acn-group.ch Thu Jul 1 02:14:17 2010 From: c.aeschlimann at acn-group.ch (Christophe Aeschlimann) Date: Thu, 01 Jul 2010 09:14:17 +0200 Subject: GPIO in userspace In-Reply-To: References: <70E876B0EA86DD4BAF101844BC814DFE08E0856234@Cloud.RL.local> <4C2AF220.3070605@acn-group.ch> <201006302029.56161.caglarakyuz@gmail.com> Message-ID: <4C2C4049.8020404@acn-group.ch> On 30.06.2010 19:43, Nicolas Luna wrote: > I changed it: > > MUX_CFG(DA850, GPIO_LED0, 18, 12, 15, 8, false) If you changed just that line it didn't do anything... After reading the following thread you should know everything that there is to know concerning the PINMUX configuration : http://news.gmane.org/gmane.linux.davinci/cutoff=19131 Regards, -- Christophe Aeschlimann Embedded Software Engineer Advanced Communications Networks S.A. Rue du Puits-Godet 8a 2000 Neuch?tel, Switzerland T?l. +41 32 724 74 31 c.aeschlimann at acn-group.ch From jaya.krishnan at samsung.com Thu Jul 1 03:02:36 2010 From: jaya.krishnan at samsung.com (Jaya krishnan) Date: Thu, 01 Jul 2010 08:02:36 +0000 (GMT) Subject: DM6467 McASP Related Message-ID: <30144611.736671277971356776.JavaMail.weblogic@epml08> Hi I have to design an audio system where DM6467 McASP is the Master (Providing frame sync and data) to a passive, oversampled DAC(CS4353, Cirrus Logic). The serial clock is provided by CDCE949. McASP frame sync (for Tx) depends on 1) Serial Clock (SCLK) 2) No of slots/Frame 3) Slot size. 2 & 3 can be programmed thru McASP registers, and serial clock is fixed. Currently SCLK =256KHz, no of slots=2 (I2S), slot size= 32 bits. In this case frame Sync is 4 KHz. Surprisingly, the DAC gives output for a stream originally sampled at 8 KHz, 16 bit/Sample. When I increase the frame sync to 8 KHz, by making slot size=16, the play back is not normal (plays at double speed). Why is it so? I get some noise with the audio , when the frame sync is at 4 KHz. How, in an audio system based on DM6467 , similar to the above , can support streams with multiple sampling rates? Is there any problem with the DAC I am using? How DM6467-AIC33 combination is able support various sample rates? Regards JK Jayakrishnan M M Research Engineer R&D Team-2 , Group-5 Security Solutions Division SAMSUNG TECHWIN CO.,LTD TEL +82-70-7147-8482 FAX +82-31-8018-3712 Mobile +82-10-6409-3619 E-mail:jaya.krishnan at samsung.com From nsekhar at ti.com Thu Jul 1 04:42:02 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Thu, 1 Jul 2010 15:12:02 +0530 Subject: [PATCH 1/2] davinci: da8xx: sparse cleanup: remove duplicate entries in irq priorities structure In-Reply-To: <87bpato5j3.fsf@deeprootsystems.com> References: <1277725598-20559-1-git-send-email-nsekhar@ti.com> <87bpato5j3.fsf@deeprootsystems.com> Message-ID: On Wed, Jun 30, 2010 at 03:39:04, Kevin Hilman wrote: > "Nori, Sekhar" writes: > > > On Mon, Jun 28, 2010 at 17:16:37, I wrote: > >> This patch helps get rid of the following sparse warnings > >> of the type: > >> > >> CHECK arch/arm/mach-davinci/da830.c > >> arch/arm/mach-davinci/da830.c:1026:3: warning: Initializer entry defined twice > >> arch/arm/mach-davinci/da830.c:1027:3: also defined here > >> > >> coming from the irq priorities structure init. > > > > Argh, that's an array not a structure. Will repost > > with updated patch description after checking if there are > > any other comments. > > Looks good to me. I'll update the changelog. > > Applying this series and queuing or 2.6.36 in davinci-next Thanks Kevin! Regards, Sekhar From nsekhar at ti.com Thu Jul 1 05:01:57 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Thu, 1 Jul 2010 15:31:57 +0530 Subject: [PATCH] davinci: introduce support for AM1x ARM9 microprocessors Message-ID: <1277978517-7378-1-git-send-email-nsekhar@ti.com> The Sitara AM17x SoCs from TI are an OMAP-L137 pin-to-pin compatible ARM9 microprocessor offering from TI. The Sitara AM18x SoCs from TI are an OMAP-L138 pin-to-pin compatible ARM9 microprocessor offering from TI. More information about these processors available at: www.ti.com/am1x Because of their compatibiliy with OMAP-L1x, the kernel support for OMAP-L1x is fully relevant to AM1x processors. This patch updates the Kconfig prompt and help text to include the AM1x part names to help users select configurations required for these parts easily. Also, the hardware information that shows up in /proc/cpuinfo is updated to show applicability of the respective OMAP-L1x EVMs for AM1x parts. Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/Kconfig | 30 +++++++++++++++--------------- arch/arm/mach-davinci/board-da830-evm.c | 2 +- arch/arm/mach-davinci/board-da850-evm.c | 2 +- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 71f90f8..94f2a2c 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -30,13 +30,13 @@ config ARCH_DAVINCI_DM646x select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DA830 - bool "DA830/OMAP-L137 based system" + bool "DA830/OMAP-L137/AM17x based system" select CP_INTC select ARCH_DAVINCI_DA8XX select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1 config ARCH_DAVINCI_DA850 - bool "DA850/OMAP-L138 based system" + bool "DA850/OMAP-L138/AM18x based system" select CP_INTC select ARCH_DAVINCI_DA8XX select ARCH_HAS_CPUFREQ @@ -115,21 +115,21 @@ config MACH_DAVINCI_DM365_EVM for development is a DM365 EVM config MACH_DAVINCI_DA830_EVM - bool "TI DA830/OMAP-L137 Reference Platform" + bool "TI DA830/OMAP-L137/AM17x Reference Platform" default ARCH_DAVINCI_DA830 depends on ARCH_DAVINCI_DA830 select GPIO_PCF857X help - Say Y here to select the TI DA830/OMAP-L137 Evaluation Module. + Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. choice - prompt "Select DA830/OMAP-L137 UI board peripheral" + prompt "Select DA830/OMAP-L137/AM17x UI board peripheral" depends on MACH_DAVINCI_DA830_EVM help - The presence of UI card on the DA830/OMAP-L137 EVM is detected - automatically based on successful probe of the I2C based GPIO - expander on that board. This option selected in this menu has - an effect only in case of a successful UI card detection. + The presence of UI card on the DA830/OMAP-L137/AM17x EVM is + detected automatically based on successful probe of the I2C + based GPIO expander on that board. This option selected in this + menu has an effect only in case of a successful UI card detection. config DA830_UI_LCD bool "LCD" @@ -145,18 +145,18 @@ config DA830_UI_NAND endchoice config MACH_DAVINCI_DA850_EVM - bool "TI DA850/OMAP-L138 Reference Platform" + bool "TI DA850/OMAP-L138/AM18x Reference Platform" default ARCH_DAVINCI_DA850 depends on ARCH_DAVINCI_DA850 select GPIO_PCA953X help - Say Y here to select the TI DA850/OMAP-L138 Evaluation Module. + Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module. choice prompt "Select peripherals connected to expander on UI board" depends on MACH_DAVINCI_DA850_EVM help - The presence of User Interface (UI) card on the DA850/OMAP-L138 + The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x EVM is detected automatically based on successful probe of the I2C based GPIO expander on that card. This option selected in this menu has an effect only in case of a successful UI card detection. @@ -165,13 +165,13 @@ config DA850_UI_NONE bool "No peripheral is enabled" help Say Y if you do not want to enable any of the peripherals connected - to TCA6416 expander on DA850/OMAP-L138 EVM UI card + to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card config DA850_UI_RMII bool "RMII Ethernet PHY" help - Say Y if you want to use the RMII PHY on the DA850/OMAP-L138 EVM. - This PHY is found on the UI daughter card that is supplied with + Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x + EVM. This PHY is found on the UI daughter card that is supplied with the EVM. NOTE: Please take care while choosing this option, MII PHY will not be functional if RMII mode is selected. diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 212d970..2e27c76 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -566,7 +566,7 @@ static void __init da830_evm_map_io(void) da830_init(); } -MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM") +MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DA8XX_DDR_BASE + 0x100), diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 2ec3095..a31f37a 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -758,7 +758,7 @@ static void __init da850_evm_map_io(void) da850_init(); } -MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM") +MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DA8XX_DDR_BASE + 0x100), -- 1.6.2.4 From sshtylyov at mvista.com Thu Jul 1 05:24:09 2010 From: sshtylyov at mvista.com (Sergei Shtylyov) Date: Thu, 01 Jul 2010 14:24:09 +0400 Subject: [PATCH] davinci: introduce support for AM1x ARM9 microprocessors In-Reply-To: <1277978517-7378-1-git-send-email-nsekhar@ti.com> References: <1277978517-7378-1-git-send-email-nsekhar@ti.com> Message-ID: <4C2C6CC9.7080902@mvista.com> Hello. Sekhar Nori wrote: > The Sitara AM17x SoCs from TI are an OMAP-L137 pin-to-pin > compatible ARM9 microprocessor offering from TI. > The Sitara AM18x SoCs from TI are an OMAP-L138 pin-to-pin > compatible ARM9 microprocessor offering from TI. > More information about these processors available at: > www.ti.com/am1x > Because of their compatibiliy with OMAP-L1x, the kernel > support for OMAP-L1x is fully relevant to AM1x processors. > This patch updates the Kconfig prompt and help text to include > the AM1x part names to help users select configurations required > for these parts easily. > Also, the hardware information that shows up in /proc/cpuinfo > is updated to show applicability of the respective OMAP-L1x EVMs > for AM1x parts. > Signed-off-by: Sekhar Nori [...] > diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig > index 71f90f8..94f2a2c 100644 > --- a/arch/arm/mach-davinci/Kconfig > +++ b/arch/arm/mach-davinci/Kconfig > @@ -30,13 +30,13 @@ config ARCH_DAVINCI_DM646x > select ARCH_DAVINCI_DMx > > config ARCH_DAVINCI_DA830 > - bool "DA830/OMAP-L137 based system" > + bool "DA830/OMAP-L137/AM17x based system" Could you replace spaces by tab here, while at it? WBR, Sergei From raghu_ramaraj at mindtree.com Thu Jul 1 05:59:04 2010 From: raghu_ramaraj at mindtree.com (Raghu Ramaraj) Date: Thu, 1 Jul 2010 16:29:04 +0530 Subject: DM6467T-1Ghz ddr2(MT47H128M16HG-3E) turning in UBL code Message-ID: Hi, Has anybody done ddr2(MT47H128M16HG-3E) turning in UBL code . The following entries are not working ... static const Uint8 DDR_NM = 0;//? static const Uint8 DDR_CL = 5; static const Uint8 DDR_IBANK = 3; static const Uint8 DDR_PAGESIZE = 2; static const Uint8 DDR_T_RFC = 75 static const Uint8 DDR_T_RP = 8; static const Uint8 DDR_T_RCD = 15 ; static const Uint8 DDR_T_WR = 15;; static const Uint8 DDR_T_RAS = 45; static const Uint8 DDR_T_RC = 55; static const Uint8 DDR_T_RRD = 10; static const Uint8 DDR_T_WTR = 8; static const Uint8 DDR_T_RASMAX = 200; static const Uint8 DDR_T_XP = 2; static const Uint8 DDR_T_XSNR = 85; static const Uint8 DDR_T_XSRD = 0xc7; static const Uint8 DDR_T_RTP = 8; static const Uint8 DDR_T_CKE = 3; static const Uint16 DDR_RR = 0xc57; static const Uint8 DDR_READ_Latency = 7; Thanks & Regards, Raghu Ramaraj ________________________________ http://www.mindtree.com/email/disclaimer.html -------------- next part -------------- An HTML attachment was scrubbed... URL: From nsekhar at ti.com Thu Jul 1 06:00:47 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Thu, 1 Jul 2010 16:30:47 +0530 Subject: [PATCH] davinci: introduce support for AM1x ARM9 microprocessors In-Reply-To: <4C2C6CC9.7080902@mvista.com> References: <1277978517-7378-1-git-send-email-nsekhar@ti.com> <4C2C6CC9.7080902@mvista.com> Message-ID: Hi Sergei, On Thu, Jul 01, 2010 at 15:54:09, Sergei Shtylyov wrote: > Hello. > > Sekhar Nori wrote: > > > The Sitara AM17x SoCs from TI are an OMAP-L137 pin-to-pin > > compatible ARM9 microprocessor offering from TI. > > > The Sitara AM18x SoCs from TI are an OMAP-L138 pin-to-pin > > compatible ARM9 microprocessor offering from TI. > > > More information about these processors available at: > > www.ti.com/am1x > > > Because of their compatibiliy with OMAP-L1x, the kernel > > support for OMAP-L1x is fully relevant to AM1x processors. > > > This patch updates the Kconfig prompt and help text to include > > the AM1x part names to help users select configurations required > > for these parts easily. > > > Also, the hardware information that shows up in /proc/cpuinfo > > is updated to show applicability of the respective OMAP-L1x EVMs > > for AM1x parts. > > > Signed-off-by: Sekhar Nori > [...] > > diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig > > index 71f90f8..94f2a2c 100644 > > --- a/arch/arm/mach-davinci/Kconfig > > +++ b/arch/arm/mach-davinci/Kconfig > > @@ -30,13 +30,13 @@ config ARCH_DAVINCI_DM646x > > select ARCH_DAVINCI_DMx > > > > config ARCH_DAVINCI_DA830 > > - bool "DA830/OMAP-L137 based system" > > + bool "DA830/OMAP-L137/AM17x based system" > > Could you replace spaces by tab here, while at it? Sure. Will repost. Thanks, Sekhar From nsekhar at ti.com Thu Jul 1 08:30:50 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Thu, 1 Jul 2010 19:00:50 +0530 Subject: [PATCH v2 2/2] davinci: introduce support for AM1x ARM9 microprocessors In-Reply-To: <1277991050-5218-1-git-send-email-nsekhar@ti.com> References: <1277991050-5218-1-git-send-email-nsekhar@ti.com> Message-ID: <1277991050-5218-2-git-send-email-nsekhar@ti.com> The Sitara AM17x SoCs from TI are an OMAP-L137 pin-to-pin compatible ARM9 microprocessor offering from TI. The Sitara AM18x SoCs from TI are an OMAP-L138 pin-to-pin compatible ARM9 microprocessor offering from TI. More information about these processors available at: www.ti.com/am1x Because of their compatibiliy with OMAP-L1x, the kernel support for OMAP-L1x is fully relevant to AM1x processors. This patch updates the Kconfig prompt and help text to include the AM1x part names to help users select configurations required for these parts easily. Also, the hardware information that shows up in /proc/cpuinfo is updated to show applicability of the respective OMAP-L1x EVMs for AM1x parts. Signed-off-by: Sekhar Nori --- This patch triggers a non-relevant checkpatch warning because of insufficient help text for DA850_UI_NONE. arch/arm/mach-davinci/Kconfig | 30 +++++++++++++++--------------- arch/arm/mach-davinci/board-da830-evm.c | 2 +- arch/arm/mach-davinci/board-da850-evm.c | 2 +- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index b291da1..2bf03e9 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -30,13 +30,13 @@ config ARCH_DAVINCI_DM646x select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DA830 - bool "DA830/OMAP-L137 based system" + bool "DA830/OMAP-L137/AM17x based system" select CP_INTC select ARCH_DAVINCI_DA8XX select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1 config ARCH_DAVINCI_DA850 - bool "DA850/OMAP-L138 based system" + bool "DA850/OMAP-L138/AM18x based system" select CP_INTC select ARCH_DAVINCI_DA8XX select ARCH_HAS_CPUFREQ @@ -115,21 +115,21 @@ config MACH_DAVINCI_DM365_EVM for development is a DM365 EVM config MACH_DAVINCI_DA830_EVM - bool "TI DA830/OMAP-L137 Reference Platform" + bool "TI DA830/OMAP-L137/AM17x Reference Platform" default ARCH_DAVINCI_DA830 depends on ARCH_DAVINCI_DA830 select GPIO_PCF857X help - Say Y here to select the TI DA830/OMAP-L137 Evaluation Module. + Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. choice - prompt "Select DA830/OMAP-L137 UI board peripheral" + prompt "Select DA830/OMAP-L137/AM17x UI board peripheral" depends on MACH_DAVINCI_DA830_EVM help - The presence of UI card on the DA830/OMAP-L137 EVM is detected - automatically based on successful probe of the I2C based GPIO - expander on that board. This option selected in this menu has - an effect only in case of a successful UI card detection. + The presence of UI card on the DA830/OMAP-L137/AM17x EVM is + detected automatically based on successful probe of the I2C + based GPIO expander on that board. This option selected in this + menu has an effect only in case of a successful UI card detection. config DA830_UI_LCD bool "LCD" @@ -145,18 +145,18 @@ config DA830_UI_NAND endchoice config MACH_DAVINCI_DA850_EVM - bool "TI DA850/OMAP-L138 Reference Platform" + bool "TI DA850/OMAP-L138/AM18x Reference Platform" default ARCH_DAVINCI_DA850 depends on ARCH_DAVINCI_DA850 select GPIO_PCA953X help - Say Y here to select the TI DA850/OMAP-L138 Evaluation Module. + Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module. choice prompt "Select peripherals connected to expander on UI board" depends on MACH_DAVINCI_DA850_EVM help - The presence of User Interface (UI) card on the DA850/OMAP-L138 + The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x EVM is detected automatically based on successful probe of the I2C based GPIO expander on that card. This option selected in this menu has an effect only in case of a successful UI card detection. @@ -165,13 +165,13 @@ config DA850_UI_NONE bool "No peripheral is enabled" help Say Y if you do not want to enable any of the peripherals connected - to TCA6416 expander on DA850/OMAP-L138 EVM UI card + to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card config DA850_UI_RMII bool "RMII Ethernet PHY" help - Say Y if you want to use the RMII PHY on the DA850/OMAP-L138 EVM. - This PHY is found on the UI daughter card that is supplied with + Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x + EVM. This PHY is found on the UI daughter card that is supplied with the EVM. NOTE: Please take care while choosing this option, MII PHY will not be functional if RMII mode is selected. diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 212d970..2e27c76 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -566,7 +566,7 @@ static void __init da830_evm_map_io(void) da830_init(); } -MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM") +MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DA8XX_DDR_BASE + 0x100), diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 2ec3095..a31f37a 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -758,7 +758,7 @@ static void __init da850_evm_map_io(void) da850_init(); } -MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM") +MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DA8XX_DDR_BASE + 0x100), -- 1.6.2.4 From nsekhar at ti.com Thu Jul 1 08:30:49 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Thu, 1 Jul 2010 19:00:49 +0530 Subject: [PATCH 1/2] davinci: clean up inconsistent usage of spaces in Kconfig Message-ID: <1277991050-5218-1-git-send-email-nsekhar@ti.com> In arch/arm/mach-davinci/Kconfig, some of the configuration items are indented with multiple spaces instead of tabs. Also, in couple of places, two spaces are used in the middle of help text where one should do. This patch fixes both issues. Signed-off-by: Sekhar Nori --- This patch triggers a non-relevant checkpatch warning because of insufficient help text for DAVINCI_MUX_DEBUG. arch/arm/mach-davinci/Kconfig | 32 ++++++++++++++++---------------- 1 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 71f90f8..b291da1 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -20,17 +20,17 @@ config ARCH_DAVINCI_DM644x select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DM355 - bool "DaVinci 355 based system" + bool "DaVinci 355 based system" select AINTC select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DM646x - bool "DaVinci 646x based system" + bool "DaVinci 646x based system" select AINTC select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DA830 - bool "DA830/OMAP-L137 based system" + bool "DA830/OMAP-L137 based system" select CP_INTC select ARCH_DAVINCI_DA8XX select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1 @@ -140,7 +140,7 @@ config DA830_UI_LCD config DA830_UI_NAND bool "NAND flash" help - Say Y here to use the NAND flash. Do not forget to setup + Say Y here to use the NAND flash. Do not forget to setup the switch correctly. endchoice @@ -195,20 +195,20 @@ config DAVINCI_MUX say Y. config DAVINCI_MUX_DEBUG - bool "Multiplexing debug output" - depends on DAVINCI_MUX - help - Makes the multiplexing functions print out a lot of debug info. - This is useful if you want to find out the correct values of the - multiplexing registers. + bool "Multiplexing debug output" + depends on DAVINCI_MUX + help + Makes the multiplexing functions print out a lot of debug info. + This is useful if you want to find out the correct values of the + multiplexing registers. config DAVINCI_MUX_WARNINGS - bool "Warn about pins the bootloader didn't set up" - depends on DAVINCI_MUX - help - Choose Y here to warn whenever driver initialization logic needs - to change the pin multiplexing setup. When there are no warnings - printed, it's safe to deselect DAVINCI_MUX for your product. + bool "Warn about pins the bootloader didn't set up" + depends on DAVINCI_MUX + help + Choose Y here to warn whenever driver initialization logic needs + to change the pin multiplexing setup. When there are no warnings + printed, it's safe to deselect DAVINCI_MUX for your product. config DAVINCI_RESET_CLOCKS bool "Reset unused clocks during boot" -- 1.6.2.4 From jp.francois at cynove.com Thu Jul 1 11:23:37 2010 From: jp.francois at cynove.com (jean-philippe francois) Date: Thu, 1 Jul 2010 18:23:37 +0200 Subject: [PATCH 1/6] davinci: add support for aemif timing configuration In-Reply-To: <1277912633-26118-1-git-send-email-nsekhar@ti.com> References: <1277912633-26118-1-git-send-email-nsekhar@ti.com> Message-ID: 2010/6/30 Sekhar Nori : > This patch adds support to configure the AEMIF interface > with supplied timing values. > > Signed-off-by: Sekhar Nori > --- > ?arch/arm/mach-davinci/Makefile ? ? ? ? ? ? | ? ?2 +- > ?arch/arm/mach-davinci/aemif.c ? ? ? ? ? ? ?| ?131 ++++++++++++++++++++++++++++ > ?arch/arm/mach-davinci/include/mach/aemif.h | ? 36 ++++++++ > ?3 files changed, 168 insertions(+), 1 deletions(-) > ?create mode 100644 arch/arm/mach-davinci/aemif.c > ?create mode 100644 arch/arm/mach-davinci/include/mach/aemif.h > > > diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c > new file mode 100644 > index 0000000..62d7cce > --- /dev/null > +++ b/arch/arm/mach-davinci/aemif.c > @@ -0,0 +1,131 @@ > +/* > + * AEMIF support for DaVinci SoCs > + * > + * Copyright (C) 2010 Texas Instruments Incorporated. http://www.ti.com/ > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +/* Timing value configuration */ > + > +#define TA(x) ? ? ? ? ?((x) << 2) > +#define RHOLD(x) ? ? ? ((x) << 4) > +#define RSTROBE(x) ? ? ((x) << 7) > +#define RSETUP(x) ? ? ?((x) << 13) > +#define WHOLD(x) ? ? ? ((x) << 17) > +#define WSTROBE(x) ? ? ((x) << 20) > +#define WSETUP(x) ? ? ?((x) << 26) > + > +#define TA_MAX ? ? ? ? 0x3 > +#define RHOLD_MAX ? ? ?0x7 > +#define RSTROBE_MAX ? ?0x3f > +#define RSETUP_MAX ? ? 0xf > +#define WHOLD_MAX ? ? ?0x7 > +#define WSTROBE_MAX ? ?0x3f > +#define WSETUP_MAX ? ? 0xf > + > +#define TIMING_MASK ? ?(TA(TA_MAX) | \ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? RHOLD(RHOLD_MAX) | \ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? RSTROBE(RSTROBE_MAX) | ?\ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? RSETUP(RSETUP_MAX) | \ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? WHOLD(WHOLD_MAX) | \ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? WSTROBE(WSTROBE_MAX) | \ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? WSETUP(WSETUP_MAX)) > + > +#define NS_IN_KHZ ? ? ?1000000 > + Why are the defines splitted like this between the .h and the .c ? If users of this code don't care about these defines, they can be with the code. But I can't see how the defines in the header file are more useful to external code then these ones. > +/* > + * aemif_calc_rate - calculate timing data. > + * @wanted: The cycle time needed in nanoseconds. > + * @clk: The input clock rate in kHz. > + * @max: The maximum divider value that can be programmed. > + * > + * Returns the calculated timing value minus 1 for easy programming into > + * AEMIF timing registers. > + */ > +static int aemif_calc_rate(int wanted, unsigned long clk, int max) > +{ > + ? ? ? int result; > + > + ? ? ? result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ) - 1; > + > + ? ? ? pr_debug("%s: result %d from %ld, %d\n", __func__, result, clk, wanted); > + > + ? ? ? if (result < 0) > + ? ? ? ? ? ? ? result = 0; > + ? ? ? else if (result > max) > + ? ? ? ? ? ? ? result = max; > + > + ? ? ? return result; > +} I think you should either return a negative value when result > max, or remove the check for negative value in the code below. I think a negative value would make more sense. After all, if one increases the frequency, past the limit of a particular device, then users should be warned that their device will run out of spec. > + > +/** > + * davinci_aemif_setup_timing - setup timing values for a given AEMIF interface > + * @t: timing values to be progammed > + * @base: The virtual base address of the AEMIF interface > + * @cs: chip-select to program the timing values for > + * > + * This function programs the given timing values (in real clock) into the > + * AEMIF registers taking the AEMIF clock into account. > + * > + * This function does not use any locking while programming the AEMIF > + * because it is expected that there is only one user of a given > + * chip-select. > + * > + * Returns 0 on success, else negative errno. > + */ > +int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? void __iomem *base, unsigned cs) > +{ > + ? ? ? unsigned set, val; > + ? ? ? unsigned ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; > + ? ? ? unsigned offset = A1CR_OFFSET + cs * 4; > + ? ? ? struct clk *aemif_clk; > + ? ? ? unsigned long clkrate; > + > + ? ? ? if (!t) > + ? ? ? ? ? ? ? return 0; ? ? ? /* Nothing to do */ > + > + ? ? ? aemif_clk = clk_get(NULL, "aemif"); > + ? ? ? if (IS_ERR(aemif_clk)) > + ? ? ? ? ? ? ? return PTR_ERR(aemif_clk); > + > + ? ? ? clkrate = clk_get_rate(aemif_clk); > + > + ? ? ? clkrate /= 1000; ? ? ? ?/* turn clock into kHz for ease of use */ > + > + ? ? ? ta ? ? ?= aemif_calc_rate(t->ta, clkrate, TA_MAX); > + ? ? ? rhold ? = aemif_calc_rate(t->rhold, clkrate, RHOLD_MAX); > + ? ? ? rstrobe = aemif_calc_rate(t->rstrobe, clkrate, RSTROBE_MAX); > + ? ? ? rsetup ?= aemif_calc_rate(t->rsetup, clkrate, RSETUP_MAX); > + ? ? ? whold ? = aemif_calc_rate(t->whold, clkrate, WHOLD_MAX); > + ? ? ? wstrobe = aemif_calc_rate(t->wstrobe, clkrate, WSTROBE_MAX); > + ? ? ? wsetup ?= aemif_calc_rate(t->wsetup, clkrate, WSETUP_MAX); > + > + ? ? ? if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || > + ? ? ? ? ? ? ? ? ? ? ? whold < 0 || wstrobe < 0 || wsetup < 0) { > + ? ? ? ? ? ? ? pr_err("%s: cannot get suitable timings\n", __func__); > + ? ? ? ? ? ? ? return -EINVAL; > + ? ? ? } See my comment above about returning negative value. Currently, this test is always false. > + > + ? ? ? set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | > + ? ? ? ? ? ? ? WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); > + > + ? ? ? val = __raw_readl(base + offset); > + ? ? ? val &= ~TIMING_MASK; > + ? ? ? val |= set; > + ? ? ? __raw_writel(val, base + offset); > + > + ? ? ? return 0; > +} > +EXPORT_SYMBOL(davinci_aemif_setup_timing); > diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h > new file mode 100644 > index 0000000..05b2934 > --- /dev/null > +++ b/arch/arm/mach-davinci/include/mach/aemif.h > @@ -0,0 +1,36 @@ > +/* > + * TI DaVinci AEMIF support > + * > + * Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/ > + * > + * This file is licensed under the terms of the GNU General Public License > + * version 2. This program is licensed "as is" without any warranty of any > + * kind, whether express or implied. > + */ > +#ifndef _MACH_DAVINCI_AEMIF_H > +#define _MACH_DAVINCI_AEMIF_H > + > +#define NRCSR_OFFSET ? ? ? ? ? 0x00 > +#define AWCCR_OFFSET ? ? ? ? ? 0x04 > +#define A1CR_OFFSET ? ? ? ? ? ?0x10 > + > +#define ACR_ASIZE_MASK ? ? ? ? 0x3 > +#define ACR_EW_MASK ? ? ? ? ? ?BIT(30) > +#define ACR_SS_MASK ? ? ? ? ? ?BIT(31) > + > +/* All timings in nanoseconds */ > +struct davinci_aemif_timing { > + ? ? ? u8 ? ? ?wsetup; > + ? ? ? u8 ? ? ?wstrobe; > + ? ? ? u8 ? ? ?whold; > + > + ? ? ? u8 ? ? ?rsetup; > + ? ? ? u8 ? ? ?rstrobe; > + ? ? ? u8 ? ? ?rhold; > + > + ? ? ? u8 ? ? ?ta; > +}; > + So, maximum strobe time is 255 ns ? Looks a bit low for a max value. Isn't this a good place to define chip select register base value ? Or are they better defined in the cpu file ? > +int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? void __iomem *base, unsigned cs); > +#endif > -- Jean-Philippe Fran?oi From rohan_javed at yahoo.co.uk Fri Jul 2 01:05:39 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Fri, 2 Jul 2010 06:05:39 +0000 (GMT) Subject: BSD on davinci Message-ID: <664283.89475.qm@web24105.mail.ird.yahoo.com> anyone having any idea of porting BSD on davinci platform Regard's RT -------------- next part -------------- An HTML attachment was scrubbed... URL: From rohan_javed at yahoo.co.uk Fri Jul 2 01:51:07 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Fri, 2 Jul 2010 06:51:07 +0000 (GMT) Subject: using jffs2 or ramdisk saving flash Message-ID: <790554.10296.qm@web24102.mail.ird.yahoo.com> I am using DM6446 have written device drivers each time my system boots i need to do insmod to install many drivers.for jffs2 file system these drivers are installed in flash that is lsmod displays the flash address this means each time i boot i write to flash in real product with time the flash will die so i have to switch to ramdisk image but problem with this is that it takes alot of time to boot the system. Anyone know how to save flash and boot quickly Regard's RT -------------- next part -------------- An HTML attachment was scrubbed... URL: From nsekhar at ti.com Fri Jul 2 07:58:01 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Fri, 2 Jul 2010 18:28:01 +0530 Subject: [PATCH 1/6] davinci: add support for aemif timing configuration In-Reply-To: References: <1277912633-26118-1-git-send-email-nsekhar@ti.com> Message-ID: Hi jean-philippe, On Thu, Jul 01, 2010 at 21:53:37, jean-philippe francois wrote: > 2010/6/30 Sekhar Nori : > > This patch adds support to configure the AEMIF interface > > with supplied timing values. > > > > > Signed-off-by: Sekhar Nori > > --- > > arch/arm/mach-davinci/Makefile | 2 +- > > arch/arm/mach-davinci/aemif.c | 131 ++++++++++++++++++++++++++++ > > arch/arm/mach-davinci/include/mach/aemif.h | 36 ++++++++ > > 3 files changed, 168 insertions(+), 1 deletions(-) > > create mode 100644 arch/arm/mach-davinci/aemif.c > > create mode 100644 arch/arm/mach-davinci/include/mach/aemif.h > > > > > > diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c > > new file mode 100644 > > index 0000000..62d7cce > > --- /dev/null > > +++ b/arch/arm/mach-davinci/aemif.c > > @@ -0,0 +1,131 @@ > > +/* > > + * AEMIF support for DaVinci SoCs > > + * > > + * Copyright (C) 2010 Texas Instruments Incorporated. http://www.ti.com/ > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > + > > +/* Timing value configuration */ > > + > > +#define TA(x) ((x) << 2) > > +#define RHOLD(x) ((x) << 4) > > +#define RSTROBE(x) ((x) << 7) > > +#define RSETUP(x) ((x) << 13) > > +#define WHOLD(x) ((x) << 17) > > +#define WSTROBE(x) ((x) << 20) > > +#define WSETUP(x) ((x) << 26) > > + > > +#define TA_MAX 0x3 > > +#define RHOLD_MAX 0x7 > > +#define RSTROBE_MAX 0x3f > > +#define RSETUP_MAX 0xf > > +#define WHOLD_MAX 0x7 > > +#define WSTROBE_MAX 0x3f > > +#define WSETUP_MAX 0xf > > + > > +#define TIMING_MASK (TA(TA_MAX) | \ > > + RHOLD(RHOLD_MAX) | \ > > + RSTROBE(RSTROBE_MAX) | \ > > + RSETUP(RSETUP_MAX) | \ > > + WHOLD(WHOLD_MAX) | \ > > + WSTROBE(WSTROBE_MAX) | \ > > + WSETUP(WSETUP_MAX)) > > + > > +#define NS_IN_KHZ 1000000 > > + > > Why are the defines splitted like this between the .h and the .c ? If > users of this code > don't care about these defines, they can be with the code. > But I can't see how the defines in the header file are more useful to > external code then these ones. Defines in the header file are register offsets and register bit defines which can be used by AEMIF users like NAND driver. Defines in this file are expected to be used by this file only. That said, this part of the patch can use some clean-up - I just realized that A1CR_OFFSET is defined in nand.h as well so that needs to be removed. > > > +/* > > + * aemif_calc_rate - calculate timing data. > > + * @wanted: The cycle time needed in nanoseconds. > > + * @clk: The input clock rate in kHz. > > + * @max: The maximum divider value that can be programmed. > > + * > > + * Returns the calculated timing value minus 1 for easy programming into > > + * AEMIF timing registers. > > + */ > > +static int aemif_calc_rate(int wanted, unsigned long clk, int max) > > +{ > > + int result; > > + > > + result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ) - 1; > > + > > + pr_debug("%s: result %d from %ld, %d\n", __func__, result, clk, wanted); > > + > > + if (result < 0) > > + result = 0; > > + else if (result > max) > > + result = max; > > + > > + return result; > > +} > > I think you should either return a negative value when result > max, or remove > the check for negative value in the code below. I think a negative > value would make more sense. Right, as you can probably guess, there was a bit of a tussle on which path to take and ended up with a bit of both. [...] > > diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h > > new file mode 100644 > > index 0000000..05b2934 > > --- /dev/null > > +++ b/arch/arm/mach-davinci/include/mach/aemif.h > > @@ -0,0 +1,36 @@ > > +/* > > + * TI DaVinci AEMIF support > > + * > > + * Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/ > > + * > > + * This file is licensed under the terms of the GNU General Public License > > + * version 2. This program is licensed "as is" without any warranty of any > > + * kind, whether express or implied. > > + */ > > +#ifndef _MACH_DAVINCI_AEMIF_H > > +#define _MACH_DAVINCI_AEMIF_H > > + > > +#define NRCSR_OFFSET 0x00 > > +#define AWCCR_OFFSET 0x04 > > +#define A1CR_OFFSET 0x10 > > + > > +#define ACR_ASIZE_MASK 0x3 > > +#define ACR_EW_MASK BIT(30) > > +#define ACR_SS_MASK BIT(31) > > + > > +/* All timings in nanoseconds */ > > +struct davinci_aemif_timing { > > + u8 wsetup; > > + u8 wstrobe; > > + u8 whold; > > + > > + u8 rsetup; > > + u8 rstrobe; > > + u8 rhold; > > + > > + u8 ta; > > +}; > > + > > So, maximum strobe time is 255 ns ? > Looks a bit low for a max value. As can be seen from patches 3-4, the max value we are having to program is about 50ns. That still leaves a lot of room. This can be changed later if there is a need for more bits. > Isn't this a good place to define chip select register base value ? You mean the A1CR_OFFSET above? The AEMIF base address comes to the drivers from platform data. Thanks, Sekhar From lamiaposta71 at gmail.com Fri Jul 2 12:12:24 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Fri, 2 Jul 2010 19:12:24 +0200 Subject: No subject Message-ID: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> The actual DaVinci tree McBSP driver, used for i2S interface, supports clk and frame sync only if generated externally (see for instance evm-dm365). This patch series add two new clocking possibilities and also it allows to select the clock input pin. It is also possible, with the last patch, to better approximate the frequency, accepting a non symmetric waveform. From lamiaposta71 at gmail.com Fri Jul 2 12:12:25 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Fri, 2 Jul 2010 19:12:25 +0200 Subject: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S) In-Reply-To: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> References: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> Message-ID: <1278090747-5124-2-git-send-email-lamiaposta71@gmail.com> From: Raffaele Recalcati Added two clocking options for dm365 McBSP peripheral when used with I2S timings, that are SND_SOC_DAIFMT_CBS_CFS (the cpu generates clock and frame sync) and SND_SOC_DAIFMT_CBS_CFM (the cpu gets clock from external pin and generates frame sync). A slave clock management can be important when the external codec needs the system clock and the bit clock synchronized (tested with uda1345). This patch has been developed against the: http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git git tree and has been tested on bmx board (similar to dm365 evm, but using uda1345 as external audio codec). Signed-off-by: Raffaele Recalcati Signed-off-by: Davide Bonfanti --- sound/soc/davinci/davinci-i2s.c | 111 +++++++++++++++++++++++++++++++++++--- sound/soc/davinci/davinci-i2s.h | 5 ++ 2 files changed, 107 insertions(+), 9 deletions(-) diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c index adadcd3..a893538 100644 --- a/sound/soc/davinci/davinci-i2s.c +++ b/sound/soc/davinci/davinci-i2s.c @@ -26,6 +26,7 @@ #include #include "davinci-pcm.h" +#include "davinci-i2s.h" /* @@ -68,16 +69,21 @@ #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) #define DAVINCI_MCBSP_RCR_RFIG (1 << 18) #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) +#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24) +#define DAVINCI_MCBSP_RCR_RPHASE (1 << 31) #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) #define DAVINCI_MCBSP_XCR_XFIG (1 << 18) #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) +#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24) +#define DAVINCI_MCBSP_XCR_XPHASE (1 << 31) #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) +#define DAVINCI_MCBSP_SRGR_CLKSM (1 << 29) #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0) #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) @@ -144,6 +150,9 @@ struct davinci_mcbsp_dev { * won't end up being swapped because of the underrun. */ unsigned enable_channel_combine:1; + + unsigned int fmt; + int clk_div; }; static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, @@ -254,10 +263,12 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, struct davinci_mcbsp_dev *dev = cpu_dai->private_data; unsigned int pcr; unsigned int srgr; + /* Attention srgr is updated by hw_params! */ srgr = DAVINCI_MCBSP_SRGR_FSGM | DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); + dev->fmt = fmt; /* set master/slave audio interface */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: @@ -372,6 +383,19 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, return 0; } +static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, + int div_id, int div) +{ + struct davinci_mcbsp_dev *dev = cpu_dai->private_data; + int srgr; + + if (div_id != DAVINCI_MCBSP_CLKGDV) + return -ENODEV; + + dev->clk_div = div; + return 0; +} + static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -380,8 +404,8 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, struct davinci_pcm_dma_params *dma_params = &dev->dma_params[substream->stream]; struct snd_interval *i = NULL; - int mcbsp_word_length; - unsigned int rcr, xcr, srgr; + int mcbsp_word_length, master; + unsigned int rcr, xcr, srgr, clk_div, freq, framesize; u32 spcr; snd_pcm_format_t fmt; unsigned element_cnt = 1; @@ -396,12 +420,47 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); } - i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); - srgr = DAVINCI_MCBSP_SRGR_FSGM; - srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); + master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; + fmt = params_format(params); + mcbsp_word_length = asp_word_length[fmt]; - i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); - srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); + switch (master) { + case SND_SOC_DAIFMT_CBS_CFS: + freq = clk_get_rate(dev->clk); + srgr = DAVINCI_MCBSP_SRGR_FSGM | + DAVINCI_MCBSP_SRGR_CLKSM; + srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * + 8 - 1); + /* symmetric waveforms */ + clk_div = freq / (mcbsp_word_length * 16) / + params->rate_num * params->rate_den; + srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * + 16 - 1); + clk_div &= 0xFF; + srgr |= clk_div; + break; + case SND_SOC_DAIFMT_CBM_CFS: + srgr = DAVINCI_MCBSP_SRGR_FSGM; + clk_div = dev->clk_div - 1; + srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1); + srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1); + clk_div &= 0xFF; + srgr |= clk_div; + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* Clock and frame sync given from external sources */ + i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); + srgr = DAVINCI_MCBSP_SRGR_FSGM; + srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); + pr_debug("%s - %d FWID set: re-read srgr = %X\n", + __func__, __LINE__, snd_interval_value(i) - 1); + + i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); + srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); + break; + default: + return -EINVAL; + } davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); rcr = DAVINCI_MCBSP_RCR_RFIG; @@ -426,12 +485,41 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, element_cnt = 1; fmt = double_fmt[fmt]; } + switch (master) { + case SND_SOC_DAIFMT_CBS_CFS: + case SND_SOC_DAIFMT_CBS_CFM: + rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0); + xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0); + rcr |= DAVINCI_MCBSP_RCR_RPHASE; + xcr |= DAVINCI_MCBSP_XCR_XPHASE; + break; + case SND_SOC_DAIFMT_CBM_CFM: + case SND_SOC_DAIFMT_CBM_CFS: + rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1); + xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1); + break; + default: + return -EINVAL; + } } dma_params->acnt = dma_params->data_type = data_type[fmt]; dma_params->fifo_level = 0; mcbsp_word_length = asp_word_length[fmt]; - rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1); - xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1); + + switch (master) { + case SND_SOC_DAIFMT_CBS_CFS: + case SND_SOC_DAIFMT_CBS_CFM: + rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0); + xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0); + break; + case SND_SOC_DAIFMT_CBM_CFM: + case SND_SOC_DAIFMT_CBM_CFS: + rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1); + xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1); + break; + default: + return -EINVAL; + } rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length); @@ -442,6 +530,10 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); else davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); + + pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr); + pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr); + pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr); return 0; } @@ -500,6 +592,7 @@ static struct snd_soc_dai_ops davinci_i2s_dai_ops = { .trigger = davinci_i2s_trigger, .hw_params = davinci_i2s_hw_params, .set_fmt = davinci_i2s_set_dai_fmt, + .set_clkdiv = davinci_i2s_dai_set_clkdiv, }; diff --git a/sound/soc/davinci/davinci-i2s.h b/sound/soc/davinci/davinci-i2s.h index 241648c..0b1e77b 100644 --- a/sound/soc/davinci/davinci-i2s.h +++ b/sound/soc/davinci/davinci-i2s.h @@ -12,6 +12,11 @@ #ifndef _DAVINCI_I2S_H #define _DAVINCI_I2S_H +/* McBSP dividers */ +enum davinci_mcbsp_div { + DAVINCI_MCBSP_CLKGDV, /* Sample rate generator divider */ +}; + extern struct snd_soc_dai davinci_i2s_dai; #endif -- 1.7.0.4 From lamiaposta71 at gmail.com Fri Jul 2 12:12:26 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Fri, 2 Jul 2010 19:12:26 +0200 Subject: [PATCH 2/3] ASoC: DaVinci: Added selection of clk input pin for McBSP In-Reply-To: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> References: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> Message-ID: <1278090747-5124-3-git-send-email-lamiaposta71@gmail.com> From: Raffaele Recalcati When McBSP peripheral gets the clock from an external pin, there are three possible chooses, MCBSP_CLKX, MCBSP_CLKR and MCBSP_CLKS. evm-dm365 uses MCBSP_CLKR, instead in bmx board I have a different hardware connection and I use MCBSP_CLKS, so I have added this possibility. This patch has been developed against the: http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git git tree and has been tested on bmx board (similar to dm365 evm) Signed-off-by: Raffaele Recalcati Signed-off-by: Davide Bonfanti --- arch/arm/mach-davinci/include/mach/asp.h | 15 +++++++++++++++ sound/soc/davinci/davinci-i2s.c | 27 ++++++++++++++++++++++----- 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index 834725f..0847d21 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -63,6 +63,16 @@ struct snd_platform_data { unsigned sram_size_playback; unsigned sram_size_capture; + /* + * If McBSP peripheral gets the clock from an external pin, + * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR + * and MCBSP_CLKS. + * Depending on different hardware connections it is possible + * to use this setting to change the behaviour of McBSP + * driver. The dm365_clk_input_pin enum is available for dm365 + */ + int clk_input_pin; + /* McASP specific fields */ int tdm_slots; u8 op_mode; @@ -78,6 +88,11 @@ enum { MCASP_VERSION_2, /* DA8xx/OMAPL1x */ }; +enum dm365_clk_input_pin { + MCBSP_CLKR = 0, /* DM365 */ + MCBSP_CLKS, +}; + #define INACTIVE_MODE 0 #define TX_MODE 1 #define RX_MODE 2 diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c index a893538..17f594f 100644 --- a/sound/soc/davinci/davinci-i2s.c +++ b/sound/soc/davinci/davinci-i2s.c @@ -153,6 +153,7 @@ struct davinci_mcbsp_dev { unsigned int fmt; int clk_div; + int clk_input_pin; }; static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, @@ -279,11 +280,26 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, DAVINCI_MCBSP_PCR_CLKRM; break; case SND_SOC_DAIFMT_CBM_CFS: - /* McBSP CLKR pin is the input for the Sample Rate Generator. - * McBSP FSR and FSX are driven by the Sample Rate Generator. */ - pcr = DAVINCI_MCBSP_PCR_SCLKME | - DAVINCI_MCBSP_PCR_FSXM | - DAVINCI_MCBSP_PCR_FSRM; + pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM; + /* + * Selection of the clock input pin that is the + * input for the Sample Rate Generator. + * McBSP FSR and FSX are driven by the Sample Rate + * Generator. + */ + switch (dev->clk_input_pin) { + case MCBSP_CLKS: + pcr |= DAVINCI_MCBSP_PCR_CLKXM | + DAVINCI_MCBSP_PCR_CLKRM; + break; + case MCBSP_CLKR: + pcr |= DAVINCI_MCBSP_PCR_SCLKME; + break; + default: + dev_err(&pdev->dev, "bad clk_input_pin\n"); + return -EINVAL; + } + break; case SND_SOC_DAIFMT_CBM_CFM: /* codec is master */ @@ -645,6 +661,7 @@ static int davinci_i2s_probe(struct platform_device *pdev) pdata->sram_size_playback; dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size = pdata->sram_size_capture; + dev->clk_input_pin = pdata->clk_input_pin; } dev->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(dev->clk)) { -- 1.7.0.4 From lamiaposta71 at gmail.com Fri Jul 2 12:12:27 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Fri, 2 Jul 2010 19:12:27 +0200 Subject: [PATCH 3/3] ASoC: DaVinci: More accurate calculation for clock divider for McBSP (I2S) In-Reply-To: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> References: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> Message-ID: <1278090747-5124-4-git-send-email-lamiaposta71@gmail.com> From: Raffaele Recalcati i2s_accurate_clock switch can be used to have a better approximate frequency. The trade off is between more accurate clock (fast clock) and less accurate clock (slow clock). The waveform will be not symmetric. Probably it is possible to get a better algorithm for calculating the divider, trying to keep a slower clock as possible. This patch has been developed against the http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git git tree and has been tested on bmx board (similar to dm365 evm, but using uda1345 as external audio codec). Signed-off-by: Raffaele Recalcati Signed-off-by: Davide Bonfanti --- arch/arm/mach-davinci/include/mach/asp.h | 7 +++++++ sound/soc/davinci/davinci-i2s.c | 20 ++++++++++++++++++++ 2 files changed, 27 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index 0847d21..21c886e 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -73,6 +73,13 @@ struct snd_platform_data { */ int clk_input_pin; + /* + * This define works when both clock and FS are output for the cpu + * and makes clock more accurate (FS is not symmetrical and the + * clock is very fast. + */ + bool i2s_accurate_clock; + /* McASP specific fields */ int tdm_slots; u8 op_mode; diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c index 17f594f..2fb1209 100644 --- a/sound/soc/davinci/davinci-i2s.c +++ b/sound/soc/davinci/davinci-i2s.c @@ -154,6 +154,7 @@ struct davinci_mcbsp_dev { unsigned int fmt; int clk_div; int clk_input_pin; + bool i2s_accurate_clock; }; static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, @@ -447,6 +448,24 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, DAVINCI_MCBSP_SRGR_CLKSM; srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1); + if (dev->i2s_accurate_clock) { + clk_div = 256; + do { + framesize = (freq / (--clk_div)) / + params->rate_num * + params->rate_den; + } while (((framesize < 33) || (framesize > 4095)) && + (clk_div)); + clk_div--; + srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1); + } else { + /* symmetric waveforms */ + clk_div = freq / (mcbsp_word_length * 16) / + params->rate_num * params->rate_den; + srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * + 16 - 1); + } + /* symmetric waveforms */ clk_div = freq / (mcbsp_word_length * 16) / params->rate_num * params->rate_den; @@ -662,6 +681,7 @@ static int davinci_i2s_probe(struct platform_device *pdev) dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size = pdata->sram_size_capture; dev->clk_input_pin = pdata->clk_input_pin; + dev->i2s_accurate_clock = pdata->i2s_accurate_clock; } dev->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(dev->clk)) { -- 1.7.0.4 From troy.kisky at boundarydevices.com Fri Jul 2 15:57:33 2010 From: troy.kisky at boundarydevices.com (Troy Kisky) Date: Fri, 02 Jul 2010 13:57:33 -0700 Subject: [PATCH 3/3] ASoC: DaVinci: More accurate calculation for clock divider for McBSP (I2S) In-Reply-To: <1278090747-5124-4-git-send-email-lamiaposta71@gmail.com> References: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> <1278090747-5124-4-git-send-email-lamiaposta71@gmail.com> Message-ID: <4C2E52BD.8060508@boundarydevices.com> Raffaele Recalcati wrote: > @@ -447,6 +448,24 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, > 8 - 1); > + if (dev->i2s_accurate_clock) { > + clk_div = 256; > + do { > + framesize = (freq / (--clk_div)) / > + params->rate_num * > + params->rate_den; > + } while (((framesize < 33) || (framesize > 4095)) && > + (clk_div)); > + clk_div--; > + srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1); > + } else { > + /* symmetric waveforms */ > + clk_div = freq / (mcbsp_word_length * 16) / > + params->rate_num * params->rate_den; > + srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * > + 16 - 1); > + } > + > /* symmetric waveforms */ > clk_div = freq / (mcbsp_word_length * 16) / > params->rate_num * params->rate_den; Can you test to see if this works to replace all the above ? unsigned cycles; framesize = mcbsp_word_length * 16; cycles = (freq / params->rate_num) * params->rate_den; clk_div = cycles / framesize; if (dev->i2s_accurate_clock) { framesize = cycles / clk_div; if (framesize > 4096)) framesize = 4096; } srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1); From bniebuhr3 at gmail.com Fri Jul 2 17:38:53 2010 From: bniebuhr3 at gmail.com (Brian Niebuhr) Date: Fri, 2 Jul 2010 17:38:53 -0500 Subject: [PATCH v2 0/1] davinci: spi: replace existing driver Message-ID: <1278110334-13943-1-git-send-email-bniebuhr@efjohnson.com> I have included all of the recommended changes in this version of the patch. I also combined the patches into one patch to avoid bisecting issues. This makes the diff on davinci_spi.c very large. If people who are using this driver could test this version of the driver and Ack it, I would appreciate it. ** NOTE ** This patch requires the EDMA patch at: http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-March/018022.html which is queued waiting on another driver fix, for DMA mode to work correctly. Brian Niebuhr (1): davinci: spi: replace existing driver arch/arm/mach-davinci/board-dm355-evm.c | 10 + arch/arm/mach-davinci/board-dm355-leopard.c | 10 + arch/arm/mach-davinci/board-dm365-evm.c | 10 + arch/arm/mach-davinci/dm355.c | 12 +- arch/arm/mach-davinci/dm365.c | 12 +- arch/arm/mach-davinci/include/mach/spi.h | 37 +- drivers/spi/davinci_spi.c | 1328 ++++++++++++--------------- 7 files changed, 648 insertions(+), 771 deletions(-) From bniebuhr3 at gmail.com Fri Jul 2 17:38:54 2010 From: bniebuhr3 at gmail.com (Brian Niebuhr) Date: Fri, 2 Jul 2010 17:38:54 -0500 Subject: [PATCH v2 1/1] davinci: spi: replace existing driver In-Reply-To: <1278110334-13943-1-git-send-email-bniebuhr@efjohnson.com> References: <1278110334-13943-1-git-send-email-bniebuhr@efjohnson.com> Message-ID: <1278110334-13943-2-git-send-email-bniebuhr@efjohnson.com> INTRODUCTION I have been working on a custom OMAP-L138 board that has multiple spi devices (seven) on one controller. These devices have a wide range of transfer parameters (speed, phase, polarity, internal and gpio chip selects). During my testing I found multiple errors in the davinci spi driver as a result of this complex setup. The primary issues were: 1. There is a race condition due to the SPIBUF read busy-waits for slow devices 2. I found some DMA transfer length errors under some conditions 3. The chip select code caused extra byte transfers (with no chip select active) due to writes to SPIDAT1 4. Several issues prevented using multiple SPI devices, especially the DMA code, as disucussed previously on the davinci list. The fixes to these problems were not simple. I ended up making fairly large changes to the driver, and those changes are contained in these patches. The full list of changes follows. CHANGE LIST 1. davinci_spi_chipelect() now performs both activation and deactivation of chip selects. This lets spi_bitbang fully control chip select activation, as intended by the SPI API. 2. Chip select activation does not cause extra writes to the SPI bus 3. Chip select activation does not use SPIDEF for control. This change will also allow for implementation of inverted (active high) chip selects in the future. 4. Added back gpio chip select capability from the old driver 5. Fixed prescale calculation for non-integer fractions of spi clock 6. Allow specification of SPI transfer parameters on a per-device (instead of per-controller) basis 7. Allow specification of polled, interrupt-based, or DMA operation on a per-device basis 8. Allow DMA with when more than one device is connected 9. Combined pio and dma txrx_bufs functions into one since they share large parts of their functionality, and to simplify item (8). 10. Use only SPIFMT0 to allow more than 4 devices TESTING I have tested the driver using a custom SPI stress test on my OMAP-L138-based board with three devices connected. I have tested configurations with all three devices polled, all three interrupt-based, all three DMA, and a mixture. I have compiled with the davinci_all_defconfig, but I don't have EVMs for the other davinci platforms to test with. Signed-off-by: Brian Niebuhr --- arch/arm/mach-davinci/board-dm355-evm.c | 10 + arch/arm/mach-davinci/board-dm355-leopard.c | 10 + arch/arm/mach-davinci/board-dm365-evm.c | 10 + arch/arm/mach-davinci/dm355.c | 12 +- arch/arm/mach-davinci/dm365.c | 12 +- arch/arm/mach-davinci/include/mach/spi.h | 37 +- drivers/spi/davinci_spi.c | 1328 ++++++++++++--------------- 7 files changed, 648 insertions(+), 771 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index a319101..d2e9f20 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -32,6 +32,7 @@ #include #include #include +#include /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you @@ -300,10 +301,19 @@ static struct spi_eeprom at25640a = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640a_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm355_evm_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640a, + .controller_data = &at25640a_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index f1d8132..63078dc 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -29,6 +29,7 @@ #include #include #include +#include /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you @@ -222,10 +223,19 @@ static struct spi_eeprom at25640a = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640a_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm355_leopard_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640a, + .controller_data = &at25640a_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 5bb86b2..5bc3622 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -39,6 +39,7 @@ #include #include #include +#include #include @@ -579,10 +580,19 @@ static struct spi_eeprom at25640 = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm365_evm_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640, + .controller_data = &at25640_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 3834781..378d41c 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -397,27 +397,21 @@ static struct resource dm355_spi0_resources[] = { }, { .start = 17, - .flags = IORESOURCE_DMA, + .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN, }, { .start = 16, - .flags = IORESOURCE_DMA, + .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN, }, { .start = EVENTQ_1, - .flags = IORESOURCE_DMA, + .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q, }, }; static struct davinci_spi_platform_data dm355_spi0_pdata = { .version = SPI_VERSION_1, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, }; static struct platform_device dm355_spi0_device = { .name = "spi_davinci", diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 652f4b6..8e68f8c 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); static struct davinci_spi_platform_data dm365_spi0_pdata = { .version = SPI_VERSION_1, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, }; static struct resource dm365_spi0_resources[] = { @@ -645,15 +639,15 @@ static struct resource dm365_spi0_resources[] = { }, { .start = 17, - .flags = IORESOURCE_DMA, + .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN, }, { .start = 16, - .flags = IORESOURCE_DMA, + .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN, }, { .start = EVENTQ_3, - .flags = IORESOURCE_DMA, + .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q, }, }; diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h index 910efbf..b69a2f5 100644 --- a/arch/arm/mach-davinci/include/mach/spi.h +++ b/arch/arm/mach-davinci/include/mach/spi.h @@ -19,6 +19,13 @@ #ifndef __ARCH_ARM_DAVINCI_SPI_H #define __ARCH_ARM_DAVINCI_SPI_H +#define SPI_INTERN_CS 0xFF + +/* resource flags for IORESOURCE_DMA resources */ +#define IORESOURCE_DMA_RX_CHAN 0x01 +#define IORESOURCE_DMA_TX_CHAN 0x02 +#define IORESOURCE_DMA_EVENT_Q 0x04 + enum { SPI_VERSION_1, /* For DM355/DM365/DM6467 */ SPI_VERSION_2, /* For DA8xx */ @@ -26,19 +33,25 @@ enum { struct davinci_spi_platform_data { u8 version; - u8 num_chipselect; - u8 wdelay; - u8 odd_parity; - u8 parity_enable; - u8 wait_enable; - u8 timer_disable; - u8 clk_internal; - u8 cs_hold; + u16 num_chipselect; + u8 *chip_sel; +}; + +struct davinci_spi_config { + bool odd_parity; + bool parity_enable; u8 intr_level; - u8 poll_mode; - u8 use_dma; - u8 c2tdelay; - u8 t2cdelay; + u8 io_type; +#define SPI_IO_TYPE_INTR 0 +#define SPI_IO_TYPE_POLL 1 +#define SPI_IO_TYPE_DMA 2 + u8 bytes_per_word; + u8 wdelay; + bool timer_disable; + u8 c2t_delay; + u8 t2c_delay; + u8 t2e_delay; + u8 c2e_delay; }; #endif /* __ARCH_ARM_DAVINCI_SPI_H */ diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index b85090c..10d5c34 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2009 Texas Instruments. + * Copyright (C) 2010 EF Johnson Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,197 +28,218 @@ #include #include #include -#include #include #include -#define SPI_NO_RESOURCE ((resource_size_t)-1) - -#define SPI_MAX_CHIPSELECT 2 - -#define CS_DEFAULT 0xFF - -#define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 - -#define SPIFMT_PHASE_MASK BIT(16) -#define SPIFMT_POLARITY_MASK BIT(17) -#define SPIFMT_DISTIMER_MASK BIT(18) -#define SPIFMT_SHIFTDIR_MASK BIT(20) -#define SPIFMT_WAITENA_MASK BIT(21) -#define SPIFMT_PARITYENA_MASK BIT(22) -#define SPIFMT_ODD_PARITY_MASK BIT(23) -#define SPIFMT_WDELAY_MASK 0x3f000000u -#define SPIFMT_WDELAY_SHIFT 24 -#define SPIFMT_CHARLEN_MASK 0x0000001Fu +#define CS_DEFAULT 0xFF +#define SCS0_SELECT 0x01 +#define SCS1_SELECT 0x02 +#define SCS2_SELECT 0x04 +#define SCS3_SELECT 0x08 +#define SCS4_SELECT 0x10 +#define SCS5_SELECT 0x20 +#define SCS6_SELECT 0x40 +#define SCS7_SELECT 0x80 + +#define SPIFMT_PHASE_MASK BIT(16) +#define SPIFMT_POLARITY_MASK BIT(17) +#define SPIFMT_DISTIMER_MASK BIT(18) +#define SPIFMT_SHIFTDIR_MASK BIT(20) +#define SPIFMT_WAITENA_MASK BIT(21) +#define SPIFMT_PARITYENA_MASK BIT(22) +#define SPIFMT_ODD_PARITY_MASK BIT(23) +#define SPIFMT_WDELAY_MASK 0x3f000000u +#define SPIFMT_WDELAY_SHIFT 24 +#define SPIFMT_CHARLEN_MASK 0x0000001Fu +#define SPIFMT_PRESCALE_SHIFT 8 /* SPIGCR1 */ -#define SPIGCR1_SPIENA_MASK 0x01000000u +#define SPIGCR1_SPIENA_MASK BIT(24) +#define SPIGCR1_POWERDOWN_MASK BIT(8) /* SPIPC0 */ -#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ -#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ -#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ -#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ -#define SPIPC0_EN1FUN_MASK BIT(1) -#define SPIPC0_EN0FUN_MASK BIT(0) - -#define SPIINT_MASKALL 0x0101035F -#define SPI_INTLVL_1 0x000001FFu -#define SPI_INTLVL_0 0x00000000u +#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ +#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ +#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ +#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ +#define SPIPC0_EN1FUN_MASK BIT(1) +#define SPIPC0_EN0FUN_MASK BIT(0) + +#define SPIINT_MASKALL 0x0101035Fu +#define SPIINT_MASKINT 0x0000035Fu +#define SPI_INTLVL_1 0x000001FFu +#define SPI_INTLVL_0 0x00000000u /* SPIDAT1 */ +#define SPIDAT1_CSHOLD_MASK BIT(28) #define SPIDAT1_CSHOLD_SHIFT 28 +#define SPIDAT1_WDEL_MASK BIT(26) +#define SPIDAT1_CSNR_MASK 0x00FF0000u #define SPIDAT1_CSNR_SHIFT 16 +#define SPIDAT1_DFSEL_MASK (BIT(24 | BIT(25)) #define SPIGCR1_CLKMOD_MASK BIT(1) -#define SPIGCR1_MASTER_MASK BIT(0) +#define SPIGCR1_MASTER_MASK BIT(0) #define SPIGCR1_LOOPBACK_MASK BIT(16) /* SPIBUF */ -#define SPIBUF_TXFULL_MASK BIT(29) -#define SPIBUF_RXEMPTY_MASK BIT(31) +#define SPIBUF_TXFULL_MASK BIT(29) +#define SPIBUF_RXEMPTY_MASK BIT(31) + +/* SPIDELAY */ +#define SPIDELAY_C2TDELAY_MASK 0xFF000000u +#define SPIDELAY_C2TDELAY_SHIFT 24 +#define SPIDELAY_T2CDELAY_MASK 0x00FF0000u +#define SPIDELAY_T2CDELAY_SHIFT 16 +#define SPIDELAY_T2EDELAY_MASK 0x0000FF00u +#define SPIDELAY_T2EDELAY_SHIFT 8 +#define SPIDELAY_C2EDELAY_MASK 0x000000FFu +#define SPIDELAY_C2EDELAY_SHIFT 0 + +/* SPIDEF */ +#define SPIDEF_CSDEF_MASK 0x000000FFu /* Error Masks */ -#define SPIFLG_DLEN_ERR_MASK BIT(0) -#define SPIFLG_TIMEOUT_MASK BIT(1) -#define SPIFLG_PARERR_MASK BIT(2) -#define SPIFLG_DESYNC_MASK BIT(3) -#define SPIFLG_BITERR_MASK BIT(4) -#define SPIFLG_OVRRUN_MASK BIT(6) -#define SPIFLG_RX_INTR_MASK BIT(8) -#define SPIFLG_TX_INTR_MASK BIT(9) -#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) -#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \ - | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ - | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ - | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \ - | SPIFLG_TX_INTR_MASK \ - | SPIFLG_BUF_INIT_ACTIVE_MASK) - -#define SPIINT_DLEN_ERR_INTR BIT(0) -#define SPIINT_TIMEOUT_INTR BIT(1) -#define SPIINT_PARERR_INTR BIT(2) -#define SPIINT_DESYNC_INTR BIT(3) -#define SPIINT_BITERR_INTR BIT(4) -#define SPIINT_OVRRUN_INTR BIT(6) -#define SPIINT_RX_INTR BIT(8) -#define SPIINT_TX_INTR BIT(9) -#define SPIINT_DMA_REQ_EN BIT(16) -#define SPIINT_ENABLE_HIGHZ BIT(24) - -#define SPI_T2CDELAY_SHIFT 16 -#define SPI_C2TDELAY_SHIFT 24 - +#define SPIFLG_DLEN_ERR_MASK BIT(0) +#define SPIFLG_TIMEOUT_MASK BIT(1) +#define SPIFLG_PARERR_MASK BIT(2) +#define SPIFLG_DESYNC_MASK BIT(3) +#define SPIFLG_BITERR_MASK BIT(4) +#define SPIFLG_OVRRUN_MASK BIT(6) +#define SPIFLG_RX_INTR_MASK BIT(8) +#define SPIFLG_TX_INTR_MASK BIT(9) +#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) +#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ + | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ + | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ + | SPIFLG_OVRRUN_MASK) +#define SPIFLG_MASK (SPIFLG_ERROR_MASK \ + | SPIFLG_RX_INTR_MASK | SPIFLG_TX_INTR_MASK \ + | SPIFLG_BUF_INIT_ACTIVE_MASK) + +#define SPIINT_DLEN_ERR_INTR BIT(0) +#define SPIINT_TIMEOUT_INTR BIT(1) +#define SPIINT_PARERR_INTR BIT(2) +#define SPIINT_DESYNC_INTR BIT(3) +#define SPIINT_BITERR_INTR BIT(4) +#define SPIINT_OVRRUN_INTR BIT(6) +#define SPIINT_RX_INTR BIT(8) +#define SPIINT_TX_INTR BIT(9) +#define SPIINT_DMA_REQ_EN BIT(16) +#define SPIINT_ENABLE_HIGHZ BIT(24) + +#define SPI_T2CDELAY_SHIFT 16 +#define SPI_C2TDELAY_SHIFT 24 /* SPI Controller registers */ -#define SPIGCR0 0x00 -#define SPIGCR1 0x04 -#define SPIINT 0x08 -#define SPILVL 0x0c -#define SPIFLG 0x10 -#define SPIPC0 0x14 -#define SPIPC1 0x18 -#define SPIPC2 0x1c -#define SPIPC3 0x20 -#define SPIPC4 0x24 -#define SPIPC5 0x28 -#define SPIPC6 0x2c -#define SPIPC7 0x30 -#define SPIPC8 0x34 -#define SPIDAT0 0x38 -#define SPIDAT1 0x3c -#define SPIBUF 0x40 -#define SPIEMU 0x44 -#define SPIDELAY 0x48 -#define SPIDEF 0x4c -#define SPIFMT0 0x50 -#define SPIFMT1 0x54 -#define SPIFMT2 0x58 -#define SPIFMT3 0x5c -#define TGINTVEC0 0x60 -#define TGINTVEC1 0x64 - -struct davinci_spi_slave { - u32 cmd_to_write; - u32 clk_ctrl_to_write; - u32 bytes_per_word; - u8 active_cs; +#define SPIGCR0 0x00 +#define SPIGCR1 0x04 +#define SPIINT 0x08 +#define SPILVL 0x0c +#define SPIFLG 0x10 +#define SPIPC0 0x14 +#define SPIPC1 0x18 +#define SPIPC2 0x1c +#define SPIPC3 0x20 +#define SPIPC4 0x24 +#define SPIPC5 0x28 +#define SPIPC6 0x2c +#define SPIPC7 0x30 +#define SPIPC8 0x34 +#define SPIDAT0 0x38 +#define SPIDAT1 0x3c +#define SPIBUF 0x40 +#define SPIEMU 0x44 +#define SPIDELAY 0x48 +#define SPIDEF 0x4c +#define SPIFMT0 0x50 +#define SPIFMT1 0x54 +#define SPIFMT2 0x58 +#define SPIFMT3 0x5c +#define TGINTVEC0 0x60 +#define TGINTVEC1 0x64 + +#define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) + +const char * const io_type_names[] = { + [SPI_IO_TYPE_INTR] = "Interrupt", + [SPI_IO_TYPE_POLL] = "Polled", + [SPI_IO_TYPE_DMA] = "DMA", }; /* We have 2 DMA channels per CS, one for RX and one for TX */ struct davinci_spi_dma { - int dma_tx_channel; - int dma_rx_channel; - int dma_tx_sync_dev; - int dma_rx_sync_dev; - enum dma_event_q eventq; - - struct completion dma_tx_completion; - struct completion dma_rx_completion; + int dma_tx_channel; + int dma_rx_channel; + int dma_tx_sync_dev; + int dma_rx_sync_dev; + int dummy_param_slot; + enum dma_event_q eventq; }; /* SPI Controller driver's private data. */ struct davinci_spi { - struct spi_bitbang bitbang; - struct clk *clk; - - u8 version; - resource_size_t pbase; - void __iomem *base; - size_t region_size; - u32 irq; - struct completion done; - - const void *tx; - void *rx; - u8 *tmp_buf; - int count; - struct davinci_spi_dma *dma_channels; - struct davinci_spi_platform_data *pdata; - - void (*get_rx)(u32 rx_data, struct davinci_spi *); - u32 (*get_tx)(struct davinci_spi *); - - struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT]; + struct spi_bitbang bitbang; + struct clk *clk; + + u8 version; + resource_size_t pbase; + void __iomem *base; + size_t region_size; + u32 irq; + struct completion done; + + const void *tx; + void *rx; + u8 *tmp_buf; + int rcount; + int wcount; + u32 errors; + struct davinci_spi_dma dma_channels; + struct davinci_spi_platform_data *pdata; + + void (*get_rx)(u32 rx_data, struct davinci_spi *); + u32 (*get_tx)(struct davinci_spi *); }; -static unsigned use_dma; +#define DAVINCI_SPI_NO_RESOURCE ((resource_size_t)-1) static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) { - u8 *rx = davinci_spi->rx; - - *rx++ = (u8)data; - davinci_spi->rx = rx; + if (davinci_spi->rx) { + u8 *rx = davinci_spi->rx; + *rx++ = (u8)data; + davinci_spi->rx = rx; + } } static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) { - u16 *rx = davinci_spi->rx; - - *rx++ = (u16)data; - davinci_spi->rx = rx; + if (davinci_spi->rx) { + u16 *rx = davinci_spi->rx; + *rx++ = (u16)data; + davinci_spi->rx = rx; + } } static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) { - u32 data; - const u8 *tx = davinci_spi->tx; - - data = *tx++; - davinci_spi->tx = tx; + u32 data = 0; + if (davinci_spi->tx) { + const u8 *tx = davinci_spi->tx; + data = *tx++; + davinci_spi->tx = tx; + } return data; } static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) { - u32 data; - const u16 *tx = davinci_spi->tx; - - data = *tx++; - davinci_spi->tx = tx; + u32 data = 0; + if (davinci_spi->tx) { + const u16 *tx = davinci_spi->tx; + data = *tx++; + davinci_spi->tx = tx; + } return data; } @@ -237,26 +259,6 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits) iowrite32(v, addr); } -static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num) -{ - set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); -} - -static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num) -{ - clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); -} - -static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) -{ - struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); - - if (enable) - set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); - else - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); -} - /* * Interface to control the chip select signal */ @@ -264,28 +266,57 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) { struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; - u32 data1_reg_val = 0; + u8 i, chip_sel = spi->chip_select; + u32 spidat1; + u16 spidat1_cfg; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; - /* - * Board specific chip select logic decides the polarity and cs - * line for the controller - */ - if (value == BITBANG_CS_INACTIVE) { - set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT); - - data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT; - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); + spidat1 = SPIDAT1_CSNR_MASK; + if (value == BITBANG_CS_ACTIVE) + spidat1 |= SPIDAT1_CSHOLD_MASK; + else + spidat1 |= SPIDAT1_WDEL_MASK; - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); + if (pdata->chip_sel == NULL) { + if (value == BITBANG_CS_ACTIVE) + spidat1 &= ~((0x1 << chip_sel) << SPIDAT1_CSNR_SHIFT); + } else { + for (i = 0; i < pdata->num_chipselect; i++) { + if (pdata->chip_sel[i] == SPI_INTERN_CS) { + if ((i == chip_sel) && + (value == BITBANG_CS_ACTIVE)) { + spidat1 &= ~((0x1 << chip_sel) + << SPIDAT1_CSNR_SHIFT); + } + } else { + if (value == BITBANG_CS_INACTIVE) + gpio_set_value(pdata->chip_sel[i], 1); + else if (i == chip_sel) + gpio_set_value(pdata->chip_sel[i], 0); + } + } } + + spidat1_cfg = spidat1 >> SPIDAT1_CSNR_SHIFT; + iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); +} + +/* + * davinci_spi_get_prescale - Calculates the correct prescale value + * @max_speed_hz: the maximum rate the SPI clock can run at + * + * This function calculates the prescale value that generates a clock rate + * less than or equal to the specified maximum + */ +static inline u32 davinci_spi_get_prescale(struct davinci_spi *davinci_spi, + u32 max_speed_hz) +{ + return ((clk_get_rate(davinci_spi->clk) - 1) / max_speed_hz) & 0xff; } -/** +/* * davinci_spi_setup_transfer - This functions will determine transfer method * @spi: spi device on which data transfer to be done * @t: spi transfer in which transfer info is filled @@ -297,14 +328,15 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) static int davinci_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { - struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; + struct davinci_spi_config *spi_cfg; u8 bits_per_word = 0; - u32 hz = 0, prescale = 0, clkspeed; + u32 hz = 0, spifmt = 0, prescale, delay = 0; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; + spi_cfg = spi->controller_data; if (t) { bits_per_word = t->bits_per_word; @@ -322,76 +354,112 @@ static int davinci_spi_setup_transfer(struct spi_device *spi, if (bits_per_word <= 8 && bits_per_word >= 2) { davinci_spi->get_rx = davinci_spi_rx_buf_u8; davinci_spi->get_tx = davinci_spi_tx_buf_u8; - davinci_spi->slave[spi->chip_select].bytes_per_word = 1; + spi_cfg->bytes_per_word = 1; } else if (bits_per_word <= 16 && bits_per_word >= 2) { davinci_spi->get_rx = davinci_spi_rx_buf_u16; davinci_spi->get_tx = davinci_spi_tx_buf_u16; - davinci_spi->slave[spi->chip_select].bytes_per_word = 2; + spi_cfg->bytes_per_word = 2; } else return -EINVAL; if (!hz) hz = spi->max_speed_hz; - clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK, - spi->chip_select); - set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f, - spi->chip_select); + prescale = davinci_spi_get_prescale(davinci_spi, hz); + spifmt |= (prescale << SPIFMT_PRESCALE_SHIFT); + + spifmt |= (bits_per_word & 0x1f); + + if (spi->mode & SPI_LSB_FIRST) + spifmt |= SPIFMT_SHIFTDIR_MASK; - clkspeed = clk_get_rate(davinci_spi->clk); - if (hz > clkspeed / 2) - prescale = 1 << 8; - if (hz < clkspeed / 256) - prescale = 255 << 8; - if (!prescale) - prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00; + if (spi->mode & SPI_CPOL) + spifmt |= SPIFMT_POLARITY_MASK; - clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select); - set_fmt_bits(davinci_spi->base, prescale, spi->chip_select); + if (!(spi->mode & SPI_CPHA)) + spifmt |= SPIFMT_PHASE_MASK; + + if (davinci_spi->version == SPI_VERSION_2) { + spifmt |= ((spi_cfg->wdelay << SPIFMT_WDELAY_SHIFT) + & SPIFMT_WDELAY_MASK); + + if (spi_cfg->odd_parity) + spifmt |= SPIFMT_ODD_PARITY_MASK; + + if (spi_cfg->parity_enable) + spifmt |= SPIFMT_PARITYENA_MASK; + + if (spi->mode & SPI_READY) { + spifmt |= SPIFMT_WAITENA_MASK; + delay |= (spi_cfg->t2e_delay + << SPIDELAY_T2EDELAY_SHIFT) + & SPIDELAY_T2EDELAY_MASK; + delay |= (spi_cfg->c2e_delay + << SPIDELAY_C2EDELAY_SHIFT) + & SPIDELAY_C2EDELAY_MASK; + } + + if (spi_cfg->timer_disable) { + spifmt |= SPIFMT_DISTIMER_MASK; + } else { + delay |= (spi_cfg->c2t_delay + << SPIDELAY_C2TDELAY_SHIFT) + & SPIDELAY_C2TDELAY_MASK; + delay |= (spi_cfg->t2c_delay + << SPIDELAY_T2CDELAY_SHIFT) + & SPIDELAY_T2CDELAY_MASK; + } + + iowrite32(delay, davinci_spi->base + SPIDELAY); + } + + iowrite32(spifmt, davinci_spi->base + SPIFMT0); + + if (spi_cfg->intr_level) + iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); + else + iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); + + if (spi->mode & SPI_LOOP) + set_io_bits(davinci_spi->base + SPIGCR1, + SPIGCR1_LOOPBACK_MASK); + else + clear_io_bits(davinci_spi->base + SPIGCR1, + SPIGCR1_LOOPBACK_MASK); return 0; } static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) { - struct spi_device *spi = (struct spi_device *)data; - struct davinci_spi *davinci_spi; + struct davinci_spi *davinci_spi = (struct davinci_spi *)data; struct davinci_spi_dma *davinci_spi_dma; struct davinci_spi_platform_data *pdata; - davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); + davinci_spi_dma = &(davinci_spi->dma_channels); pdata = davinci_spi->pdata; + edma_stop(davinci_spi_dma->dma_rx_channel); + if (ch_status == DMA_COMPLETE) - edma_stop(davinci_spi_dma->dma_rx_channel); - else - edma_clean_channel(davinci_spi_dma->dma_rx_channel); + davinci_spi->rcount = 0; - complete(&davinci_spi_dma->dma_rx_completion); - /* We must disable the DMA RX request */ - davinci_spi_set_dma_req(spi, 0); + complete(&davinci_spi->done); } static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) { - struct spi_device *spi = (struct spi_device *)data; - struct davinci_spi *davinci_spi; + struct davinci_spi *davinci_spi = (struct davinci_spi *)data; struct davinci_spi_dma *davinci_spi_dma; struct davinci_spi_platform_data *pdata; - davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); + davinci_spi_dma = &(davinci_spi->dma_channels); pdata = davinci_spi->pdata; - if (ch_status == DMA_COMPLETE) - edma_stop(davinci_spi_dma->dma_tx_channel); - else - edma_clean_channel(davinci_spi_dma->dma_tx_channel); + edma_stop(davinci_spi_dma->dma_tx_channel); - complete(&davinci_spi_dma->dma_tx_completion); - /* We must disable the DMA TX request */ - davinci_spi_set_dma_req(spi, 0); + if (ch_status == DMA_COMPLETE) + davinci_spi->wcount = 0; } static int davinci_spi_request_dma(struct spi_device *spi) @@ -403,33 +471,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) int r; davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; + davinci_spi_dma = &davinci_spi->dma_channels; pdata = davinci_spi->pdata; sdev = davinci_spi->bitbang.master->dev.parent; r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, - davinci_spi_dma_rx_callback, spi, + davinci_spi_dma_rx_callback, davinci_spi, davinci_spi_dma->eventq); if (r < 0) { - dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); - return -EAGAIN; + dev_dbg(sdev, "Unable to request DMA channel for MibSPI RX\n"); + r = -EAGAIN; + goto rx_dma_failed; } davinci_spi_dma->dma_rx_channel = r; + r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, - davinci_spi_dma_tx_callback, spi, + davinci_spi_dma_tx_callback, davinci_spi, davinci_spi_dma->eventq); if (r < 0) { - edma_free_channel(davinci_spi_dma->dma_rx_channel); - davinci_spi_dma->dma_rx_channel = -1; - dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); - return -EAGAIN; + dev_dbg(sdev, "Unable to request DMA channel for MibSPI TX\n"); + r = -EAGAIN; + goto tx_dma_failed; } davinci_spi_dma->dma_tx_channel = r; + r = edma_alloc_slot(EDMA_CTLR(davinci_spi_dma->dma_tx_sync_dev), + EDMA_SLOT_ANY); + if (r < 0) { + dev_dbg(sdev, "Unable to request SPI DMA param slot\n"); + r = -EAGAIN; + goto param_failed; + } + davinci_spi_dma->dummy_param_slot = r; + edma_link(davinci_spi_dma->dummy_param_slot, + davinci_spi_dma->dummy_param_slot); + return 0; + +param_failed: + edma_free_channel(davinci_spi_dma->dma_tx_channel); + davinci_spi_dma->dma_tx_channel = -1; +tx_dma_failed: + edma_free_channel(davinci_spi_dma->dma_rx_channel); + davinci_spi_dma->dma_rx_channel = -1; +rx_dma_failed: + return r; } -/** +/* * davinci_spi_setup - This functions will set default transfer method * @spi: spi device on which data transfer to be done * @@ -438,129 +527,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) static int davinci_spi_setup(struct spi_device *spi) { - int retval; + int retval = 0; struct davinci_spi *davinci_spi; - struct davinci_spi_dma *davinci_spi_dma; - struct device *sdev; + struct davinci_spi_dma *davinci_dma; + struct davinci_spi_platform_data *pdata; + struct davinci_spi_config *spi_cfg; + u32 prescale; davinci_spi = spi_master_get_devdata(spi->master); - sdev = davinci_spi->bitbang.master->dev.parent; + pdata = davinci_spi->pdata; + spi_cfg = (struct davinci_spi_config *)spi->controller_data; + davinci_dma = &(davinci_spi->dma_channels); /* if bits per word length is zero then set it default 8 */ if (!spi->bits_per_word) spi->bits_per_word = 8; - davinci_spi->slave[spi->chip_select].cmd_to_write = 0; - - if (use_dma && davinci_spi->dma_channels) { - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if ((davinci_spi_dma->dma_rx_channel == -1) - || (davinci_spi_dma->dma_tx_channel == -1)) { - retval = davinci_spi_request_dma(spi); - if (retval < 0) - return retval; - } - } + if (!(spi->mode & SPI_NO_CS)) { + if ((pdata->chip_sel == NULL) || + (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) + set_io_bits(davinci_spi->base + SPIPC0, + 1 << spi->chip_select); - /* - * SPI in DaVinci and DA8xx operate between - * 600 KHz and 50 MHz - */ - if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) { - dev_dbg(sdev, "Operating frequency is not in acceptable " - "range\n"); - return -EINVAL; } - /* - * Set up SPIFMTn register, unique to this chipselect. - * - * NOTE: we could do all of these with one write. Also, some - * of the "version 2" features are found in chips that don't - * support all of them... - */ - if (spi->mode & SPI_LSB_FIRST) - set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, - spi->chip_select); + if (spi->mode & SPI_READY) + set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); - if (spi->mode & SPI_CPOL) - set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, - spi->chip_select); + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + davinci_dma = &(davinci_spi->dma_channels); - if (!(spi->mode & SPI_CPHA)) - set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, - spi->chip_select); + if ((davinci_dma->dma_tx_sync_dev == DAVINCI_SPI_NO_RESOURCE) || + (davinci_dma->dma_rx_sync_dev == DAVINCI_SPI_NO_RESOURCE) || + (davinci_dma->eventq == DAVINCI_SPI_NO_RESOURCE)) + spi_cfg->io_type = SPI_IO_TYPE_INTR; + else if ((davinci_dma->dma_rx_channel == -1) || + (davinci_dma->dma_tx_channel == -1)) + retval = davinci_spi_request_dma(spi); + } /* - * Version 1 hardware supports two basic SPI modes: - * - Standard SPI mode uses 4 pins, with chipselect - * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) - * (distinct from SPI_3WIRE, with just one data wire; - * or similar variants without MOSI or without MISO) - * - * Version 2 hardware supports an optional handshaking signal, - * so it can support two more modes: - * - 5 pin SPI variant is standard SPI plus SPI_READY - * - 4 pin with enable is (SPI_READY | SPI_NO_CS) + * Validate desired clock rate */ + prescale = davinci_spi_get_prescale(davinci_spi, spi->max_speed_hz); + if ((prescale < 2) || (prescale > 255)) + return -EINVAL; - if (davinci_spi->version == SPI_VERSION_2) { - clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK, - spi->chip_select); - set_fmt_bits(davinci_spi->base, - (davinci_spi->pdata->wdelay - << SPIFMT_WDELAY_SHIFT) - & SPIFMT_WDELAY_MASK, - spi->chip_select); - - if (davinci_spi->pdata->odd_parity) - set_fmt_bits(davinci_spi->base, - SPIFMT_ODD_PARITY_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_ODD_PARITY_MASK, - spi->chip_select); - - if (davinci_spi->pdata->parity_enable) - set_fmt_bits(davinci_spi->base, - SPIFMT_PARITYENA_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_PARITYENA_MASK, - spi->chip_select); - - if (davinci_spi->pdata->wait_enable) - set_fmt_bits(davinci_spi->base, - SPIFMT_WAITENA_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_WAITENA_MASK, - spi->chip_select); - - if (davinci_spi->pdata->timer_disable) - set_fmt_bits(davinci_spi->base, - SPIFMT_DISTIMER_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_DISTIMER_MASK, - spi->chip_select); - } - - retval = davinci_spi_setup_transfer(spi, NULL); + dev_info(&spi->dev, "DaVinci SPI driver in %s mode\n", + io_type_names[spi_cfg->io_type]); return retval; } @@ -569,50 +583,19 @@ static void davinci_spi_cleanup(struct spi_device *spi) { struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); struct davinci_spi_dma *davinci_spi_dma; + struct davinci_spi_platform_data *pdata; - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if (use_dma && davinci_spi->dma_channels) { - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if ((davinci_spi_dma->dma_rx_channel != -1) - && (davinci_spi_dma->dma_tx_channel != -1)) { - edma_free_channel(davinci_spi_dma->dma_tx_channel); - edma_free_channel(davinci_spi_dma->dma_rx_channel); - } - } -} - -static int davinci_spi_bufs_prep(struct spi_device *spi, - struct davinci_spi *davinci_spi) -{ - int op_mode = 0; - - /* - * REVISIT unless devices disagree about SPI_LOOP or - * SPI_READY (SPI_NO_CS only allows one device!), this - * should not need to be done before each message... - * optimize for both flags staying cleared. - */ - - op_mode = SPIPC0_DIFUN_MASK - | SPIPC0_DOFUN_MASK - | SPIPC0_CLKFUN_MASK; - if (!(spi->mode & SPI_NO_CS)) - op_mode |= 1 << spi->chip_select; - if (spi->mode & SPI_READY) - op_mode |= SPIPC0_SPIENA_MASK; + davinci_spi_dma = &davinci_spi->dma_channels; + pdata = davinci_spi->pdata; - iowrite32(op_mode, davinci_spi->base + SPIPC0); + if (davinci_spi_dma->dma_rx_channel != -1) + edma_free_channel(davinci_spi_dma->dma_rx_channel); - if (spi->mode & SPI_LOOP) - set_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_LOOPBACK_MASK); - else - clear_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_LOOPBACK_MASK); + if (davinci_spi_dma->dma_tx_channel != -1) + edma_free_channel(davinci_spi_dma->dma_tx_channel); - return 0; + if (davinci_spi_dma->dummy_param_slot != -1) + edma_free_slot(davinci_spi_dma->dummy_param_slot); } static int davinci_spi_check_error(struct davinci_spi *davinci_spi, @@ -659,356 +642,248 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi, return 0; } -/** - * davinci_spi_bufs - functions which will handle transfer data - * @spi: spi device on which data transfer to be done - * @t: spi transfer in which transfer info is filled +/* + * davinci_spi_process_events - check for and handle any SPI controller events + * @davinci_spi - the controller data * - * This function will put data to be transferred into data register - * of SPI controller and then wait until the completion will be marked - * by the IRQ Handler. + * This function will check the SPIFLG register and handle any events that are + * detected there */ -static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) +static int davinci_spi_process_events(struct davinci_spi *davinci_spi) { - struct davinci_spi *davinci_spi; - int int_status, count, ret; - u8 conv, tmp; - u32 tx_data, data1_reg_val; - u32 buf_val, flg_val; - struct davinci_spi_platform_data *pdata; - - davinci_spi = spi_master_get_devdata(spi->master); - pdata = davinci_spi->pdata; - - davinci_spi->tx = t->tx_buf; - davinci_spi->rx = t->rx_buf; - - /* convert len to words based on bits_per_word */ - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; - davinci_spi->count = t->len / conv; - - INIT_COMPLETION(davinci_spi->done); - - ret = davinci_spi_bufs_prep(spi, davinci_spi); - if (ret) - return ret; - - /* Enable SPI */ - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), - davinci_spi->base + SPIDELAY); - - count = davinci_spi->count; - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; - tmp = ~(0x1 << spi->chip_select); - - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); - - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; - - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); - - /* Determine the command to execute READ or WRITE */ - if (t->tx_buf) { - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); - - while (1) { - tx_data = davinci_spi->get_tx(davinci_spi); - - data1_reg_val &= ~(0xFFFF); - data1_reg_val |= (0xFFFF & tx_data); - - buf_val = ioread32(davinci_spi->base + SPIBUF); - if ((buf_val & SPIBUF_TXFULL_MASK) == 0) { - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - count--; - } - while (ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) - cpu_relax(); - - /* getting the returned byte */ - if (t->rx_buf) { - buf_val = ioread32(davinci_spi->base + SPIBUF); - davinci_spi->get_rx(buf_val, davinci_spi); - } - if (count <= 0) - break; - } - } else { - if (pdata->poll_mode) { - while (1) { - /* keeps the serial clock going */ - if ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_TXFULL_MASK) == 0) - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - while (ioread32(davinci_spi->base + SPIBUF) & - SPIBUF_RXEMPTY_MASK) - cpu_relax(); - - flg_val = ioread32(davinci_spi->base + SPIFLG); - buf_val = ioread32(davinci_spi->base + SPIBUF); - - davinci_spi->get_rx(buf_val, davinci_spi); - - count--; - if (count <= 0) - break; - } - } else { /* Receive in Interrupt mode */ - int i; - - for (i = 0; i < davinci_spi->count; i++) { - set_io_bits(davinci_spi->base + SPIINT, - SPIINT_BITERR_INTR - | SPIINT_OVRRUN_INTR - | SPIINT_RX_INTR); - - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - while (ioread32(davinci_spi->base + SPIINT) & - SPIINT_RX_INTR) - cpu_relax(); - } - iowrite32((data1_reg_val & 0x0ffcffff), - davinci_spi->base + SPIDAT1); - } + u32 status, tx_data, rx_data, spidat1; + u8 tx_word = 0; + + status = ioread32(davinci_spi->base + SPIFLG); + + if ((davinci_spi->version == SPI_VERSION_2) && + (likely(status & SPIFLG_TX_INTR_MASK)) && + (likely(davinci_spi->wcount > 0))) + tx_word = 1; + + if (likely(status & SPIFLG_RX_INTR_MASK)) { + rx_data = ioread32(davinci_spi->base + SPIBUF) & 0xFFFF; + davinci_spi->get_rx(rx_data, davinci_spi); + davinci_spi->rcount--; + if ((davinci_spi->version != SPI_VERSION_2) && + (likely(davinci_spi->wcount > 0))) + tx_word = 1; } - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - int_status = ioread32(davinci_spi->base + SPIFLG); - - ret = davinci_spi_check_error(davinci_spi, int_status); - if (ret != 0) - return ret; + if (unlikely(status & SPIFLG_ERROR_MASK)) { + davinci_spi->errors = (status & SPIFLG_ERROR_MASK); + return -1; + } - /* SPI Framework maintains the count only in bytes so convert back */ - davinci_spi->count *= conv; + if (likely(tx_word)) { + spidat1 = ioread32(davinci_spi->base + SPIDAT1); + davinci_spi->wcount--; + tx_data = davinci_spi->get_tx(davinci_spi); + spidat1 &= 0xFFFF0000; + spidat1 |= (tx_data & 0xFFFF); + iowrite32(spidat1, davinci_spi->base + SPIDAT1); + } - return t->len; + return 0; } -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 - -static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) +/* + * davinci_spi_txrx_bufs - function which will handle transfer data + * @spi: spi device on which data transfer to be done + * @t: spi transfer in which transfer info is filled + * + * This function will put data to be transferred into data register + * of SPI controller and then wait until the completion will be marked + * by the IRQ Handler. + */ +static int davinci_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) { struct davinci_spi *davinci_spi; - int int_status = 0; - int count, temp_count; - u8 conv = 1; - u8 tmp; - u32 data1_reg_val; - struct davinci_spi_dma *davinci_spi_dma; - int word_len, data_type, ret; - unsigned long tx_reg, rx_reg; + int data_type, ret = 0; + u32 tx_data, spidat1; + u16 tx_buf_count = 0, rx_buf_count = 0; + struct davinci_spi_config *spi_cfg; struct davinci_spi_platform_data *pdata; + struct davinci_spi_dma *davinci_dma; struct device *sdev; + dma_addr_t tx_reg, rx_reg; + void *tx_buf, *rx_buf; + struct edmacc_param rx_param, tx_param; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; - sdev = davinci_spi->bitbang.master->dev.parent; - - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; - rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; + spi_cfg = (struct davinci_spi_config *)spi->controller_data; + davinci_dma = &(davinci_spi->dma_channels); davinci_spi->tx = t->tx_buf; davinci_spi->rx = t->rx_buf; + davinci_spi->wcount = t->len / spi_cfg->bytes_per_word; + davinci_spi->rcount = davinci_spi->wcount; + davinci_spi->errors = 0; - /* convert len to words based on bits_per_word */ - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; - davinci_spi->count = t->len / conv; - - INIT_COMPLETION(davinci_spi->done); + spidat1 = ioread32(davinci_spi->base + SPIDAT1); - init_completion(&davinci_spi_dma->dma_rx_completion); - init_completion(&davinci_spi_dma->dma_tx_completion); - - word_len = conv * 8; - - if (word_len <= 8) - data_type = DAVINCI_DMA_DATA_TYPE_S8; - else if (word_len <= 16) - data_type = DAVINCI_DMA_DATA_TYPE_S16; - else if (word_len <= 32) - data_type = DAVINCI_DMA_DATA_TYPE_S32; - else - return -EINVAL; - - ret = davinci_spi_bufs_prep(spi, davinci_spi); - if (ret) - return ret; - - /* Put delay val if required */ - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), - davinci_spi->base + SPIDELAY); - - count = davinci_spi->count; /* the number of elements */ - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; - - /* CS default = 0xFF */ - tmp = ~(0x1 << spi->chip_select); - - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); - - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; - - /* disable all interrupts for dma transfers */ - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); - /* Disable SPI to write configuration bits in SPIDAT */ - clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); - /* Enable SPI */ + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); - + INIT_COMPLETION(davinci_spi->done); - if (t->tx_buf) { - t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, - DMA_TO_DEVICE); - if (dma_mapping_error(&spi->dev, t->tx_dma)) { - dev_dbg(sdev, "Unable to DMA map a %d bytes" - " TX buffer\n", count); - return -ENOMEM; + if ((spi_cfg->io_type == SPI_IO_TYPE_INTR) || + (spi_cfg->io_type == SPI_IO_TYPE_POLL)) { + + if (spi_cfg->io_type == SPI_IO_TYPE_INTR) + set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); + + /* start the transfer */ + davinci_spi->wcount--; + tx_data = davinci_spi->get_tx(davinci_spi); + spidat1 &= 0xFFFF0000; + spidat1 |= (tx_data & 0xFFFF); + iowrite32(spidat1, davinci_spi->base + SPIDAT1); + + } else if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + data_type = spi_cfg->bytes_per_word; + tx_reg = (dma_addr_t)davinci_spi->pbase + SPIDAT1; + rx_reg = (dma_addr_t)davinci_spi->pbase + SPIBUF; + + if (t->tx_buf) { + tx_buf = ((void *)t->tx_buf); + tx_buf_count = davinci_spi->wcount; + } else { + tx_buf = (void *)davinci_spi->tmp_buf; + tx_buf_count = SPI_BUFSIZ; } - temp_count = count; - } else { - /* We need TX clocking for RX transaction */ - t->tx_dma = dma_map_single(&spi->dev, - (void *)davinci_spi->tmp_buf, count + 1, - DMA_TO_DEVICE); - if (dma_mapping_error(&spi->dev, t->tx_dma)) { - dev_dbg(sdev, "Unable to DMA map a %d bytes" - " TX tmp buffer\n", count); - return -ENOMEM; + if (t->rx_buf) { + rx_buf = (void *)t->rx_buf; + rx_buf_count = davinci_spi->rcount; + } else { + rx_buf = (void *)davinci_spi->tmp_buf; + rx_buf_count = SPI_BUFSIZ; } - temp_count = count + 1; + + t->tx_dma = dma_map_single(&spi->dev, tx_buf, + tx_buf_count, DMA_TO_DEVICE); + t->rx_dma = dma_map_single(&spi->dev, rx_buf, + rx_buf_count, DMA_FROM_DEVICE); + + tx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_tx_channel); + tx_param.src = t->tx_buf ? t->tx_dma : tx_reg; + tx_param.a_b_cnt = davinci_spi->wcount << 16 | data_type; + tx_param.dst = tx_reg; + tx_param.src_dst_bidx = t->tx_buf ? data_type : 0; + tx_param.link_bcntrld = 0xffff; + tx_param.src_dst_cidx = 0; + tx_param.ccnt = 1; + edma_write_slot(davinci_dma->dma_tx_channel, &tx_param); + edma_link(davinci_dma->dma_tx_channel, + davinci_dma->dummy_param_slot); + + rx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_rx_channel); + rx_param.src = rx_reg; + rx_param.a_b_cnt = davinci_spi->rcount << 16 | data_type; + rx_param.dst = t->rx_dma; + rx_param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; + rx_param.link_bcntrld = 0xffff; + rx_param.src_dst_cidx = 0; + rx_param.ccnt = 1; + edma_write_slot(davinci_dma->dma_rx_channel, &rx_param); + + iowrite16(spidat1 >> SPIDAT1_CSNR_SHIFT, + davinci_spi->base + SPIDAT1 + 2); + + edma_start(davinci_dma->dma_rx_channel); + edma_start(davinci_dma->dma_tx_channel); + set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); } - edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, - data_type, temp_count, 1, 0, ASYNC); - edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); - edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT); - edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0); - edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); - - if (t->rx_buf) { - /* initiate transaction */ - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); - - t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, - DMA_FROM_DEVICE); - if (dma_mapping_error(&spi->dev, t->rx_dma)) { - dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", - count); - if (t->tx_buf != NULL) - dma_unmap_single(NULL, t->tx_dma, - count, DMA_TO_DEVICE); - return -ENOMEM; + /* Wait for the transfer to complete */ + if (spi_cfg->io_type != SPI_IO_TYPE_POLL) { + wait_for_completion_interruptible(&(davinci_spi->done)); + } else { + while ((davinci_spi->rcount > 0) && (ret == 0)) { + ret = davinci_spi_process_events(davinci_spi); + cpu_relax(); } - edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, - data_type, count, 1, 0, ASYNC); - edma_set_src(davinci_spi_dma->dma_rx_channel, - rx_reg, INCR, W8BIT); - edma_set_dest(davinci_spi_dma->dma_rx_channel, - t->rx_dma, INCR, W8BIT); - edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); - edma_set_dest_index(davinci_spi_dma->dma_rx_channel, - data_type, 0); } - if ((t->tx_buf) || (t->rx_buf)) - edma_start(davinci_spi_dma->dma_tx_channel); - - if (t->rx_buf) - edma_start(davinci_spi_dma->dma_rx_channel); - - if ((t->rx_buf) || (t->tx_buf)) - davinci_spi_set_dma_req(spi, 1); - - if (t->tx_buf) - wait_for_completion_interruptible( - &davinci_spi_dma->dma_tx_completion); - - if (t->rx_buf) - wait_for_completion_interruptible( - &davinci_spi_dma->dma_rx_completion); - - dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE); - - if (t->rx_buf) - dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); - - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - int_status = ioread32(davinci_spi->base + SPIFLG); + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + dma_unmap_single(NULL, t->tx_dma, tx_buf_count, + DMA_TO_DEVICE); + dma_unmap_single(NULL, t->rx_dma, rx_buf_count, + DMA_FROM_DEVICE); + } - ret = davinci_spi_check_error(davinci_spi, int_status); - if (ret != 0) - return ret; + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - /* SPI Framework maintains the count only in bytes so convert back */ - davinci_spi->count *= conv; + if (davinci_spi->errors) { + ret = davinci_spi_check_error(davinci_spi, davinci_spi->errors); + if (ret != 0) + return ret; + } + if ((davinci_spi->rcount != 0) || (davinci_spi->wcount != 0)) { + sdev = davinci_spi->bitbang.master->dev.parent; + dev_info(sdev, "SPI data transfer error\n"); + return -EIO; + } return t->len; } -/** - * davinci_spi_irq - IRQ handler for DaVinci SPI +/* + * davinci_spi_irq - probe function for SPI Master Controller * @irq: IRQ number for this SPI Master * @context_data: structure for SPI Master controller davinci_spi + * + * ISR will determine that interrupt arrives either for READ or WRITE command. + * According to command it will do the appropriate action. It will check + * transfer length and if it is not zero then dispatch transfer command again. + * If transfer length is zero then it will indicate the COMPLETION so that + * davinci_spi_bufs function can go ahead. */ static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) { struct davinci_spi *davinci_spi = context_data; - u32 int_status, rx_data = 0; - irqreturn_t ret = IRQ_NONE; - - int_status = ioread32(davinci_spi->base + SPIFLG); + int status; - while ((int_status & SPIFLG_RX_INTR_MASK)) { - if (likely(int_status & SPIFLG_RX_INTR_MASK)) { - ret = IRQ_HANDLED; + status = davinci_spi_process_events(davinci_spi); + if (unlikely(status != 0)) + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); - rx_data = ioread32(davinci_spi->base + SPIBUF); - davinci_spi->get_rx(rx_data, davinci_spi); + if ((davinci_spi->rcount == 0) || (status != 0)) + complete(&(davinci_spi->done)); - /* Disable Receive Interrupt */ - iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR), - davinci_spi->base + SPIINT); - } else - (void)davinci_spi_check_error(davinci_spi, int_status); + return IRQ_HANDLED; +} - int_status = ioread32(davinci_spi->base + SPIFLG); +resource_size_t davinci_spi_get_dma_by_flag(struct platform_device *dev, + unsigned long flag) +{ + struct resource *r; + int i; + + for (i = 0; i < dev->num_resources; i++) { + r = platform_get_resource(dev, IORESOURCE_DMA, i); + if (r == NULL) + break; + if ((r->flags & flag) == flag) + return r->start; } - return ret; + return DAVINCI_SPI_NO_RESOURCE; } -/** +/* * davinci_spi_probe - probe function for SPI Master Controller * @pdev: platform_device structure which contains plateform specific data + * + * According to Linux Device Model this function will be invoked by Linux + * with platform_device struct which contains the device specific info. + * This function will map the SPI controller's memory, register IRQ, + * Reset SPI controller and setting its registers to default value. + * It will invoke spi_bitbang_start to create work queue so that client driver + * can register transfer method to work queue. */ static int davinci_spi_probe(struct platform_device *pdev) { @@ -1016,10 +891,11 @@ static int davinci_spi_probe(struct platform_device *pdev) struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; struct resource *r, *mem; - resource_size_t dma_rx_chan = SPI_NO_RESOURCE; - resource_size_t dma_tx_chan = SPI_NO_RESOURCE; - resource_size_t dma_eventq = SPI_NO_RESOURCE; + resource_size_t dma_rx_chan = DAVINCI_SPI_NO_RESOURCE; + resource_size_t dma_tx_chan = DAVINCI_SPI_NO_RESOURCE; + resource_size_t dma_eventq = DAVINCI_SPI_NO_RESOURCE; int i = 0, ret = 0; + u32 spipc0; pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -1073,14 +949,16 @@ static int davinci_spi_probe(struct platform_device *pdev) ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED, dev_name(&pdev->dev), davinci_spi); - if (ret) + if (ret != 0) { + ret = -EAGAIN; goto unmap_io; + } /* Allocate tmp_buf for tx_buf */ davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); if (davinci_spi->tmp_buf == NULL) { ret = -ENOMEM; - goto irq_free; + goto err1; } davinci_spi->bitbang.master = spi_master_get(master); @@ -1104,55 +982,23 @@ static int davinci_spi_probe(struct platform_device *pdev) davinci_spi->bitbang.chipselect = davinci_spi_chipselect; davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; + davinci_spi->bitbang.txrx_bufs = davinci_spi_txrx_bufs; davinci_spi->version = pdata->version; - use_dma = pdata->use_dma; davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; if (davinci_spi->version == SPI_VERSION_2) davinci_spi->bitbang.flags |= SPI_READY; - if (use_dma) { - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (r) - dma_rx_chan = r->start; - r = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (r) - dma_tx_chan = r->start; - r = platform_get_resource(pdev, IORESOURCE_DMA, 2); - if (r) - dma_eventq = r->start; - } - - if (!use_dma || - dma_rx_chan == SPI_NO_RESOURCE || - dma_tx_chan == SPI_NO_RESOURCE || - dma_eventq == SPI_NO_RESOURCE) { - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; - use_dma = 0; - } else { - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; - davinci_spi->dma_channels = kzalloc(master->num_chipselect - * sizeof(struct davinci_spi_dma), GFP_KERNEL); - if (davinci_spi->dma_channels == NULL) { - ret = -ENOMEM; - goto free_clk; - } - - for (i = 0; i < master->num_chipselect; i++) { - davinci_spi->dma_channels[i].dma_rx_channel = -1; - davinci_spi->dma_channels[i].dma_rx_sync_dev = - dma_rx_chan; - davinci_spi->dma_channels[i].dma_tx_channel = -1; - davinci_spi->dma_channels[i].dma_tx_sync_dev = - dma_tx_chan; - davinci_spi->dma_channels[i].eventq = dma_eventq; - } - dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" - "Using RX channel = %d , TX channel = %d and " - "event queue = %d", dma_rx_chan, dma_tx_chan, - dma_eventq); - } + dma_rx_chan = davinci_spi_get_dma_by_flag(pdev, IORESOURCE_DMA_RX_CHAN); + dma_tx_chan = davinci_spi_get_dma_by_flag(pdev, IORESOURCE_DMA_TX_CHAN); + dma_eventq = davinci_spi_get_dma_by_flag(pdev, IORESOURCE_DMA_EVENT_Q); + davinci_spi->dma_channels.dma_rx_channel = -1; + davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan; + davinci_spi->dma_channels.dma_tx_channel = -1; + davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan; + davinci_spi->dma_channels.dummy_param_slot = -1; + davinci_spi->dma_channels.eventq = dma_eventq; davinci_spi->get_rx = davinci_spi_rx_buf_u8; davinci_spi->get_tx = davinci_spi_tx_buf_u8; @@ -1164,32 +1010,29 @@ static int davinci_spi_probe(struct platform_device *pdev) udelay(100); iowrite32(1, davinci_spi->base + SPIGCR0); - /* Clock internal */ - if (davinci_spi->pdata->clk_internal) - set_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_CLKMOD_MASK); - else - clear_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_CLKMOD_MASK); + /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ + spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; + iowrite32(spipc0, davinci_spi->base + SPIPC0); - /* master mode default */ - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + /* initialize chip selects */ + if (pdata->chip_sel != NULL) { + for (i = 0; i < pdata->num_chipselect; i++) { + if (pdata->chip_sel[i] != SPI_INTERN_CS) + gpio_direction_output(pdata->chip_sel[i], 1); + } + } + iowrite32(SPIDEF_CSDEF_MASK, davinci_spi->base + SPIDEF); - if (davinci_spi->pdata->intr_level) - iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); - else - iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); ret = spi_bitbang_start(&davinci_spi->bitbang); - if (ret) + if (ret != 0) goto free_clk; dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base); - if (!pdata->poll_mode) - dev_info(&pdev->dev, "Operating in interrupt mode" - " using IRQ %d\n", davinci_spi->irq); - return ret; free_clk: @@ -1199,7 +1042,7 @@ put_master: spi_master_put(master); free_tmp_buf: kfree(davinci_spi->tmp_buf); -irq_free: +err1: free_irq(davinci_spi->irq, davinci_spi); unmap_io: iounmap(davinci_spi->base); @@ -1211,7 +1054,7 @@ err: return ret; } -/** +/* * davinci_spi_remove - remove function for SPI Master Controller * @pdev: platform_device structure which contains plateform specific data * @@ -1220,7 +1063,7 @@ err: * It will also call spi_bitbang_stop to destroy the work queue which was * created by spi_bitbang_start. */ -static int __exit davinci_spi_remove(struct platform_device *pdev) +static int __devexit davinci_spi_remove(struct platform_device *pdev) { struct davinci_spi *davinci_spi; struct spi_master *master; @@ -1242,8 +1085,11 @@ static int __exit davinci_spi_remove(struct platform_device *pdev) } static struct platform_driver davinci_spi_driver = { - .driver.name = "spi_davinci", - .remove = __exit_p(davinci_spi_remove), + .driver = { + .name = "spi_davinci", + .owner = THIS_MODULE, + }, + .remove = __devexit_p(davinci_spi_remove), }; static int __init davinci_spi_init(void) -- 1.6.3.3 From grant.likely at secretlab.ca Sun Jul 4 00:47:22 2010 From: grant.likely at secretlab.ca (Grant Likely) Date: Sat, 3 Jul 2010 23:47:22 -0600 Subject: [PATCH v2 1/1] davinci: spi: replace existing driver In-Reply-To: <1278110334-13943-2-git-send-email-bniebuhr@efjohnson.com> References: <1278110334-13943-1-git-send-email-bniebuhr@efjohnson.com> <1278110334-13943-2-git-send-email-bniebuhr@efjohnson.com> Message-ID: On Fri, Jul 2, 2010 at 4:38 PM, Brian Niebuhr wrote: > INTRODUCTION > > I have been working on a custom OMAP-L138 board that has multiple spi > devices (seven) on one controller. ?These devices have a wide range of > transfer parameters (speed, phase, polarity, internal and gpio chip > selects). ?During my testing I found multiple errors in the davinci spi > driver as a result of this complex setup. ?The primary issues were: > > 1. There is a race condition due to the SPIBUF read busy-waits for slow > ? ? ? ?devices > 2. I found some DMA transfer length errors under some conditions > 3. The chip select code caused extra byte transfers (with no chip > ? ? ? ?select active) due to writes to SPIDAT1 > 4. Several issues prevented using multiple SPI devices, especially > ? ? ? ?the DMA code, as disucussed previously on the davinci list. > > The fixes to these problems were not simple. ?I ended up making fairly > large changes to the driver, and those changes are contained in these > patches. ?The full list of changes follows. [...] > Signed-off-by: Brian Niebuhr Hi Brian, Thanks for the quick respin. Some more comments below... > --- > ?arch/arm/mach-davinci/board-dm355-evm.c ? ? | ? 10 + > ?arch/arm/mach-davinci/board-dm355-leopard.c | ? 10 + > ?arch/arm/mach-davinci/board-dm365-evm.c ? ? | ? 10 + > ?arch/arm/mach-davinci/dm355.c ? ? ? ? ? ? ? | ? 12 +- > ?arch/arm/mach-davinci/dm365.c ? ? ? ? ? ? ? | ? 12 +- > ?arch/arm/mach-davinci/include/mach/spi.h ? ?| ? 37 +- > ?drivers/spi/davinci_spi.c ? ? ? ? ? ? ? ? ? | 1328 ++++++++++++--------------- > ?7 files changed, 648 insertions(+), 771 deletions(-) > > diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c > index a319101..d2e9f20 100644 > --- a/arch/arm/mach-davinci/board-dm355-evm.c > +++ b/arch/arm/mach-davinci/board-dm355-evm.c > @@ -32,6 +32,7 @@ > ?#include > ?#include > ?#include > +#include > > ?/* NOTE: ?this is geared for the standard config, with a socketed > ?* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. ?If you > @@ -300,10 +301,19 @@ static struct spi_eeprom at25640a = { > ? ? ? ?.flags ? ? ? ? ?= EE_ADDR2, > ?}; > > +static struct davinci_spi_config at25640a_spi_cfg = { > + ? ? ? .parity_enable ?= false, > + ? ? ? .intr_level ? ? = 0, > + ? ? ? .io_type ? ? ? ?= SPI_IO_TYPE_DMA, > + ? ? ? .wdelay ? ? ? ? = 0, > + ? ? ? .timer_disable ?= true, > +}; > + > ?static struct spi_board_info dm355_evm_spi_info[] __initconst = { > ? ? ? ?{ > ? ? ? ? ? ? ? ?.modalias ? ? ? = "at25", > ? ? ? ? ? ? ? ?.platform_data ?= &at25640a, > + ? ? ? ? ? ? ? .controller_data = &at25640a_spi_cfg, > ? ? ? ? ? ? ? ?.max_speed_hz ? = 10 * 1000 * 1000, ? ? /* at 3v3 */ > ? ? ? ? ? ? ? ?.bus_num ? ? ? ?= 0, > ? ? ? ? ? ? ? ?.chip_select ? ?= 0, > diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c > index f1d8132..63078dc 100644 > --- a/arch/arm/mach-davinci/board-dm355-leopard.c > +++ b/arch/arm/mach-davinci/board-dm355-leopard.c > @@ -29,6 +29,7 @@ > ?#include > ?#include > ?#include > +#include > > ?/* NOTE: ?this is geared for the standard config, with a socketed > ?* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. ?If you > @@ -222,10 +223,19 @@ static struct spi_eeprom at25640a = { > ? ? ? ?.flags ? ? ? ? ?= EE_ADDR2, > ?}; > > +static struct davinci_spi_config at25640a_spi_cfg = { > + ? ? ? ?.parity_enable ?= false, > + ? ? ? ?.intr_level ? ? = 0, > + ? ? ? ?.io_type ? ? ? ?= SPI_IO_TYPE_DMA, > + ? ? ? ?.wdelay ? ? ? ? = 0, > + ? ? ? ?.timer_disable ?= true, > +}; > + > ?static struct spi_board_info dm355_leopard_spi_info[] __initconst = { > ? ? ? ?{ > ? ? ? ? ? ? ? ?.modalias ? ? ? = "at25", > ? ? ? ? ? ? ? ?.platform_data ?= &at25640a, > + ? ? ? ? ? ? ? .controller_data = &at25640a_spi_cfg, > ? ? ? ? ? ? ? ?.max_speed_hz ? = 10 * 1000 * 1000, ? ? /* at 3v3 */ > ? ? ? ? ? ? ? ?.bus_num ? ? ? ?= 0, > ? ? ? ? ? ? ? ?.chip_select ? ?= 0, > diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c > index 5bb86b2..5bc3622 100644 > --- a/arch/arm/mach-davinci/board-dm365-evm.c > +++ b/arch/arm/mach-davinci/board-dm365-evm.c > @@ -39,6 +39,7 @@ > ?#include > ?#include > ?#include > +#include > > ?#include > > @@ -579,10 +580,19 @@ static struct spi_eeprom at25640 = { > ? ? ? ?.flags ? ? ? ? ?= EE_ADDR2, > ?}; > > +static struct davinci_spi_config at25640_spi_cfg = { > + ? ? ? ?.parity_enable ?= false, > + ? ? ? ?.intr_level ? ? = 0, > + ? ? ? ?.io_type ? ? ? ?= SPI_IO_TYPE_DMA, > + ? ? ? ?.wdelay ? ? ? ? = 0, > + ? ? ? ?.timer_disable ?= true, > +}; > + > ?static struct spi_board_info dm365_evm_spi_info[] __initconst = { > ? ? ? ?{ > ? ? ? ? ? ? ? ?.modalias ? ? ? = "at25", > ? ? ? ? ? ? ? ?.platform_data ?= &at25640, > + ? ? ? ? ? ? ? .controller_data = &at25640_spi_cfg, > ? ? ? ? ? ? ? ?.max_speed_hz ? = 10 * 1000 * 1000, > ? ? ? ? ? ? ? ?.bus_num ? ? ? ?= 0, > ? ? ? ? ? ? ? ?.chip_select ? ?= 0, > diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c > index 3834781..378d41c 100644 > --- a/arch/arm/mach-davinci/dm355.c > +++ b/arch/arm/mach-davinci/dm355.c > @@ -397,27 +397,21 @@ static struct resource dm355_spi0_resources[] = { > ? ? ? ?}, > ? ? ? ?{ > ? ? ? ? ? ? ? ?.start = 17, > - ? ? ? ? ? ? ? .flags = IORESOURCE_DMA, > + ? ? ? ? ? ? ? .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN, > ? ? ? ?}, > ? ? ? ?{ > ? ? ? ? ? ? ? ?.start = 16, > - ? ? ? ? ? ? ? .flags = IORESOURCE_DMA, > + ? ? ? ? ? ? ? .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN, > ? ? ? ?}, > ? ? ? ?{ > ? ? ? ? ? ? ? ?.start = EVENTQ_1, > - ? ? ? ? ? ? ? .flags = IORESOURCE_DMA, > + ? ? ? ? ? ? ? .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q, > ? ? ? ?}, > ?}; > > ?static struct davinci_spi_platform_data dm355_spi0_pdata = { > ? ? ? ?.version ? ? ? ?= SPI_VERSION_1, > ? ? ? ?.num_chipselect = 2, > - ? ? ? .clk_internal ? = 1, > - ? ? ? .cs_hold ? ? ? ?= 1, > - ? ? ? .intr_level ? ? = 0, > - ? ? ? .poll_mode ? ? ?= 1, ? ?/* 0 -> interrupt mode 1-> polling mode */ > - ? ? ? .c2tdelay ? ? ? = 0, > - ? ? ? .t2cdelay ? ? ? = 0, > ?}; > ?static struct platform_device dm355_spi0_device = { > ? ? ? ?.name = "spi_davinci", > diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c > index 652f4b6..8e68f8c 100644 > --- a/arch/arm/mach-davinci/dm365.c > +++ b/arch/arm/mach-davinci/dm365.c > @@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); > ?static struct davinci_spi_platform_data dm365_spi0_pdata = { > ? ? ? ?.version ? ? ? ?= SPI_VERSION_1, > ? ? ? ?.num_chipselect = 2, > - ? ? ? .clk_internal ? = 1, > - ? ? ? .cs_hold ? ? ? ?= 1, > - ? ? ? .intr_level ? ? = 0, > - ? ? ? .poll_mode ? ? ?= 1, ? ?/* 0 -> interrupt mode 1-> polling mode */ > - ? ? ? .c2tdelay ? ? ? = 0, > - ? ? ? .t2cdelay ? ? ? = 0, > ?}; > > ?static struct resource dm365_spi0_resources[] = { > @@ -645,15 +639,15 @@ static struct resource dm365_spi0_resources[] = { > ? ? ? ?}, > ? ? ? ?{ > ? ? ? ? ? ? ? ?.start = 17, > - ? ? ? ? ? ? ? .flags = IORESOURCE_DMA, > + ? ? ? ? ? ? ? .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN, > ? ? ? ?}, > ? ? ? ?{ > ? ? ? ? ? ? ? ?.start = 16, > - ? ? ? ? ? ? ? .flags = IORESOURCE_DMA, > + ? ? ? ? ? ? ? .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN, > ? ? ? ?}, > ? ? ? ?{ > ? ? ? ? ? ? ? ?.start = EVENTQ_3, > - ? ? ? ? ? ? ? .flags = IORESOURCE_DMA, > + ? ? ? ? ? ? ? .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q, > ? ? ? ?}, > ?}; > > diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h > index 910efbf..b69a2f5 100644 > --- a/arch/arm/mach-davinci/include/mach/spi.h > +++ b/arch/arm/mach-davinci/include/mach/spi.h > @@ -19,6 +19,13 @@ > ?#ifndef __ARCH_ARM_DAVINCI_SPI_H > ?#define __ARCH_ARM_DAVINCI_SPI_H > > +#define SPI_INTERN_CS ?0xFF > + > +/* resource flags for IORESOURCE_DMA resources */ > +#define IORESOURCE_DMA_RX_CHAN ? ? ? ? 0x01 > +#define IORESOURCE_DMA_TX_CHAN ? ? ? ? 0x02 > +#define IORESOURCE_DMA_EVENT_Q ? ? ? ? 0x04 > + Not a good idea. IORESOURCE_* definitions are defined in ioport.h and the lower 8 bits are tagged for bus-specific use (not device-specific). Overloading them with arch-specific meanings is just asking for breakage. If index is unreliable, you can differentiate the resources by .name. > ?enum { > ? ? ? ?SPI_VERSION_1, /* For DM355/DM365/DM6467 */ > ? ? ? ?SPI_VERSION_2, /* For DA8xx */ > @@ -26,19 +33,25 @@ enum { > > ?struct davinci_spi_platform_data { > ? ? ? ?u8 ? ? ?version; > - ? ? ? u8 ? ? ?num_chipselect; > - ? ? ? u8 ? ? ?wdelay; > - ? ? ? u8 ? ? ?odd_parity; > - ? ? ? u8 ? ? ?parity_enable; > - ? ? ? u8 ? ? ?wait_enable; > - ? ? ? u8 ? ? ?timer_disable; > - ? ? ? u8 ? ? ?clk_internal; > - ? ? ? u8 ? ? ?cs_hold; > + ? ? ? u16 ? ? num_chipselect; > + ? ? ? u8 ? ? ?*chip_sel; > +}; > + > +struct davinci_spi_config { > + ? ? ? bool ? ?odd_parity; > + ? ? ? bool ? ?parity_enable; > ? ? ? ?u8 ? ? ?intr_level; > - ? ? ? u8 ? ? ?poll_mode; > - ? ? ? u8 ? ? ?use_dma; > - ? ? ? u8 ? ? ?c2tdelay; > - ? ? ? u8 ? ? ?t2cdelay; > + ? ? ? u8 ? ? ?io_type; > +#define SPI_IO_TYPE_INTR ? ?0 > +#define SPI_IO_TYPE_POLL ? ?1 > +#define SPI_IO_TYPE_DMA ? ? 2 > + ? ? ? u8 ? ? ?bytes_per_word; > + ? ? ? u8 ? ? ?wdelay; > + ? ? ? bool ? ?timer_disable; > + ? ? ? u8 ? ? ?c2t_delay; > + ? ? ? u8 ? ? ?t2c_delay; > + ? ? ? u8 ? ? ?t2e_delay; > + ? ? ? u8 ? ? ?c2e_delay; > ?}; > > ?#endif /* __ARCH_ARM_DAVINCI_SPI_H */ > diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c > index b85090c..10d5c34 100644 > --- a/drivers/spi/davinci_spi.c > +++ b/drivers/spi/davinci_spi.c > @@ -1,5 +1,6 @@ > ?/* > ?* Copyright (C) 2009 Texas Instruments. > + * Copyright (C) 2010 EF Johnson Technologies > ?* > ?* This program is free software; you can redistribute it and/or modify > ?* it under the terms of the GNU General Public License as published by > @@ -27,197 +28,218 @@ > ?#include > ?#include > ?#include > -#include > > ?#include > ?#include > > -#define SPI_NO_RESOURCE ? ? ? ? ? ? ? ?((resource_size_t)-1) > - > -#define SPI_MAX_CHIPSELECT ? ? 2 > - > -#define CS_DEFAULT ? ? 0xFF > - > -#define SPI_BUFSIZ ? ? (SMP_CACHE_BYTES + 1) > -#define DAVINCI_DMA_DATA_TYPE_S8 ? ? ? 0x01 > -#define DAVINCI_DMA_DATA_TYPE_S16 ? ? ?0x02 > -#define DAVINCI_DMA_DATA_TYPE_S32 ? ? ?0x04 > - > -#define SPIFMT_PHASE_MASK ? ? ?BIT(16) > -#define SPIFMT_POLARITY_MASK ? BIT(17) > -#define SPIFMT_DISTIMER_MASK ? BIT(18) > -#define SPIFMT_SHIFTDIR_MASK ? BIT(20) > -#define SPIFMT_WAITENA_MASK ? ?BIT(21) > -#define SPIFMT_PARITYENA_MASK ?BIT(22) > -#define SPIFMT_ODD_PARITY_MASK BIT(23) > -#define SPIFMT_WDELAY_MASK ? ? 0x3f000000u > -#define SPIFMT_WDELAY_SHIFT ? ?24 > -#define SPIFMT_CHARLEN_MASK ? ?0x0000001Fu > +#define CS_DEFAULT ? ? ?0xFF > +#define SCS0_SELECT ? ? 0x01 > +#define SCS1_SELECT ? ? 0x02 > +#define SCS2_SELECT ? ? 0x04 > +#define SCS3_SELECT ? ? 0x08 > +#define SCS4_SELECT ? ? 0x10 > +#define SCS5_SELECT ? ? 0x20 > +#define SCS6_SELECT ? ? 0x40 > +#define SCS7_SELECT ? ? 0x80 > + > +#define SPIFMT_PHASE_MASK ? ? ? BIT(16) > +#define SPIFMT_POLARITY_MASK ? ?BIT(17) > +#define SPIFMT_DISTIMER_MASK ? ?BIT(18) > +#define SPIFMT_SHIFTDIR_MASK ? ?BIT(20) > +#define SPIFMT_WAITENA_MASK ? ? BIT(21) > +#define SPIFMT_PARITYENA_MASK ? BIT(22) > +#define SPIFMT_ODD_PARITY_MASK ?BIT(23) > +#define SPIFMT_WDELAY_MASK ? ? ?0x3f000000u > +#define SPIFMT_WDELAY_SHIFT ? ? 24 > +#define SPIFMT_CHARLEN_MASK ? ? 0x0000001Fu > +#define SPIFMT_PRESCALE_SHIFT ? 8 > > ?/* SPIGCR1 */ > -#define SPIGCR1_SPIENA_MASK ? ?0x01000000u > +#define SPIGCR1_SPIENA_MASK ? ? BIT(24) > +#define SPIGCR1_POWERDOWN_MASK ?BIT(8) > > ?/* SPIPC0 */ > -#define SPIPC0_DIFUN_MASK ? ? ?BIT(11) ? ? ? ? /* MISO */ > -#define SPIPC0_DOFUN_MASK ? ? ?BIT(10) ? ? ? ? /* MOSI */ > -#define SPIPC0_CLKFUN_MASK ? ? BIT(9) ? ? ? ? ?/* CLK */ > -#define SPIPC0_SPIENA_MASK ? ? BIT(8) ? ? ? ? ?/* nREADY */ > -#define SPIPC0_EN1FUN_MASK ? ? BIT(1) > -#define SPIPC0_EN0FUN_MASK ? ? BIT(0) > - > -#define SPIINT_MASKALL ? ? ? ? 0x0101035F > -#define SPI_INTLVL_1 ? ? ? ? ? 0x000001FFu > -#define SPI_INTLVL_0 ? ? ? ? ? 0x00000000u > +#define SPIPC0_DIFUN_MASK ? ? ? BIT(11) ? ? ? ? /* MISO */ > +#define SPIPC0_DOFUN_MASK ? ? ? BIT(10) ? ? ? ? /* MOSI */ > +#define SPIPC0_CLKFUN_MASK ? ? ?BIT(9) ? ? ? ? ?/* CLK */ > +#define SPIPC0_SPIENA_MASK ? ? ?BIT(8) ? ? ? ? ?/* nREADY */ > +#define SPIPC0_EN1FUN_MASK ? ? ?BIT(1) > +#define SPIPC0_EN0FUN_MASK ? ? ?BIT(0) > + > +#define SPIINT_MASKALL ? ? ? ? ?0x0101035Fu > +#define SPIINT_MASKINT ? ? ? ? ?0x0000035Fu > +#define SPI_INTLVL_1 ? ? ? ? ? ?0x000001FFu > +#define SPI_INTLVL_0 ? ? ? ? ? ?0x00000000u > > ?/* SPIDAT1 */ > +#define SPIDAT1_CSHOLD_MASK ? ?BIT(28) > ?#define SPIDAT1_CSHOLD_SHIFT ? 28 > +#define SPIDAT1_WDEL_MASK ? ? ?BIT(26) > +#define SPIDAT1_CSNR_MASK ? ? ?0x00FF0000u > ?#define SPIDAT1_CSNR_SHIFT ? ? 16 > +#define SPIDAT1_DFSEL_MASK ? ? (BIT(24 | BIT(25)) > ?#define SPIGCR1_CLKMOD_MASK ? ?BIT(1) > -#define SPIGCR1_MASTER_MASK ? ? BIT(0) > +#define SPIGCR1_MASTER_MASK ? ?BIT(0) > ?#define SPIGCR1_LOOPBACK_MASK ?BIT(16) > > ?/* SPIBUF */ > -#define SPIBUF_TXFULL_MASK ? ? BIT(29) > -#define SPIBUF_RXEMPTY_MASK ? ?BIT(31) > +#define SPIBUF_TXFULL_MASK ? ? ?BIT(29) > +#define SPIBUF_RXEMPTY_MASK ? ? BIT(31) > + > +/* SPIDELAY */ > +#define SPIDELAY_C2TDELAY_MASK ?0xFF000000u > +#define SPIDELAY_C2TDELAY_SHIFT 24 > +#define SPIDELAY_T2CDELAY_MASK ?0x00FF0000u > +#define SPIDELAY_T2CDELAY_SHIFT 16 > +#define SPIDELAY_T2EDELAY_MASK ?0x0000FF00u > +#define SPIDELAY_T2EDELAY_SHIFT 8 > +#define SPIDELAY_C2EDELAY_MASK ?0x000000FFu > +#define SPIDELAY_C2EDELAY_SHIFT 0 > + > +/* SPIDEF */ > +#define SPIDEF_CSDEF_MASK ? ? ? 0x000000FFu > > ?/* Error Masks */ > -#define SPIFLG_DLEN_ERR_MASK ? ? ? ? ? BIT(0) > -#define SPIFLG_TIMEOUT_MASK ? ? ? ? ? ?BIT(1) > -#define SPIFLG_PARERR_MASK ? ? ? ? ? ? BIT(2) > -#define SPIFLG_DESYNC_MASK ? ? ? ? ? ? BIT(3) > -#define SPIFLG_BITERR_MASK ? ? ? ? ? ? BIT(4) > -#define SPIFLG_OVRRUN_MASK ? ? ? ? ? ? BIT(6) > -#define SPIFLG_RX_INTR_MASK ? ? ? ? ? ?BIT(8) > -#define SPIFLG_TX_INTR_MASK ? ? ? ? ? ?BIT(9) > -#define SPIFLG_BUF_INIT_ACTIVE_MASK ? ?BIT(24) > -#define SPIFLG_MASK ? ? ? ? ? ? ? ? ? ?(SPIFLG_DLEN_ERR_MASK \ > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \ > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | SPIFLG_TX_INTR_MASK \ > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | SPIFLG_BUF_INIT_ACTIVE_MASK) > - > -#define SPIINT_DLEN_ERR_INTR ? BIT(0) > -#define SPIINT_TIMEOUT_INTR ? ?BIT(1) > -#define SPIINT_PARERR_INTR ? ? BIT(2) > -#define SPIINT_DESYNC_INTR ? ? BIT(3) > -#define SPIINT_BITERR_INTR ? ? BIT(4) > -#define SPIINT_OVRRUN_INTR ? ? BIT(6) > -#define SPIINT_RX_INTR ? ? ? ? BIT(8) > -#define SPIINT_TX_INTR ? ? ? ? BIT(9) > -#define SPIINT_DMA_REQ_EN ? ? ?BIT(16) > -#define SPIINT_ENABLE_HIGHZ ? ?BIT(24) > - > -#define SPI_T2CDELAY_SHIFT ? ? 16 > -#define SPI_C2TDELAY_SHIFT ? ? 24 > - > +#define SPIFLG_DLEN_ERR_MASK ? ? ? ? ? ?BIT(0) > +#define SPIFLG_TIMEOUT_MASK ? ? ? ? ? ? BIT(1) > +#define SPIFLG_PARERR_MASK ? ? ? ? ? ? ?BIT(2) > +#define SPIFLG_DESYNC_MASK ? ? ? ? ? ? ?BIT(3) > +#define SPIFLG_BITERR_MASK ? ? ? ? ? ? ?BIT(4) > +#define SPIFLG_OVRRUN_MASK ? ? ? ? ? ? ?BIT(6) > +#define SPIFLG_RX_INTR_MASK ? ? ? ? ? ? BIT(8) > +#define SPIFLG_TX_INTR_MASK ? ? ? ? ? ? BIT(9) > +#define SPIFLG_BUF_INIT_ACTIVE_MASK ? ? BIT(24) > +#define SPIFLG_ERROR_MASK ? ? ? ? ? ? ? (SPIFLG_DLEN_ERR_MASK \ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| SPIFLG_OVRRUN_MASK) > +#define SPIFLG_MASK ? ? ? ? ? ? ? ? ? ? (SPIFLG_ERROR_MASK \ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| SPIFLG_RX_INTR_MASK | SPIFLG_TX_INTR_MASK \ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| SPIFLG_BUF_INIT_ACTIVE_MASK) > + > +#define SPIINT_DLEN_ERR_INTR ? ?BIT(0) > +#define SPIINT_TIMEOUT_INTR ? ? BIT(1) > +#define SPIINT_PARERR_INTR ? ? ?BIT(2) > +#define SPIINT_DESYNC_INTR ? ? ?BIT(3) > +#define SPIINT_BITERR_INTR ? ? ?BIT(4) > +#define SPIINT_OVRRUN_INTR ? ? ?BIT(6) > +#define SPIINT_RX_INTR ? ? ? ? ?BIT(8) > +#define SPIINT_TX_INTR ? ? ? ? ?BIT(9) > +#define SPIINT_DMA_REQ_EN ? ? ? BIT(16) > +#define SPIINT_ENABLE_HIGHZ ? ? BIT(24) > + > +#define SPI_T2CDELAY_SHIFT ? ? ?16 > +#define SPI_C2TDELAY_SHIFT ? ? ?24 > ?/* SPI Controller registers */ > -#define SPIGCR0 ? ? ? ? ? ? ? ?0x00 > -#define SPIGCR1 ? ? ? ? ? ? ? ?0x04 > -#define SPIINT ? ? ? ? 0x08 > -#define SPILVL ? ? ? ? 0x0c > -#define SPIFLG ? ? ? ? 0x10 > -#define SPIPC0 ? ? ? ? 0x14 > -#define SPIPC1 ? ? ? ? 0x18 > -#define SPIPC2 ? ? ? ? 0x1c > -#define SPIPC3 ? ? ? ? 0x20 > -#define SPIPC4 ? ? ? ? 0x24 > -#define SPIPC5 ? ? ? ? 0x28 > -#define SPIPC6 ? ? ? ? 0x2c > -#define SPIPC7 ? ? ? ? 0x30 > -#define SPIPC8 ? ? ? ? 0x34 > -#define SPIDAT0 ? ? ? ? ? ? ? ?0x38 > -#define SPIDAT1 ? ? ? ? ? ? ? ?0x3c > -#define SPIBUF ? ? ? ? 0x40 > -#define SPIEMU ? ? ? ? 0x44 > -#define SPIDELAY ? ? ? 0x48 > -#define SPIDEF ? ? ? ? 0x4c > -#define SPIFMT0 ? ? ? ? ? ? ? ?0x50 > -#define SPIFMT1 ? ? ? ? ? ? ? ?0x54 > -#define SPIFMT2 ? ? ? ? ? ? ? ?0x58 > -#define SPIFMT3 ? ? ? ? ? ? ? ?0x5c > -#define TGINTVEC0 ? ? ?0x60 > -#define TGINTVEC1 ? ? ?0x64 > - > -struct davinci_spi_slave { > - ? ? ? u32 ? ? cmd_to_write; > - ? ? ? u32 ? ? clk_ctrl_to_write; > - ? ? ? u32 ? ? bytes_per_word; > - ? ? ? u8 ? ? ?active_cs; > +#define SPIGCR0 ? ? ? ? 0x00 > +#define SPIGCR1 ? ? ? ? 0x04 > +#define SPIINT ? ? ? ? ?0x08 > +#define SPILVL ? ? ? ? ?0x0c > +#define SPIFLG ? ? ? ? ?0x10 > +#define SPIPC0 ? ? ? ? ?0x14 > +#define SPIPC1 ? ? ? ? ?0x18 > +#define SPIPC2 ? ? ? ? ?0x1c > +#define SPIPC3 ? ? ? ? ?0x20 > +#define SPIPC4 ? ? ? ? ?0x24 > +#define SPIPC5 ? ? ? ? ?0x28 > +#define SPIPC6 ? ? ? ? ?0x2c > +#define SPIPC7 ? ? ? ? ?0x30 > +#define SPIPC8 ? ? ? ? ?0x34 > +#define SPIDAT0 ? ? ? ? 0x38 > +#define SPIDAT1 ? ? ? ? 0x3c > +#define SPIBUF ? ? ? ? ?0x40 > +#define SPIEMU ? ? ? ? ?0x44 > +#define SPIDELAY ? ? ? ?0x48 > +#define SPIDEF ? ? ? ? ?0x4c > +#define SPIFMT0 ? ? ? ? 0x50 > +#define SPIFMT1 ? ? ? ? 0x54 > +#define SPIFMT2 ? ? ? ? 0x58 > +#define SPIFMT3 ? ? ? ? 0x5c > +#define TGINTVEC0 ? ? ? 0x60 > +#define TGINTVEC1 ? ? ? 0x64 > + > +#define SPI_BUFSIZ ? ? ?(SMP_CACHE_BYTES + 1) > + > +const char * const io_type_names[] = { > + ? ? ? [SPI_IO_TYPE_INTR] = "Interrupt", > + ? ? ? [SPI_IO_TYPE_POLL] = "Polled", > + ? ? ? [SPI_IO_TYPE_DMA] = "DMA", > ?}; > > ?/* We have 2 DMA channels per CS, one for RX and one for TX */ > ?struct davinci_spi_dma { > - ? ? ? int ? ? ? ? ? ? ? ? ? ? dma_tx_channel; > - ? ? ? int ? ? ? ? ? ? ? ? ? ? dma_rx_channel; > - ? ? ? int ? ? ? ? ? ? ? ? ? ? dma_tx_sync_dev; > - ? ? ? int ? ? ? ? ? ? ? ? ? ? dma_rx_sync_dev; > - ? ? ? enum dma_event_q ? ? ? ?eventq; > - > - ? ? ? struct completion ? ? ? dma_tx_completion; > - ? ? ? struct completion ? ? ? dma_rx_completion; > + ? ? ? ?int ? ? ? ? ? ? ? ? ? ? dma_tx_channel; > + ? ? ? ?int ? ? ? ? ? ? ? ? ? ? dma_rx_channel; > + ? ? ? ?int ? ? ? ? ? ? ? ? ? ? dma_tx_sync_dev; > + ? ? ? ?int ? ? ? ? ? ? ? ? ? ? dma_rx_sync_dev; > + ? ? ? ?int ? ? ? ? ? ? ? ? ? ? dummy_param_slot; > + ? ? ? ?enum dma_event_q ? ? ? ?eventq; > ?}; > > ?/* SPI Controller driver's private data. */ > ?struct davinci_spi { > - ? ? ? struct spi_bitbang ? ? ?bitbang; > - ? ? ? struct clk ? ? ? ? ? ? ?*clk; > - > - ? ? ? u8 ? ? ? ? ? ? ? ? ? ? ?version; > - ? ? ? resource_size_t ? ? ? ? pbase; > - ? ? ? void __iomem ? ? ? ? ? ?*base; > - ? ? ? size_t ? ? ? ? ? ? ? ? ?region_size; > - ? ? ? u32 ? ? ? ? ? ? ? ? ? ? irq; > - ? ? ? struct completion ? ? ? done; > - > - ? ? ? const void ? ? ? ? ? ? ?*tx; > - ? ? ? void ? ? ? ? ? ? ? ? ? ?*rx; > - ? ? ? u8 ? ? ? ? ? ? ? ? ? ? ?*tmp_buf; > - ? ? ? int ? ? ? ? ? ? ? ? ? ? count; > - ? ? ? struct davinci_spi_dma ?*dma_channels; > - ? ? ? struct ? ? ? ? ? ? ? ? ?davinci_spi_platform_data *pdata; > - > - ? ? ? void ? ? ? ? ? ? ? ? ? ?(*get_rx)(u32 rx_data, struct davinci_spi *); > - ? ? ? u32 ? ? ? ? ? ? ? ? ? ? (*get_tx)(struct davinci_spi *); > - > - ? ? ? struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT]; > + ? ? ? ?struct spi_bitbang ? ? ?bitbang; > + ? ? ? ?struct clk ? ? ? ? ? ? ?*clk; > + > + ? ? ? ?u8 ? ? ? ? ? ? ? ? ? ? ?version; > + ? ? ? ?resource_size_t ? ? ? ? pbase; > + ? ? ? ?void __iomem ? ? ? ? ? ?*base; > + ? ? ? ?size_t ? ? ? ? ? ? ? ? ?region_size; > + ? ? ? ?u32 ? ? ? ? ? ? ? ? ? ? irq; > + ? ? ? ?struct completion ? ? ? done; > + > + ? ? ? ?const void ? ? ? ? ? ? ?*tx; > + ? ? ? ?void ? ? ? ? ? ? ? ? ? ?*rx; > + ? ? ? ?u8 ? ? ? ? ? ? ? ? ? ? ?*tmp_buf; > + ? ? ? ?int ? ? ? ? ? ? ? ? ? ? rcount; > + ? ? ? ?int ? ? ? ? ? ? ? ? ? ? wcount; > + ? ? ? ?u32 ? ? ? ? ? ? ? ? ? ? errors; > + ? ? ? ?struct davinci_spi_dma ?dma_channels; > + ? ? ? ?struct davinci_spi_platform_data *pdata; > + > + ? ? ? ?void ? ? ? ? ? ? ? ? ? ?(*get_rx)(u32 rx_data, struct davinci_spi *); > + ? ? ? ?u32 ? ? ? ? ? ? ? ? ? ? (*get_tx)(struct davinci_spi *); > ?}; > > -static unsigned use_dma; > +#define ? ? ? ?DAVINCI_SPI_NO_RESOURCE ? ? ? ? ((resource_size_t)-1) > > ?static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) > ?{ > - ? ? ? u8 *rx = davinci_spi->rx; > - > - ? ? ? *rx++ = (u8)data; > - ? ? ? davinci_spi->rx = rx; > + ? ? ? if (davinci_spi->rx) { > + ? ? ? ? ? ? ? u8 *rx = davinci_spi->rx; > + ? ? ? ? ? ? ? *rx++ = (u8)data; > + ? ? ? ? ? ? ? davinci_spi->rx = rx; > + ? ? ? } > ?} > > ?static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) > ?{ > - ? ? ? u16 *rx = davinci_spi->rx; > - > - ? ? ? *rx++ = (u16)data; > - ? ? ? davinci_spi->rx = rx; > + ? ? ? if (davinci_spi->rx) { > + ? ? ? ? ? ? ? u16 *rx = davinci_spi->rx; > + ? ? ? ? ? ? ? *rx++ = (u16)data; > + ? ? ? ? ? ? ? davinci_spi->rx = rx; > + ? ? ? } > ?} > > ?static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) > ?{ > - ? ? ? u32 data; > - ? ? ? const u8 *tx = davinci_spi->tx; > - > - ? ? ? data = *tx++; > - ? ? ? davinci_spi->tx = tx; > + ? ? ? u32 data = 0; > + ? ? ? if (davinci_spi->tx) { > + ? ? ? ? ? ? ? const u8 *tx = davinci_spi->tx; > + ? ? ? ? ? ? ? data = *tx++; > + ? ? ? ? ? ? ? davinci_spi->tx = tx; > + ? ? ? } > ? ? ? ?return data; > ?} > > ?static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) > ?{ > - ? ? ? u32 data; > - ? ? ? const u16 *tx = davinci_spi->tx; > - > - ? ? ? data = *tx++; > - ? ? ? davinci_spi->tx = tx; > + ? ? ? u32 data = 0; > + ? ? ? if (davinci_spi->tx) { > + ? ? ? ? ? ? ? const u16 *tx = davinci_spi->tx; > + ? ? ? ? ? ? ? data = *tx++; > + ? ? ? ? ? ? ? davinci_spi->tx = tx; > + ? ? ? } > ? ? ? ?return data; > ?} > > @@ -237,26 +259,6 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits) > ? ? ? ?iowrite32(v, addr); > ?} > > -static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num) > -{ > - ? ? ? set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); > -} > - > -static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num) > -{ > - ? ? ? clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); > -} > - > -static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) > -{ > - ? ? ? struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); > - > - ? ? ? if (enable) > - ? ? ? ? ? ? ? set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); > - ? ? ? else > - ? ? ? ? ? ? ? clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); > -} > - > ?/* > ?* Interface to control the chip select signal > ?*/ > @@ -264,28 +266,57 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) > ?{ > ? ? ? ?struct davinci_spi *davinci_spi; > ? ? ? ?struct davinci_spi_platform_data *pdata; > - ? ? ? u32 data1_reg_val = 0; > + ? ? ? u8 i, chip_sel = spi->chip_select; > + ? ? ? u32 spidat1; > + ? ? ? u16 spidat1_cfg; > > ? ? ? ?davinci_spi = spi_master_get_devdata(spi->master); > ? ? ? ?pdata = davinci_spi->pdata; > > - ? ? ? /* > - ? ? ? ?* Board specific chip select logic decides the polarity and cs > - ? ? ? ?* line for the controller > - ? ? ? ?*/ > - ? ? ? if (value == BITBANG_CS_INACTIVE) { > - ? ? ? ? ? ? ? set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT); > - > - ? ? ? ? ? ? ? data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT; > - ? ? ? ? ? ? ? iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); > + ? ? ? spidat1 = SPIDAT1_CSNR_MASK; > + ? ? ? if (value == BITBANG_CS_ACTIVE) > + ? ? ? ? ? ? ? spidat1 |= SPIDAT1_CSHOLD_MASK; > + ? ? ? else > + ? ? ? ? ? ? ? spidat1 |= SPIDAT1_WDEL_MASK; > > - ? ? ? ? ? ? ? while ((ioread32(davinci_spi->base + SPIBUF) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIBUF_RXEMPTY_MASK) == 0) > - ? ? ? ? ? ? ? ? ? ? ? cpu_relax(); > + ? ? ? if (pdata->chip_sel == NULL) { > + ? ? ? ? ? ? ? if (value == BITBANG_CS_ACTIVE) > + ? ? ? ? ? ? ? ? ? ? ? spidat1 &= ~((0x1 << chip_sel) << SPIDAT1_CSNR_SHIFT); > + ? ? ? } else { > + ? ? ? ? ? ? ? for (i = 0; i < pdata->num_chipselect; i++) { > + ? ? ? ? ? ? ? ? ? ? ? if (pdata->chip_sel[i] == SPI_INTERN_CS) { > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? if ((i == chip_sel) && > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (value == BITBANG_CS_ACTIVE)) { > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spidat1 &= ~((0x1 << chip_sel) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? << SPIDAT1_CSNR_SHIFT); > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? } > + ? ? ? ? ? ? ? ? ? ? ? } else { > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? if (value == BITBANG_CS_INACTIVE) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? gpio_set_value(pdata->chip_sel[i], 1); > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? else if (i == chip_sel) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? gpio_set_value(pdata->chip_sel[i], 0); > + ? ? ? ? ? ? ? ? ? ? ? } > + ? ? ? ? ? ? ? } > ? ? ? ?} > + > + ? ? ? spidat1_cfg = spidat1 >> SPIDAT1_CSNR_SHIFT; > + ? ? ? iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); > +} > + > +/* > + * davinci_spi_get_prescale - Calculates the correct prescale value > + * @max_speed_hz: the maximum rate the SPI clock can run at > + * > + * This function calculates the prescale value that generates a clock rate > + * less than or equal to the specified maximum > + */ > +static inline u32 davinci_spi_get_prescale(struct davinci_spi *davinci_spi, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? u32 max_speed_hz) > +{ > + ? ? ? return ((clk_get_rate(davinci_spi->clk) - 1) / max_speed_hz) & 0xff; > ?} > > -/** > +/* > ?* davinci_spi_setup_transfer - This functions will determine transfer method > ?* @spi: spi device on which data transfer to be done > ?* @t: spi transfer in which transfer info is filled > @@ -297,14 +328,15 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) > ?static int davinci_spi_setup_transfer(struct spi_device *spi, > ? ? ? ? ? ? ? ?struct spi_transfer *t) > ?{ > - > ? ? ? ?struct davinci_spi *davinci_spi; > ? ? ? ?struct davinci_spi_platform_data *pdata; > + ? ? ? struct davinci_spi_config *spi_cfg; > ? ? ? ?u8 bits_per_word = 0; > - ? ? ? u32 hz = 0, prescale = 0, clkspeed; > + ? ? ? u32 hz = 0, spifmt = 0, prescale, delay = 0; > > ? ? ? ?davinci_spi = spi_master_get_devdata(spi->master); > ? ? ? ?pdata = davinci_spi->pdata; > + ? ? ? spi_cfg = spi->controller_data; > > ? ? ? ?if (t) { > ? ? ? ? ? ? ? ?bits_per_word = t->bits_per_word; > @@ -322,76 +354,112 @@ static int davinci_spi_setup_transfer(struct spi_device *spi, > ? ? ? ?if (bits_per_word <= 8 && bits_per_word >= 2) { > ? ? ? ? ? ? ? ?davinci_spi->get_rx = davinci_spi_rx_buf_u8; > ? ? ? ? ? ? ? ?davinci_spi->get_tx = davinci_spi_tx_buf_u8; > - ? ? ? ? ? ? ? davinci_spi->slave[spi->chip_select].bytes_per_word = 1; > + ? ? ? ? ? ? ? spi_cfg->bytes_per_word = 1; > ? ? ? ?} else if (bits_per_word <= 16 && bits_per_word >= 2) { > ? ? ? ? ? ? ? ?davinci_spi->get_rx = davinci_spi_rx_buf_u16; > ? ? ? ? ? ? ? ?davinci_spi->get_tx = davinci_spi_tx_buf_u16; > - ? ? ? ? ? ? ? davinci_spi->slave[spi->chip_select].bytes_per_word = 2; > + ? ? ? ? ? ? ? spi_cfg->bytes_per_word = 2; > ? ? ? ?} else > ? ? ? ? ? ? ? ?return -EINVAL; > > ? ? ? ?if (!hz) > ? ? ? ? ? ? ? ?hz = spi->max_speed_hz; > > - ? ? ? clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK, > - ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - ? ? ? set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f, > - ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > + ? ? ? prescale = davinci_spi_get_prescale(davinci_spi, hz); > + ? ? ? spifmt |= (prescale << SPIFMT_PRESCALE_SHIFT); > + > + ? ? ? spifmt |= (bits_per_word & 0x1f); > + > + ? ? ? if (spi->mode & SPI_LSB_FIRST) > + ? ? ? ? ? ? ? spifmt |= SPIFMT_SHIFTDIR_MASK; > > - ? ? ? clkspeed = clk_get_rate(davinci_spi->clk); > - ? ? ? if (hz > clkspeed / 2) > - ? ? ? ? ? ? ? prescale = 1 << 8; > - ? ? ? if (hz < clkspeed / 256) > - ? ? ? ? ? ? ? prescale = 255 << 8; > - ? ? ? if (!prescale) > - ? ? ? ? ? ? ? prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00; > + ? ? ? if (spi->mode & SPI_CPOL) > + ? ? ? ? ? ? ? spifmt |= SPIFMT_POLARITY_MASK; > > - ? ? ? clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select); > - ? ? ? set_fmt_bits(davinci_spi->base, prescale, spi->chip_select); > + ? ? ? if (!(spi->mode & SPI_CPHA)) > + ? ? ? ? ? ? ? spifmt |= SPIFMT_PHASE_MASK; > + > + ? ? ? if (davinci_spi->version == SPI_VERSION_2) { > + ? ? ? ? ? ? ? spifmt |= ((spi_cfg->wdelay << SPIFMT_WDELAY_SHIFT) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIFMT_WDELAY_MASK); > + > + ? ? ? ? ? ? ? if (spi_cfg->odd_parity) > + ? ? ? ? ? ? ? ? ? ? ? spifmt |= SPIFMT_ODD_PARITY_MASK; > + > + ? ? ? ? ? ? ? if (spi_cfg->parity_enable) > + ? ? ? ? ? ? ? ? ? ? ? spifmt |= SPIFMT_PARITYENA_MASK; > + > + ? ? ? ? ? ? ? if (spi->mode & SPI_READY) { > + ? ? ? ? ? ? ? ? ? ? ? spifmt |= SPIFMT_WAITENA_MASK; > + ? ? ? ? ? ? ? ? ? ? ? delay |= (spi_cfg->t2e_delay > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? << SPIDELAY_T2EDELAY_SHIFT) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIDELAY_T2EDELAY_MASK; > + ? ? ? ? ? ? ? ? ? ? ? delay |= (spi_cfg->c2e_delay > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? << SPIDELAY_C2EDELAY_SHIFT) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIDELAY_C2EDELAY_MASK; > + ? ? ? ? ? ? ? } > + > + ? ? ? ? ? ? ? if (spi_cfg->timer_disable) { > + ? ? ? ? ? ? ? ? ? ? ? spifmt |= SPIFMT_DISTIMER_MASK; > + ? ? ? ? ? ? ? } else { > + ? ? ? ? ? ? ? ? ? ? ? delay |= (spi_cfg->c2t_delay > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? << SPIDELAY_C2TDELAY_SHIFT) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIDELAY_C2TDELAY_MASK; > + ? ? ? ? ? ? ? ? ? ? ? delay |= (spi_cfg->t2c_delay > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? << SPIDELAY_T2CDELAY_SHIFT) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIDELAY_T2CDELAY_MASK; > + ? ? ? ? ? ? ? } > + > + ? ? ? ? ? ? ? iowrite32(delay, davinci_spi->base + SPIDELAY); > + ? ? ? } > + > + ? ? ? iowrite32(spifmt, davinci_spi->base + SPIFMT0); > + > + ? ? ? if (spi_cfg->intr_level) > + ? ? ? ? ? ? ? iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); > + ? ? ? else > + ? ? ? ? ? ? ? iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); > + > + ? ? ? if (spi->mode & SPI_LOOP) > + ? ? ? ? ? ? ? set_io_bits(davinci_spi->base + SPIGCR1, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIGCR1_LOOPBACK_MASK); > + ? ? ? else > + ? ? ? ? ? ? ? clear_io_bits(davinci_spi->base + SPIGCR1, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIGCR1_LOOPBACK_MASK); > > ? ? ? ?return 0; > ?} > > ?static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) > ?{ > - ? ? ? struct spi_device *spi = (struct spi_device *)data; > - ? ? ? struct davinci_spi *davinci_spi; > + ? ? ? struct davinci_spi *davinci_spi = (struct davinci_spi *)data; > ? ? ? ?struct davinci_spi_dma *davinci_spi_dma; > ? ? ? ?struct davinci_spi_platform_data *pdata; > > - ? ? ? davinci_spi = spi_master_get_devdata(spi->master); > - ? ? ? davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); > + ? ? ? davinci_spi_dma = &(davinci_spi->dma_channels); > ? ? ? ?pdata = davinci_spi->pdata; > > + ? ? ? edma_stop(davinci_spi_dma->dma_rx_channel); > + > ? ? ? ?if (ch_status == DMA_COMPLETE) > - ? ? ? ? ? ? ? edma_stop(davinci_spi_dma->dma_rx_channel); > - ? ? ? else > - ? ? ? ? ? ? ? edma_clean_channel(davinci_spi_dma->dma_rx_channel); > + ? ? ? ? ? ? ? davinci_spi->rcount = 0; > > - ? ? ? complete(&davinci_spi_dma->dma_rx_completion); > - ? ? ? /* We must disable the DMA RX request */ > - ? ? ? davinci_spi_set_dma_req(spi, 0); > + ? ? ? complete(&davinci_spi->done); > ?} > > ?static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) > ?{ > - ? ? ? struct spi_device *spi = (struct spi_device *)data; > - ? ? ? struct davinci_spi *davinci_spi; > + ? ? ? struct davinci_spi *davinci_spi = (struct davinci_spi *)data; > ? ? ? ?struct davinci_spi_dma *davinci_spi_dma; > ? ? ? ?struct davinci_spi_platform_data *pdata; > > - ? ? ? davinci_spi = spi_master_get_devdata(spi->master); > - ? ? ? davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); > + ? ? ? davinci_spi_dma = &(davinci_spi->dma_channels); > ? ? ? ?pdata = davinci_spi->pdata; > > - ? ? ? if (ch_status == DMA_COMPLETE) > - ? ? ? ? ? ? ? edma_stop(davinci_spi_dma->dma_tx_channel); > - ? ? ? else > - ? ? ? ? ? ? ? edma_clean_channel(davinci_spi_dma->dma_tx_channel); > + ? ? ? edma_stop(davinci_spi_dma->dma_tx_channel); > > - ? ? ? complete(&davinci_spi_dma->dma_tx_completion); > - ? ? ? /* We must disable the DMA TX request */ > - ? ? ? davinci_spi_set_dma_req(spi, 0); > + ? ? ? if (ch_status == DMA_COMPLETE) > + ? ? ? ? ? ? ? davinci_spi->wcount = 0; > ?} > > ?static int davinci_spi_request_dma(struct spi_device *spi) > @@ -403,33 +471,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) > ? ? ? ?int r; > > ? ? ? ?davinci_spi = spi_master_get_devdata(spi->master); > - ? ? ? davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > + ? ? ? davinci_spi_dma = &davinci_spi->dma_channels; > ? ? ? ?pdata = davinci_spi->pdata; > ? ? ? ?sdev = davinci_spi->bitbang.master->dev.parent; > > ? ? ? ?r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? davinci_spi_dma_rx_callback, spi, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? davinci_spi_dma_rx_callback, davinci_spi, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?davinci_spi_dma->eventq); > ? ? ? ?if (r < 0) { > - ? ? ? ? ? ? ? dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); > - ? ? ? ? ? ? ? return -EAGAIN; > + ? ? ? ? ? ? ? dev_dbg(sdev, "Unable to request DMA channel for MibSPI RX\n"); > + ? ? ? ? ? ? ? r = ?-EAGAIN; > + ? ? ? ? ? ? ? goto rx_dma_failed; > ? ? ? ?} > ? ? ? ?davinci_spi_dma->dma_rx_channel = r; > + > ? ? ? ?r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? davinci_spi_dma_tx_callback, spi, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? davinci_spi_dma_tx_callback, davinci_spi, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?davinci_spi_dma->eventq); > ? ? ? ?if (r < 0) { > - ? ? ? ? ? ? ? edma_free_channel(davinci_spi_dma->dma_rx_channel); > - ? ? ? ? ? ? ? davinci_spi_dma->dma_rx_channel = -1; > - ? ? ? ? ? ? ? dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); > - ? ? ? ? ? ? ? return -EAGAIN; > + ? ? ? ? ? ? ? dev_dbg(sdev, "Unable to request DMA channel for MibSPI TX\n"); > + ? ? ? ? ? ? ? r = -EAGAIN; > + ? ? ? ? ? ? ? goto tx_dma_failed; > ? ? ? ?} > ? ? ? ?davinci_spi_dma->dma_tx_channel = r; > > + ? ? ? r = edma_alloc_slot(EDMA_CTLR(davinci_spi_dma->dma_tx_sync_dev), > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? EDMA_SLOT_ANY); > + ? ? ? if (r < 0) { > + ? ? ? ? ? ? ? dev_dbg(sdev, "Unable to request SPI DMA param slot\n"); > + ? ? ? ? ? ? ? r = -EAGAIN; > + ? ? ? ? ? ? ? goto param_failed; > + ? ? ? } > + ? ? ? davinci_spi_dma->dummy_param_slot = r; > + ? ? ? edma_link(davinci_spi_dma->dummy_param_slot, > + ? ? ? ? ? ? ? ? davinci_spi_dma->dummy_param_slot); > + > ? ? ? ?return 0; > + > +param_failed: > + ? ? ? edma_free_channel(davinci_spi_dma->dma_tx_channel); > + ? ? ? davinci_spi_dma->dma_tx_channel = -1; > +tx_dma_failed: > + ? ? ? edma_free_channel(davinci_spi_dma->dma_rx_channel); > + ? ? ? davinci_spi_dma->dma_rx_channel = -1; > +rx_dma_failed: > + ? ? ? return r; > ?} > > -/** > +/* > ?* davinci_spi_setup - This functions will set default transfer method > ?* @spi: spi device on which data transfer to be done > ?* > @@ -438,129 +527,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) > > ?static int davinci_spi_setup(struct spi_device *spi) > ?{ > - ? ? ? int retval; > + ? ? ? int retval = 0; > ? ? ? ?struct davinci_spi *davinci_spi; > - ? ? ? struct davinci_spi_dma *davinci_spi_dma; > - ? ? ? struct device *sdev; > + ? ? ? struct davinci_spi_dma *davinci_dma; > + ? ? ? struct davinci_spi_platform_data *pdata; > + ? ? ? struct davinci_spi_config *spi_cfg; > + ? ? ? u32 prescale; > > ? ? ? ?davinci_spi = spi_master_get_devdata(spi->master); > - ? ? ? sdev = davinci_spi->bitbang.master->dev.parent; > + ? ? ? pdata = davinci_spi->pdata; > + ? ? ? spi_cfg = (struct davinci_spi_config *)spi->controller_data; > + ? ? ? davinci_dma = &(davinci_spi->dma_channels); > > ? ? ? ?/* if bits per word length is zero then set it default 8 */ > ? ? ? ?if (!spi->bits_per_word) > ? ? ? ? ? ? ? ?spi->bits_per_word = 8; > > - ? ? ? davinci_spi->slave[spi->chip_select].cmd_to_write = 0; > - > - ? ? ? if (use_dma && davinci_spi->dma_channels) { > - ? ? ? ? ? ? ? davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > - > - ? ? ? ? ? ? ? if ((davinci_spi_dma->dma_rx_channel == -1) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? || (davinci_spi_dma->dma_tx_channel == -1)) { > - ? ? ? ? ? ? ? ? ? ? ? retval = davinci_spi_request_dma(spi); > - ? ? ? ? ? ? ? ? ? ? ? if (retval < 0) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? return retval; > - ? ? ? ? ? ? ? } > - ? ? ? } > + ? ? ? if (!(spi->mode & SPI_NO_CS)) { > + ? ? ? ? ? ? ? if ((pdata->chip_sel == NULL) || > + ? ? ? ? ? ? ? ? ? (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) > + ? ? ? ? ? ? ? ? ? ? ? set_io_bits(davinci_spi->base + SPIPC0, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 << spi->chip_select); > > - ? ? ? /* > - ? ? ? ?* SPI in DaVinci and DA8xx operate between > - ? ? ? ?* 600 KHz and 50 MHz > - ? ? ? ?*/ > - ? ? ? if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) { > - ? ? ? ? ? ? ? dev_dbg(sdev, "Operating frequency is not in acceptable " > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "range\n"); > - ? ? ? ? ? ? ? return -EINVAL; > ? ? ? ?} > > - ? ? ? /* > - ? ? ? ?* Set up SPIFMTn register, unique to this chipselect. > - ? ? ? ?* > - ? ? ? ?* NOTE: we could do all of these with one write. ?Also, some > - ? ? ? ?* of the "version 2" features are found in chips that don't > - ? ? ? ?* support all of them... > - ? ? ? ?*/ > - ? ? ? if (spi->mode & SPI_LSB_FIRST) > - ? ? ? ? ? ? ? set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - ? ? ? else > - ? ? ? ? ? ? ? clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > + ? ? ? if (spi->mode & SPI_READY) > + ? ? ? ? ? ? ? set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); > > - ? ? ? if (spi->mode & SPI_CPOL) > - ? ? ? ? ? ? ? set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - ? ? ? else > - ? ? ? ? ? ? ? clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > + ? ? ? if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { > + ? ? ? ? ? ? ? davinci_dma = &(davinci_spi->dma_channels); > > - ? ? ? if (!(spi->mode & SPI_CPHA)) > - ? ? ? ? ? ? ? set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - ? ? ? else > - ? ? ? ? ? ? ? clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > + ? ? ? ? ? ? ? if ((davinci_dma->dma_tx_sync_dev == DAVINCI_SPI_NO_RESOURCE) || > + ? ? ? ? ? ? ? ? ? (davinci_dma->dma_rx_sync_dev == DAVINCI_SPI_NO_RESOURCE) || > + ? ? ? ? ? ? ? ? ? (davinci_dma->eventq == DAVINCI_SPI_NO_RESOURCE)) > + ? ? ? ? ? ? ? ? ? ? ? spi_cfg->io_type = SPI_IO_TYPE_INTR; > + ? ? ? ? ? ? ? else if ((davinci_dma->dma_rx_channel == -1) || > + ? ? ? ? ? ? ? ? ? ? ? ?(davinci_dma->dma_tx_channel == -1)) > + ? ? ? ? ? ? ? ? ? ? ? retval = davinci_spi_request_dma(spi); > + ? ? ? } > > ? ? ? ?/* > - ? ? ? ?* Version 1 hardware supports two basic SPI modes: > - ? ? ? ?* ?- Standard SPI mode uses 4 pins, with chipselect > - ? ? ? ?* ?- 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) > - ? ? ? ?* ? ? ?(distinct from SPI_3WIRE, with just one data wire; > - ? ? ? ?* ? ? ?or similar variants without MOSI or without MISO) > - ? ? ? ?* > - ? ? ? ?* Version 2 hardware supports an optional handshaking signal, > - ? ? ? ?* so it can support two more modes: > - ? ? ? ?* ?- 5 pin SPI variant is standard SPI plus SPI_READY > - ? ? ? ?* ?- 4 pin with enable is (SPI_READY | SPI_NO_CS) > + ? ? ? ?* Validate desired clock rate > ? ? ? ? */ > + ? ? ? prescale = davinci_spi_get_prescale(davinci_spi, spi->max_speed_hz); > + ? ? ? if ((prescale < 2) || (prescale > 255)) > + ? ? ? ? ? ? ? return -EINVAL; > > - ? ? ? if (davinci_spi->version == SPI_VERSION_2) { > - ? ? ? ? ? ? ? clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - ? ? ? ? ? ? ? set_fmt_bits(davinci_spi->base, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (davinci_spi->pdata->wdelay > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? << SPIFMT_WDELAY_SHIFT) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIFMT_WDELAY_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - > - ? ? ? ? ? ? ? if (davinci_spi->pdata->odd_parity) > - ? ? ? ? ? ? ? ? ? ? ? set_fmt_bits(davinci_spi->base, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIFMT_ODD_PARITY_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - ? ? ? ? ? ? ? else > - ? ? ? ? ? ? ? ? ? ? ? clear_fmt_bits(davinci_spi->base, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIFMT_ODD_PARITY_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - > - ? ? ? ? ? ? ? if (davinci_spi->pdata->parity_enable) > - ? ? ? ? ? ? ? ? ? ? ? set_fmt_bits(davinci_spi->base, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIFMT_PARITYENA_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - ? ? ? ? ? ? ? else > - ? ? ? ? ? ? ? ? ? ? ? clear_fmt_bits(davinci_spi->base, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIFMT_PARITYENA_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - > - ? ? ? ? ? ? ? if (davinci_spi->pdata->wait_enable) > - ? ? ? ? ? ? ? ? ? ? ? set_fmt_bits(davinci_spi->base, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIFMT_WAITENA_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - ? ? ? ? ? ? ? else > - ? ? ? ? ? ? ? ? ? ? ? clear_fmt_bits(davinci_spi->base, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIFMT_WAITENA_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - > - ? ? ? ? ? ? ? if (davinci_spi->pdata->timer_disable) > - ? ? ? ? ? ? ? ? ? ? ? set_fmt_bits(davinci_spi->base, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIFMT_DISTIMER_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - ? ? ? ? ? ? ? else > - ? ? ? ? ? ? ? ? ? ? ? clear_fmt_bits(davinci_spi->base, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIFMT_DISTIMER_MASK, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi->chip_select); > - ? ? ? } > - > - ? ? ? retval = davinci_spi_setup_transfer(spi, NULL); > + ? ? ? dev_info(&spi->dev, "DaVinci SPI driver in %s mode\n", > + ? ? ? ? ? ? ? ? ? ? ? io_type_names[spi_cfg->io_type]); > > ? ? ? ?return retval; > ?} > @@ -569,50 +583,19 @@ static void davinci_spi_cleanup(struct spi_device *spi) > ?{ > ? ? ? ?struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); > ? ? ? ?struct davinci_spi_dma *davinci_spi_dma; > + ? ? ? struct davinci_spi_platform_data *pdata; > > - ? ? ? davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > - > - ? ? ? if (use_dma && davinci_spi->dma_channels) { > - ? ? ? ? ? ? ? davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > - > - ? ? ? ? ? ? ? if ((davinci_spi_dma->dma_rx_channel != -1) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? && (davinci_spi_dma->dma_tx_channel != -1)) { > - ? ? ? ? ? ? ? ? ? ? ? edma_free_channel(davinci_spi_dma->dma_tx_channel); > - ? ? ? ? ? ? ? ? ? ? ? edma_free_channel(davinci_spi_dma->dma_rx_channel); > - ? ? ? ? ? ? ? } > - ? ? ? } > -} > - > -static int davinci_spi_bufs_prep(struct spi_device *spi, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct davinci_spi *davinci_spi) > -{ > - ? ? ? int op_mode = 0; > - > - ? ? ? /* > - ? ? ? ?* REVISIT ?unless devices disagree about SPI_LOOP or > - ? ? ? ?* SPI_READY (SPI_NO_CS only allows one device!), this > - ? ? ? ?* should not need to be done before each message... > - ? ? ? ?* optimize for both flags staying cleared. > - ? ? ? ?*/ > - > - ? ? ? op_mode = SPIPC0_DIFUN_MASK > - ? ? ? ? ? ? ? | SPIPC0_DOFUN_MASK > - ? ? ? ? ? ? ? | SPIPC0_CLKFUN_MASK; > - ? ? ? if (!(spi->mode & SPI_NO_CS)) > - ? ? ? ? ? ? ? op_mode |= 1 << spi->chip_select; > - ? ? ? if (spi->mode & SPI_READY) > - ? ? ? ? ? ? ? op_mode |= SPIPC0_SPIENA_MASK; > + ? ? ? davinci_spi_dma = &davinci_spi->dma_channels; > + ? ? ? pdata = davinci_spi->pdata; > > - ? ? ? iowrite32(op_mode, davinci_spi->base + SPIPC0); > + ? ? ? if (davinci_spi_dma->dma_rx_channel != -1) > + ? ? ? ? ? ? ? edma_free_channel(davinci_spi_dma->dma_rx_channel); > > - ? ? ? if (spi->mode & SPI_LOOP) > - ? ? ? ? ? ? ? set_io_bits(davinci_spi->base + SPIGCR1, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIGCR1_LOOPBACK_MASK); > - ? ? ? else > - ? ? ? ? ? ? ? clear_io_bits(davinci_spi->base + SPIGCR1, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIGCR1_LOOPBACK_MASK); > + ? ? ? if (davinci_spi_dma->dma_tx_channel != -1) > + ? ? ? ? ? ? ? edma_free_channel(davinci_spi_dma->dma_tx_channel); > > - ? ? ? return 0; > + ? ? ? if (davinci_spi_dma->dummy_param_slot != -1) > + ? ? ? ? ? ? ? edma_free_slot(davinci_spi_dma->dummy_param_slot); > ?} > > ?static int davinci_spi_check_error(struct davinci_spi *davinci_spi, > @@ -659,356 +642,248 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi, > ? ? ? ?return 0; > ?} > > -/** > - * davinci_spi_bufs - functions which will handle transfer data > - * @spi: spi device on which data transfer to be done > - * @t: spi transfer in which transfer info is filled > +/* > + * davinci_spi_process_events - check for and handle any SPI controller events > + * @davinci_spi - the controller data > ?* > - * This function will put data to be transferred into data register > - * of SPI controller and then wait until the completion will be marked > - * by the IRQ Handler. > + * This function will check the SPIFLG register and handle any events that are > + * detected there > ?*/ > -static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) > +static int davinci_spi_process_events(struct davinci_spi *davinci_spi) > ?{ > - ? ? ? struct davinci_spi *davinci_spi; > - ? ? ? int int_status, count, ret; > - ? ? ? u8 conv, tmp; > - ? ? ? u32 tx_data, data1_reg_val; > - ? ? ? u32 buf_val, flg_val; > - ? ? ? struct davinci_spi_platform_data *pdata; > - > - ? ? ? davinci_spi = spi_master_get_devdata(spi->master); > - ? ? ? pdata = davinci_spi->pdata; > - > - ? ? ? davinci_spi->tx = t->tx_buf; > - ? ? ? davinci_spi->rx = t->rx_buf; > - > - ? ? ? /* convert len to words based on bits_per_word */ > - ? ? ? conv = davinci_spi->slave[spi->chip_select].bytes_per_word; > - ? ? ? davinci_spi->count = t->len / conv; > - > - ? ? ? INIT_COMPLETION(davinci_spi->done); > - > - ? ? ? ret = davinci_spi_bufs_prep(spi, davinci_spi); > - ? ? ? if (ret) > - ? ? ? ? ? ? ? return ret; > - > - ? ? ? /* Enable SPI */ > - ? ? ? set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); > - > - ? ? ? iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | > - ? ? ? ? ? ? ? ? ? ? ? (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), > - ? ? ? ? ? ? ? ? ? ? ? davinci_spi->base + SPIDELAY); > - > - ? ? ? count = davinci_spi->count; > - ? ? ? data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; > - ? ? ? tmp = ~(0x1 << spi->chip_select); > - > - ? ? ? clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); > - > - ? ? ? data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; > - > - ? ? ? while ((ioread32(davinci_spi->base + SPIBUF) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIBUF_RXEMPTY_MASK) == 0) > - ? ? ? ? ? ? ? cpu_relax(); > - > - ? ? ? /* Determine the command to execute READ or WRITE */ > - ? ? ? if (t->tx_buf) { > - ? ? ? ? ? ? ? clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); > - > - ? ? ? ? ? ? ? while (1) { > - ? ? ? ? ? ? ? ? ? ? ? tx_data = davinci_spi->get_tx(davinci_spi); > - > - ? ? ? ? ? ? ? ? ? ? ? data1_reg_val &= ~(0xFFFF); > - ? ? ? ? ? ? ? ? ? ? ? data1_reg_val |= (0xFFFF & tx_data); > - > - ? ? ? ? ? ? ? ? ? ? ? buf_val = ioread32(davinci_spi->base + SPIBUF); > - ? ? ? ? ? ? ? ? ? ? ? if ((buf_val & SPIBUF_TXFULL_MASK) == 0) { > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? iowrite32(data1_reg_val, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? davinci_spi->base + SPIDAT1); > - > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? count--; > - ? ? ? ? ? ? ? ? ? ? ? } > - ? ? ? ? ? ? ? ? ? ? ? while (ioread32(davinci_spi->base + SPIBUF) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIBUF_RXEMPTY_MASK) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cpu_relax(); > - > - ? ? ? ? ? ? ? ? ? ? ? /* getting the returned byte */ > - ? ? ? ? ? ? ? ? ? ? ? if (t->rx_buf) { > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? buf_val = ioread32(davinci_spi->base + SPIBUF); > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? davinci_spi->get_rx(buf_val, davinci_spi); > - ? ? ? ? ? ? ? ? ? ? ? } > - ? ? ? ? ? ? ? ? ? ? ? if (count <= 0) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? break; > - ? ? ? ? ? ? ? } > - ? ? ? } else { > - ? ? ? ? ? ? ? if (pdata->poll_mode) { > - ? ? ? ? ? ? ? ? ? ? ? while (1) { > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* keeps the serial clock going */ > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? if ((ioread32(davinci_spi->base + SPIBUF) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIBUF_TXFULL_MASK) == 0) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? iowrite32(data1_reg_val, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? davinci_spi->base + SPIDAT1); > - > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? while (ioread32(davinci_spi->base + SPIBUF) & > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIBUF_RXEMPTY_MASK) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cpu_relax(); > - > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? flg_val = ioread32(davinci_spi->base + SPIFLG); > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? buf_val = ioread32(davinci_spi->base + SPIBUF); > - > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? davinci_spi->get_rx(buf_val, davinci_spi); > - > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? count--; > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? if (count <= 0) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? break; > - ? ? ? ? ? ? ? ? ? ? ? } > - ? ? ? ? ? ? ? } else { ? ? ? ?/* Receive in Interrupt mode */ > - ? ? ? ? ? ? ? ? ? ? ? int i; > - > - ? ? ? ? ? ? ? ? ? ? ? for (i = 0; i < davinci_spi->count; i++) { > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? set_io_bits(davinci_spi->base + SPIINT, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIINT_BITERR_INTR > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | SPIINT_OVRRUN_INTR > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | SPIINT_RX_INTR); > - > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? iowrite32(data1_reg_val, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? davinci_spi->base + SPIDAT1); > - > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? while (ioread32(davinci_spi->base + SPIINT) & > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIINT_RX_INTR) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cpu_relax(); > - ? ? ? ? ? ? ? ? ? ? ? } > - ? ? ? ? ? ? ? ? ? ? ? iowrite32((data1_reg_val & 0x0ffcffff), > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? davinci_spi->base + SPIDAT1); > - ? ? ? ? ? ? ? } > + ? ? ? u32 status, tx_data, rx_data, spidat1; > + ? ? ? u8 tx_word = 0; > + > + ? ? ? status = ioread32(davinci_spi->base + SPIFLG); > + > + ? ? ? if ((davinci_spi->version == SPI_VERSION_2) && > + ? ? ? ? ? (likely(status & SPIFLG_TX_INTR_MASK)) && > + ? ? ? ? ? (likely(davinci_spi->wcount > 0))) > + ? ? ? ? ? ? ? tx_word = 1; > + > + ? ? ? if (likely(status & SPIFLG_RX_INTR_MASK)) { > + ? ? ? ? ? ? ? rx_data = ioread32(davinci_spi->base + SPIBUF) & 0xFFFF; > + ? ? ? ? ? ? ? davinci_spi->get_rx(rx_data, davinci_spi); > + ? ? ? ? ? ? ? davinci_spi->rcount--; > + ? ? ? ? ? ? ? if ((davinci_spi->version != SPI_VERSION_2) && > + ? ? ? ? ? ? ? ? ? (likely(davinci_spi->wcount > 0))) > + ? ? ? ? ? ? ? ? ? ? ? tx_word = 1; > ? ? ? ?} > > - ? ? ? /* > - ? ? ? ?* Check for bit error, desync error,parity error,timeout error and > - ? ? ? ?* receive overflow errors > - ? ? ? ?*/ > - ? ? ? int_status = ioread32(davinci_spi->base + SPIFLG); > - > - ? ? ? ret = davinci_spi_check_error(davinci_spi, int_status); > - ? ? ? if (ret != 0) > - ? ? ? ? ? ? ? return ret; > + ? ? ? if (unlikely(status & SPIFLG_ERROR_MASK)) { > + ? ? ? ? ? ? ? davinci_spi->errors = (status & SPIFLG_ERROR_MASK); > + ? ? ? ? ? ? ? return -1; > + ? ? ? } > > - ? ? ? /* SPI Framework maintains the count only in bytes so convert back */ > - ? ? ? davinci_spi->count *= conv; > + ? ? ? if (likely(tx_word)) { > + ? ? ? ? ? ? ? spidat1 = ioread32(davinci_spi->base + SPIDAT1); > + ? ? ? ? ? ? ? davinci_spi->wcount--; > + ? ? ? ? ? ? ? tx_data = davinci_spi->get_tx(davinci_spi); > + ? ? ? ? ? ? ? spidat1 &= 0xFFFF0000; > + ? ? ? ? ? ? ? spidat1 |= (tx_data & 0xFFFF); > + ? ? ? ? ? ? ? iowrite32(spidat1, davinci_spi->base + SPIDAT1); > + ? ? ? } > > - ? ? ? return t->len; > + ? ? ? return 0; > ?} > > -#define DAVINCI_DMA_DATA_TYPE_S8 ? ? ? 0x01 > -#define DAVINCI_DMA_DATA_TYPE_S16 ? ? ?0x02 > -#define DAVINCI_DMA_DATA_TYPE_S32 ? ? ?0x04 > - > -static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) > +/* > + * davinci_spi_txrx_bufs - function which will handle transfer data > + * @spi: spi device on which data transfer to be done > + * @t: spi transfer in which transfer info is filled > + * > + * This function will put data to be transferred into data register > + * of SPI controller and then wait until the completion will be marked > + * by the IRQ Handler. > + */ > +static int davinci_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) > ?{ > ? ? ? ?struct davinci_spi *davinci_spi; > - ? ? ? int int_status = 0; > - ? ? ? int count, temp_count; > - ? ? ? u8 conv = 1; > - ? ? ? u8 tmp; > - ? ? ? u32 data1_reg_val; > - ? ? ? struct davinci_spi_dma *davinci_spi_dma; > - ? ? ? int word_len, data_type, ret; > - ? ? ? unsigned long tx_reg, rx_reg; > + ? ? ? int data_type, ret = 0; > + ? ? ? u32 tx_data, spidat1; > + ? ? ? u16 tx_buf_count = 0, rx_buf_count = 0; > + ? ? ? struct davinci_spi_config *spi_cfg; > ? ? ? ?struct davinci_spi_platform_data *pdata; > + ? ? ? struct davinci_spi_dma *davinci_dma; > ? ? ? ?struct device *sdev; > + ? ? ? dma_addr_t tx_reg, rx_reg; > + ? ? ? void *tx_buf, *rx_buf; > + ? ? ? struct edmacc_param rx_param, tx_param; > > ? ? ? ?davinci_spi = spi_master_get_devdata(spi->master); > ? ? ? ?pdata = davinci_spi->pdata; > - ? ? ? sdev = davinci_spi->bitbang.master->dev.parent; > - > - ? ? ? davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > - > - ? ? ? tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; > - ? ? ? rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; > + ? ? ? spi_cfg = (struct davinci_spi_config *)spi->controller_data; > + ? ? ? davinci_dma = &(davinci_spi->dma_channels); > > ? ? ? ?davinci_spi->tx = t->tx_buf; > ? ? ? ?davinci_spi->rx = t->rx_buf; > + ? ? ? davinci_spi->wcount = t->len / spi_cfg->bytes_per_word; > + ? ? ? davinci_spi->rcount = davinci_spi->wcount; > + ? ? ? davinci_spi->errors = 0; > > - ? ? ? /* convert len to words based on bits_per_word */ > - ? ? ? conv = davinci_spi->slave[spi->chip_select].bytes_per_word; > - ? ? ? davinci_spi->count = t->len / conv; > - > - ? ? ? INIT_COMPLETION(davinci_spi->done); > + ? ? ? spidat1 = ioread32(davinci_spi->base + SPIDAT1); > > - ? ? ? init_completion(&davinci_spi_dma->dma_rx_completion); > - ? ? ? init_completion(&davinci_spi_dma->dma_tx_completion); > - > - ? ? ? word_len = conv * 8; > - > - ? ? ? if (word_len <= 8) > - ? ? ? ? ? ? ? data_type = DAVINCI_DMA_DATA_TYPE_S8; > - ? ? ? else if (word_len <= 16) > - ? ? ? ? ? ? ? data_type = DAVINCI_DMA_DATA_TYPE_S16; > - ? ? ? else if (word_len <= 32) > - ? ? ? ? ? ? ? data_type = DAVINCI_DMA_DATA_TYPE_S32; > - ? ? ? else > - ? ? ? ? ? ? ? return -EINVAL; > - > - ? ? ? ret = davinci_spi_bufs_prep(spi, davinci_spi); > - ? ? ? if (ret) > - ? ? ? ? ? ? ? return ret; > - > - ? ? ? /* Put delay val if required */ > - ? ? ? iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | > - ? ? ? ? ? ? ? ? ? ? ? (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), > - ? ? ? ? ? ? ? ? ? ? ? davinci_spi->base + SPIDELAY); > - > - ? ? ? count = davinci_spi->count; ? ? /* the number of elements */ > - ? ? ? data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; > - > - ? ? ? /* CS default = 0xFF */ > - ? ? ? tmp = ~(0x1 << spi->chip_select); > - > - ? ? ? clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); > - > - ? ? ? data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; > - > - ? ? ? /* disable all interrupts for dma transfers */ > - ? ? ? clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); > - ? ? ? /* Disable SPI to write configuration bits in SPIDAT */ > - ? ? ? clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); > - ? ? ? iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); > - ? ? ? /* Enable SPI */ > + ? ? ? clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); > ? ? ? ?set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); > > - ? ? ? while ((ioread32(davinci_spi->base + SPIBUF) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIBUF_RXEMPTY_MASK) == 0) > - ? ? ? ? ? ? ? cpu_relax(); > - > + ? ? ? INIT_COMPLETION(davinci_spi->done); > > - ? ? ? if (t->tx_buf) { > - ? ? ? ? ? ? ? t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DMA_TO_DEVICE); > - ? ? ? ? ? ? ? if (dma_mapping_error(&spi->dev, t->tx_dma)) { > - ? ? ? ? ? ? ? ? ? ? ? dev_dbg(sdev, "Unable to DMA map a %d bytes" > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? " TX buffer\n", count); > - ? ? ? ? ? ? ? ? ? ? ? return -ENOMEM; > + ? ? ? if ((spi_cfg->io_type == SPI_IO_TYPE_INTR) || > + ? ? ? ? ? (spi_cfg->io_type == SPI_IO_TYPE_POLL)) { > + > + ? ? ? ? ? ? ? if (spi_cfg->io_type == SPI_IO_TYPE_INTR) > + ? ? ? ? ? ? ? ? ? ? ? set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); > + > + ? ? ? ? ? ? ? /* start the transfer */ > + ? ? ? ? ? ? ? davinci_spi->wcount--; > + ? ? ? ? ? ? ? tx_data = davinci_spi->get_tx(davinci_spi); > + ? ? ? ? ? ? ? spidat1 &= 0xFFFF0000; > + ? ? ? ? ? ? ? spidat1 |= (tx_data & 0xFFFF); > + ? ? ? ? ? ? ? iowrite32(spidat1, davinci_spi->base + SPIDAT1); > + > + ? ? ? } else if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { > + ? ? ? ? ? ? ? data_type = spi_cfg->bytes_per_word; > + ? ? ? ? ? ? ? tx_reg = (dma_addr_t)davinci_spi->pbase + SPIDAT1; > + ? ? ? ? ? ? ? rx_reg = (dma_addr_t)davinci_spi->pbase + SPIBUF; > + > + ? ? ? ? ? ? ? if (t->tx_buf) { > + ? ? ? ? ? ? ? ? ? ? ? tx_buf = ((void *)t->tx_buf); > + ? ? ? ? ? ? ? ? ? ? ? tx_buf_count = davinci_spi->wcount; > + ? ? ? ? ? ? ? } else { > + ? ? ? ? ? ? ? ? ? ? ? tx_buf = (void *)davinci_spi->tmp_buf; > + ? ? ? ? ? ? ? ? ? ? ? tx_buf_count = SPI_BUFSIZ; > ? ? ? ? ? ? ? ?} > - ? ? ? ? ? ? ? temp_count = count; > - ? ? ? } else { > - ? ? ? ? ? ? ? /* We need TX clocking for RX transaction */ > - ? ? ? ? ? ? ? t->tx_dma = dma_map_single(&spi->dev, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (void *)davinci_spi->tmp_buf, count + 1, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DMA_TO_DEVICE); > - ? ? ? ? ? ? ? if (dma_mapping_error(&spi->dev, t->tx_dma)) { > - ? ? ? ? ? ? ? ? ? ? ? dev_dbg(sdev, "Unable to DMA map a %d bytes" > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? " TX tmp buffer\n", count); > - ? ? ? ? ? ? ? ? ? ? ? return -ENOMEM; > + ? ? ? ? ? ? ? if (t->rx_buf) { > + ? ? ? ? ? ? ? ? ? ? ? rx_buf = (void *)t->rx_buf; > + ? ? ? ? ? ? ? ? ? ? ? rx_buf_count = davinci_spi->rcount; > + ? ? ? ? ? ? ? } else { > + ? ? ? ? ? ? ? ? ? ? ? rx_buf = (void *)davinci_spi->tmp_buf; > + ? ? ? ? ? ? ? ? ? ? ? rx_buf_count = SPI_BUFSIZ; > ? ? ? ? ? ? ? ?} > - ? ? ? ? ? ? ? temp_count = count + 1; > + > + ? ? ? ? ? ? ? t->tx_dma = dma_map_single(&spi->dev, tx_buf, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tx_buf_count, DMA_TO_DEVICE); > + ? ? ? ? ? ? ? t->rx_dma = dma_map_single(&spi->dev, rx_buf, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rx_buf_count, DMA_FROM_DEVICE); > + > + ? ? ? ? ? ? ? tx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_tx_channel); > + ? ? ? ? ? ? ? tx_param.src = t->tx_buf ? t->tx_dma : tx_reg; > + ? ? ? ? ? ? ? tx_param.a_b_cnt = davinci_spi->wcount << 16 | data_type; > + ? ? ? ? ? ? ? tx_param.dst = tx_reg; > + ? ? ? ? ? ? ? tx_param.src_dst_bidx = t->tx_buf ? data_type : 0; > + ? ? ? ? ? ? ? tx_param.link_bcntrld = 0xffff; > + ? ? ? ? ? ? ? tx_param.src_dst_cidx = 0; > + ? ? ? ? ? ? ? tx_param.ccnt = 1; > + ? ? ? ? ? ? ? edma_write_slot(davinci_dma->dma_tx_channel, &tx_param); > + ? ? ? ? ? ? ? edma_link(davinci_dma->dma_tx_channel, > + ? ? ? ? ? ? ? ? ? ? ? ? davinci_dma->dummy_param_slot); > + > + ? ? ? ? ? ? ? rx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_rx_channel); > + ? ? ? ? ? ? ? rx_param.src = rx_reg; > + ? ? ? ? ? ? ? rx_param.a_b_cnt = davinci_spi->rcount << 16 | data_type; > + ? ? ? ? ? ? ? rx_param.dst = t->rx_dma; > + ? ? ? ? ? ? ? rx_param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; > + ? ? ? ? ? ? ? rx_param.link_bcntrld = 0xffff; > + ? ? ? ? ? ? ? rx_param.src_dst_cidx = 0; > + ? ? ? ? ? ? ? rx_param.ccnt = 1; > + ? ? ? ? ? ? ? edma_write_slot(davinci_dma->dma_rx_channel, &rx_param); > + > + ? ? ? ? ? ? ? iowrite16(spidat1 >> SPIDAT1_CSNR_SHIFT, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? davinci_spi->base + SPIDAT1 + 2); > + > + ? ? ? ? ? ? ? edma_start(davinci_dma->dma_rx_channel); > + ? ? ? ? ? ? ? edma_start(davinci_dma->dma_tx_channel); > + ? ? ? ? ? ? ? set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); > ? ? ? ?} > > - ? ? ? edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data_type, temp_count, 1, 0, ASYNC); > - ? ? ? edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); > - ? ? ? edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT); > - ? ? ? edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0); > - ? ? ? edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); > - > - ? ? ? if (t->rx_buf) { > - ? ? ? ? ? ? ? /* initiate transaction */ > - ? ? ? ? ? ? ? iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); > - > - ? ? ? ? ? ? ? t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DMA_FROM_DEVICE); > - ? ? ? ? ? ? ? if (dma_mapping_error(&spi->dev, t->rx_dma)) { > - ? ? ? ? ? ? ? ? ? ? ? dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? count); > - ? ? ? ? ? ? ? ? ? ? ? if (t->tx_buf != NULL) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dma_unmap_single(NULL, t->tx_dma, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?count, DMA_TO_DEVICE); > - ? ? ? ? ? ? ? ? ? ? ? return -ENOMEM; > + ? ? ? /* Wait for the transfer to complete */ > + ? ? ? if (spi_cfg->io_type != SPI_IO_TYPE_POLL) { > + ? ? ? ? ? ? ? wait_for_completion_interruptible(&(davinci_spi->done)); > + ? ? ? } else { > + ? ? ? ? ? ? ? while ((davinci_spi->rcount > 0) && (ret == 0)) { > + ? ? ? ? ? ? ? ? ? ? ? ret = davinci_spi_process_events(davinci_spi); > + ? ? ? ? ? ? ? ? ? ? ? cpu_relax(); > ? ? ? ? ? ? ? ?} > - ? ? ? ? ? ? ? edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data_type, count, 1, 0, ASYNC); > - ? ? ? ? ? ? ? edma_set_src(davinci_spi_dma->dma_rx_channel, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rx_reg, INCR, W8BIT); > - ? ? ? ? ? ? ? edma_set_dest(davinci_spi_dma->dma_rx_channel, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t->rx_dma, INCR, W8BIT); > - ? ? ? ? ? ? ? edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); > - ? ? ? ? ? ? ? edma_set_dest_index(davinci_spi_dma->dma_rx_channel, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data_type, 0); > ? ? ? ?} > > - ? ? ? if ((t->tx_buf) || (t->rx_buf)) > - ? ? ? ? ? ? ? edma_start(davinci_spi_dma->dma_tx_channel); > - > - ? ? ? if (t->rx_buf) > - ? ? ? ? ? ? ? edma_start(davinci_spi_dma->dma_rx_channel); > - > - ? ? ? if ((t->rx_buf) || (t->tx_buf)) > - ? ? ? ? ? ? ? davinci_spi_set_dma_req(spi, 1); > - > - ? ? ? if (t->tx_buf) > - ? ? ? ? ? ? ? wait_for_completion_interruptible( > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &davinci_spi_dma->dma_tx_completion); > - > - ? ? ? if (t->rx_buf) > - ? ? ? ? ? ? ? wait_for_completion_interruptible( > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &davinci_spi_dma->dma_rx_completion); > - > - ? ? ? dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE); > - > - ? ? ? if (t->rx_buf) > - ? ? ? ? ? ? ? dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); > - > - ? ? ? /* > - ? ? ? ?* Check for bit error, desync error,parity error,timeout error and > - ? ? ? ?* receive overflow errors > - ? ? ? ?*/ > - ? ? ? int_status = ioread32(davinci_spi->base + SPIFLG); > + ? ? ? clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); > + ? ? ? if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { > + ? ? ? ? ? ? ? dma_unmap_single(NULL, t->tx_dma, tx_buf_count, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DMA_TO_DEVICE); > + ? ? ? ? ? ? ? dma_unmap_single(NULL, t->rx_dma, rx_buf_count, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DMA_FROM_DEVICE); > + ? ? ? } > > - ? ? ? ret = davinci_spi_check_error(davinci_spi, int_status); > - ? ? ? if (ret != 0) > - ? ? ? ? ? ? ? return ret; > + ? ? ? clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); > + ? ? ? set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); > > - ? ? ? /* SPI Framework maintains the count only in bytes so convert back */ > - ? ? ? davinci_spi->count *= conv; > + ? ? ? if (davinci_spi->errors) { > + ? ? ? ? ? ? ? ret = davinci_spi_check_error(davinci_spi, davinci_spi->errors); > + ? ? ? ? ? ? ? if (ret != 0) > + ? ? ? ? ? ? ? ? ? ? ? return ret; > + ? ? ? } > + ? ? ? if ((davinci_spi->rcount != 0) || (davinci_spi->wcount != 0)) { > + ? ? ? ? ? ? ? sdev = davinci_spi->bitbang.master->dev.parent; > + ? ? ? ? ? ? ? dev_info(sdev, "SPI data transfer error\n"); > + ? ? ? ? ? ? ? return -EIO; > + ? ? ? } > > ? ? ? ?return t->len; > ?} > > -/** > - * davinci_spi_irq - IRQ handler for DaVinci SPI > +/* > + * davinci_spi_irq - probe function for SPI Master Controller > ?* @irq: IRQ number for this SPI Master > ?* @context_data: structure for SPI Master controller davinci_spi > + * > + * ISR will determine that interrupt arrives either for READ or WRITE command. > + * According to command it will do the appropriate action. It will check > + * transfer length and if it is not zero then dispatch transfer command again. > + * If transfer length is zero then it will indicate the COMPLETION so that > + * davinci_spi_bufs function can go ahead. > ?*/ > ?static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) > ?{ > ? ? ? ?struct davinci_spi *davinci_spi = context_data; > - ? ? ? u32 int_status, rx_data = 0; > - ? ? ? irqreturn_t ret = IRQ_NONE; > - > - ? ? ? int_status = ioread32(davinci_spi->base + SPIFLG); > + ? ? ? int status; > > - ? ? ? while ((int_status & SPIFLG_RX_INTR_MASK)) { > - ? ? ? ? ? ? ? if (likely(int_status & SPIFLG_RX_INTR_MASK)) { > - ? ? ? ? ? ? ? ? ? ? ? ret = IRQ_HANDLED; > + ? ? ? status = davinci_spi_process_events(davinci_spi); > + ? ? ? if (unlikely(status != 0)) > + ? ? ? ? ? ? ? clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); > > - ? ? ? ? ? ? ? ? ? ? ? rx_data = ioread32(davinci_spi->base + SPIBUF); > - ? ? ? ? ? ? ? ? ? ? ? davinci_spi->get_rx(rx_data, davinci_spi); > + ? ? ? if ((davinci_spi->rcount == 0) || (status != 0)) > + ? ? ? ? ? ? ? complete(&(davinci_spi->done)); > > - ? ? ? ? ? ? ? ? ? ? ? /* Disable Receive Interrupt */ > - ? ? ? ? ? ? ? ? ? ? ? iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR), > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? davinci_spi->base + SPIINT); > - ? ? ? ? ? ? ? } else > - ? ? ? ? ? ? ? ? ? ? ? (void)davinci_spi_check_error(davinci_spi, int_status); > + ? ? ? return IRQ_HANDLED; > +} > > - ? ? ? ? ? ? ? int_status = ioread32(davinci_spi->base + SPIFLG); > +resource_size_t davinci_spi_get_dma_by_flag(struct platform_device *dev, > + ? ? ? ? ? ? ? unsigned long flag) > +{ > + ? ? ? struct resource *r; > + ? ? ? int i; > + > + ? ? ? for (i = 0; i < dev->num_resources; i++) { > + ? ? ? ? ? ? ? r = platform_get_resource(dev, IORESOURCE_DMA, i); > + ? ? ? ? ? ? ? if (r == NULL) > + ? ? ? ? ? ? ? ? ? ? ? break; > + ? ? ? ? ? ? ? if ((r->flags & flag) == flag) > + ? ? ? ? ? ? ? ? ? ? ? return r->start; > ? ? ? ?} > > - ? ? ? return ret; > + ? ? ? return DAVINCI_SPI_NO_RESOURCE; > ?} > > -/** > +/* > ?* davinci_spi_probe - probe function for SPI Master Controller > ?* @pdev: platform_device structure which contains plateform specific data > + * > + * According to Linux Device Model this function will be invoked by Linux > + * with platform_device struct which contains the device specific info. > + * This function will map the SPI controller's memory, register IRQ, > + * Reset SPI controller and setting its registers to default value. > + * It will invoke spi_bitbang_start to create work queue so that client driver > + * can register transfer method to work queue. > ?*/ > ?static int davinci_spi_probe(struct platform_device *pdev) > ?{ > @@ -1016,10 +891,11 @@ static int davinci_spi_probe(struct platform_device *pdev) > ? ? ? ?struct davinci_spi *davinci_spi; > ? ? ? ?struct davinci_spi_platform_data *pdata; > ? ? ? ?struct resource *r, *mem; > - ? ? ? resource_size_t dma_rx_chan = SPI_NO_RESOURCE; > - ? ? ? resource_size_t dma_tx_chan = SPI_NO_RESOURCE; > - ? ? ? resource_size_t dma_eventq = SPI_NO_RESOURCE; > + ? ? ? resource_size_t dma_rx_chan = DAVINCI_SPI_NO_RESOURCE; > + ? ? ? resource_size_t dma_tx_chan = DAVINCI_SPI_NO_RESOURCE; > + ? ? ? resource_size_t dma_eventq = DAVINCI_SPI_NO_RESOURCE; > ? ? ? ?int i = 0, ret = 0; > + ? ? ? u32 spipc0; > > ? ? ? ?pdata = pdev->dev.platform_data; > ? ? ? ?if (pdata == NULL) { > @@ -1073,14 +949,16 @@ static int davinci_spi_probe(struct platform_device *pdev) > > ? ? ? ?ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED, > ? ? ? ? ? ? ? ? ? ? ? ? ?dev_name(&pdev->dev), davinci_spi); > - ? ? ? if (ret) > + ? ? ? if (ret != 0) { > + ? ? ? ? ? ? ? ret = -EAGAIN; > ? ? ? ? ? ? ? ?goto unmap_io; > + ? ? ? } > > ? ? ? ?/* Allocate tmp_buf for tx_buf */ > ? ? ? ?davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); > ? ? ? ?if (davinci_spi->tmp_buf == NULL) { > ? ? ? ? ? ? ? ?ret = -ENOMEM; > - ? ? ? ? ? ? ? goto irq_free; > + ? ? ? ? ? ? ? goto err1; > ? ? ? ?} > > ? ? ? ?davinci_spi->bitbang.master = spi_master_get(master); > @@ -1104,55 +982,23 @@ static int davinci_spi_probe(struct platform_device *pdev) > > ? ? ? ?davinci_spi->bitbang.chipselect = davinci_spi_chipselect; > ? ? ? ?davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; > + ? ? ? davinci_spi->bitbang.txrx_bufs = davinci_spi_txrx_bufs; > > ? ? ? ?davinci_spi->version = pdata->version; > - ? ? ? use_dma = pdata->use_dma; > > ? ? ? ?davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; > ? ? ? ?if (davinci_spi->version == SPI_VERSION_2) > ? ? ? ? ? ? ? ?davinci_spi->bitbang.flags |= SPI_READY; > > - ? ? ? if (use_dma) { > - ? ? ? ? ? ? ? ? ? ? ? r = platform_get_resource(pdev, IORESOURCE_DMA, 0); > - ? ? ? ? ? ? ? ? ? ? ? if (r) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dma_rx_chan = r->start; > - ? ? ? ? ? ? ? ? ? ? ? r = platform_get_resource(pdev, IORESOURCE_DMA, 1); > - ? ? ? ? ? ? ? ? ? ? ? if (r) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dma_tx_chan = r->start; > - ? ? ? ? ? ? ? ? ? ? ? r = platform_get_resource(pdev, IORESOURCE_DMA, 2); > - ? ? ? ? ? ? ? ? ? ? ? if (r) > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dma_eventq = r->start; > - ? ? ? } > - > - ? ? ? if (!use_dma || > - ? ? ? ? ? dma_rx_chan == SPI_NO_RESOURCE || > - ? ? ? ? ? dma_tx_chan == SPI_NO_RESOURCE || > - ? ? ? ? ? dma_eventq ?== SPI_NO_RESOURCE) { > - ? ? ? ? ? ? ? davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; > - ? ? ? ? ? ? ? use_dma = 0; > - ? ? ? } else { > - ? ? ? ? ? ? ? davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; > - ? ? ? ? ? ? ? davinci_spi->dma_channels = kzalloc(master->num_chipselect > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * sizeof(struct davinci_spi_dma), GFP_KERNEL); > - ? ? ? ? ? ? ? if (davinci_spi->dma_channels == NULL) { > - ? ? ? ? ? ? ? ? ? ? ? ret = -ENOMEM; > - ? ? ? ? ? ? ? ? ? ? ? goto free_clk; > - ? ? ? ? ? ? ? } > - > - ? ? ? ? ? ? ? for (i = 0; i < master->num_chipselect; i++) { > - ? ? ? ? ? ? ? ? ? ? ? davinci_spi->dma_channels[i].dma_rx_channel = -1; > - ? ? ? ? ? ? ? ? ? ? ? davinci_spi->dma_channels[i].dma_rx_sync_dev = > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dma_rx_chan; > - ? ? ? ? ? ? ? ? ? ? ? davinci_spi->dma_channels[i].dma_tx_channel = -1; > - ? ? ? ? ? ? ? ? ? ? ? davinci_spi->dma_channels[i].dma_tx_sync_dev = > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dma_tx_chan; > - ? ? ? ? ? ? ? ? ? ? ? davinci_spi->dma_channels[i].eventq = dma_eventq; > - ? ? ? ? ? ? ? } > - ? ? ? ? ? ? ? dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "Using RX channel = %d , TX channel = %d and " > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "event queue = %d", dma_rx_chan, dma_tx_chan, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dma_eventq); > - ? ? ? } > + ? ? ? dma_rx_chan = davinci_spi_get_dma_by_flag(pdev, IORESOURCE_DMA_RX_CHAN); > + ? ? ? dma_tx_chan = davinci_spi_get_dma_by_flag(pdev, IORESOURCE_DMA_TX_CHAN); > + ? ? ? dma_eventq ?= davinci_spi_get_dma_by_flag(pdev, IORESOURCE_DMA_EVENT_Q); > + ? ? ? davinci_spi->dma_channels.dma_rx_channel = -1; > + ? ? ? davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan; > + ? ? ? davinci_spi->dma_channels.dma_tx_channel = -1; > + ? ? ? davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan; > + ? ? ? davinci_spi->dma_channels.dummy_param_slot = -1; > + ? ? ? davinci_spi->dma_channels.eventq = dma_eventq; > > ? ? ? ?davinci_spi->get_rx = davinci_spi_rx_buf_u8; > ? ? ? ?davinci_spi->get_tx = davinci_spi_tx_buf_u8; > @@ -1164,32 +1010,29 @@ static int davinci_spi_probe(struct platform_device *pdev) > ? ? ? ?udelay(100); > ? ? ? ?iowrite32(1, davinci_spi->base + SPIGCR0); > > - ? ? ? /* Clock internal */ > - ? ? ? if (davinci_spi->pdata->clk_internal) > - ? ? ? ? ? ? ? set_io_bits(davinci_spi->base + SPIGCR1, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIGCR1_CLKMOD_MASK); > - ? ? ? else > - ? ? ? ? ? ? ? clear_io_bits(davinci_spi->base + SPIGCR1, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SPIGCR1_CLKMOD_MASK); > + ? ? ? /* Set up SPIPC0. ?CS and ENA init is done in davinci_spi_setup */ > + ? ? ? spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; > + ? ? ? iowrite32(spipc0, davinci_spi->base + SPIPC0); > > - ? ? ? /* master mode default */ > - ? ? ? set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); > + ? ? ? /* initialize chip selects */ > + ? ? ? if (pdata->chip_sel != NULL) { > + ? ? ? ? ? ? ? for (i = 0; i < pdata->num_chipselect; i++) { > + ? ? ? ? ? ? ? ? ? ? ? if (pdata->chip_sel[i] != SPI_INTERN_CS) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? gpio_direction_output(pdata->chip_sel[i], 1); > + ? ? ? ? ? ? ? } > + ? ? ? } > + ? ? ? iowrite32(SPIDEF_CSDEF_MASK, davinci_spi->base + SPIDEF); > > - ? ? ? if (davinci_spi->pdata->intr_level) > - ? ? ? ? ? ? ? iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); > - ? ? ? else > - ? ? ? ? ? ? ? iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); > + ? ? ? set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); > + ? ? ? set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); > + ? ? ? set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); > > ? ? ? ?ret = spi_bitbang_start(&davinci_spi->bitbang); > - ? ? ? if (ret) > + ? ? ? if (ret != 0) > ? ? ? ? ? ? ? ?goto free_clk; > > ? ? ? ?dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base); > > - ? ? ? if (!pdata->poll_mode) > - ? ? ? ? ? ? ? dev_info(&pdev->dev, "Operating in interrupt mode" > - ? ? ? ? ? ? ? ? ? ? ? " using IRQ %d\n", davinci_spi->irq); > - > ? ? ? ?return ret; > > ?free_clk: > @@ -1199,7 +1042,7 @@ put_master: > ? ? ? ?spi_master_put(master); > ?free_tmp_buf: > ? ? ? ?kfree(davinci_spi->tmp_buf); > -irq_free: > +err1: > ? ? ? ?free_irq(davinci_spi->irq, davinci_spi); > ?unmap_io: > ? ? ? ?iounmap(davinci_spi->base); > @@ -1211,7 +1054,7 @@ err: > ? ? ? ?return ret; > ?} > > -/** > +/* > ?* davinci_spi_remove - remove function for SPI Master Controller > ?* @pdev: platform_device structure which contains plateform specific data > ?* > @@ -1220,7 +1063,7 @@ err: > ?* It will also call spi_bitbang_stop to destroy the work queue which was > ?* created by spi_bitbang_start. > ?*/ > -static int __exit davinci_spi_remove(struct platform_device *pdev) > +static int __devexit davinci_spi_remove(struct platform_device *pdev) > ?{ > ? ? ? ?struct davinci_spi *davinci_spi; > ? ? ? ?struct spi_master *master; > @@ -1242,8 +1085,11 @@ static int __exit davinci_spi_remove(struct platform_device *pdev) > ?} > > ?static struct platform_driver davinci_spi_driver = { > - ? ? ? .driver.name = "spi_davinci", > - ? ? ? .remove = __exit_p(davinci_spi_remove), > + ? ? ? .driver = { > + ? ? ? ? ? ? ? .name = "spi_davinci", > + ? ? ? ? ? ? ? .owner = THIS_MODULE, > + ? ? ? }, > + ? ? ? .remove = __devexit_p(davinci_spi_remove), > ?}; > > ?static int __init davinci_spi_init(void) > -- > 1.6.3.3 > > -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. From broonie at opensource.wolfsonmicro.com Sun Jul 4 03:57:00 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Sun, 4 Jul 2010 17:57:00 +0900 Subject: [PATCH 3/3] ASoC: DaVinci: More accurate calculation for clock divider for McBSP (I2S) In-Reply-To: <1278090747-5124-4-git-send-email-lamiaposta71@gmail.com> References: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> <1278090747-5124-4-git-send-email-lamiaposta71@gmail.com> Message-ID: <20100704085659.GB16825@opensource.wolfsonmicro.com> On Fri, Jul 02, 2010 at 07:12:27PM +0200, Raffaele Recalcati wrote: > + * This define works when both clock and FS are output for the cpu > + * and makes clock more accurate (FS is not symmetrical and the > + * clock is very fast. As I've said before please say which clock you are discussing here. The user needs to be able to understand that it is the externally visible bit clock which will be affected rather than an internal clock since this has interoperability implications. The same thing probably applies to the name of the flag. From broonie at opensource.wolfsonmicro.com Sun Jul 4 04:15:13 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Sun, 4 Jul 2010 18:15:13 +0900 Subject: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S) In-Reply-To: <1278090747-5124-2-git-send-email-lamiaposta71@gmail.com> References: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> <1278090747-5124-2-git-send-email-lamiaposta71@gmail.com> Message-ID: <20100704091512.GE16825@opensource.wolfsonmicro.com> On Fri, Jul 02, 2010 at 07:12:25PM +0200, Raffaele Recalcati wrote: > From: Raffaele Recalcati > > Added two clocking options for dm365 McBSP peripheral when used > with I2S timings, that are SND_SOC_DAIFMT_CBS_CFS (the cpu generates You've not sent any of these patches to the ALSA list or to Liam Girdwood, the other ASoC maintainer. In general you should be looking to include at least the subsystem maintainers and mailing list for the relevant code, anyone who actively works on the driver and possibly an architecture-specific list. The first two patches look OK, though I'd like to see some DaVinci people confirming they're OK. From ephemeralmail-linuxdavinci at yahoo.com Sun Jul 4 08:39:32 2010 From: ephemeralmail-linuxdavinci at yahoo.com (Steve Sanders) Date: Sun, 4 Jul 2010 06:39:32 -0700 (PDT) Subject: MMC/SD problem - OMAPL137 EVM In-Reply-To: References: Message-ID: <1278250772123-5253224.post@n2.nabble.com> I had the same problem, and tracked it down to the SYSCFG "KICK" registers NOT being set to allow writes to the PINMUX registers. During MMC/SD pinmux setup, appropriate writes were being done to the PINMUX registers, but these were having no effect because KICK0R and KICK1R were not set to allow writes. Perhaps Sudhakar's bootloader leaves the KICK registers enabled and that's why he's able to have success. Added unlocking of the KICK registers and my MMC/SD cards now works fine: void __init da830_init(void) { davinci_common_init(&davinci_soc_info_da830); da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"); /* Unlock the KICK registers */ __raw_writel(0x83e70b13, da8xx_syscfg0_base + 0x38); __raw_writel(0x95a4f1e0, da8xx_syscfg0_base + 0x3c); } May warrant a more general patch... Grzegorz Skiba wrote: > > I have problem with MMC/SD Linux device driver, I have OMAPL137 EVM board, > 2.6.33-rc4 linux ver, form DaVinci-PSP-SDK-03.20.00.11. Linux kernel > doesn't recognize either RS MMC or SD. I commented out part related to LCD > and NAND to make sure that pinmux configuration is ok. Even with default > config I'm unable to access to SD or MMC cord. I compiled MMC/SD driver > with > debug and I this is what I get: > > This is what I get without SD/MMC card: > 0.070000] Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled > [ 0.070000] serial8250.0: ttyS0 at MMIO 0x1c42000 (irq = 25) is a > 16550A > [ 0.070000] serial8250.0: ttyS1 at MMIO 0x1d0c000 (irq = 53) is a > 16550A > [ 0.070000] serial8250.0: ttyS2 at MMIO 0x1d0d000 (irq = 61) is a > 16550A > [ 0.080000] brd: module loaded > [ 0.080000] spi_davinci spi_davinci.0: DaVinci SPI driver in EDMA mode > [ 0.080000] Using RX channel = 14 , TX channel = 15 and event queue = 1 > [ 0.080000] spi_davinci spi_davinci.0: Controller at 0xfec41000 > [ 0.080000] console [netcon0] enabled > [ 0.080000] netconsole: network logging started > [ 0.080000] i2c /dev entries driver > [ 0.080000] sdhci: Secure Digital Host Controller Interface driver > [ 0.080000] sdhci: Copyright(c) Pierre Ossman > [ 0.080000] davinci_mmc davinci_mmc.0: max_phys_segs=16 > [ 0.080000] davinci_mmc davinci_mmc.0: max_hw_segs=16 > [ 0.080000] davinci_mmc davinci_mmc.0: max_blk_size=4095 > [ 0.080000] davinci_mmc davinci_mmc.0: max_req_size=268365825 > [ 0.080000] davinci_mmc davinci_mmc.0: max_seg_size=2097120 > [ 0.080000] mmc0: clock 0Hz busmode 1 powermode 0 cs 0 Vdd 0 width 0 > timing 0 > [ 0.080000] davinci_mmc davinci_mmc.0: clock 0Hz busmode 1 powermode 0 > Vdd 0000 > [ 0.080000] davinci_mmc davinci_mmc.0: Disabling 4 bit mode > [ 0.080000] davinci_mmc davinci_mmc.0: Using DMA, 4-bit mode > > When I plug in SD card: > > [ 3.480000] Warning: unable to open an initial console. > [ 282.080000] mmc0: clock 0Hz busmode 1 powermode 1 cs 0 Vdd 21 width 0 > timing 0 > [ 282.080000] davinci_mmc davinci_mmc.0: clock 0Hz busmode 1 powermode 1 > Vdd 0015 > [ 282.080000] davinci_mmc davinci_mmc.0: Disabling 4 bit mode > [ 282.100000] mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 > width > 0 timing 0 > [ 282.100000] davinci_mmc davinci_mmc.0: clock 400000Hz busmode 1 > powermode > 2 Vdd 0015 > [ 282.100000] davinci_mmc davinci_mmc.0: Disabling 4 bit mode > [ 282.120000] mmc0: clock 400000Hz busmode 1 powermode 2 cs 1 Vdd 21 > width > 0 timing 0 > [ 282.120000] davinci_mmc davinci_mmc.0: clock 400000Hz busmode 1 > powermode > 2 Vdd 0015 > [ 282.120000] davinci_mmc davinci_mmc.0: Disabling 4 bit mode > [ 282.120000] mmc0: starting CMD0 arg 00000000 flags 000000c0 > [ 282.120000] davinci_mmc davinci_mmc.0: CMD0, arg 0x00000000, (R? > response) > [ 282.120000] davinci_mmc davinci_mmc.0: unknown resp_type 0000 > [ 282.120000] mmc0: req done (CMD0): 0: 00000000 00000000 00000000 > 00000000 > [ 282.120000] mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 > width > 0 timing 0 > [ 282.120000] davinci_mmc davinci_mmc.0: clock 400000Hz busmode 1 > powermode > 2 Vdd 0015 > [ 282.120000] davinci_mmc davinci_mmc.0: Disabling 4 bit mode > [ 282.120000] mmc0: starting CMD8 arg 000001aa flags 000002f5 > [ 282.120000] davinci_mmc davinci_mmc.0: CMD8, arg 0x000001aa, > R1/R5/R6/R7 > response > [ 282.120000] mmc0: req done (CMD8): 0: 00000000 00000000 00000000 > 00000000 > [ 282.120000] mmc0: starting CMD5 arg 00000000 flags 000002e1 > [ 282.120000] davinci_mmc davinci_mmc.0: CMD5, arg 0x00000000, R3/R4 > response > [ 282.120000] mmc0: req done (CMD5): 0: 00000000 00000000 00000000 > 00000000 > [ 282.120000] mmc0: host doesn't support card's voltages > > Here is kernel config related to MMC: > CONFIG_MMC=y > CONFIG_MMC_DEBUG=y > # CONFIG_MMC_UNSAFE_RESUME is not set > > # > # MMC/SD/SDIO Card Drivers > # > CONFIG_MMC_BLOCK=y > CONFIG_MMC_BLOCK_BOUNCE=y > # CONFIG_SDIO_UART is not set > # CONFIG_MMC_TEST is not set > > # > # MMC/SD/SDIO Host Controller Drivers > # > CONFIG_MMC_SDHCI=y > # CONFIG_MMC_SDHCI_PLTFM is not set > # CONFIG_MMC_AT91 is not set > # CONFIG_MMC_ATMELMCI is not set > CONFIG_MMC_DAVINCI=y > # CONFIG_MMC_SPI is not set > > Any ideas what I'm doing wrong ? I use 2 MB SD card and 1GB MMC card and I > have the same result > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > -- View this message in context: http://davinci-linux-open-source.1494791.n2.nabble.com/MMC-SD-problem-OMAPL137-EVM-tp4946329p5253224.html Sent from the davinci-linux-open-source mailing list archive at Nabble.com. From rohan_javed at yahoo.co.uk Mon Jul 5 05:52:49 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Mon, 5 Jul 2010 10:52:49 +0000 (GMT) Subject: Question on RAMDISK Message-ID: <403497.59727.qm@web24104.mail.ird.yahoo.com> Hello everyone I am using a ramdisk image to boot the system its takes around 7secs to copy the ramdisk image from the flash to the RAM and then takes 3.6 seconds after kernal uncompressing to the linux prompt I want to know that how to reduce this time of 7seconds. Also can anyone tell how to update the ramdisk image from the linux prompt.e.g if i have created a file and now iwant it at the next boot then how to make this file part of the old ramdisk image Regard's RT -------------- next part -------------- An HTML attachment was scrubbed... URL: From johnny at tpsee.com Mon Jul 5 07:25:06 2010 From: johnny at tpsee.com (johnny) Date: Mon, 5 Jul 2010 20:25:06 +0800 Subject: change the source of "simplewidget" and compile it has no effect on our own application, can we change the code and rebuild the lib simplewidget? Message-ID: <201007052025046875726@tpsee.com> Hi all, For some reason I have to change the code of dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget/Button.c and Button.h, I complie the direcotry of simplewidget for dm365 but the new interface added by us can not be found. I found only one simplewidget_dm365.a470MV in the whole directory dvsdk_2_10_01_18 in directory dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget/lib/, but after I delete the file dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget/lib/simplewidget_dm365.a470MV, we can still compile our application successfully. How could this happen? can we change the code and rebuild the lib simplewidget? 2010-07-05 johnny -------------- next part -------------- An HTML attachment was scrubbed... URL: From lamiaposta71 at gmail.com Mon Jul 5 07:50:12 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Mon, 5 Jul 2010 14:50:12 +0200 Subject: Question on RAMDISK In-Reply-To: <403497.59727.qm@web24104.mail.ird.yahoo.com> References: <403497.59727.qm@web24104.mail.ird.yahoo.com> Message-ID: 2010/7/5 rohan tabish > Hello everyone > > I am using a ramdisk image to boot the system its takes around 7secs to > copy the ramdisk image from the flash to the RAM and then takes 3.6 seconds > after kernal uncompressing to the linux prompt > > I want to know that how to reduce this time of 7seconds. > you can use, if not already done, cp.l and not cp.b and divide the lenght to copy by 4. > > Also can anyone tell how to update the ramdisk image from the linux > prompt.e.g if i have created a file and now iwant it at the next boot then > how to make this file part of the old ramdisk image > > Regard's > RT > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > -- www.opensurf.it -------------- next part -------------- An HTML attachment was scrubbed... URL: From rohan_javed at yahoo.co.uk Mon Jul 5 07:50:36 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Mon, 5 Jul 2010 12:50:36 +0000 (GMT) Subject: Choosing filesytems JFFS2 or Ramdisk Message-ID: <130809.26915.qm@web24108.mail.ird.yahoo.com> Hello I have an application requirement which performs alot of read write operations on the file system so what is the recommended file system i should use i guess using jffs2 is the option because having ram disk as file system will not be able to save the configuration on next boot. There is also a problem with JFFS2 as file system doing many file operations on flash will finish its life over the time as flash have limited life Kindly suggest what should be the preferred way out Regard's R0H at n -------------- next part -------------- An HTML attachment was scrubbed... URL: From tharma at e-consystems.com Mon Jul 5 09:14:02 2010 From: tharma at e-consystems.com (Tharmarajan Ganeshan) Date: Mon, 05 Jul 2010 19:44:02 +0530 Subject: DM355 - 256MB RAM memory issue Message-ID: <1278339242.18556.10.camel@tharma-laptop> Hi All, We are working on a DM355 processor based Development board. The Board has 256MB mDDR RAM and 5MP image sensor MT9P031. We are using the kernel version 2.6.10 We have modified the driver code for capturing 5MP raw image and converting this 5MP raw into YUV. For this 5MP image capturing , we have reserved 30MB. We have allocated 56MB to the CMEM driver. The reserved memory 30MB and the 56MB memory for CMEM are at top of the RAM. We are passing the remaining memory size to the kernel in bootargs as mem=170M. And we are using the NFS rootfilesystem. But we are getting kernel hanging issues while testing the IPNC_APP applications and 5MP still image capturing. Sometimes the kernel is hanging while booting itself. If we reserve the 30MB from the address region 0x83200000 - 0x84FFFFFF and pass the memory size to kernel in bootargs as mem=50M, then we are NOT having any issues in running the applications. But we want to use the exact remaining memory. And also we are not able to program the NAND flash memory in kernel level if we are not passing the mem=50M in bootargs. What could be the cause for this kernel hanging issue ? Are we missing any configurations while building the kernel image ? Our Bootargs is : mem=50M console=ttyS1,115200n8 root=/dev/nfs rootwait rw ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 nfsroot=192.168.1.99:/tftpboot/bellatrix_rootfilesystem,nolock eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 Regards, Tharmarajan G -------------- next part -------------- An HTML attachment was scrubbed... URL: From broonie at opensource.wolfsonmicro.com Mon Jul 5 09:33:22 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Mon, 5 Jul 2010 23:33:22 +0900 Subject: Rif: Re: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S) In-Reply-To: References: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> <1278090747-5124-2-git-send-email-lamiaposta71@gmail.com> <20100704091512.GE16825@opensource.wolfsonmicro.com> Message-ID: <20100705143320.GA24158@opensource.wolfsonmicro.com> On Mon, Jul 05, 2010 at 07:05:43AM +0200, raffaele.recalcati at bticino.it wrote: > -----Mark Brown ha scritto: ----- > >Per:?Raffaele?Recalcati? You might want to look at your MUA configuration - it's started mangling things so extra line endings are being added... Anyway: > anyway, if get_mantainer is not right, it is better to fix it, instead of > guessing who to send the patches to. The problem is that it's not really possible to determine this automatically - you need to apply a certain amount of intelligence to see why someone is showing up in there. People might have been doing things like general cleanup work which touch the file a lot and cause them to show up in the logs, but they may also be touching the file a lot due being very interested in it. From diego.dompe at ridgerun.com Mon Jul 5 12:46:23 2010 From: diego.dompe at ridgerun.com (Diego Dompe) Date: Mon, 5 Jul 2010 11:46:23 -0600 Subject: Lauterbach and DM365 In-Reply-To: <4C28A09D.8090401@gmail.com> References: <4C28A09D.8090401@gmail.com> Message-ID: Hi, Yes, you can attach the lauterbach to a DM365. I think is even on the list of processors supported on recent versions. Diego On Jun 28, 2010, at 7:16 AM, Kieran Bingham wrote: > Hi Guys, > > Has anyone used a lauterbach to connect the DM365? > > I can't find documentation anywhere on what settings to use... > > -- > Regards > Kieran > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source From sudhakar.raj at ti.com Tue Jul 6 00:46:44 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Tue, 6 Jul 2010 11:16:44 +0530 Subject: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S) In-Reply-To: <1278090747-5124-2-git-send-email-lamiaposta71@gmail.com> References: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> <1278090747-5124-2-git-send-email-lamiaposta71@gmail.com> Message-ID: <000101cb1cce$9dd82520$d9886f60$@raj@ti.com> Hi, On Fri, Jul 02, 2010 at 22:42:25, Raffaele Recalcati wrote: > From: Raffaele Recalcati > > Added two clocking options for dm365 McBSP peripheral when used > with I2S timings, that are SND_SOC_DAIFMT_CBS_CFS (the cpu generates > clock and frame sync) and SND_SOC_DAIFMT_CBS_CFM (the cpu gets clock > from external pin and generates frame sync). > A slave clock management can be important when the external codec needs > the system clock and the bit clock synchronized (tested with uda1345). > This patch has been developed against the: > http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git > git tree and has been tested on bmx board (similar to dm365 evm, but using > uda1345 as external audio codec). > > Signed-off-by: Raffaele Recalcati > Signed-off-by: Davide Bonfanti > --- > sound/soc/davinci/davinci-i2s.c | 111 +++++++++++++++++++++++++++++++++++--- > sound/soc/davinci/davinci-i2s.h | 5 ++ > 2 files changed, 107 insertions(+), 9 deletions(-) > > diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c > index adadcd3..a893538 100644 > --- a/sound/soc/davinci/davinci-i2s.c > +++ b/sound/soc/davinci/davinci-i2s.c > @@ -26,6 +26,7 @@ > #include > > #include "davinci-pcm.h" > +#include "davinci-i2s.h" > [...] > @@ -372,6 +383,19 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, > return 0; > } > > +static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, > + int div_id, int div) > +{ > + struct davinci_mcbsp_dev *dev = cpu_dai->private_data; > + int srgr; srgr variable is not being used in this function. Consider removing it. Regards, Sudhakar From sudhakar.raj at ti.com Tue Jul 6 00:49:40 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Tue, 6 Jul 2010 11:19:40 +0530 Subject: [PATCH 2/3] ASoC: DaVinci: Added selection of clk input pin for McBSP In-Reply-To: <1278090747-5124-3-git-send-email-lamiaposta71@gmail.com> References: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> <1278090747-5124-3-git-send-email-lamiaposta71@gmail.com> Message-ID: <000201cb1ccf$067c5290$1374f7b0$@raj@ti.com> Hi, On Fri, Jul 02, 2010 at 22:42:26, Raffaele Recalcati wrote: > From: Raffaele Recalcati > > When McBSP peripheral gets the clock from an external pin, > there are three possible chooses, MCBSP_CLKX, MCBSP_CLKR > and MCBSP_CLKS. > evm-dm365 uses MCBSP_CLKR, instead in bmx board I have a different > hardware connection and I use MCBSP_CLKS, so I have added > this possibility. > > This patch has been developed against the: > http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git > git tree and has been tested on bmx board (similar to dm365 evm) > > Signed-off-by: Raffaele Recalcati > Signed-off-by: Davide Bonfanti > --- > arch/arm/mach-davinci/include/mach/asp.h | 15 +++++++++++++++ > sound/soc/davinci/davinci-i2s.c | 27 ++++++++++++++++++++++----- > 2 files changed, 37 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h > index 834725f..0847d21 100644 > --- a/arch/arm/mach-davinci/include/mach/asp.h > +++ b/arch/arm/mach-davinci/include/mach/asp.h > @@ -153,6 +153,7 @@ struct davinci_mcbsp_dev { [...] > > unsigned int fmt; > int clk_div; > + int clk_input_pin; > }; > > static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, > @@ -279,11 +280,26 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, > DAVINCI_MCBSP_PCR_CLKRM; > break; > case SND_SOC_DAIFMT_CBM_CFS: > - /* McBSP CLKR pin is the input for the Sample Rate Generator. > - * McBSP FSR and FSX are driven by the Sample Rate Generator. */ > - pcr = DAVINCI_MCBSP_PCR_SCLKME | > - DAVINCI_MCBSP_PCR_FSXM | > - DAVINCI_MCBSP_PCR_FSRM; > + pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM; > + /* > + * Selection of the clock input pin that is the > + * input for the Sample Rate Generator. > + * McBSP FSR and FSX are driven by the Sample Rate > + * Generator. > + */ > + switch (dev->clk_input_pin) { > + case MCBSP_CLKS: > + pcr |= DAVINCI_MCBSP_PCR_CLKXM | > + DAVINCI_MCBSP_PCR_CLKRM; > + break; > + case MCBSP_CLKR: > + pcr |= DAVINCI_MCBSP_PCR_SCLKME; > + break; > + default: > + dev_err(&pdev->dev, "bad clk_input_pin\n"); The above line results on compilation error as pdev is not defined in this function. Regards, Sudhakar From sudhakar.raj at ti.com Tue Jul 6 00:53:21 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Tue, 6 Jul 2010 11:23:21 +0530 Subject: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S) In-Reply-To: <20100704091512.GE16825@opensource.wolfsonmicro.com> References: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> <1278090747-5124-2-git-send-email-lamiaposta71@gmail.com> <20100704091512.GE16825@opensource.wolfsonmicro.com> Message-ID: <000301cb1ccf$8acd9d10$a068d730$@raj@ti.com> Hi, On Sun, Jul 04, 2010 at 14:45:13, Mark Brown wrote: > On Fri, Jul 02, 2010 at 07:12:25PM +0200, Raffaele Recalcati wrote: > > From: Raffaele Recalcati > > > > Added two clocking options for dm365 McBSP peripheral when used > > with I2S timings, that are SND_SOC_DAIFMT_CBS_CFS (the cpu generates > > You've not sent any of these patches to the ALSA list or to Liam > Girdwood, the other ASoC maintainer. In general you should be looking > to include at least the subsystem maintainers and mailing list for the > relevant code, anyone who actively works on the driver and possibly an > architecture-specific list. > > The first two patches look OK, though I'd like to see some DaVinci > people confirming they're OK. I tested this series on DM644x, DM355 and DM365 EVMs and audio is working fine with these patches. I have commented on first 2 patches of this series which needs to be fixed. Thanks, Sudhakar From lamiaposta71 at gmail.com Tue Jul 6 01:07:47 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Tue, 6 Jul 2010 08:07:47 +0200 Subject: Lauterbach and DM365 In-Reply-To: References: <4C28A09D.8090401@gmail.com> Message-ID: 2010/7/5 Diego Dompe > Hi, > > Yes, you can attach the lauterbach to a DM365. I think is even on the list > of processors supported on recent versions. > > Diego > > > On Jun 28, 2010, at 7:16 AM, Kieran Bingham wrote: > > > Hi Guys, > > > > Has anyone used a lauterbach to connect the DM365? > > > > I can't find documentation anywhere on what settings to use... > it works perfectly. Ask to Lauterbach, they will help you! > > > > -- > > Regards > > Kieran > > _______________________________________________ > > Davinci-linux-open-source mailing list > > Davinci-linux-open-source at linux.davincidsp.com > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > -- www.opensurf.it -------------- next part -------------- An HTML attachment was scrubbed... URL: From sudhakar.raj at ti.com Tue Jul 6 01:20:11 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Tue, 6 Jul 2010 11:50:11 +0530 Subject: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S) In-Reply-To: <1278090747-5124-2-git-send-email-lamiaposta71@gmail.com> References: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> <1278090747-5124-2-git-send-email-lamiaposta71@gmail.com> Message-ID: <001001cb1cd3$4a18d650$de4a82f0$@raj@ti.com> Hi, On Fri, Jul 02, 2010 at 22:42:25, Raffaele Recalcati wrote: > From: Raffaele Recalcati > > Added two clocking options for dm365 McBSP peripheral when used > with I2S timings, that are SND_SOC_DAIFMT_CBS_CFS (the cpu generates > clock and frame sync) and SND_SOC_DAIFMT_CBS_CFM (the cpu gets clock > from external pin and generates frame sync). > A slave clock management can be important when the external codec needs > the system clock and the bit clock synchronized (tested with uda1345). > This patch has been developed against the: > http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git > git tree and has been tested on bmx board (similar to dm365 evm, but using > uda1345 as external audio codec). > > Signed-off-by: Raffaele Recalcati > Signed-off-by: Davide Bonfanti > --- > sound/soc/davinci/davinci-i2s.c | 111 +++++++++++++++++++++++++++++++++++--- > sound/soc/davinci/davinci-i2s.h | 5 ++ > 2 files changed, 107 insertions(+), 9 deletions(-) > > diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c > index adadcd3..a893538 100644 > --- a/sound/soc/davinci/davinci-i2s.c > +++ b/sound/soc/davinci/davinci-i2s.c > @@ -26,6 +26,7 @@ > #include > > #include "davinci-pcm.h" > +#include "davinci-i2s.h" > > > /* > @@ -68,16 +69,21 @@ > #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) > #define DAVINCI_MCBSP_RCR_RFIG (1 << 18) > #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) > +#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24) > +#define DAVINCI_MCBSP_RCR_RPHASE (1 << 31) > > #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) > #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) > #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) > #define DAVINCI_MCBSP_XCR_XFIG (1 << 18) > #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) > +#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24) > +#define DAVINCI_MCBSP_XCR_XPHASE (1 << 31) > > #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) > #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) > #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) > +#define DAVINCI_MCBSP_SRGR_CLKSM (1 << 29) > Use "BIT(x)" instead of (1 << x). Regards, Sudhakar From sudhakar.raj at ti.com Tue Jul 6 03:36:57 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Tue, 6 Jul 2010 14:06:57 +0530 Subject: [PATCH v2 0/1] davinci: spi: replace existing driver In-Reply-To: <1278110334-13943-1-git-send-email-bniebuhr@efjohnson.com> References: <1278110334-13943-1-git-send-email-bniebuhr@efjohnson.com> Message-ID: <002301cb1ce6$64fba3e0$2ef2eba0$@raj@ti.com> Hi, On Sat, Jul 03, 2010 at 04:08:53, Brian Niebuhr wrote: > I have included all of the recommended changes in this version of the patch. > I also combined the patches into one patch to avoid bisecting issues. This > makes the diff on davinci_spi.c very large. > > If people who are using this driver could test this version of the driver > and Ack it, I would appreciate it. > > ** NOTE ** > > This patch requires the EDMA patch at: > > http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-March/018022.html > > which is queued waiting on another driver fix, for DMA mode to work correctly. > > > Brian Niebuhr (1): > davinci: spi: replace existing driver > > arch/arm/mach-davinci/board-dm355-evm.c | 10 + > arch/arm/mach-davinci/board-dm355-leopard.c | 10 + > arch/arm/mach-davinci/board-dm365-evm.c | 10 + > arch/arm/mach-davinci/dm355.c | 12 +- > arch/arm/mach-davinci/dm365.c | 12 +- > arch/arm/mach-davinci/include/mach/spi.h | 37 +- > drivers/spi/davinci_spi.c | 1328 ++++++++++++--------------- > 7 files changed, 648 insertions(+), 771 deletions(-) > Quick update. I tested this patch on DM355 and DM365 EVMs. On DM355 all the 3 modes (DMA, Polled and Interrupt) worked fine. But in interrupt mode, on DM355, if I set "intr_level = 1", then kernel hangs during booting after printing "spi spi0.0: DaVinci SPI driver in Interrupt mode" on the console. On DM365 only DMA and Polled mode worked fine. In interrupt mode, whether I set intr_level to ZERO or ONE, kernel booting hangs, similar to DM355. I'll update the status of testing on OMAP-L1x EVMs later. I am using the Linux kernel from [1] for testing. [1] http://git.kernel.org/?p=linux/kernel/git/khilman/linux-davinci.git;a=summary Regards, Sudhakar From nsekhar at ti.com Tue Jul 6 05:04:16 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Tue, 6 Jul 2010 15:34:16 +0530 Subject: [PATCH v2 1/6] davinci: add support for aemif timing configuration Message-ID: <1278410661-18211-1-git-send-email-nsekhar@ti.com> This patch adds support to configure the AEMIF interface with supplied timing values. Since this capability is useful both from NOR and NAND flashes, it is provided as a new interface and in a file of its own. AEMIF timing configuration is required in cases: 1) Where the AEMIF clock rate can change at runtime (a side affect of cpu frequency change). 2) Where U-Boot does not support NAND/NOR but supports other media like SPI Flash or MMC/SD and thus does not care about setting up the AEMIF timing for kernel to use. 3) Where U-Boot just hasn't configured the timing values and cannot be upgraded because the box is already in the field. Since there is now a header file for AEMIF interface, the common (non-NAND specific) defines for AEMIF registers have been moved from nand.h into the newly created aemif.h Signed-off-by: Sekhar Nori --- v2: 1) return error from aemif_clk_rate() in case the timing values obtained exceed the max allowed 2) removed common aemif register definitions from nand.h arch/arm/mach-davinci/Makefile | 2 +- arch/arm/mach-davinci/aemif.c | 134 ++++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/aemif.h | 36 ++++++++ arch/arm/mach-davinci/include/mach/nand.h | 3 - drivers/mtd/nand/davinci_nand.c | 1 + 5 files changed, 172 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-davinci/aemif.c create mode 100644 arch/arm/mach-davinci/include/mach/aemif.h diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index eab4c0f..77a0f71 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,7 +5,7 @@ # Common objects obj-y := time.o clock.o serial.o io.o psc.o \ - gpio.o dma.o usb.o common.o sram.o + gpio.o dma.o usb.o common.o sram.o aemif.o obj-$(CONFIG_DAVINCI_MUX) += mux.o diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c new file mode 100644 index 0000000..12b712f --- /dev/null +++ b/arch/arm/mach-davinci/aemif.c @@ -0,0 +1,134 @@ +/* + * AEMIF support for DaVinci SoCs + * + * Copyright (C) 2010 Texas Instruments Incorporated. http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +/* Timing value configuration */ + +#define TA(x) ((x) << 2) +#define RHOLD(x) ((x) << 4) +#define RSTROBE(x) ((x) << 7) +#define RSETUP(x) ((x) << 13) +#define WHOLD(x) ((x) << 17) +#define WSTROBE(x) ((x) << 20) +#define WSETUP(x) ((x) << 26) + +#define TA_MAX 0x3 +#define RHOLD_MAX 0x7 +#define RSTROBE_MAX 0x3f +#define RSETUP_MAX 0xf +#define WHOLD_MAX 0x7 +#define WSTROBE_MAX 0x3f +#define WSETUP_MAX 0xf + +#define TIMING_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +#define NS_IN_KHZ 1000000 + +/* + * aemif_calc_rate - calculate timing data. + * @wanted: The cycle time needed in nanoseconds. + * @clk: The input clock rate in kHz. + * @max: The maximum divider value that can be programmed. + * + * On success, returns the calculated timing value minus 1 for easy + * programming into AEMIF timing registers, else negative errno. + */ +static int aemif_calc_rate(int wanted, unsigned long clk, int max) +{ + int result; + + result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ) - 1; + + pr_debug("%s: result %d from %ld, %d\n", __func__, result, clk, wanted); + + /* It is generally OK to have a more relaxed timing than requested... */ + if (result < 0) + result = 0; + + /* ... But configuring tighter timings is not an option. */ + else if (result > max) + result = -EINVAL; + + return result; +} + +/** + * davinci_aemif_setup_timing - setup timing values for a given AEMIF interface + * @t: timing values to be progammed + * @base: The virtual base address of the AEMIF interface + * @cs: chip-select to program the timing values for + * + * This function programs the given timing values (in real clock) into the + * AEMIF registers taking the AEMIF clock into account. + * + * This function does not use any locking while programming the AEMIF + * because it is expected that there is only one user of a given + * chip-select. + * + * Returns 0 on success, else negative errno. + */ +int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, + void __iomem *base, unsigned cs) +{ + unsigned set, val; + unsigned ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; + unsigned offset = A1CR_OFFSET + cs * 4; + struct clk *aemif_clk; + unsigned long clkrate; + + if (!t) + return 0; /* Nothing to do */ + + aemif_clk = clk_get(NULL, "aemif"); + if (IS_ERR(aemif_clk)) + return PTR_ERR(aemif_clk); + + clkrate = clk_get_rate(aemif_clk); + + clkrate /= 1000; /* turn clock into kHz for ease of use */ + + ta = aemif_calc_rate(t->ta, clkrate, TA_MAX); + rhold = aemif_calc_rate(t->rhold, clkrate, RHOLD_MAX); + rstrobe = aemif_calc_rate(t->rstrobe, clkrate, RSTROBE_MAX); + rsetup = aemif_calc_rate(t->rsetup, clkrate, RSETUP_MAX); + whold = aemif_calc_rate(t->whold, clkrate, WHOLD_MAX); + wstrobe = aemif_calc_rate(t->wstrobe, clkrate, WSTROBE_MAX); + wsetup = aemif_calc_rate(t->wsetup, clkrate, WSETUP_MAX); + + if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || + whold < 0 || wstrobe < 0 || wsetup < 0) { + pr_err("%s: cannot get suitable timings\n", __func__); + return -EINVAL; + } + + set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | + WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); + + val = __raw_readl(base + offset); + val &= ~TIMING_MASK; + val |= set; + __raw_writel(val, base + offset); + + return 0; +} +EXPORT_SYMBOL(davinci_aemif_setup_timing); diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h new file mode 100644 index 0000000..05b2934 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/aemif.h @@ -0,0 +1,36 @@ +/* + * TI DaVinci AEMIF support + * + * Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +#ifndef _MACH_DAVINCI_AEMIF_H +#define _MACH_DAVINCI_AEMIF_H + +#define NRCSR_OFFSET 0x00 +#define AWCCR_OFFSET 0x04 +#define A1CR_OFFSET 0x10 + +#define ACR_ASIZE_MASK 0x3 +#define ACR_EW_MASK BIT(30) +#define ACR_SS_MASK BIT(31) + +/* All timings in nanoseconds */ +struct davinci_aemif_timing { + u8 wsetup; + u8 wstrobe; + u8 whold; + + u8 rsetup; + u8 rstrobe; + u8 rhold; + + u8 ta; +}; + +int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, + void __iomem *base, unsigned cs); +#endif diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h index b2ad809..b5893f0 100644 --- a/arch/arm/mach-davinci/include/mach/nand.h +++ b/arch/arm/mach-davinci/include/mach/nand.h @@ -30,9 +30,6 @@ #include -#define NRCSR_OFFSET 0x00 -#define AWCCR_OFFSET 0x04 -#define A1CR_OFFSET 0x10 #define NANDFCR_OFFSET 0x60 #define NANDFSR_OFFSET 0x64 #define NANDF1ECC_OFFSET 0x70 diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 2ac7367..8e2d56c 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -35,6 +35,7 @@ #include #include +#include #include -- 1.6.2.4 From nsekhar at ti.com Tue Jul 6 05:04:21 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Tue, 6 Jul 2010 15:34:21 +0530 Subject: [PATCH v2 6/6] davinci: dm6467t evm: setup NAND flash timing In-Reply-To: <1278410661-18211-5-git-send-email-nsekhar@ti.com> References: <1278410661-18211-1-git-send-email-nsekhar@ti.com> <1278410661-18211-2-git-send-email-nsekhar@ti.com> <1278410661-18211-3-git-send-email-nsekhar@ti.com> <1278410661-18211-4-git-send-email-nsekhar@ti.com> <1278410661-18211-5-git-send-email-nsekhar@ti.com> Message-ID: <1278410661-18211-6-git-send-email-nsekhar@ti.com> Setup NAND flash timing on DM6467T EVM. Without the timing setup, the NAND flash on DM6467T RevC EVM reports a number of random bad blocks because of read errors. Also, with this, copying a 100M file on RevB EVM takes ~35 sec against 1 minute 30 seconds earlier. Signed-off-by: Sekhar Nori --- v2: DM6467T and DM6467 EVMs use slightly different NAND parts, made the timing configuration specific to DM6467T. arch/arm/mach-davinci/board-dm646x-evm.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 6d88893..749aef8 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -42,6 +42,7 @@ #include #include #include +#include #include "clock.h" @@ -71,6 +72,16 @@ static struct mtd_partition davinci_nand_partitions[] = { } }; +static struct davinci_aemif_timing dm6467tevm_nandflash_timing = { + .wsetup = 29, + .wstrobe = 24, + .whold = 14, + .rsetup = 19, + .rstrobe = 33, + .rhold = 0, + .ta = 29, +}; + static struct davinci_nand_pdata davinci_nand_data = { .mask_cle = 0x80000, .mask_ale = 0x40000, @@ -730,6 +741,9 @@ static __init void evm_init(void) dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); + if (machine_is_davinci_dm6467tevm()) + davinci_nand_data.timing = &dm6467tevm_nandflash_timing; + platform_device_register(&davinci_nand_device); if (HAS_ATA) -- 1.6.2.4 From nsekhar at ti.com Tue Jul 6 05:04:17 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Tue, 6 Jul 2010 15:34:17 +0530 Subject: [PATCH v2 2/6] nand: davinci: add support for timing configuration In-Reply-To: <1278410661-18211-1-git-send-email-nsekhar@ti.com> References: <1278410661-18211-1-git-send-email-nsekhar@ti.com> Message-ID: <1278410661-18211-2-git-send-email-nsekhar@ti.com> This patch modifies the DaVinci NAND driver to use the new AEMIF timing setup API to configure the NAND access timings. Earlier, AEMIF configuration was being done as a special case for DM644x board, but now more boards emerge which have capability to boot for other media (SPI flash, NOR flash) and have the kernel access NAND flash. This means that kernel cannot always depend on the bootloader to setup the NAND. Also, on platforms such as da850/omap-l138, the aemif input frequency changes as cpu frequency changes; necessiating re-calculation of timimg values as part of cpufreq transtitions. This patch forms the basis for adding that support. Signed-off-by: Sekhar Nori --- v2: no need to include aemif.h in nand.c in this patch since patch 1/6 does that now. arch/arm/mach-davinci/include/mach/nand.h | 3 + drivers/mtd/nand/davinci_nand.c | 60 ++++++++++------------------ 2 files changed, 25 insertions(+), 38 deletions(-) diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h index b5893f0..0251510 100644 --- a/arch/arm/mach-davinci/include/mach/nand.h +++ b/arch/arm/mach-davinci/include/mach/nand.h @@ -80,6 +80,9 @@ struct davinci_nand_pdata { /* platform_data */ /* Main and mirror bbt descriptor overrides */ struct nand_bbt_descr *bbt_td; struct nand_bbt_descr *bbt_md; + + /* Access timings */ + struct davinci_aemif_timing *timing; }; #endif /* __ARCH_ARM_DAVINCI_NAND_H */ diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 8e2d56c..8beb0d0 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -75,6 +75,8 @@ struct davinci_nand_info { uint32_t mask_cle; uint32_t core_chipsel; + + struct davinci_aemif_timing *timing; }; static DEFINE_SPINLOCK(davinci_nand_lock); @@ -479,36 +481,6 @@ static int nand_davinci_dev_ready(struct mtd_info *mtd) return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0); } -static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info) -{ - uint32_t regval, a1cr; - - /* - * NAND FLASH timings @ PLL1 == 459 MHz - * - AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz - * - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns - */ - regval = 0 - | (0 << 31) /* selectStrobe */ - | (0 << 30) /* extWait (never with NAND) */ - | (1 << 26) /* writeSetup 10 ns */ - | (3 << 20) /* writeStrobe 40 ns */ - | (1 << 17) /* writeHold 10 ns */ - | (0 << 13) /* readSetup 10 ns */ - | (3 << 7) /* readStrobe 60 ns */ - | (0 << 4) /* readHold 10 ns */ - | (3 << 2) /* turnAround ?? ns */ - | (0 << 0) /* asyncSize 8-bit bus */ - ; - a1cr = davinci_nand_readl(info, A1CR_OFFSET); - if (a1cr != regval) { - dev_dbg(info->dev, "Warning: NAND config: Set A1CR " \ - "reg to 0x%08x, was 0x%08x, should be done by " \ - "bootloader.\n", regval, a1cr); - davinci_nand_writel(info, A1CR_OFFSET, regval); - } -} - /*----------------------------------------------------------------------*/ /* An ECC layout for using 4-bit ECC with small-page flash, storing @@ -612,6 +584,7 @@ static int __init nand_davinci_probe(struct platform_device *pdev) info->chip.options = pdata->options; info->chip.bbt_td = pdata->bbt_td; info->chip.bbt_md = pdata->bbt_md; + info->timing = pdata->timing; info->ioaddr = (uint32_t __force) vaddr; @@ -689,15 +662,25 @@ static int __init nand_davinci_probe(struct platform_device *pdev) goto err_clk_enable; } - /* EMIF timings should normally be set by the boot loader, - * especially after boot-from-NAND. The *only* reason to - * have this special casing for the DM6446 EVM is to work - * with boot-from-NOR ... with CS0 manually re-jumpered - * (after startup) so it addresses the NAND flash, not NOR. - * Even for dev boards, that's unusually rude... + /* + * Setup Async configuration register in case we did not boot from + * NAND and so bootloader did not bother to set it up. */ - if (machine_is_davinci_evm()) - nand_dm6446evm_flash_init(info); + val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4); + + /* Extended Wait is not valid and Select Strobe mode is not used */ + val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK); + if (info->chip.options & NAND_BUSWIDTH_16) + val |= 0x1; + + davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val); + + ret = davinci_aemif_setup_timing(info->timing, info->base, + info->core_chipsel); + if (ret < 0) { + dev_dbg(&pdev->dev, "NAND timing values setup fail\n"); + goto err_timing; + } spin_lock_irq(&davinci_nand_lock); @@ -810,6 +793,7 @@ syndrome_done: return 0; err_scan: +err_timing: clk_disable(info->clk); err_clk_enable: -- 1.6.2.4 From nsekhar at ti.com Tue Jul 6 05:04:18 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Tue, 6 Jul 2010 15:34:18 +0530 Subject: [PATCH 3/6] davinci: dm644x evm: setup NAND flash timing In-Reply-To: <1278410661-18211-2-git-send-email-nsekhar@ti.com> References: <1278410661-18211-1-git-send-email-nsekhar@ti.com> <1278410661-18211-2-git-send-email-nsekhar@ti.com> Message-ID: <1278410661-18211-3-git-send-email-nsekhar@ti.com> The DM644x EVM nand flash timing was earlier being done as a special case in the NAND driver itself. With the NAND driver now capable of progamming the AEMIF interface using timing data passed from the platform, the timing values are being moved into their rightful place in the EVM specific board file. The values being programmed match what was being done earlier and thus do not represent any change in performance/functionality. Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/board-dm644x-evm.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 34c8b41..65bb940 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -37,6 +37,7 @@ #include #include #include +#include #define DM644X_EVM_PHY_MASK (0x2) #define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ @@ -137,11 +138,22 @@ static struct mtd_partition davinci_evm_nandflash_partition[] = { */ }; +static struct davinci_aemif_timing davinci_evm_nandflash_timing = { + .wsetup = 20, + .wstrobe = 40, + .whold = 20, + .rsetup = 10, + .rstrobe = 40, + .rhold = 10, + .ta = 40, +}; + static struct davinci_nand_pdata davinci_evm_nandflash_data = { .parts = davinci_evm_nandflash_partition, .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition), .ecc_mode = NAND_ECC_HW, .options = NAND_USE_FLASH_BBT, + .timing = &davinci_evm_nandflash_timing, }; static struct resource davinci_evm_nandflash_resource[] = { -- 1.6.2.4 From nsekhar at ti.com Tue Jul 6 05:04:20 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Tue, 6 Jul 2010 15:34:20 +0530 Subject: [PATCH 5/6] davinci: am18x/da850/omap-l138 evm: setup NAND flash timing In-Reply-To: <1278410661-18211-4-git-send-email-nsekhar@ti.com> References: <1278410661-18211-1-git-send-email-nsekhar@ti.com> <1278410661-18211-2-git-send-email-nsekhar@ti.com> <1278410661-18211-3-git-send-email-nsekhar@ti.com> <1278410661-18211-4-git-send-email-nsekhar@ti.com> Message-ID: <1278410661-18211-5-git-send-email-nsekhar@ti.com> Setup the NAND flash timings for DA850 EVM Before configuring the timing values, throughput calculation using dd command yielded 469 kB/s write and 966 kB/s read speed. After the timing configuration, the throughput was measured to be 2.4 MB/s write and 5 MB/s read. [Mukul Bhatnagar: actual calculation of timing values from the NAND datasheet] Signed-off-by: Sekhar Nori Cc: Mukul Bhatnagar --- arch/arm/mach-davinci/board-da850-evm.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 2ec3095..85e6e58 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -35,6 +35,7 @@ #include #include #include +#include #define DA850_EVM_PHY_MASK 0x1 #define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ @@ -142,12 +143,23 @@ struct mtd_partition da850_evm_nandflash_partition[] = { }, }; +static struct davinci_aemif_timing da850_evm_nandflash_timing = { + .wsetup = 24, + .wstrobe = 21, + .whold = 14, + .rsetup = 19, + .rstrobe = 50, + .rhold = 0, + .ta = 20, +}; + static struct davinci_nand_pdata da850_evm_nandflash_data = { .parts = da850_evm_nandflash_partition, .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), .ecc_mode = NAND_ECC_HW, .ecc_bits = 4, .options = NAND_USE_FLASH_BBT, + .timing = &da850_evm_nandflash_timing, }; static struct resource da850_evm_nandflash_resource[] = { -- 1.6.2.4 From nsekhar at ti.com Tue Jul 6 05:04:19 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Tue, 6 Jul 2010 15:34:19 +0530 Subject: [PATCH 4/6] davinci: am17x/da830/omap-l137 evm: setup NAND flash timing In-Reply-To: <1278410661-18211-3-git-send-email-nsekhar@ti.com> References: <1278410661-18211-1-git-send-email-nsekhar@ti.com> <1278410661-18211-2-git-send-email-nsekhar@ti.com> <1278410661-18211-3-git-send-email-nsekhar@ti.com> Message-ID: <1278410661-18211-4-git-send-email-nsekhar@ti.com> From: Sudhakar Rajashekhara Setup the NAND flash timings for DA830 EVM. Before configuring the timing values, throughput calculation using dd command yielded 477 kB/s write and 970 kB/s read speed. After the timing configuration, the throughput was measured to be 2.5 MB/s write and 5.1 MB/s read. [Mukul Bhatnagar: actual calculation of timing values from the NAND datasheet] Signed-off-by: Sudhakar Rajashekhara Cc: Mukul Bhatnagar Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/board-da830-evm.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 212d970..c0dce08 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -29,6 +29,7 @@ #include #include #include +#include #define DA830_EVM_PHY_MASK 0x0 #define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ @@ -360,6 +361,16 @@ static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = { .pattern = da830_evm_nand_mirror_pattern }; +static struct davinci_aemif_timing da830_evm_nandflash_timing = { + .wsetup = 24, + .wstrobe = 21, + .whold = 14, + .rsetup = 19, + .rstrobe = 50, + .rhold = 0, + .ta = 20, +}; + static struct davinci_nand_pdata da830_evm_nand_pdata = { .parts = da830_evm_nand_partitions, .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions), @@ -368,6 +379,7 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = { .options = NAND_USE_FLASH_BBT, .bbt_td = &da830_evm_nand_bbt_main_descr, .bbt_md = &da830_evm_nand_bbt_mirror_descr, + .timing = &da830_evm_nandflash_timing, }; static struct resource da830_evm_nand_resources[] = { -- 1.6.2.4 From BNiebuhr at efjohnson.com Tue Jul 6 09:15:56 2010 From: BNiebuhr at efjohnson.com (Brian Niebuhr) Date: Tue, 6 Jul 2010 09:15:56 -0500 Subject: [spi-devel-general] [PATCH v2 0/1] davinci: spi: replaceexisting driver In-Reply-To: <002301cb1ce6$64fba3e0$2ef2eba0$@raj@ti.com> References: <1278110334-13943-1-git-send-email-bniebuhr@efjohnson.com> <002301cb1ce6$64fba3e0$2ef2eba0$@raj@ti.com> Message-ID: > On Sat, Jul 03, 2010 at 04:08:53, Brian Niebuhr wrote: > > I have included all of the recommended changes in this > version of the patch. > > I also combined the patches into one patch to avoid > bisecting issues. This > > makes the diff on davinci_spi.c very large. > > > > If people who are using this driver could test this version > of the driver > > and Ack it, I would appreciate it. > > > > ** NOTE ** > > > > This patch requires the EDMA patch at: > > > > > http://linux.davincidsp.com/pipermail/davinci-linux-open-sourc > e/2010-March/018022.html > > > > which is queued waiting on another driver fix, for DMA mode > to work correctly. > > > > > > Brian Niebuhr (1): > > davinci: spi: replace existing driver > > > > arch/arm/mach-davinci/board-dm355-evm.c | 10 + > > arch/arm/mach-davinci/board-dm355-leopard.c | 10 + > > arch/arm/mach-davinci/board-dm365-evm.c | 10 + > > arch/arm/mach-davinci/dm355.c | 12 +- > > arch/arm/mach-davinci/dm365.c | 12 +- > > arch/arm/mach-davinci/include/mach/spi.h | 37 +- > > drivers/spi/davinci_spi.c | 1328 > ++++++++++++--------------- > > 7 files changed, 648 insertions(+), 771 deletions(-) > > > > Quick update. > > I tested this patch on DM355 and DM365 EVMs. On DM355 all the > 3 modes (DMA, > Polled and Interrupt) worked fine. But in interrupt mode, on > DM355, if I set > "intr_level = 1", then kernel hangs during booting after printing > "spi spi0.0: DaVinci SPI driver in Interrupt mode" on the console. Sudhakar - When you changed the interrupt level, did you also change the IORESOURCE_IRQ entry for SPI0? Maybe we could set the interrupt level automatically based on the IORESOURCE_IRQ provided? The problem is, I don't see any way of doing that without a bunch of machine-specific ifdefs in the driver. > On DM365 only DMA and Polled mode worked fine. In interrupt > mode, whether I > set intr_level to ZERO or ONE, kernel booting hangs, similar to DM355. Does the interrupt mode of the existing driver work on DM365? I don't have one of these boards, so I can't debug the issue. If you have any ideas where the problem might be I'd appreciate the help in getting this resolved. If the change I mentioned above fixes the issue on DM355, then I've got to imagine that it's just a configuration issue of some sort on DM365. > I'll update the status of testing on OMAP-L1x EVMs later. > > I am using the Linux kernel from [1] for testing. > > [1] > http://git.kernel.org/?p=linux/kernel/git/khilman/linux-davinc > i.git;a=summary From todd.fischer at ridgerun.com Tue Jul 6 10:00:15 2010 From: todd.fischer at ridgerun.com (Todd Fischer) Date: Tue, 06 Jul 2010 09:00:15 -0600 Subject: DM355 - 256MB RAM memory issue In-Reply-To: <1278339242.18556.10.camel@tharma-laptop> References: <1278339242.18556.10.camel@tharma-laptop> Message-ID: <1278428415.14942.19703.camel@sax-lx> Tharmarajan, I believe you need to rebuild your codec server with a different memory map. Another idea is to have a hole in the kernel memory space (specify mem= in the kernel command line twice). I am not sure if the kernel version you are using for dm355 supports a hole in the kernel memory space. Todd On Mon, 2010-07-05 at 19:44 +0530, Tharmarajan Ganeshan wrote: > Hi All, > We are working on a DM355 processor based Development > board. The Board has 256MB mDDR RAM and 5MP image sensor MT9P031. > > We are using the kernel version 2.6.10 > > We have modified the driver code for capturing 5MP raw > image and converting this 5MP raw into YUV. For this 5MP image > capturing , we have reserved 30MB. > > We have allocated 56MB to the CMEM driver. > > The reserved memory 30MB and the 56MB memory for CMEM are > at top of the RAM. > > We are passing the remaining memory size to the kernel in > bootargs as mem=170M. And we are using the NFS rootfilesystem. > > But we are getting kernel hanging issues while testing the > IPNC_APP applications and 5MP still image capturing. Sometimes the > kernel is hanging while booting itself. > > > If we reserve the 30MB from the address region 0x83200000 > - 0x84FFFFFF and pass the memory size to kernel in bootargs as > mem=50M, then we are NOT having any issues in running the > applications. But we want to use the exact remaining memory. > > And also we are not able to program the NAND flash memory > in kernel level if we are not passing the mem=50M in bootargs. > > What could be the cause for this kernel hanging issue ? > > Are we missing any configurations while building the > kernel image ? > > Our Bootargs is : > mem=50M console=ttyS1,115200n8 root=/dev/nfs rootwait rw > ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 > nfsroot=192.168.1.99:/tftpboot/bellatrix_rootfilesystem,nolock > eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 > > > > Regards, > Tharmarajan G > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -------------- next part -------------- An HTML attachment was scrubbed... URL: From spoulsen at css-design.com Tue Jul 6 10:38:02 2010 From: spoulsen at css-design.com (Steve Poulsen) Date: Tue, 06 Jul 2010 10:38:02 -0500 Subject: Choosing filesytems JFFS2 or Ramdisk In-Reply-To: <130809.26915.qm@web24108.mail.ird.yahoo.com> References: <130809.26915.qm@web24108.mail.ird.yahoo.com> Message-ID: <4C334DDA.3000308@css-design.com> How about using CRAMFS with a JFFS or YAFFS partition which is for configuration/logging. If your writable partitions become corrupt, you only lose configuration/logging and not your entire filesystem. Steve On 07/05/2010 07:50 AM, rohan tabish wrote: > Hello > > I have an application requirement which performs alot of read write > operations on the file system so what is the recommended file system i > should use i guess using jffs2 is the option because having ram disk > as file system will not be able to save the configuration on next boot. > > There is also a problem with JFFS2 as file system doing many file > operations on flash will finish its life over the time as flash have > limited life > > Kindly suggest what should be the preferred way out > > Regard's > R0H at n > > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------- next part -------------- An HTML attachment was scrubbed... URL: From spoulsen at css-design.com Tue Jul 6 10:42:19 2010 From: spoulsen at css-design.com (Steve Poulsen) Date: Tue, 06 Jul 2010 10:42:19 -0500 Subject: Question on RAMDISK In-Reply-To: <403497.59727.qm@web24104.mail.ird.yahoo.com> References: <403497.59727.qm@web24104.mail.ird.yahoo.com> Message-ID: <4C334EDB.4030007@css-design.com> On 07/05/2010 05:52 AM, rohan tabish wrote: > Hello everyone > > I am using a ramdisk image to boot the system its takes around 7secs > to copy the ramdisk image from the flash to the RAM and then takes 3.6 > seconds after kernal uncompressing to the linux prompt > Reduce your RAMDISK size. Maybe use two partitions, one that is CRAMFS and another that is RAMDISK. > > I want to know that how to reduce this time of 7seconds. > > Also can anyone tell how to update the ramdisk image from the linux > prompt.e.g if i have created a file and now iwant it at the next boot > then how to make this file part of the old ramdisk image > How about booting the system quickly with CRAMFS, with a JFFS2 filesystem that is smaller and a RAM disk to match the JFFS2. At startup, you can mount the JFFS2 (hidden mount point) and RAM disk, copy the JFFS2 contents to RAM, then on shutdown, copy it back. > > Regard's > RT > > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------- next part -------------- An HTML attachment was scrubbed... URL: From spoulsen at css-design.com Tue Jul 6 10:47:26 2010 From: spoulsen at css-design.com (Steve Poulsen) Date: Tue, 06 Jul 2010 10:47:26 -0500 Subject: change the source of "simplewidget" and compile it has no effect on our own application, can we change the code and rebuild the lib simplewidget? In-Reply-To: <201007052025046875726@tpsee.com> References: <201007052025046875726@tpsee.com> Message-ID: <4C33500E.3000105@css-design.com> You should look at the DVSDK documentation which shows how to rebuild the CodecEngine "Codec Server". This process is a bit more tricky since it is building for two processors. The library that links with your application does not contain all the code for these components. There is the "server" portion which handles the request. I am not familiar with simplewidget, but it is likely that you are not getting the updated "server" which is going to be a mix of ARM/DSP code. Steve On 07/05/2010 07:25 AM, johnny wrote: > Hi all, > For some reason I have to change the code of > dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget/Button.c and Button.h, > I complie the direcotry of simplewidget for dm365 but the new > interface added by us can not be found. > I found only one simplewidget_dm365.a470MV in the whole directory > dvsdk_2_10_01_18 in directory > dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget/lib/, but after I > delete the file > dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget/lib/simplewidget_dm365.a470MV, > we can still compile our application successfully. > > How could this happen? > can we change the code and rebuild the lib simplewidget? > 2010-07-05 > ------------------------------------------------------------------------ > johnny > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------- next part -------------- An HTML attachment was scrubbed... URL: From spoulsen at css-design.com Tue Jul 6 10:48:03 2010 From: spoulsen at css-design.com (Steve Poulsen) Date: Tue, 06 Jul 2010 10:48:03 -0500 Subject: using jffs2 or ramdisk saving flash In-Reply-To: <790554.10296.qm@web24102.mail.ird.yahoo.com> References: <790554.10296.qm@web24102.mail.ird.yahoo.com> Message-ID: <4C335033.3040503@css-design.com> Using an uncompressed kernel will also help your speed. On 07/02/2010 01:51 AM, rohan tabish wrote: > I am using DM6446 have written device drivers each time my system > boots i need to do insmod to install many drivers.for jffs2 file > system these drivers are installed in flash that is lsmod displays the > flash address this means each time i boot i write to flash in real > product with time the flash will die so i have to switch to ramdisk > image but problem with this is that it takes alot of time to boot the > system. > > Anyone know how to save flash and boot quickly > > > Regard's > > RT > > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------- next part -------------- An HTML attachment was scrubbed... URL: From cring at ti.com Tue Jul 6 10:59:29 2010 From: cring at ti.com (Ring, Chris) Date: Tue, 6 Jul 2010 10:59:29 -0500 Subject: DM355 - 256MB RAM memory issue In-Reply-To: <1278428415.14942.19703.camel@sax-lx> References: <1278339242.18556.10.camel@tharma-laptop> <1278428415.14942.19703.camel@sax-lx> Message-ID: <92CDD168D1E81F4F9D3839DC45903FC6785F6BBE@dlee03.ent.ti.com> DM355 doesn't include a DSP, and therefore has no Codec Server. The Codecs are configured to run 'locally' on the ARM. Chris ________________________________ From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Todd Fischer Sent: Tuesday, July 06, 2010 8:00 AM To: tharma at e-consystems.com Cc: davinci-linux-open-source at linux.davincidsp.com; dhineshkumar; Mohamed Thalib H; maharajan Subject: Re: DM355 - 256MB RAM memory issue Tharmarajan, I believe you need to rebuild your codec server with a different memory map. Another idea is to have a hole in the kernel memory space (specify mem= in the kernel command line twice). I am not sure if the kernel version you are using for dm355 supports a hole in the kernel memory space. Todd On Mon, 2010-07-05 at 19:44 +0530, Tharmarajan Ganeshan wrote: Hi All, We are working on a DM355 processor based Development board. The Board has 256MB mDDR RAM and 5MP image sensor MT9P031. We are using the kernel version 2.6.10 We have modified the driver code for capturing 5MP raw image and converting this 5MP raw into YUV. For this 5MP image capturing , we have reserved 30MB. We have allocated 56MB to the CMEM driver. The reserved memory 30MB and the 56MB memory for CMEM are at top of the RAM. We are passing the remaining memory size to the kernel in bootargs as mem=170M. And we are using the NFS rootfilesystem. But we are getting kernel hanging issues while testing the IPNC_APP applications and 5MP still image capturing. Sometimes the kernel is hanging while booting itself. If we reserve the 30MB from the address region 0x83200000 - 0x84FFFFFF and pass the memory size to kernel in bootargs as mem=50M, then we are NOT having any issues in running the applications. But we want to use the exact remaining memory. And also we are not able to program the NAND flash memory in kernel level if we are not passing the mem=50M in bootargs. What could be the cause for this kernel hanging issue ? Are we missing any configurations while building the kernel image ? Our Bootargs is : mem=50M console=ttyS1,115200n8 root=/dev/nfs rootwait rw ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 nfsroot=192.168.1.99:/tftpboot/bellatrix_rootfilesystem,nolock eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 Regards, Tharmarajan G _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -------------- next part -------------- An HTML attachment was scrubbed... URL: From spoulsen at css-design.com Tue Jul 6 11:11:43 2010 From: spoulsen at css-design.com (Steve Poulsen) Date: Tue, 06 Jul 2010 11:11:43 -0500 Subject: DM355 - 256MB RAM memory issue In-Reply-To: <92CDD168D1E81F4F9D3839DC45903FC6785F6BBE@dlee03.ent.ti.com> References: <1278339242.18556.10.camel@tharma-laptop> <1278428415.14942.19703.camel@sax-lx> <92CDD168D1E81F4F9D3839DC45903FC6785F6BBE@dlee03.ent.ti.com> Message-ID: <4C3355BF.1030807@css-design.com> Chris, I've only went through this exercise on the DM64x products and wrongfully assumed that it would still build the two libraries for the DM3xx devices, even if it just finally linked them all together in the end. Steve On 07/06/2010 10:59 AM, Ring, Chris wrote: > DM355 doesn't include a DSP, and therefore has no Codec Server. The > Codecs are configured to run 'locally' on the ARM. > Chris > > ------------------------------------------------------------------------ > *From:* davinci-linux-open-source-bounces at linux.davincidsp.com > [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] > *On Behalf Of *Todd Fischer > *Sent:* Tuesday, July 06, 2010 8:00 AM > *To:* tharma at e-consystems.com > *Cc:* davinci-linux-open-source at linux.davincidsp.com; > dhineshkumar; Mohamed Thalib H; maharajan > *Subject:* Re: DM355 - 256MB RAM memory issue > > Tharmarajan, > > I believe you need to rebuild your codec server with a different > memory map. Another idea is to have a hole in the kernel memory > space (specify mem= in the kernel command line twice). I am not > sure if the kernel version you are using for dm355 supports a hole > in the kernel memory space. > > Todd > > On Mon, 2010-07-05 at 19:44 +0530, Tharmarajan Ganeshan wrote: >> Hi All, >> We are working on a DM355 processor based Development >> board. The Board has 256MB mDDR RAM and 5MP image sensor MT9P031. >> >> We are using the kernel version 2.6.10 >> >> We have modified the driver code for capturing 5MP >> raw image and converting this 5MP raw into YUV. For this 5MP >> image capturing , we have reserved 30MB. >> >> We have allocated 56MB to the CMEM driver. >> >> The reserved memory 30MB and the 56MB memory for >> CMEM are at top of the RAM. >> >> We are passing the remaining memory size to the >> kernel in bootargs as mem=170M. And we are using the NFS >> rootfilesystem. >> >> But we are getting kernel hanging issues while >> testing the IPNC_APP applications and 5MP still image capturing. >> Sometimes the kernel is hanging while booting itself. >> >> >> If we reserve the 30MB from the address region >> 0x83200000 - 0x84FFFFFF and pass the memory size to kernel in >> bootargs as mem=50M, then we are NOT having any issues in running >> the applications. But we want to use the exact remaining memory. >> >> And also we are not able to program the NAND flash >> memory in kernel level if we are not passing the mem=50M in bootargs. >> >> What could be the cause for this kernel hanging issue ? >> >> Are we missing any configurations while building the >> kernel image ? >> >> Our Bootargs is : >> mem=50M console=ttyS1,115200n8 root=/dev/nfs rootwait rw >> ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 >> nfsroot=192.168.1.99:/tftpboot/bellatrix_rootfilesystem,nolock >> eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 >> >> >> >> Regards, >> Tharmarajan G >> >> _______________________________________________ >> Davinci-linux-open-source mailing list >> Davinci-linux-open-source at linux.davincidsp.com >> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source >> > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------- next part -------------- An HTML attachment was scrubbed... URL: From spoulsen at css-design.com Tue Jul 6 11:14:31 2010 From: spoulsen at css-design.com (Steve Poulsen) Date: Tue, 06 Jul 2010 11:14:31 -0500 Subject: DM355 - 256MB RAM memory issue In-Reply-To: <4C3355BF.1030807@css-design.com> References: <1278339242.18556.10.camel@tharma-laptop> <1278428415.14942.19703.camel@sax-lx> <92CDD168D1E81F4F9D3839DC45903FC6785F6BBE@dlee03.ent.ti.com> <4C3355BF.1030807@css-design.com> Message-ID: <4C335667.2020404@css-design.com> Chris, Disregard my message. I mistakenly applied your response to one of my replies. Steve On 07/06/2010 11:11 AM, Steve Poulsen wrote: > Chris, > > I've only went through this exercise on the DM64x products and > wrongfully assumed that it would still build the two libraries for the > DM3xx devices, even if it just finally linked them all together in the > end. > > Steve > > On 07/06/2010 10:59 AM, Ring, Chris wrote: >> DM355 doesn't include a DSP, and therefore has no Codec Server. The >> Codecs are configured to run 'locally' on the ARM. >> Chris >> >> ------------------------------------------------------------------------ >> *From:* davinci-linux-open-source-bounces at linux.davincidsp.com >> [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] >> *On Behalf Of *Todd Fischer >> *Sent:* Tuesday, July 06, 2010 8:00 AM >> *To:* tharma at e-consystems.com >> *Cc:* davinci-linux-open-source at linux.davincidsp.com; >> dhineshkumar; Mohamed Thalib H; maharajan >> *Subject:* Re: DM355 - 256MB RAM memory issue >> >> Tharmarajan, >> >> I believe you need to rebuild your codec server with a different >> memory map. Another idea is to have a hole in the kernel memory >> space (specify mem= in the kernel command line twice). I am not >> sure if the kernel version you are using for dm355 supports a >> hole in the kernel memory space. >> >> Todd >> >> On Mon, 2010-07-05 at 19:44 +0530, Tharmarajan Ganeshan wrote: >>> Hi All, >>> We are working on a DM355 processor based >>> Development board. The Board has 256MB mDDR RAM and 5MP image >>> sensor MT9P031. >>> >>> We are using the kernel version 2.6.10 >>> >>> We have modified the driver code for capturing 5MP >>> raw image and converting this 5MP raw into YUV. For this 5MP >>> image capturing , we have reserved 30MB. >>> >>> We have allocated 56MB to the CMEM driver. >>> >>> The reserved memory 30MB and the 56MB memory for >>> CMEM are at top of the RAM. >>> >>> We are passing the remaining memory size to the >>> kernel in bootargs as mem=170M. And we are using the NFS >>> rootfilesystem. >>> >>> But we are getting kernel hanging issues while >>> testing the IPNC_APP applications and 5MP still image capturing. >>> Sometimes the kernel is hanging while booting itself. >>> >>> >>> If we reserve the 30MB from the address region >>> 0x83200000 - 0x84FFFFFF and pass the memory size to kernel in >>> bootargs as mem=50M, then we are NOT having any issues in >>> running the applications. But we want to use the exact remaining >>> memory. >>> >>> And also we are not able to program the NAND flash >>> memory in kernel level if we are not passing the mem=50M in >>> bootargs. >>> >>> What could be the cause for this kernel hanging issue ? >>> >>> Are we missing any configurations while building >>> the kernel image ? >>> >>> Our Bootargs is : >>> mem=50M console=ttyS1,115200n8 root=/dev/nfs rootwait rw >>> ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 >>> nfsroot=192.168.1.99:/tftpboot/bellatrix_rootfilesystem,nolock >>> eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 >>> >>> >>> >>> Regards, >>> Tharmarajan G >>> >>> _______________________________________________ >>> Davinci-linux-open-source mailing list >>> Davinci-linux-open-source at linux.davincidsp.com >>> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source >>> >> >> >> -- >> This message has been scanned for viruses and >> dangerous content by *MailScanner* , >> and is >> believed to be clean. >> >> >> _______________________________________________ >> Davinci-linux-open-source mailing list >> Davinci-linux-open-source at linux.davincidsp.com >> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source >> > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------- next part -------------- An HTML attachment was scrubbed... URL: From troy.kisky at boundarydevices.com Tue Jul 6 13:35:28 2010 From: troy.kisky at boundarydevices.com (Troy Kisky) Date: Tue, 06 Jul 2010 11:35:28 -0700 Subject: Rif: Re: [PATCH 3/3] ASoC: DaVinci: More accurate calculation for clock divider for McBSP (I2S) In-Reply-To: References: Message-ID: <4C337770.3070007@boundarydevices.com> raffaele.recalcati at bticino.it wrote: > -----Troy Kisky ha scritto: ----- > >> Per: Raffaele Recalcati >> Da: Troy Kisky >> Data: 02/07/2010 22.57 >> Cc: davinci-linux-open-source at linux.davincidsp.com, Mark Brown >> , Raffaele Recalcati >> >> Oggetto: Re: [PATCH 3/3] ASoC: DaVinci: More accurate calculation for >> clock divider for McBSP (I2S) >> >> Raffaele Recalcati wrote: >>> @@ -447,6 +448,24 @@ static int davinci_i2s_hw_params(struct >> snd_pcm_substream *substream, > 8 - 1); >>> + if (dev->i2s_accurate_clock) { >>> + clk_div = 256; >>> + do { >>> + > framesize = (freq / (--clk_div)) / >>> + params->rate_num * >>> + params-> > rate_den; >>> + > } while (((framesize < 33) || (framesize > 4095)) >> && >>> + (clk_div)); >>> + clk_div--; >>> + srgr |= DAVINCI_MCBSP_SRGR_FPER > (framesize - 1); >>> + } else { >>> + /* symmetric waveforms */ >>> + > clk_div = freq / (mcbsp_word_length * 16) / >>> + params-> > rate_num * params->rate_den; >>> + srgr |= DAVINCI_MCBSP_SRGR_FPER > (mcbsp_word_length * >>> + > 16 - 1); >>> + } >>> + >>> /* symmetric waveforms */ >>> clk_div = freq / (mcbsp_word_length * 16) / >>> params->rate_num * params-> > rate_den; >> Can you test to see if this works to replace all the above ? >> >> unsigned cycles; >> framesize = mcbsp_word_length * 16; >> cycles = (freq / params->rate_num) * params-> > rate_den; >> clk_div = cycles / framesize; >> >> if (dev->i2s_accurate_clock) { >> framesize = cycles / clk_div; >> if (framesize > 4096)) >> framesize = 4096; >> } >> srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1); > > yes, it works. > Now I'm trying to understand the differences: > > your solution with i2s_accurate_clock enabled: > davinci-asp davinci-asp.0: framesize = 32 > davinci-asp davinci-asp.0: clk_div = 86 > > your solution with i2s_accurate_clock NOT enabled: > > davinci-asp davinci-asp.0: framesize = 32 > > davinci-asp davinci-asp.0: clk_div = 86 > > the same. > > > > my solution with i2s_accurate_clock enabled: > > davinci-asp davinci-asp.0: my framesize = 33 > davinci-asp > davinci-asp.0: clk_div = 82 > > here the continuous serial clock is faster > > my solution with i2s_accurate_clock NOT enabled > davinci-asp davinci-asp.0: my framesize = 32 > davinci-asp davinci-asp.0: clk_div = 86 > > here the continuous > serial clock is the same as yours. > > > it "seems" better my and Davide solution. > Indeed, your algorithm may produce more accurate results for the specific rate that you tested for. However, that seems more luck than anything. How do you know that a frame size of 33 will always give more accurate results than a frame size of 32? If your going to loop, you need to calculate the error and minimize that and not just stop when framesize finally reaches your minimum size of 33. Also, you may want to stop when your framesize > twice your minimum framesize. Otherwise you may end up with a very very fast clock most of which is garbage cycles. Troy From raffaele.recalcati at bticino.it Thu Jul 1 00:59:51 2010 From: raffaele.recalcati at bticino.it (raffaele.recalcati at bticino.it) Date: Thu, 1 Jul 2010 07:59:51 +0200 Subject: Rif: Re: [PATCH] spi: davinci: Added support for chip select using gpio In-Reply-To: References: <1277707655-3468-1-git-send-email-lamiaposta71@gmail.com>, Message-ID: -----glikely at secretlab.ca ha scritto: ----- >Per:?Raffaele?Recalcati?,?Brian?Niebuhr > >Da:?Grant?Likely? >Inviato?da:?glikely at secretlab.ca >Data:?01/07/2010?01.03 >Cc:?davinci-linux-open-source at linux.davincidsp.com,?Raffaele >Recalcati?,?Davide?Bonfanti >,?Russell?King?, >Sandeep?Paulraj?,?Cyril?Chemparathy?, >Miguel?Aguilar?,?Thomas?Koeller >,?David?Brownell >,?Philby?John?, >Sudhakar?Rajashekhara?, >linux-arm-kernel at lists.infradead.org,?linux-kernel at vger.kernel.org, >spi-devel-general at lists.sourceforge.net >Oggetto:?Re:?[PATCH]?spi:?davinci:?Added?support?for?chip?select >using?gpio > >On?Mon,?Jun?28,?2010?at?12:47?AM,?Raffaele?Recalcati >?wrote: >>?From:?Raffaele?Recalcati? >> >>????It?is?not?everytime?possible,?due?to?hardware?constraints, >>????to?use?the?hw?chip?select?available?on?spi?port. >>????So?I?add?this?possibility?using?a?gpio?as?chip?select. >>????If?controller_data?variable?is?not?null?it?is >>????the?gpio?to?be?used?as?chip?select. >>????The?default?case?is?compatible?with?evmdm365. >>????This?patch?has?been?developed?against?the >> >http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci. >git >>????git?tree?and?has?been?tested?on?bmx?board?(similar?to?dm365?evm >but?with >>????gpio?as?spi?chip?select). >> >>?Signed-off-by:?Raffaele?Recalcati? >>?Signed-off-by:?Davide?Bonfanti? > >The?davinci?SPI?driver?is?getting?completely?replaced?(as?soon?as?I >receive?the?respun?patches),?and?I?assume?this?patch?will?no?longer >apply?after?the?fact,?so?I'm?not?going?to?pick?this?patch?up.??You >should?coordinate?with?Brian?Niebuhr?to?get?this?feature?into?his?new >driver. I'm not very lucky with davinci-linux-open-source patching. Thank you for the information. The patch is really simple and so it will be not a real problem to up port it. I'd like anyway a timing roadmap, because, if now the best kernel choose for dm365 is surely http://arago-project.org/git/projects/linux-davinci.git because of dvsdk (video codec) compatibility, it is possible that next year 2.6.36 will be stable and compatible to dvsdk (video codec). The kernel of dm365 (that is a video processor) has to be compatible to its video codec. How to manage the transition? >Cheers, >g. > >>?--- >>??arch/arm/mach-davinci/dm365.c?|???10?++++++---- >>??drivers/spi/davinci_spi.c?????|???27?++++++++++++++++++--------- >>??2?files?changed,?24?insertions(+),?13?deletions(-) >> >>?diff?--git?a/arch/arm/mach-davinci/dm365.c >b/arch/arm/mach-davinci/dm365.c >>?index?a146849..42fd4a4?100644 >>?---?a/arch/arm/mach-davinci/dm365.c >>?+++?b/arch/arm/mach-davinci/dm365.c >>?@@?-677,10?+677,12?@@?void?__init?dm365_init_spi0(unsigned >chipselect_mask, >>????????davinci_cfg_reg(DM365_SPI0_SDO); >> >>????????/*?not?all?slaves?will?be?wired?up?*/ >>?-???????if?(chipselect_mask?&?BIT(0)) >>?-???????????????davinci_cfg_reg(DM365_SPI0_SDENA0); >>?-???????if?(chipselect_mask?&?BIT(1)) >>?-???????????????davinci_cfg_reg(DM365_SPI0_SDENA1); >>?+???????if??(!((unsigned?long)?info->controller_data))?{ >>?+???????????????if?(chipselect_mask?&?BIT(0)) >>?+???????????????????????davinci_cfg_reg(DM365_SPI0_SDENA0); >>?+???????????????if?(chipselect_mask?&?BIT(1)) >>?+???????????????????????davinci_cfg_reg(DM365_SPI0_SDENA1); >>?+???????} >> >>????????spi_register_board_info(info,?len); >> >>?diff?--git?a/drivers/spi/davinci_spi.c?b/drivers/spi/davinci_spi.c >>?index?95afb6b..621ae46?100644 >>?---?a/drivers/spi/davinci_spi.c >>?+++?b/drivers/spi/davinci_spi.c >>?@@?-29,6?+29,7?@@ >>??#include? >>??#include? >> >>?+#include? >>??#include? >>??#include? >> >>?@@?-270,18?+271,26?@@?static?void?davinci_spi_chipselect(struct >spi_device?*spi,?int?value) >>????????pdata?=?davinci_spi->pdata; >> >>????????/* >>?-????????*?Board?specific?chip?select?logic?decides?the?polarity >and?cs >>?-????????*?line?for?the?controller >>?-????????*/ >>?+???????*?Board?specific?chip?select?logic?decides?the?polarity?and >cs >>?+???????*?line?for?the?controller >>?+???????*/ >>????????if?(value?==?BITBANG_CS_INACTIVE)?{ >>?-???????????????set_io_bits(davinci_spi->base?+?SPIDEF, >CS_DEFAULT); >>?- >>?-???????????????data1_reg_val?|=?CS_DEFAULT?<>?-???????????????iowrite32(data1_reg_val,?davinci_spi->base?+ >SPIDAT1); >>?- >>?+???????????????if??((unsigned?long)?spi->controller_data)?{ >>?+???????????????????????gpio_set_value(spi->controller_data,?\ >>?+???????????????????????????????!(spi->mode?&?SPI_CS_HIGH)); >>?+???????????????}?else?{ >>?+???????????????????????set_io_bits(davinci_spi->base?+?SPIDEF, >CS_DEFAULT); >>?+ >>?+???????????????????????data1_reg_val?|=?CS_DEFAULT?<< >SPIDAT1_CSNR_SHIFT; >>?+???????????????????????iowrite32(data1_reg_val,?davinci_spi->base >+?SPIDAT1); >>?+???????????????} >>????????????????while?((ioread32(davinci_spi->base?+?SPIBUF) >>?-???????????????????????????????????????&?SPIBUF_RXEMPTY_MASK)?== >0) >>?+???????????????????????????????&?SPIBUF_RXEMPTY_MASK)?==?0) >>????????????????????????cpu_relax(); >>?+???????}?else?{ >>?+???????????????if??((unsigned?long)?spi->controller_data) >>?+???????????????????????gpio_set_value(spi->controller_data,?\ >>?+???????????????????????????????(spi->mode?&?SPI_CS_HIGH)); >>????????} >>??} >> >>?-- >>?1.7.0.4 >> >> > > > >-- >Grant?Likely,?B.Sc.,?P.Eng. >Secret?Lab?Technologies?Ltd. Ce message, ainsi que tous les fichiers joints ? ce message, peuvent contenir des informations sensibles et/ ou confidentielles ne devant pas ?tre divulgu?es. Si vous n'?tes pas le destinataire de ce message (ou que vous recevez ce message par erreur), nous vous remercions de le notifier imm?diatement ? son exp?diteur, et de d?truire ce message. Toute copie, divulgation, modification, utilisation ou diffusion, non autoris?e, directe ou indirecte, de tout ou partie de ce message, est strictement interdite. This e-mail, and any document attached hereby, may contain confidential and/or privileged information. If you are not the intended recipient (or have received this e-mail in error) please notify the sender immediately and destroy this e-mail. Any unauthorized, direct or indirect, copying, disclosure, distribution or other use of the material or parts thereof is strictly forbidden. From broonie at opensource.wolfsonmicro.com Thu Jul 1 09:35:40 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Thu, 1 Jul 2010 15:35:40 +0100 Subject: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S) In-Reply-To: <1277905678-4695-2-git-send-email-lamiaposta71@gmail.com> References: <1277905678-4695-1-git-send-email-lamiaposta71@gmail.com> <1277905678-4695-2-git-send-email-lamiaposta71@gmail.com> Message-ID: <20100701143540.GC8742@rakim.wolfsonmicro.main> On Wed, Jun 30, 2010 at 03:47:56PM +0200, Raffaele Recalcati wrote: > +static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, > + int div_id, int div) > +{ > + struct davinci_mcbsp_dev *dev = cpu_dai->private_data; > + int srgr; > + > + dev->clk_div = div; > + return 0; > +} As previously mentioned this should check the div_id argument. > + switch (master) { > + case SND_SOC_DAIFMT_CBS_CFS: ... > + case SND_SOC_DAIFMT_CBM_CFS: ... > + default: > + /* Clock and frame sync given from external sources */ The two remaining options (_CBM_CFM and _CBS_CFM) are different, your description matches _CBM_CFM. > + if (master == SND_SOC_DAIFMT_CBS_CFS || > + master == SND_SOC_DAIFMT_CBS_CFM) { Switch statement again. > + if (master == SND_SOC_DAIFMT_CBS_CFS || > + master == SND_SOC_DAIFMT_CBS_CFM) { > + rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0); > + xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0); > + } else { ...and another. Please fix all these. From broonie at opensource.wolfsonmicro.com Thu Jul 1 09:36:38 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Thu, 1 Jul 2010 15:36:38 +0100 Subject: [PATCH 2/3] ASoC: DaVinci: Added selection of clk input pin for McBSP In-Reply-To: <1277905678-4695-3-git-send-email-lamiaposta71@gmail.com> References: <1277905678-4695-1-git-send-email-lamiaposta71@gmail.com> <1277905678-4695-3-git-send-email-lamiaposta71@gmail.com> Message-ID: <20100701143638.GD8742@rakim.wolfsonmicro.main> On Wed, Jun 30, 2010 at 03:47:57PM +0200, Raffaele Recalcati wrote: > + /* To be used when cpu gets clock from external pin */ > + int clk_input_pin; > + As previously indicated please say how to use this. > + default: > + printk(KERN_ERR "%s:bad clk_input_pin\n", __func__); Use dev_err(). From broonie at opensource.wolfsonmicro.com Thu Jul 1 10:01:40 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Thu, 1 Jul 2010 16:01:40 +0100 Subject: [PATCH 3/3] ASoC: DaVinci: Added fast clock timing for McBSP (I2S) In-Reply-To: <1277905678-4695-4-git-send-email-lamiaposta71@gmail.com> References: <1277905678-4695-1-git-send-email-lamiaposta71@gmail.com> <1277905678-4695-4-git-send-email-lamiaposta71@gmail.com> Message-ID: <20100701150140.GE8742@rakim.wolfsonmicro.main> On Wed, Jun 30, 2010 at 03:47:58PM +0200, Raffaele Recalcati wrote: > + /* > + * This define works when both clock and FS are output for the cpu > + * and makes clock very fast (FS is not symmetrical, but sampling > + * frequency is better approximated > + */ > + bool i2s_fast_clock; I'm having a hard time following the description here - which clock is being made very fast? The output clocks, which are the ones people can observe, will presumably not suddenly start running very fast. It's probably better to rename this option to reflect the actual function (trading off between frequency accuracy and mark/space ratio) rather than the way it's implemented internally. > - srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * > - 16 - 1); > + if (dev->i2s_fast_clock) { > + clk_div = 256; > + do { > + framesize = (freq / (--clk_div)) / > + params->rate_num * > + params->rate_den; > + } while (((framesize < 33) || (framesize > 4095)) && > + (clk_div)); > + clk_div--; > + srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1); > + } else { > + /* symmetric waveforms */ > + clk_div = freq / (mcbsp_word_length * 16) / > + params->rate_num * params->rate_den; > + srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * > + 16 - 1); > + } Hrm. This doesn't really correspond to your commit message at all. Your commit message makes it sound like you've changed something about the clocking setup of the device, such as adding another clock source, but what you've actually done here is change the method used to calculate the divider. I'm *guessing* that the actual effect of your change is that you will normally end up selecting a very much higher bit clock than would otherwise be the case. It strikes me that there must be a better algorithm for the calculation - for example, working up from the minimum clock rate - which will give the same results as we currently have where the driver is already generating accurate rates. From broonie at opensource.wolfsonmicro.com Thu Jul 1 10:03:10 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Thu, 1 Jul 2010 16:03:10 +0100 Subject: [PATCH 3/3] ASoC: DaVinci: Added fast clock timing for McBSP (I2S) In-Reply-To: <1277905678-4695-4-git-send-email-lamiaposta71@gmail.com> References: <1277905678-4695-1-git-send-email-lamiaposta71@gmail.com> <1277905678-4695-4-git-send-email-lamiaposta71@gmail.com> Message-ID: <20100701150310.GF8742@rakim.wolfsonmicro.main> On Wed, Jun 30, 2010 at 03:47:58PM +0200, Raffaele Recalcati wrote: > From: Raffaele Recalcati > > i2s_fast_clock switch can be used to have a better approximate Oh, and please look at the CC list for these posts. You're CCing *very* widely and at least one address (chaithrika at ti.com) actually bounces. From raffaele.recalcati at bticino.it Mon Jul 5 00:05:43 2010 From: raffaele.recalcati at bticino.it (raffaele.recalcati at bticino.it) Date: Mon, 5 Jul 2010 07:05:43 +0200 Subject: Rif: Re: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S) In-Reply-To: <20100704091512.GE16825@opensource.wolfsonmicro.com> References: <1278090747-5124-1-git-send-email-lamiaposta71@gmail.com> <1278090747-5124-2-git-send-email-lamiaposta71@gmail.com>, <20100704091512.GE16825@opensource.wolfsonmicro.com> Message-ID: -----Mark Brown ha scritto: ----- >Per:?Raffaele?Recalcati? >Da:?Mark?Brown? >Data:?04/07/2010?11.15 >Cc:?davinci-linux-open-source at linux.davincidsp.com,?Raffaele >Recalcati?,?Davide?Bonfanti >,?lrg at slimlogic.co.uk >Oggetto:?Re:?[PATCH?1/3]?ASoC:?DaVinci:?Added?two?clocking >possibilities?to?McBSP?(I2S) > >On?Fri,?Jul?02,?2010?at?07:12:25PM?+0200,?Raffaele?Recalcati?wrote: >>?From:?Raffaele?Recalcati? >> >>?????Added?two?clocking?options?for?dm365?McBSP?peripheral?when?used >>?????with?I2S?timings,?that?are?SND_SOC_DAIFMT_CBS_CFS?(the?cpu >generates > >You've?not?sent?any?of?these?patches?to?the?ALSA?list?or?to?Liam >Girdwood,?the?other?ASoC?maintainer.??In?general?you?should?be >looking >to?include?at?least?the?subsystem?maintainers?and?mailing?list?for >the >relevant?code,?anyone?who?actively?works?on?the?driver?and?possibly >an >architecture-specific?list. ok, but, first I was using scripts/get_maintainer.pl, but it created a too long cc list. .... thinking .... anyway, if get_mantainer is not right, it is better to fix it, instead of guessing who to send the patches to. So I'll use this -cc list from the script. scripts/get_maintainer.pl -f sound/soc/davinci/davinci-i2s.c Liam Girdwood Mark Brown Jaroslav Kysela Takashi Iwai Troy Kisky Raffaele Recalcati Davide Bonfanti alsa-devel at alsa-project.org linux-kernel at vger.kernel.org >The?first?two?patches?look?OK,?though?I'd?like?to?see?some?DaVinci >people?confirming?they're?OK. I hope they answer. Raffaele Recalcati Driver Linux BSP Bticino S.p.A. Via L.Manara 4, Erba (CO), Italy Tel:??+39.(0)31.653.252 Tel2: +39.(0)31.653.652 Fax: +39.(0)31.653.283 E-mail: raffaele.recalcati at bticino.it Web: www.bticino.it Bticino Legrand Zucchini Cablofil Ortronics Ce message, ainsi que tous les fichiers joints ? ce message, peuvent contenir des informations sensibles et/ ou confidentielles ne devant pas ?tre divulgu?es. Si vous n'?tes pas le destinataire de ce message (ou que vous recevez ce message par erreur), nous vous remercions de le notifier imm?diatement ? son exp?diteur, et de d?truire ce message. Toute copie, divulgation, modification, utilisation ou diffusion, non autoris?e, directe ou indirecte, de tout ou partie de ce message, est strictement interdite. This e-mail, and any document attached hereby, may contain confidential and/or privileged information. If you are not the intended recipient (or have received this e-mail in error) please notify the sender immediately and destroy this e-mail. Any unauthorized, direct or indirect, copying, disclosure, distribution or other use of the material or parts thereof is strictly forbidden. From lamiaposta71 at gmail.com Mon Jul 5 06:08:26 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Mon, 5 Jul 2010 13:08:26 +0200 Subject: [PATCH] ASoC: DaVinci: More accurate calculation for clock divider for McBSP (I2S) Message-ID: <1278328106-3388-1-git-send-email-lamiaposta71@gmail.com> From: Raffaele Recalcati i2s_accurate_sck switch can be used to have a better approximate sampling frequency. The trade off is between more accurate clock (fast clock) and less accurate clock (slow clock). The waveform will be not symmetric. Probably it is possible to get a better algorithm for calculating the divider, trying to keep a slower clock as possible. This patch has been developed against the http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git git tree and has been tested on bmx board (similar to dm365 evm, but using uda1345 as external audio codec). Signed-off-by: Raffaele Recalcati Signed-off-by: Davide Bonfanti --- arch/arm/mach-davinci/include/mach/asp.h | 33 ++++++++++++++++++++++++++++++ sound/soc/davinci/davinci-i2s.c | 28 ++++++++++++++++++++----- 2 files changed, 55 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index 0847d21..5149abe 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -73,6 +73,39 @@ struct snd_platform_data { */ int clk_input_pin; + /* + * This flag works when both clock and FS are outputs for the cpu + * and makes clock more accurate (FS is not symmetrical and the + * clock is very fast. + * The clock becoming faster is named + * i2s continuous serial clocl (I2S_SCK) and it is an externally + * visible bit clock. + * + * first line : WordSelect + * second line : ContinuousSerialClock + * third line: SerialData + * + * SYMMETRICAL APPROACH: + * _______________________ LEFT + * _| RIGHT |______________________| + * _ _ _ _ _ _ _ _ + * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_ + * _ _ _ _ _ _ _ _ + * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_ + * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ + * + * ACCURATE CLOCK APPROACH: + * ______________ LEFT + * _| RIGHT |_______________________________| + * _ _ _ _ _ _ _ _ _ + * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| | + * _ _ _ _ dummy cycles + * _/ \_ ... _/ \_/ \_ ... _/ \__________________ + * \_/ \_/ \_/ \_/ + * + */ + bool i2s_accurate_sck; + /* McASP specific fields */ int tdm_slots; u8 op_mode; diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c index 17f594f..e6dcd81 100644 --- a/sound/soc/davinci/davinci-i2s.c +++ b/sound/soc/davinci/davinci-i2s.c @@ -122,6 +122,7 @@ static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = { }; struct davinci_mcbsp_dev { + struct device *dev; struct davinci_pcm_dma_params dma_params[2]; void __iomem *base; #define MOD_DSP_A 0 @@ -154,6 +155,7 @@ struct davinci_mcbsp_dev { unsigned int fmt; int clk_div; int clk_input_pin; + bool i2s_accurate_sck; }; static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, @@ -296,7 +298,7 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, pcr |= DAVINCI_MCBSP_PCR_SCLKME; break; default: - dev_err(&pdev->dev, "bad clk_input_pin\n"); + dev_err(dev->dev, "bad clk_input_pin\n"); return -EINVAL; } @@ -447,11 +449,23 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, DAVINCI_MCBSP_SRGR_CLKSM; srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1); - /* symmetric waveforms */ - clk_div = freq / (mcbsp_word_length * 16) / - params->rate_num * params->rate_den; - srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * - 16 - 1); + if (dev->i2s_accurate_sck) { + clk_div = 256; + do { + framesize = (freq / (--clk_div)) / + params->rate_num * + params->rate_den; + } while (((framesize < 33) || (framesize > 4095)) && + (clk_div)); + clk_div--; + srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1); + } else { + /* symmetric waveforms */ + clk_div = freq / (mcbsp_word_length * 16) / + params->rate_num * params->rate_den; + srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * + 16 - 1); + } clk_div &= 0xFF; srgr |= clk_div; break; @@ -662,6 +676,7 @@ static int davinci_i2s_probe(struct platform_device *pdev) dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size = pdata->sram_size_capture; dev->clk_input_pin = pdata->clk_input_pin; + dev->i2s_accurate_sck = pdata->i2s_accurate_sck; } dev->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(dev->clk)) { @@ -694,6 +709,7 @@ static int davinci_i2s_probe(struct platform_device *pdev) goto err_free_mem; } dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start; + dev->dev = &pdev->dev; davinci_i2s_dai.private_data = dev; davinci_i2s_dai.capture.dma_data = dev->dma_params; -- 1.7.0.4 From raffaele.recalcati at bticino.it Mon Jul 5 06:10:53 2010 From: raffaele.recalcati at bticino.it (raffaele.recalcati at bticino.it) Date: Mon, 5 Jul 2010 13:10:53 +0200 Subject: Rif: Re: [PATCH 3/3] ASoC: DaVinci: More accurate calculation for clock divider for McBSP (I2S) Message-ID: -----Troy Kisky ha scritto: ----- >Per:?Raffaele?Recalcati? >Da:?Troy?Kisky? >Data:?02/07/2010?22.57 >Cc:?davinci-linux-open-source at linux.davincidsp.com,?Mark?Brown >,?Raffaele?Recalcati > >Oggetto:?Re:?[PATCH?3/3]?ASoC:?DaVinci:?More?accurate?calculation?for >clock?divider?for?McBSP?(I2S) > >Raffaele?Recalcati?wrote: >>?@@?-447,6?+448,24?@@?static?int?davinci_i2s_hw_params(struct >snd_pcm_substream?*substream, >> 8?-?1); >>?+???? ???? if?(dev->i2s_accurate_clock)?{ >>?+???? ???? ???? clk_div?=?256; >>?+???? ???? ???? do?{ >>?+ framesize?=?(freq?/?(--clk_div))?/ >>?+???? ???? ???? ???? params->rate_num?* >>?+???? ???? ???? ???? ???? params-> rate_den; >>?+ }?while?(((framesize??4095)) >&& >>?+???? ???? ???? ???? ?(clk_div)); >>?+???? ???? ???? clk_div--; >>?+???? ???? ???? srgr?|=?DAVINCI_MCBSP_SRGR_FPER (framesize?-?1); >>?+???? ???? }?else?{ >>?+???? ???? ???? /*?symmetric?waveforms?*/ >>?+ clk_div?=?freq?/?(mcbsp_word_length?*?16)?/ >>?+???? ???? ???? ???? ??params-> rate_num?*?params->rate_den; >>?+???? ???? ???? srgr?|=?DAVINCI_MCBSP_SRGR_FPER (mcbsp_word_length?* >>?+ 16?-?1); >>?+???? ???? } >>?+ >>?????? ???? /*?symmetric?waveforms?*/ >>?????? ???? clk_div?=?freq?/?(mcbsp_word_length?*?16)?/ >>?????? ???? ???? ??params->rate_num?*?params-> rate_den; > >Can?you?test?to?see?if?this?works?to?replace?all?the?above?? > >???? ???? unsigned?cycles; >???? ???? framesize?=?mcbsp_word_length?*?16; >???? ???? cycles?=?(freq?/?params->rate_num)?*?params-> rate_den; >????? ???? clk_div?=?cycles?/?framesize; > >???? ???? if?(dev->i2s_accurate_clock)?{ >???? ???? ???? framesize?=?cycles?/?clk_div; >???? ???? ???? if?(framesize?>?4096)) >???? ???? ???? ???? framesize?=?4096; >???? ???? } >???? ???? srgr?|=?DAVINCI_MCBSP_SRGR_FPER(framesize?-?1); yes, it works. Now I'm trying to understand the differences: your solution with i2s_accurate_clock enabled: davinci-asp davinci-asp.0: framesize = 32 davinci-asp davinci-asp.0: clk_div = 86 your solution with i2s_accurate_clock NOT enabled: davinci-asp davinci-asp.0: framesize = 32 davinci-asp davinci-asp.0: clk_div = 86 the same. my solution with i2s_accurate_clock enabled: davinci-asp davinci-asp.0: my framesize = 33 davinci-asp davinci-asp.0: clk_div = 82 here the continuous serial clock is faster my solution with i2s_accurate_clock NOT enabled davinci-asp davinci-asp.0: my framesize = 32 davinci-asp davinci-asp.0: clk_div = 86 here the continuous serial clock is the same as yours. it "seems" better my and Davide solution. Raffaele Recalcati Driver Linux BSP Bticino S.p.A. Via L.Manara 4, Erba (CO), Italy Tel:??+39.(0)31.653.252 Tel2: +39.(0)31.653.652 Fax: +39.(0)31.653.283 E-mail: raffaele.recalcati at bticino.it Web: www.bticino.it Bticino Legrand Zucchini Cablofil Ortronics Ce message, ainsi que tous les fichiers joints ? ce message, peuvent contenir des informations sensibles et/ ou confidentielles ne devant pas ?tre divulgu?es. Si vous n'?tes pas le destinataire de ce message (ou que vous recevez ce message par erreur), nous vous remercions de le notifier imm?diatement ? son exp?diteur, et de d?truire ce message. Toute copie, divulgation, modification, utilisation ou diffusion, non autoris?e, directe ou indirecte, de tout ou partie de ce message, est strictement interdite. This e-mail, and any document attached hereby, may contain confidential and/or privileged information. If you are not the intended recipient (or have received this e-mail in error) please notify the sender immediately and destroy this e-mail. Any unauthorized, direct or indirect, copying, disclosure, distribution or other use of the material or parts thereof is strictly forbidden. From lamiaposta71 at gmail.com Tue Jul 6 03:39:03 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Tue, 6 Jul 2010 10:39:03 +0200 Subject: [PATCH 2/3] ASoC: DaVinci: Added selection of clk input pin for McBSP In-Reply-To: <1278405544-3852-1-git-send-email-lamiaposta71@gmail.com> References: <1278405544-3852-1-git-send-email-lamiaposta71@gmail.com> Message-ID: <1278405544-3852-3-git-send-email-lamiaposta71@gmail.com> From: Raffaele Recalcati When McBSP peripheral gets the clock from an external pin, there are three possible chooses, MCBSP_CLKX, MCBSP_CLKR and MCBSP_CLKS. evm-dm365 uses MCBSP_CLKR, instead in bmx board I have a different hardware connection and I use MCBSP_CLKS, so I have added this possibility. This patch has been developed against the: http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git git tree and has been tested on bmx board (similar to dm365 evm) Signed-off-by: Raffaele Recalcati Signed-off-by: Davide Bonfanti --- arch/arm/mach-davinci/include/mach/asp.h | 15 +++++++++++++++ sound/soc/davinci/davinci-i2s.c | 29 ++++++++++++++++++++++++----- 2 files changed, 39 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index 834725f..0847d21 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -63,6 +63,16 @@ struct snd_platform_data { unsigned sram_size_playback; unsigned sram_size_capture; + /* + * If McBSP peripheral gets the clock from an external pin, + * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR + * and MCBSP_CLKS. + * Depending on different hardware connections it is possible + * to use this setting to change the behaviour of McBSP + * driver. The dm365_clk_input_pin enum is available for dm365 + */ + int clk_input_pin; + /* McASP specific fields */ int tdm_slots; u8 op_mode; @@ -78,6 +88,11 @@ enum { MCASP_VERSION_2, /* DA8xx/OMAPL1x */ }; +enum dm365_clk_input_pin { + MCBSP_CLKR = 0, /* DM365 */ + MCBSP_CLKS, +}; + #define INACTIVE_MODE 0 #define TX_MODE 1 #define RX_MODE 2 diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c index c8f038c..ba5644b 100644 --- a/sound/soc/davinci/davinci-i2s.c +++ b/sound/soc/davinci/davinci-i2s.c @@ -122,6 +122,7 @@ static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = { }; struct davinci_mcbsp_dev { + struct device *dev; struct davinci_pcm_dma_params dma_params[2]; void __iomem *base; #define MOD_DSP_A 0 @@ -153,6 +154,7 @@ struct davinci_mcbsp_dev { unsigned int fmt; int clk_div; + int clk_input_pin; }; static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, @@ -279,11 +281,26 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, DAVINCI_MCBSP_PCR_CLKRM; break; case SND_SOC_DAIFMT_CBM_CFS: - /* McBSP CLKR pin is the input for the Sample Rate Generator. - * McBSP FSR and FSX are driven by the Sample Rate Generator. */ - pcr = DAVINCI_MCBSP_PCR_SCLKME | - DAVINCI_MCBSP_PCR_FSXM | - DAVINCI_MCBSP_PCR_FSRM; + pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM; + /* + * Selection of the clock input pin that is the + * input for the Sample Rate Generator. + * McBSP FSR and FSX are driven by the Sample Rate + * Generator. + */ + switch (dev->clk_input_pin) { + case MCBSP_CLKS: + pcr |= DAVINCI_MCBSP_PCR_CLKXM | + DAVINCI_MCBSP_PCR_CLKRM; + break; + case MCBSP_CLKR: + pcr |= DAVINCI_MCBSP_PCR_SCLKME; + break; + default: + dev_err(dev->dev, "bad clk_input_pin\n"); + return -EINVAL; + } + break; case SND_SOC_DAIFMT_CBM_CFM: /* codec is master */ @@ -644,6 +661,7 @@ static int davinci_i2s_probe(struct platform_device *pdev) pdata->sram_size_playback; dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size = pdata->sram_size_capture; + dev->clk_input_pin = pdata->clk_input_pin; } dev->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(dev->clk)) { @@ -676,6 +694,7 @@ static int davinci_i2s_probe(struct platform_device *pdev) goto err_free_mem; } dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start; + dev->dev = &pdev->dev; davinci_i2s_dai.private_data = dev; davinci_i2s_dai.capture.dma_data = dev->dma_params; -- 1.7.0.4 From lamiaposta71 at gmail.com Tue Jul 6 03:39:04 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Tue, 6 Jul 2010 10:39:04 +0200 Subject: [PATCH 3/3] ASoC: DaVinci: More accurate continuous serial clock for McBSP (I2S) In-Reply-To: <1278405544-3852-1-git-send-email-lamiaposta71@gmail.com> References: <1278405544-3852-1-git-send-email-lamiaposta71@gmail.com> Message-ID: <1278405544-3852-4-git-send-email-lamiaposta71@gmail.com> From: Raffaele Recalcati i2s_accurate_sck switch can be used to have a better approximate sampling frequency. The clock is an externally visible bit clock and it is named i2s continuous serial clock (I2S_SCK). The trade off is between more accurate clock (fast clock) and less accurate clock (slow clock). The waveform will be not symmetric. Probably it is possible to get a better algorithm for calculating the divider, trying to keep a slower clock as possible. This patch has been developed against the http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git git tree and has been tested on bmx board (similar to dm365 evm, but using uda1345 as external audio codec). Signed-off-by: Raffaele Recalcati Signed-off-by: Davide Bonfanti --- arch/arm/mach-davinci/include/mach/asp.h | 33 ++++++++++++++++++++++++++++++ sound/soc/davinci/davinci-i2s.c | 24 +++++++++++++++++---- 2 files changed, 52 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index 0847d21..b12c69e 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -73,6 +73,39 @@ struct snd_platform_data { */ int clk_input_pin; + /* + * This flag works when both clock and FS are outputs for the cpu + * and makes clock more accurate (FS is not symmetrical and the + * clock is very fast. + * The clock becoming faster is named + * i2s continuous serial clock (I2S_SCK) and it is an externally + * visible bit clock. + * + * first line : WordSelect + * second line : ContinuousSerialClock + * third line: SerialData + * + * SYMMETRICAL APPROACH: + * _______________________ LEFT + * _| RIGHT |______________________| + * _ _ _ _ _ _ _ _ + * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_ + * _ _ _ _ _ _ _ _ + * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_ + * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ + * + * ACCURATE CLOCK APPROACH: + * ______________ LEFT + * _| RIGHT |_______________________________| + * _ _ _ _ _ _ _ _ _ + * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| | + * _ _ _ _ dummy cycles + * _/ \_ ... _/ \_/ \_ ... _/ \__________________ + * \_/ \_/ \_/ \_/ + * + */ + bool i2s_accurate_sck; + /* McASP specific fields */ int tdm_slots; u8 op_mode; diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c index ba5644b..b251bc9 100644 --- a/sound/soc/davinci/davinci-i2s.c +++ b/sound/soc/davinci/davinci-i2s.c @@ -155,6 +155,7 @@ struct davinci_mcbsp_dev { unsigned int fmt; int clk_div; int clk_input_pin; + bool i2s_accurate_sck; }; static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, @@ -447,11 +448,23 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, DAVINCI_MCBSP_SRGR_CLKSM; srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1); - /* symmetric waveforms */ - clk_div = freq / (mcbsp_word_length * 16) / - params->rate_num * params->rate_den; - srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * - 16 - 1); + if (dev->i2s_accurate_sck) { + clk_div = 256; + do { + framesize = (freq / (--clk_div)) / + params->rate_num * + params->rate_den; + } while (((framesize < 33) || (framesize > 4095)) && + (clk_div)); + clk_div--; + srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1); + } else { + /* symmetric waveforms */ + clk_div = freq / (mcbsp_word_length * 16) / + params->rate_num * params->rate_den; + srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * + 16 - 1); + } clk_div &= 0xFF; srgr |= clk_div; break; @@ -662,6 +675,7 @@ static int davinci_i2s_probe(struct platform_device *pdev) dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size = pdata->sram_size_capture; dev->clk_input_pin = pdata->clk_input_pin; + dev->i2s_accurate_sck = pdata->i2s_accurate_sck; } dev->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(dev->clk)) { -- 1.7.0.4 From lamiaposta71 at gmail.com Tue Jul 6 03:39:02 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Tue, 6 Jul 2010 10:39:02 +0200 Subject: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S) In-Reply-To: <1278405544-3852-1-git-send-email-lamiaposta71@gmail.com> References: <1278405544-3852-1-git-send-email-lamiaposta71@gmail.com> Message-ID: <1278405544-3852-2-git-send-email-lamiaposta71@gmail.com> From: Raffaele Recalcati Added two clocking options for dm365 McBSP peripheral when used with I2S timings, that are SND_SOC_DAIFMT_CBS_CFS (the cpu generates clock and frame sync) and SND_SOC_DAIFMT_CBS_CFM (the cpu gets clock from external pin and generates frame sync). A slave clock management can be important when the external codec needs the system clock and the bit clock synchronized (tested with uda1345). This patch has been developed against the: http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git git tree and has been tested on bmx board (similar to dm365 evm, but using uda1345 as external audio codec). Signed-off-by: Raffaele Recalcati Signed-off-by: Davide Bonfanti --- sound/soc/davinci/davinci-i2s.c | 110 +++++++++++++++++++++++++++++++++++--- sound/soc/davinci/davinci-i2s.h | 5 ++ 2 files changed, 106 insertions(+), 9 deletions(-) diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c index adadcd3..c8f038c 100644 --- a/sound/soc/davinci/davinci-i2s.c +++ b/sound/soc/davinci/davinci-i2s.c @@ -26,6 +26,7 @@ #include #include "davinci-pcm.h" +#include "davinci-i2s.h" /* @@ -68,16 +69,21 @@ #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) #define DAVINCI_MCBSP_RCR_RFIG (1 << 18) #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) +#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24) +#define DAVINCI_MCBSP_RCR_RPHASE BIT(31) #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) #define DAVINCI_MCBSP_XCR_XFIG (1 << 18) #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) +#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24) +#define DAVINCI_MCBSP_XCR_XPHASE BIT(31) #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) +#define DAVINCI_MCBSP_SRGR_CLKSM BIT(29) #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0) #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) @@ -144,6 +150,9 @@ struct davinci_mcbsp_dev { * won't end up being swapped because of the underrun. */ unsigned enable_channel_combine:1; + + unsigned int fmt; + int clk_div; }; static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, @@ -254,10 +263,12 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, struct davinci_mcbsp_dev *dev = cpu_dai->private_data; unsigned int pcr; unsigned int srgr; + /* Attention srgr is updated by hw_params! */ srgr = DAVINCI_MCBSP_SRGR_FSGM | DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); + dev->fmt = fmt; /* set master/slave audio interface */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: @@ -372,6 +383,18 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, return 0; } +static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, + int div_id, int div) +{ + struct davinci_mcbsp_dev *dev = cpu_dai->private_data; + + if (div_id != DAVINCI_MCBSP_CLKGDV) + return -ENODEV; + + dev->clk_div = div; + return 0; +} + static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -380,8 +403,8 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, struct davinci_pcm_dma_params *dma_params = &dev->dma_params[substream->stream]; struct snd_interval *i = NULL; - int mcbsp_word_length; - unsigned int rcr, xcr, srgr; + int mcbsp_word_length, master; + unsigned int rcr, xcr, srgr, clk_div, freq, framesize; u32 spcr; snd_pcm_format_t fmt; unsigned element_cnt = 1; @@ -396,12 +419,47 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); } - i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); - srgr = DAVINCI_MCBSP_SRGR_FSGM; - srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); + master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; + fmt = params_format(params); + mcbsp_word_length = asp_word_length[fmt]; - i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); - srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); + switch (master) { + case SND_SOC_DAIFMT_CBS_CFS: + freq = clk_get_rate(dev->clk); + srgr = DAVINCI_MCBSP_SRGR_FSGM | + DAVINCI_MCBSP_SRGR_CLKSM; + srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * + 8 - 1); + /* symmetric waveforms */ + clk_div = freq / (mcbsp_word_length * 16) / + params->rate_num * params->rate_den; + srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * + 16 - 1); + clk_div &= 0xFF; + srgr |= clk_div; + break; + case SND_SOC_DAIFMT_CBM_CFS: + srgr = DAVINCI_MCBSP_SRGR_FSGM; + clk_div = dev->clk_div - 1; + srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1); + srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1); + clk_div &= 0xFF; + srgr |= clk_div; + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* Clock and frame sync given from external sources */ + i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); + srgr = DAVINCI_MCBSP_SRGR_FSGM; + srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); + pr_debug("%s - %d FWID set: re-read srgr = %X\n", + __func__, __LINE__, snd_interval_value(i) - 1); + + i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); + srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); + break; + default: + return -EINVAL; + } davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); rcr = DAVINCI_MCBSP_RCR_RFIG; @@ -426,12 +484,41 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, element_cnt = 1; fmt = double_fmt[fmt]; } + switch (master) { + case SND_SOC_DAIFMT_CBS_CFS: + case SND_SOC_DAIFMT_CBS_CFM: + rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0); + xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0); + rcr |= DAVINCI_MCBSP_RCR_RPHASE; + xcr |= DAVINCI_MCBSP_XCR_XPHASE; + break; + case SND_SOC_DAIFMT_CBM_CFM: + case SND_SOC_DAIFMT_CBM_CFS: + rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1); + xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1); + break; + default: + return -EINVAL; + } } dma_params->acnt = dma_params->data_type = data_type[fmt]; dma_params->fifo_level = 0; mcbsp_word_length = asp_word_length[fmt]; - rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1); - xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1); + + switch (master) { + case SND_SOC_DAIFMT_CBS_CFS: + case SND_SOC_DAIFMT_CBS_CFM: + rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0); + xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0); + break; + case SND_SOC_DAIFMT_CBM_CFM: + case SND_SOC_DAIFMT_CBM_CFS: + rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1); + xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1); + break; + default: + return -EINVAL; + } rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length); @@ -442,6 +529,10 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); else davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); + + pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr); + pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr); + pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr); return 0; } @@ -500,6 +591,7 @@ static struct snd_soc_dai_ops davinci_i2s_dai_ops = { .trigger = davinci_i2s_trigger, .hw_params = davinci_i2s_hw_params, .set_fmt = davinci_i2s_set_dai_fmt, + .set_clkdiv = davinci_i2s_dai_set_clkdiv, }; diff --git a/sound/soc/davinci/davinci-i2s.h b/sound/soc/davinci/davinci-i2s.h index 241648c..0b1e77b 100644 --- a/sound/soc/davinci/davinci-i2s.h +++ b/sound/soc/davinci/davinci-i2s.h @@ -12,6 +12,11 @@ #ifndef _DAVINCI_I2S_H #define _DAVINCI_I2S_H +/* McBSP dividers */ +enum davinci_mcbsp_div { + DAVINCI_MCBSP_CLKGDV, /* Sample rate generator divider */ +}; + extern struct snd_soc_dai davinci_i2s_dai; #endif -- 1.7.0.4 From amraldo at hotmail.com Tue Jul 6 04:12:36 2010 From: amraldo at hotmail.com (amr ali) Date: Tue, 6 Jul 2010 12:12:36 +0300 Subject: Angstrom File System Booting Problem Message-ID: Hi, I am booting my board using tftp for kernel and NFS for my file system through with dhcp enabled. The file system is made using Angstrom Online Builder for My Davinci 6446 evm. I selected everything for the file system. During booting and after the kernel booting and file system being mounted using nfs, the booting stops at this line: "nfs: server 10.130.201.55 not responding, still trying" I m wondering why its trying to connect to the same nfs server again? Is there away to disable this step? For example, disabling a certain configuration to overcome it? -- Amr Ali Abdel-Naby Embedded Systems Developer www.embedded-tips.blogspot.com _________________________________________________________________ Hotmail: Powerful Free email with security by Microsoft. https://signup.live.com/signup.aspx?id=60969 -------------- next part -------------- An HTML attachment was scrubbed... URL: From lrg at slimlogic.co.uk Tue Jul 6 04:45:59 2010 From: lrg at slimlogic.co.uk (Liam Girdwood) Date: Tue, 06 Jul 2010 10:45:59 +0100 Subject: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S) In-Reply-To: <1278405544-3852-2-git-send-email-lamiaposta71@gmail.com> References: <1278405544-3852-1-git-send-email-lamiaposta71@gmail.com> <1278405544-3852-2-git-send-email-lamiaposta71@gmail.com> Message-ID: <1278409559.3103.136.camel@odin> On Tue, 2010-07-06 at 10:39 +0200, Raffaele Recalcati wrote: > From: Raffaele Recalcati > > Added two clocking options for dm365 McBSP peripheral when used > with I2S timings, that are SND_SOC_DAIFMT_CBS_CFS (the cpu generates > clock and frame sync) and SND_SOC_DAIFMT_CBS_CFM (the cpu gets clock > from external pin and generates frame sync). > A slave clock management can be important when the external codec needs > the system clock and the bit clock synchronized (tested with uda1345). > This patch has been developed against the: > http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git > git tree and has been tested on bmx board (similar to dm365 evm, but using > uda1345 as external audio codec). > > Signed-off-by: Raffaele Recalcati > Signed-off-by: Davide Bonfanti All Acked-by: Liam Girdwood But lets get some feedback from the DaVinci folks on this too. > --- > sound/soc/davinci/davinci-i2s.c | 110 +++++++++++++++++++++++++++++++++++--- > sound/soc/davinci/davinci-i2s.h | 5 ++ > 2 files changed, 106 insertions(+), 9 deletions(-) > > diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c > index adadcd3..c8f038c 100644 > --- a/sound/soc/davinci/davinci-i2s.c > +++ b/sound/soc/davinci/davinci-i2s.c > @@ -26,6 +26,7 @@ > #include > > #include "davinci-pcm.h" > +#include "davinci-i2s.h" > > > /* > @@ -68,16 +69,21 @@ > #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) > #define DAVINCI_MCBSP_RCR_RFIG (1 << 18) > #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) > +#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24) > +#define DAVINCI_MCBSP_RCR_RPHASE BIT(31) > > #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) > #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) > #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) > #define DAVINCI_MCBSP_XCR_XFIG (1 << 18) > #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) > +#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24) > +#define DAVINCI_MCBSP_XCR_XPHASE BIT(31) > > #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) > #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) > #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) > +#define DAVINCI_MCBSP_SRGR_CLKSM BIT(29) > > #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0) > #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) > @@ -144,6 +150,9 @@ struct davinci_mcbsp_dev { > * won't end up being swapped because of the underrun. > */ > unsigned enable_channel_combine:1; > + > + unsigned int fmt; > + int clk_div; > }; > > static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, > @@ -254,10 +263,12 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, > struct davinci_mcbsp_dev *dev = cpu_dai->private_data; > unsigned int pcr; > unsigned int srgr; > + /* Attention srgr is updated by hw_params! */ > srgr = DAVINCI_MCBSP_SRGR_FSGM | > DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | > DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); > > + dev->fmt = fmt; > /* set master/slave audio interface */ > switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { > case SND_SOC_DAIFMT_CBS_CFS: > @@ -372,6 +383,18 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, > return 0; > } > > +static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, > + int div_id, int div) > +{ > + struct davinci_mcbsp_dev *dev = cpu_dai->private_data; > + > + if (div_id != DAVINCI_MCBSP_CLKGDV) > + return -ENODEV; > + > + dev->clk_div = div; > + return 0; > +} > + > static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, > struct snd_pcm_hw_params *params, > struct snd_soc_dai *dai) > @@ -380,8 +403,8 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, > struct davinci_pcm_dma_params *dma_params = > &dev->dma_params[substream->stream]; > struct snd_interval *i = NULL; > - int mcbsp_word_length; > - unsigned int rcr, xcr, srgr; > + int mcbsp_word_length, master; > + unsigned int rcr, xcr, srgr, clk_div, freq, framesize; > u32 spcr; > snd_pcm_format_t fmt; > unsigned element_cnt = 1; > @@ -396,12 +419,47 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, > davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); > } > > - i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); > - srgr = DAVINCI_MCBSP_SRGR_FSGM; > - srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); > + master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; > + fmt = params_format(params); > + mcbsp_word_length = asp_word_length[fmt]; > > - i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); > - srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); > + switch (master) { > + case SND_SOC_DAIFMT_CBS_CFS: > + freq = clk_get_rate(dev->clk); > + srgr = DAVINCI_MCBSP_SRGR_FSGM | > + DAVINCI_MCBSP_SRGR_CLKSM; > + srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * > + 8 - 1); > + /* symmetric waveforms */ > + clk_div = freq / (mcbsp_word_length * 16) / > + params->rate_num * params->rate_den; > + srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * > + 16 - 1); > + clk_div &= 0xFF; > + srgr |= clk_div; > + break; > + case SND_SOC_DAIFMT_CBM_CFS: > + srgr = DAVINCI_MCBSP_SRGR_FSGM; > + clk_div = dev->clk_div - 1; > + srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1); > + srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1); > + clk_div &= 0xFF; > + srgr |= clk_div; > + break; > + case SND_SOC_DAIFMT_CBM_CFM: > + /* Clock and frame sync given from external sources */ > + i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); > + srgr = DAVINCI_MCBSP_SRGR_FSGM; > + srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); > + pr_debug("%s - %d FWID set: re-read srgr = %X\n", > + __func__, __LINE__, snd_interval_value(i) - 1); > + > + i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); > + srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); > + break; > + default: > + return -EINVAL; > + } > davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); > > rcr = DAVINCI_MCBSP_RCR_RFIG; > @@ -426,12 +484,41 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, > element_cnt = 1; > fmt = double_fmt[fmt]; > } > + switch (master) { > + case SND_SOC_DAIFMT_CBS_CFS: > + case SND_SOC_DAIFMT_CBS_CFM: > + rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0); > + xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0); > + rcr |= DAVINCI_MCBSP_RCR_RPHASE; > + xcr |= DAVINCI_MCBSP_XCR_XPHASE; > + break; > + case SND_SOC_DAIFMT_CBM_CFM: > + case SND_SOC_DAIFMT_CBM_CFS: > + rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1); > + xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1); > + break; > + default: > + return -EINVAL; > + } > } > dma_params->acnt = dma_params->data_type = data_type[fmt]; > dma_params->fifo_level = 0; > mcbsp_word_length = asp_word_length[fmt]; > - rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1); > - xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1); > + > + switch (master) { > + case SND_SOC_DAIFMT_CBS_CFS: > + case SND_SOC_DAIFMT_CBS_CFM: > + rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0); > + xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0); > + break; > + case SND_SOC_DAIFMT_CBM_CFM: > + case SND_SOC_DAIFMT_CBM_CFS: > + rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1); > + xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1); > + break; > + default: > + return -EINVAL; > + } > > rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | > DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length); > @@ -442,6 +529,10 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, > davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); > else > davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); > + > + pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr); > + pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr); > + pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr); > return 0; > } > > @@ -500,6 +591,7 @@ static struct snd_soc_dai_ops davinci_i2s_dai_ops = { > .trigger = davinci_i2s_trigger, > .hw_params = davinci_i2s_hw_params, > .set_fmt = davinci_i2s_set_dai_fmt, > + .set_clkdiv = davinci_i2s_dai_set_clkdiv, > > }; > > diff --git a/sound/soc/davinci/davinci-i2s.h b/sound/soc/davinci/davinci-i2s.h > index 241648c..0b1e77b 100644 > --- a/sound/soc/davinci/davinci-i2s.h > +++ b/sound/soc/davinci/davinci-i2s.h > @@ -12,6 +12,11 @@ > #ifndef _DAVINCI_I2S_H > #define _DAVINCI_I2S_H > > +/* McBSP dividers */ > +enum davinci_mcbsp_div { > + DAVINCI_MCBSP_CLKGDV, /* Sample rate generator divider */ > +}; > + > extern struct snd_soc_dai davinci_i2s_dai; > > #endif -- Freelance Developer, SlimLogic Ltd ASoC and Voltage Regulator Maintainer. http://www.slimlogic.co.uk From amraldo at hotmail.com Tue Jul 6 04:56:26 2010 From: amraldo at hotmail.com (amr ali) Date: Tue, 6 Jul 2010 12:56:26 +0300 Subject: Angstrom File System Booting Problem Message-ID: Hi, I am booting my board using tftp for kernel and NFS for my file system through with dhcp enabled. The file system is made using Angstrom Online Builder for My Davinci 6446 evm. I selected everything for the file system. During booting and after the kernel booting and file system being mounted using nfs, the booting stops at this line: "nfs: server 10.130.201.55 not responding, still trying" I m wondering why its trying to connect to the same nfs server again? Is there away to disable this step? For example, disabling a certain configuration to overcome it? -- Amr Ali Abdel-Naby Embedded Systems Developer Hotmail: Powerful Free email with security by Microsoft. Get it now. _________________________________________________________________ Hotmail: Trusted email with Microsoft?s powerful SPAM protection. https://signup.live.com/signup.aspx?id=60969 -------------- next part -------------- An HTML attachment was scrubbed... URL: From sudhakar.raj at ti.com Tue Jul 6 06:30:24 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Tue, 6 Jul 2010 17:00:24 +0530 Subject: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S) In-Reply-To: <1278409559.3103.136.camel@odin> References: <1278405544-3852-1-git-send-email-lamiaposta71@gmail.com> <1278405544-3852-2-git-send-email-lamiaposta71@gmail.com> <1278409559.3103.136.camel@odin> Message-ID: <003001cb1cfe$a043a610$e0caf230$@raj@ti.com> Hi, On Tue, Jul 06, 2010 at 15:15:59, Liam Girdwood wrote: > On Tue, 2010-07-06 at 10:39 +0200, Raffaele Recalcati wrote: > > From: Raffaele Recalcati > > > > Added two clocking options for dm365 McBSP peripheral when used > > with I2S timings, that are SND_SOC_DAIFMT_CBS_CFS (the cpu generates > > clock and frame sync) and SND_SOC_DAIFMT_CBS_CFM (the cpu gets clock > > from external pin and generates frame sync). > > A slave clock management can be important when the external codec needs > > the system clock and the bit clock synchronized (tested with uda1345). > > This patch has been developed against the: > > http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git > > git tree and has been tested on bmx board (similar to dm365 evm, but using > > uda1345 as external audio codec). > > > > Signed-off-by: Raffaele Recalcati > > Signed-off-by: Davide Bonfanti > > All > > Acked-by: Liam Girdwood > > But lets get some feedback from the DaVinci folks on this too. > Acked-by: Sudhakar Rajashekhara Regards, Sudhakar From broonie at opensource.wolfsonmicro.com Tue Jul 6 09:54:49 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Tue, 6 Jul 2010 23:54:49 +0900 Subject: [PATCH 1/3] ASoC: DaVinci: Added two clocking possibilities to McBSP (I2S) In-Reply-To: <003001cb1cfe$a043a610$e0caf230$@raj@ti.com> References: <1278405544-3852-1-git-send-email-lamiaposta71@gmail.com> <1278405544-3852-2-git-send-email-lamiaposta71@gmail.com> <1278409559.3103.136.camel@odin> <003001cb1cfe$a043a610$e0caf230$@raj@ti.com> Message-ID: <20100706145448.GC20154@opensource.wolfsonmicro.com> On Tue, Jul 06, 2010 at 05:00:24PM +0530, Sudhakar Rajashekhara wrote: > > Acked-by: Liam Girdwood > Acked-by: Sudhakar Rajashekhara Applied all, thanks. From broonie at opensource.wolfsonmicro.com Tue Jul 6 23:17:29 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Wed, 7 Jul 2010 13:17:29 +0900 Subject: Rif: Re: [PATCH 3/3] ASoC: DaVinci: More accurate calculation for clock divider for McBSP (I2S) In-Reply-To: <4C337770.3070007@boundarydevices.com> References: <4C337770.3070007@boundarydevices.com> Message-ID: <20100707041727.GA12335@opensource.wolfsonmicro.com> On Tue, Jul 06, 2010 at 11:35:28AM -0700, Troy Kisky wrote: > Indeed, your algorithm may produce more accurate results for the specific rate > that you tested for. However, that seems more luck than anything. How do you > know that a frame size of 33 will always give more accurate results than a frame > size of 32? If your going to loop, you need to calculate the error and minimize that > and not just stop when framesize finally reaches your minimum size of 33. Yes, this is pretty much the algorithm I was trying to suggest earlier. Iterate up until you hit either an exact match or decide that the frame size is getting too big. From vij_soni at yahoo.com Tue Jul 6 23:47:16 2010 From: vij_soni at yahoo.com (Vijay Soni) Date: Tue, 6 Jul 2010 21:47:16 -0700 (PDT) Subject: pwrite in mtd Message-ID: <316378.87035.qm@web38806.mail.mud.yahoo.com> The write to mtd ? pwrite(fd, writebuf, size, mtdoffset) returns error Num 22, Invalid Arguments Any clue? From rohan_javed at yahoo.co.uk Wed Jul 7 01:54:01 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Wed, 7 Jul 2010 06:54:01 +0000 (GMT) Subject: Is populating /dev devices???? Message-ID: <785551.56977.qm@web24102.mail.ird.yahoo.com> Is populating /dev devices required at each bootup .It takes about 5sec to populate all the devices how to ignore this? Regard's Rohan Tabish -------------- next part -------------- An HTML attachment was scrubbed... URL: From cring at ti.com Wed Jul 7 02:22:55 2010 From: cring at ti.com (Ring, Chris) Date: Wed, 7 Jul 2010 02:22:55 -0500 Subject: change the source of "simplewidget" and compile it has no effect on our own application, can we change the code and rebuild the lib simplewidget? In-Reply-To: <4C33500E.3000105@css-design.com> References: <201007052025046875726@tpsee.com> <4C33500E.3000105@css-design.com> Message-ID: <92CDD168D1E81F4F9D3839DC45903FC6786F3143@dlee03.ent.ti.com> I don't know any details about the simplewidget library, but I do know it has nothing to do with the DSP - it's an ARM-only library. So you don't have to rebuild the DSP-side Codec Server executable. Chris ________________________________ From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Steve Poulsen Sent: Tuesday, July 06, 2010 8:47 AM To: davinci-linux-open-source at linux.davincidsp.com Subject: Re: change the source of "simplewidget" and compile it has no effect on our own application, can we change the code and rebuild the lib simplewidget? You should look at the DVSDK documentation which shows how to rebuild the CodecEngine "Codec Server". This process is a bit more tricky since it is building for two processors. The library that links with your application does not contain all the code for these components. There is the "server" portion which handles the request. I am not familiar with simplewidget, but it is likely that you are not getting the updated "server" which is going to be a mix of ARM/DSP code. Steve On 07/05/2010 07:25 AM, johnny wrote: Hi all, For some reason I have to change the code of dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget/Button.c and Button.h, I complie the direcotry of simplewidget for dm365 but the new interface added by us can not be found. I found only one simplewidget_dm365.a470MV in the whole directory dvsdk_2_10_01_18 in directory dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget/lib/, but after I delete the file dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget/lib/simplewidget_dm365.a470MV, we can still compile our application successfully. How could this happen? can we change the code and rebuild the lib simplewidget? 2010-07-05 ________________________________ johnny -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------- next part -------------- An HTML attachment was scrubbed... URL: From ottavio.campana at dei.unipd.it Wed Jul 7 02:29:34 2010 From: ottavio.campana at dei.unipd.it (Ottavio Campana) Date: Wed, 07 Jul 2010 09:29:34 +0200 Subject: Is populating /dev devices???? In-Reply-To: <785551.56977.qm@web24102.mail.ird.yahoo.com> References: <785551.56977.qm@web24102.mail.ird.yahoo.com> Message-ID: <4C342CDE.9080401@dei.unipd.it> On 07/07/2010 08:54 AM, rohan tabish wrote: > Is populating /dev devices required at each bootup .It takes about > 5sec to populate all the devices how to ignore this? > no, you can always provide a static /dev -------------- next part -------------- An HTML attachment was scrubbed... URL: From rohan_javed at yahoo.co.uk Wed Jul 7 02:31:19 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Wed, 7 Jul 2010 07:31:19 +0000 (GMT) Subject: Populating /dev on each boot up Message-ID: <662133.91195.qm@web24108.mail.ird.yahoo.com> Hello I have a question for you i want to know that when the system boots up u-boot copies the linux kernel from the flash to the ram and start execution.It then looks for the filesystem and mount in my case the filesystem used is jffs2 following are the steps that i do in the start up script i mount /proc /dev run some deamons all these take only 0.14seconds but populating the /dev takes almost around 5seconds and create alot of devices in the /dev it means at each bootup these devices are written in the /dev directory? off course i know that these devices are required to communicate with the hardware but i want fast boot-up so my question is that should i copy these devices to myfilesystem once and then recycle the board with removing populating deivces script is that? ok????I did this but at bootup it says can't acess? /dev/ttyS0 nosuch file or directory regard's -------------- next part -------------- An HTML attachment was scrubbed... URL: From johnny at tpsee.com Wed Jul 7 02:32:29 2010 From: johnny at tpsee.com (johnny) Date: Wed, 7 Jul 2010 15:32:29 +0800 Subject: change the source of "simplewidget" and compile it has noeffect on our own application, can we change the code and rebuild the lib simplewidget? References: <201007052025046875726@tpsee.com>, <4C33500E.3000105@css-design.com> Message-ID: <201007071532268591432@tpsee.com> Hi all, I have solved this problem. It's my mistake because I should rebuild the packages/ti/sdo/simplewidget within our application instead of dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget. thanks. 2010-07-07 johnny ???? Ring, Chris ????? 2010-07-07 15:23:13 ???? Steve Poulsen; davinci-linux-open-source at linux.davincidsp.com ??? ??? RE: change the source of "simplewidget" and compile it has noeffect on our own application,can we change the code and rebuild the lib simplewidget? I don't know any details about the simplewidget library, but I do know it has nothing to do with the DSP - it's an ARM-only library. So you don't have to rebuild the DSP-side Codec Server executable. Chris From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Steve Poulsen Sent: Tuesday, July 06, 2010 8:47 AM To: davinci-linux-open-source at linux.davincidsp.com Subject: Re: change the source of "simplewidget" and compile it has no effect on our own application, can we change the code and rebuild the lib simplewidget? You should look at the DVSDK documentation which shows how to rebuild the CodecEngine "Codec Server". This process is a bit more tricky since it is building for two processors. The library that links with your application does not contain all the code for these components. There is the "server" portion which handles the request. I am not familiar with simplewidget, but it is likely that you are not getting the updated "server" which is going to be a mix of ARM/DSP code. Steve On 07/05/2010 07:25 AM, johnny wrote: Hi all, For some reason I have to change the code of dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget/Button.c and Button.h, I complie the direcotry of simplewidget for dm365 but the new interface added by us can not be found. I found only one simplewidget_dm365.a470MV in the whole directory dvsdk_2_10_01_18 in directory dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget/lib/, but after I delete the file dvsdk_demos_2_10_00_17/packages/ti/sdo/simplewidget/lib/simplewidget_dm365.a470MV, we can still compile our application successfully. How could this happen? can we change the code and rebuild the lib simplewidget? 2010-07-05 johnny -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------- next part -------------- An HTML attachment was scrubbed... URL: From amraldo at hotmail.com Wed Jul 7 03:15:32 2010 From: amraldo at hotmail.com (amr ali) Date: Wed, 7 Jul 2010 11:15:32 +0300 Subject: Frame Buffer Device not Working Message-ID: My fb device is not working. After login, I tried this " "dmesg | grep fb Kernel command line: console=ttyS0,115200n8 noinitrd rw ip=dhcp root=/dev/nfs nfsroot=10.130.201.55l davincifb davincifb: dm_osd0_fb: 720x480x16 at 0,0 with framebuffer size 675KB davincifb davincifb: dm_vid0_fb: 0x0x16 at 0,0 with framebuffer size 1020KB davincifb davincifb: dm_osd1_fb: 720x480x4 at 0,0 with framebuffer size 675KB davincifb davincifb: dm_vid1_fb: 0x0x16 at 0,0 with framebuffer size 1020KB davincifb davincifb.0: dm_osd0_fb: Failed to obtain ownership of OSD window" How can I over come dat? -- Amr Ali Abdel-Naby Embedded Systems Developer www.embedded-tips.blogspot.com _________________________________________________________________ Hotmail: Powerful Free email with security by Microsoft. https://signup.live.com/signup.aspx?id=60969 -------------- next part -------------- An HTML attachment was scrubbed... URL: From nsekhar at ti.com Wed Jul 7 03:32:50 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Wed, 7 Jul 2010 14:02:50 +0530 Subject: [PATCH 2/2] davinci: am18x/da850/omap-l138: add support for higher frequencies In-Reply-To: <1278491570-11832-1-git-send-email-nsekhar@ti.com> References: <1278491570-11832-1-git-send-email-nsekhar@ti.com> Message-ID: <1278491570-11832-2-git-send-email-nsekhar@ti.com> AM18x/DA850/OMAP-L138 SoCs have variants that can operate at a maximum of 456 MHz at 1.3V operating point. Also the 1.2V operating point has a variant that can support a maximum of 372 MHz. This patch adds three new OPPs (456 MHz, 408 MHz and 372 MHz) to the list of DA850 OPPs. Not all silicon is qualified to run at higher speeds and unfortunately the maximum speed the chip can support can only be read from the label on the package (not software readable). Because of this, kernel configuration options have been introduced to help users enable higher speeds if they know that their slicon can support the higher speed. Signed-off-by: Sekhar Nori --- Because of the Kconfig change, this patch should be applied after "davinci: introduce support for AM1x ARM9 microprocessors" submitted earlier. arch/arm/mach-davinci/Kconfig | 23 +++++++++ arch/arm/mach-davinci/board-da850-evm.c | 2 +- arch/arm/mach-davinci/da850.c | 81 ++++++++++++++++++++++++++----- 3 files changed, 92 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 94f2a2c..f812124 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -41,6 +41,29 @@ config ARCH_DAVINCI_DA850 select ARCH_DAVINCI_DA8XX select ARCH_HAS_CPUFREQ +choice + prompt "Select Maximum DA850/OMAP-L138/AM18x SoC speed" + depends on ARCH_DAVINCI_DA850 && CPU_FREQ + help + Select the maximum speed your device can operate at. Note that + running the device at a speed more than it is qualified for can + cause permanent damage to the device. + + If unsure, leave at the default (300 MHz). + +config DA850_MAX_SPEED_300 + bool "300 MHz" + +config DA850_MAX_SPEED_372 + bool "372 MHz" + +config DA850_MAX_SPEED_408 + bool "408 MHz" + +config DA850_MAX_SPEED_456 + bool "456 MHz" +endchoice + config ARCH_DAVINCI_DA8XX select CPU_ARM926T bool diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index a31f37a..b429c2a 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -500,7 +500,7 @@ struct regulator_init_data tps65070_regulator_data[] = { { .constraints = { .min_uV = 950000, - .max_uV = 1320000, + .max_uV = 1350000, .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS), .boot_on = 1, diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index a275e8b..45599a7 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -871,6 +871,33 @@ struct da850_opp { unsigned int cvdd_max; /* in uV */ }; +static const struct da850_opp da850_opp_456 = { + .freq = 456000, + .prediv = 1, + .mult = 19, + .postdiv = 1, + .cvdd_min = 1300000, + .cvdd_max = 1350000, +}; + +static const struct da850_opp da850_opp_408 = { + .freq = 408000, + .prediv = 1, + .mult = 17, + .postdiv = 1, + .cvdd_min = 1300000, + .cvdd_max = 1350000, +}; + +static const struct da850_opp da850_opp_372 = { + .freq = 372000, + .prediv = 1, + .mult = 31, + .postdiv = 2, + .cvdd_min = 1200000, + .cvdd_max = 1320000, +}; + static const struct da850_opp da850_opp_300 = { .freq = 300000, .prediv = 1, @@ -905,6 +932,9 @@ static const struct da850_opp da850_opp_96 = { } static struct cpufreq_frequency_table da850_freq_table[] = { + OPP(456), + OPP(408), + OPP(372), OPP(300), OPP(200), OPP(96), @@ -915,6 +945,19 @@ static struct cpufreq_frequency_table da850_freq_table[] = { }; #ifdef CONFIG_REGULATOR +static int da850_set_voltage(unsigned int index); +static int da850_regulator_init(void); +#endif + +static struct davinci_cpufreq_config cpufreq_info = { + .freq_table = &da850_freq_table[0], +#ifdef CONFIG_REGULATOR + .init = da850_regulator_init, + .set_voltage = da850_set_voltage, +#endif +}; + +#ifdef CONFIG_REGULATOR static struct regulator *cvdd; static int da850_set_voltage(unsigned int index) @@ -924,7 +967,7 @@ static int da850_set_voltage(unsigned int index) if (!cvdd) return -ENODEV; - opp = (struct da850_opp *) da850_freq_table[index].index; + opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); } @@ -941,14 +984,6 @@ static int da850_regulator_init(void) } #endif -static struct davinci_cpufreq_config cpufreq_info = { - .freq_table = &da850_freq_table[0], -#ifdef CONFIG_REGULATOR - .init = da850_regulator_init, - .set_voltage = da850_set_voltage, -#endif -}; - static struct platform_device da850_cpufreq_device = { .name = "cpufreq-davinci", .dev = { @@ -956,8 +991,27 @@ static struct platform_device da850_cpufreq_device = { }, }; +#if defined CONFIG_DA850_MAX_SPEED_456 +#define DA850_MAX_SPEED 456000 +#elif defined CONFIG_DA850_MAX_SPEED_408 +#define DA850_MAX_SPEED 408000 +#elif defined CONFIG_DA850_MAX_SPEED_372 +#define DA850_MAX_SPEED 372000 +#else +#define DA850_MAX_SPEED 300000 +#endif + int __init da850_register_cpufreq(void) { + int i; + + for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) { + if (da850_freq_table[i].frequency <= DA850_MAX_SPEED) { + cpufreq_info.freq_table = &da850_freq_table[i]; + break; + } + } + return platform_device_register(&da850_cpufreq_device); } @@ -965,17 +1019,18 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate) { int i, ret = 0, diff; unsigned int best = (unsigned int) -1; + struct cpufreq_frequency_table *table = cpufreq_info.freq_table; rate /= 1000; /* convert to kHz */ - for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { - diff = da850_freq_table[i].frequency - rate; + for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) { + diff = table[i].frequency - rate; if (diff < 0) diff = -diff; if (diff < best) { best = diff; - ret = da850_freq_table[i].frequency; + ret = table[i].frequency; } } @@ -996,7 +1051,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index) struct pll_data *pll = clk->pll_data; int ret; - opp = (struct da850_opp *) da850_freq_table[index].index; + opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; prediv = opp->prediv; mult = opp->mult; postdiv = opp->postdiv; -- 1.6.2.4 From nsekhar at ti.com Wed Jul 7 03:32:49 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Wed, 7 Jul 2010 14:02:49 +0530 Subject: [PATCH 1/2] davinci: am18x/da850/omap-l138: use 'NOM' voltage defined in datasheet as min voltage Message-ID: <1278491570-11832-1-git-send-email-nsekhar@ti.com> For each DA850 OPP, the normal ('NOM') voltage defined in the tecnical reference manual (TRM) is actually the minimum voltage the frequency is supported at. The minimum ('MIN') voltage defined in TRM is meant to take care of voltage fluctuations and the device should not be run at this voltage for extended periods of time. Fix the OPP definitions to define the cvdd_min as the normal voltage defined in the datasheet. Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/da850.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 6b8331b..a275e8b 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -876,7 +876,7 @@ static const struct da850_opp da850_opp_300 = { .prediv = 1, .mult = 25, .postdiv = 2, - .cvdd_min = 1140000, + .cvdd_min = 1200000, .cvdd_max = 1320000, }; @@ -885,7 +885,7 @@ static const struct da850_opp da850_opp_200 = { .prediv = 1, .mult = 25, .postdiv = 3, - .cvdd_min = 1050000, + .cvdd_min = 1100000, .cvdd_max = 1160000, }; @@ -894,7 +894,7 @@ static const struct da850_opp da850_opp_96 = { .prediv = 1, .mult = 20, .postdiv = 5, - .cvdd_min = 950000, + .cvdd_min = 1000000, .cvdd_max = 1050000, }; -- 1.6.2.4 From jaya.krishnan at samsung.com Wed Jul 7 03:43:48 2010 From: jaya.krishnan at samsung.com (Jaya krishnan) Date: Wed, 07 Jul 2010 08:43:48 +0000 (GMT) Subject: DM6467 EDMA channel conflict Message-ID: <5766822.208571278492228498.JavaMail.weblogic@epml01> I want to use DM6467 EDMA to transfer frame data from PCI memory to DDR2. I am using the PCI Boot Driver from TI. My application uses arch/arm/mach-davinci/dma.c driver for allocating EDMA channels. Since the EDMA channels are controlled by two drivers, there is a chance of conflict. Is there a way in the arch/arm/mach-davinci/dma.c to exclude some channel/channels from being dynamically allocated?, So that channel can be safely used by the PCI boot driver. Kindly suggest. Regards JK Jayakrishnan M M Research Engineer R&D Team-2 , Group-5 Security Solutions Division SAMSUNG TECHWIN CO.,LTD TEL +82-70-7147-8482 FAX +82-31-8018-3712 Mobile +82-10-6409-3619 E-mail:jaya.krishnan at samsung.com From sudhakar.raj at ti.com Wed Jul 7 06:20:50 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Wed, 7 Jul 2010 16:50:50 +0530 Subject: [spi-devel-general] [PATCH v2 0/1] davinci: spi: replaceexisting driver In-Reply-To: References: <1278110334-13943-1-git-send-email-bniebuhr@efjohnson.com> <002301cb1ce6$64fba3e0$2ef2eba0$@raj@ti.com> Message-ID: <013901cb1dc6$747ab500$5d701f00$@raj@ti.com> Hi Brian, On Tue, Jul 06, 2010 at 19:45:56, Brian Niebuhr wrote: > > On Sat, Jul 03, 2010 at 04:08:53, Brian Niebuhr wrote: > > > I have included all of the recommended changes in this [...] > > > > Quick update. > > > > I tested this patch on DM355 and DM365 EVMs. On DM355 all the > > 3 modes (DMA, > > Polled and Interrupt) worked fine. But in interrupt mode, on > > DM355, if I set > > "intr_level = 1", then kernel hangs during booting after printing > > "spi spi0.0: DaVinci SPI driver in Interrupt mode" on the console. > > Sudhakar - > > When you changed the interrupt level, did you also change the > IORESOURCE_IRQ entry for SPI0? Maybe we could set the interrupt level > automatically based on the IORESOURCE_IRQ provided? IORESOURCE_IRQ entry for dm365 were already present in dm365.c. > > > On DM365 only DMA and Polled mode worked fine. In interrupt > > mode, whether I > > set intr_level to ZERO or ONE, kernel booting hangs, similar to DM355. > > Does the interrupt mode of the existing driver work on DM365? > AFAIK, support for interrupt mode was not present in the earlier driver by Sandeep Paulraj. > I don't have one of these boards, so I can't debug the issue. If you > have any ideas where the problem might be I'd appreciate the help in > getting this resolved. As I mentioned in my earlier e-mail, on DM365 kernel booting hangs after Printing "spi spi0.0: DaVinci SPI driver in Interrupt mode" on the console. Control is in spi_sync() function waiting for completion. > If the change I mentioned above fixes the issue on DM355, then I am not sure whether my earlier mail was clear in this regard or not but interrupt mode works fine on DM355 if intr_level = 0. Kernel booting hangs on DM355 if intr_level = 1. > I've got to imagine that it's just a configuration issue > of some sort on DM365. > I am also of the same opinion. Thanks, Sudhakar From seanp at pfk.co.za Wed Jul 7 07:54:37 2010 From: seanp at pfk.co.za (Sean Kelvin Preston) Date: Wed, 7 Jul 2010 14:54:37 +0200 Subject: Driver probe functionality Message-ID: <000a01cb1dd3$95aba470$c102ed50$@pfk.co.za> Hi I am trying to understand how the driver probe and loading works from a kernel level. I am working on changing the NAND chip used on the DM365 EVM and have managed to determine that the davinci_nand driver is not loading for the new chip because the platform_match function never finds it in the list of drivers loaded. How does a driver determine whether it should be loaded? I have seen the probe function defined in the drivers/base/platform.c as well as the drivers/mtd/nand/davinci_nand.c but am not sure of the process and how these are being used. Sorry I am new to kernel development so I am sure I have not asked this question the best way so if there is anything else I can provide to help answer my question then please let me know. Regards Sean -- Sean Preston Email: seanp at pfk.co.za From rohan_javed at yahoo.co.uk Wed Jul 7 08:07:41 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Wed, 7 Jul 2010 13:07:41 +0000 (GMT) Subject: question on /dev devices Message-ID: <567613.10982.qm@web24101.mail.ird.yahoo.com> i have written a filesytem now i want to do fast boot but populating the /dev takes about 5seconds how can i avoid populating /dev at each bootup. Also i want to know that? where these devices acutally are ??i mean in the RAM or in the flash in case of jffs2 image?if they are the part of the jffs2 then why then are not there at the other bootup?i guess they are in the ram am i right??we mount devices from the ram to our filesytem to communicate with these devices.we populate to make nodes in /dev and it takes around 5seconds how can i reduce this time.Also doing mknod create node for a device but at reboot the device does not exist this means doing mknod /dev/ /proc/sys/kernel/hotplug status $? 0 echo -n " Populating /dev??????????? : " mkdir /dev/input mkdir /dev/snd mdev -s status $? 0 i want fast boot right now i did it using jffs2 image and time is about 13seconds from ubl to linux prompt with all the services up and running. does doing alot of insmod and mknod on the jffs2 image affects the life of the flash? regard's RT -------------- next part -------------- An HTML attachment was scrubbed... URL: From spoulsen at css-design.com Wed Jul 7 08:14:38 2010 From: spoulsen at css-design.com (Steve Poulsen) Date: Wed, 07 Jul 2010 08:14:38 -0500 Subject: Populating /dev on each boot up In-Reply-To: <662133.91195.qm@web24108.mail.ird.yahoo.com> References: <662133.91195.qm@web24108.mail.ird.yahoo.com> Message-ID: <4C347DBE.2080403@css-design.com> You should copy these files into your filesystem and make sure they look the same "ls -l". A simple "cp" will not do it. I use "rsync -a" for this operation. Make sure udev no longer starts. Make sure you don't have any line in /etc/fstab corresponding to mounting /dev Steve On 07/07/2010 02:31 AM, rohan tabish wrote: > Hello > > I have a question for you i want to know that when the system boots up > u-boot copies the linux kernel from the flash to the ram and start > execution.It then looks for the filesystem and mount in my case the > filesystem used is jffs2 following are the steps that i do in the > start up script i mount /proc /dev run some deamons all these take > only 0.14seconds but populating the /dev takes almost around 5seconds > and create alot of devices in the /dev it means at each bootup these > devices are written in the /dev directory? > off course i know that these devices are required to communicate with > the hardware but i want fast boot-up so my question is that should i > copy these devices to myfilesystem once and then recycle the board > with removing populating deivces script is that ok????I did this but > at bootup it says can't acess /dev/ttyS0 nosuch file or directory > regard's > > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* , and is > believed to be clean. > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------- next part -------------- An HTML attachment was scrubbed... URL: From s-paulraj at ti.com Wed Jul 7 08:16:17 2010 From: s-paulraj at ti.com (Paulraj, Sandeep) Date: Wed, 7 Jul 2010 08:16:17 -0500 Subject: [spi-devel-general] [PATCH v2 0/1] davinci: spi: replaceexisting driver In-Reply-To: <013901cb1dc6$747ab500$5d701f00$@raj@ti.com> References: <1278110334-13943-1-git-send-email-bniebuhr@efjohnson.com> <002301cb1ce6$64fba3e0$2ef2eba0$@raj@ti.com> <013901cb1dc6$747ab500$5d701f00$@raj@ti.com> Message-ID: <0554BEF07D437848AF01B9C9B5F0BC5D9F0B6553@dlee01.ent.ti.com> > > > > Does the interrupt mode of the existing driver work on DM365? > > > > AFAIK, support for interrupt mode was not present in the earlier driver > by Sandeep Paulraj. > All three modes had worked fine on multiple TI SOC's including DM355 and DM365 when I had submitted the driver. Sandeep From jp.francois at cynove.com Wed Jul 7 08:36:36 2010 From: jp.francois at cynove.com (jean-philippe francois) Date: Wed, 7 Jul 2010 15:36:36 +0200 Subject: question on /dev devices In-Reply-To: <567613.10982.qm@web24101.mail.ird.yahoo.com> References: <567613.10982.qm@web24101.mail.ird.yahoo.com> Message-ID: > > echo -n " Mounting /proc???????????? : " > mount -n -t proc /proc /proc > status $? 1 > > echo -n " Mounting /sys????????????? : " > mount -n -t sysfs sysfs /sys > status $? 1 > > echo -n " Mounting /dev????????????? : " > mount -n -t tmpfs mdev /dev > status $? 1 > Here you are mounting a tmpfs on /dev Further access to /dev goes to this tmpfs, not to flash > echo -n " Mounting /dev/pts????????? : " > mkdir /dev/pts > mount -t devpts devpts /dev/pts > status $? 1 > > echo -n " Enabling hot-plug????????? : " > echo "/sbin/mdev" > /proc/sys/kernel/hotplug > status $? 0 > > echo -n " Populating /dev??????????? : " > mkdir /dev/input > mkdir /dev/snd > > mdev -s > status $? 0 > mdev -s is responsible for populating /dev/ with the initial device exposed by the kernel. device exists in the kernel without the /dev filesystem The /dev representation is a way for userspace to access devices in that lives in kernelspace. mdev should certainly not take 5 sec to populate /dev. If you want a faster /dev/ population, you can use devtmpfs. - Choose the DEVTMPFS option in your kernel config. - mount -t devtmpfs devtmpfs /dev in your script - keep the hotplug mechanism - remove the mdev -s line. For fast boot time : set verify=n in u-boot use uncompressed kernel and initramfs enable timing informations on printk for easier debugging try to get as small as possible kernel and initramfs > i want fast boot right now i did it using jffs2 image and time is about 13seconds from ubl to linux prompt with all the services up and running. > > does doing alot of insmod and mknod on the jffs2 image affects the life of the flash? > > regard's > RT > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > From jp.francois at cynove.com Wed Jul 7 09:35:40 2010 From: jp.francois at cynove.com (jean-philippe francois) Date: Wed, 7 Jul 2010 16:35:40 +0200 Subject: Driver probe functionality In-Reply-To: <000a01cb1dd3$95aba470$c102ed50$@pfk.co.za> References: <000a01cb1dd3$95aba470$c102ed50$@pfk.co.za> Message-ID: 2010/7/7 Sean Kelvin Preston : > Hi > > I am trying to understand how the driver probe and loading works from a > kernel level. ?I am working on changing the NAND chip used on the DM365 EVM > and have managed to determine that the davinci_nand driver is not loading > for the new chip because the platform_match function never finds it in the > list of drivers loaded. ?How does a driver determine whether it should be > loaded? I have seen the probe function defined in the > drivers/base/platform.c as well as the drivers/mtd/nand/davinci_nand.c but > am not sure of the process and how these are being used. > > Sorry I am new to kernel development so I am sure I have not asked this > question the best way so if there is anything else I can provide to help > answer my question then please let me know. > For platform bus, you can match by id or by name : for example in the board code you have : static struct platform_device davinci_nand_device = { .name = "davinci_nand", .id = 0, .num_resources = ARRAY_SIZE(davinci_nand_resources), .resource = davinci_nand_resources, .dev = { .platform_data = &davinci_nand_data, }, }; And in the driver code : static struct platform_driver nand_davinci_driver = { .remove = __exit_p(nand_davinci_remove), .driver = { .name = "davinci_nand", }, }; the device and driver name must match if you want the platform_match function to work. > Regards > Sean > > -- > Sean Preston > Email: seanp at pfk.co.za > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > From BNiebuhr at efjohnson.com Wed Jul 7 12:02:58 2010 From: BNiebuhr at efjohnson.com (Brian Niebuhr) Date: Wed, 7 Jul 2010 12:02:58 -0500 Subject: [spi-devel-general] [PATCH v2 0/1] davinci: spi:replaceexisting driver In-Reply-To: <013901cb1dc6$747ab500$5d701f00$@raj@ti.com> References: <1278110334-13943-1-git-send-email-bniebuhr@efjohnson.com><002301cb1ce6$64fba3e0$2ef2eba0$@raj@ti.com> <013901cb1dc6$747ab500$5d701f00$@raj@ti.com> Message-ID: > -----Original Message----- > From: Sudhakar Rajashekhara [mailto:sudhakar.raj at ti.com] > Sent: Wednesday, July 07, 2010 6:21 AM > To: Brian Niebuhr; 'Brian Niebuhr'; > spi-devel-general at lists.sourceforge.net > Cc: davinci-linux-open-source at linux.davincidsp.com > Subject: Re: [spi-devel-general] [PATCH v2 0/1] davinci: > spi:replaceexisting driver > > Hi Brian, > > On Tue, Jul 06, 2010 at 19:45:56, Brian Niebuhr wrote: > > > On Sat, Jul 03, 2010 at 04:08:53, Brian Niebuhr wrote: > > > > I have included all of the recommended changes in this > > [...] > > > > > > > Quick update. > > > > > > I tested this patch on DM355 and DM365 EVMs. On DM355 all the > > > 3 modes (DMA, > > > Polled and Interrupt) worked fine. But in interrupt mode, on > > > DM355, if I set > > > "intr_level = 1", then kernel hangs during booting after printing > > > "spi spi0.0: DaVinci SPI driver in Interrupt mode" on the console. > > > > Sudhakar - > > > > When you changed the interrupt level, did you also change the > > IORESOURCE_IRQ entry for SPI0? Maybe we could set the > interrupt level > > automatically based on the IORESOURCE_IRQ provided? > > IORESOURCE_IRQ entry for dm365 were already present in dm365.c. I should have been more clear: The intr_level setting chooses which IRQ is used to signal events. If you change intr_level to 1 then you also need to change the IRQ that is provided as a resource to the driver to match. On DM355 intr_level=0 corresponds to SPINT0_0 (42) and intr_level=1 corresponds to SPINT0_1 (43). > > > > > On DM365 only DMA and Polled mode worked fine. In interrupt > > > mode, whether I > > > set intr_level to ZERO or ONE, kernel booting hangs, > similar to DM355. > > > > Does the interrupt mode of the existing driver work on DM365? > > > > AFAIK, support for interrupt mode was not present in the > earlier driver > by Sandeep Paulraj. > > > I don't have one of these boards, so I can't debug the > issue. If you > > have any ideas where the problem might be I'd appreciate the help in > > getting this resolved. > > As I mentioned in my earlier e-mail, on DM365 kernel booting > hangs after > Printing "spi spi0.0: DaVinci SPI driver in Interrupt mode" > on the console. > Control is in spi_sync() function waiting for completion. I've got an idea what the problem is: When I was writing the driver I was looking at the DM355 for as an example of the "version 1" SPI controller. The DM355 doesn't have a TX interrupt, so I thought that was a feature of the "version 1" controller. However, DM365 does have a TX interrupt, even though it has a "version 1" controller. The interrupt handler in the driver changes its processing based on whether it is a "version 1" or "version 2" device, but obviously that's not quite correct. Could you try one experiment for me on the DM365 board? Could you change SPIINT_MASKINT to 0x0000015Fu and retest on the DM365 only? This should make it behave like the DM355. If that fixes the problem, then at least I know where the problem is. I don't have a good idea how to solve it yet, though. > > If the change I mentioned above fixes the issue on DM355, then > > I am not sure whether my earlier mail was clear in this regard or not > but interrupt mode works fine on DM355 if intr_level = 0. > Kernel booting > hangs on DM355 if intr_level = 1. > > > I've got to imagine that it's just a configuration issue > > of some sort on DM365. > > > > I am also of the same opinion. > > Thanks, > Sudhakar > > > > -------------------------------------------------------------- > ---------------- > This SF.net email is sponsored by Sprint > What will you do first with EVO, the first 4G phone? > Visit sprint.com/first -- http://p.sf.net/sfu/sprint-com-first > _______________________________________________ > spi-devel-general mailing list > spi-devel-general at lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/spi-devel-general > > From sudhakar.raj at ti.com Wed Jul 7 22:49:02 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Thu, 8 Jul 2010 09:19:02 +0530 Subject: [spi-devel-general] [PATCH v2 0/1] davinci: spi:replaceexisting driver In-Reply-To: References: <1278110334-13943-1-git-send-email-bniebuhr@efjohnson.com><002301cb1ce6$64fba3e0$2ef2eba0$@raj@ti.com> <013901cb1dc6$747ab500$5d701f00$@raj@ti.com> Message-ID: <01df01cb1e50$8180f400$8482dc00$@raj@ti.com> Hi, On Wed, Jul 07, 2010 at 22:32:58, Brian Niebuhr wrote: > > -----Original Message----- > > From: Sudhakar Rajashekhara [mailto:sudhakar.raj at ti.com] > > Sent: Wednesday, July 07, 2010 6:21 AM > > To: Brian Niebuhr; 'Brian Niebuhr'; > > spi-devel-general at lists.sourceforge.net > > Cc: davinci-linux-open-source at linux.davincidsp.com > > Subject: Re: [spi-devel-general] [PATCH v2 0/1] davinci: > > spi:replaceexisting driver > > > > Hi Brian, > > > > On Tue, Jul 06, 2010 at 19:45:56, Brian Niebuhr wrote: > > > > On Sat, Jul 03, 2010 at 04:08:53, Brian Niebuhr wrote: > > > > > I have included all of the recommended changes in this > > > > [...] > > > > > > > > > > Quick update. > > > > > > > > I tested this patch on DM355 and DM365 EVMs. On DM355 all the > > > > 3 modes (DMA, > > > > Polled and Interrupt) worked fine. But in interrupt mode, on > > > > DM355, if I set > > > > "intr_level = 1", then kernel hangs during booting after printing > > > > "spi spi0.0: DaVinci SPI driver in Interrupt mode" on the console. > > > > > > Sudhakar - > > > > > > When you changed the interrupt level, did you also change the > > > IORESOURCE_IRQ entry for SPI0? Maybe we could set the > > interrupt level > > > automatically based on the IORESOURCE_IRQ provided? > > > > IORESOURCE_IRQ entry for dm365 were already present in dm365.c. > > > I should have been more clear: The intr_level setting chooses which IRQ > is used to signal events. If you change intr_level to 1 then you also > need to change the IRQ that is provided as a resource to the driver to > match. On DM355 intr_level=0 corresponds to SPINT0_0 (42) and > intr_level=1 corresponds to SPINT0_1 (43). > > > > > > > > > On DM365 only DMA and Polled mode worked fine. In interrupt > > > > mode, whether I > > > > set intr_level to ZERO or ONE, kernel booting hangs, > > similar to DM355. > > > > > > Does the interrupt mode of the existing driver work on DM365? > > > > > > > AFAIK, support for interrupt mode was not present in the > > earlier driver > > by Sandeep Paulraj. > > > > > I don't have one of these boards, so I can't debug the > > issue. If you > > > have any ideas where the problem might be I'd appreciate the help in > > > getting this resolved. > > > > As I mentioned in my earlier e-mail, on DM365 kernel booting > > hangs after > > Printing "spi spi0.0: DaVinci SPI driver in Interrupt mode" > > on the console. > > Control is in spi_sync() function waiting for completion. > > > I've got an idea what the problem is: When I was writing the driver I > was looking at the DM355 for as an example of the "version 1" SPI > controller. The DM355 doesn't have a TX interrupt, so I thought that > was a feature of the "version 1" controller. However, DM365 does have a > TX interrupt, even though it has a "version 1" controller. The > interrupt handler in the driver changes its processing based on whether > it is a "version 1" or "version 2" device, but obviously that's not > quite correct. > > Could you try one experiment for me on the DM365 board? Could you > change SPIINT_MASKINT to 0x0000015Fu and retest on the DM365 only? This > should make it behave like the DM355. If that fixes the problem, then > at least I know where the problem is. I don't have a good idea how to > solve it yet, though. > Bingo. With the modification you suggested above, interrupt mode worked fine on DM365. Thanks, Sudhakar From seanp at pfk.co.za Thu Jul 8 04:25:55 2010 From: seanp at pfk.co.za (Sean Kelvin Preston) Date: Thu, 8 Jul 2010 11:25:55 +0200 Subject: Driver probe functionality In-Reply-To: References: <000a01cb1dd3$95aba470$c102ed50$@pfk.co.za> Message-ID: <000301cb1e7f$99a7c520$ccf74f60$@pfk.co.za> Hi Jean-Philippe Thanks for the response. > For platform bus, you can match by id or by name : > for example in the board code you have : > > static struct platform_device davinci_nand_device = { >> lines removed.... >> > > And in the driver code : > > static struct platform_driver nand_davinci_driver = { >> linesremoved.... >> > > the device and driver name must match if you want the > platform_match function to work. I have found this code and the observed behaviour I have is that it is doing a match by name for the TI DM365 EVM board I am using. If I have the old NAND chip (MT29F16G08FAA) plugged in then I can see platform_match going through the list and it finds the davinci_nand driver. If I plug my new NAND chip (MT29F8G08ABABA) in then I can see the same platform_match occurring but this time it does not find the driver so no match occurs. I know this particular chip is supported on this EVM as I have managed to get it working correctly with uBoot but it obviously initialises and defines things differently to the kernel. So what I do not understand or know is what decides which drivers should be loaded? Something must be doing a check based on the fact that I have enabled the driver in the board config but it is not available for the platform_match to succeed. When I looked at the execution of the code I can see the following functions being called: platform_driver_probe, platform_driver_register, platform_match (repeated looking through list of driver names), platform_driver_unregister. It does not appear that the actual matching for NAND IDs is occurring as that section of the driver code does not appear to be executed so I think I am missing something that is executed earlier to detect the hardware. I would appreciate any pointers. Regards Sean -- Sean Preston Email: seanp at pfk.co.za From pjohn at mvista.com Thu Jul 8 05:09:02 2010 From: pjohn at mvista.com (Philby John) Date: Thu, 08 Jul 2010 15:39:02 +0530 Subject: Driver probe functionality In-Reply-To: <000301cb1e7f$99a7c520$ccf74f60$@pfk.co.za> References: <000a01cb1dd3$95aba470$c102ed50$@pfk.co.za> <000301cb1e7f$99a7c520$ccf74f60$@pfk.co.za> Message-ID: <1278583742.23958.1.camel@localhost.localdomain> On Thu, 2010-07-08 at 11:25 +0200, Sean Kelvin Preston wrote: > Hi Jean-Philippe > > Thanks for the response. > > > For platform bus, you can match by id or by name : > > for example in the board code you have : > > > > static struct platform_device davinci_nand_device = { > >> lines removed.... >> > > > > And in the driver code : > > > > static struct platform_driver nand_davinci_driver = { > >> linesremoved.... >> > > > > the device and driver name must match if you want the > > platform_match function to work. > > I have found this code and the observed behaviour I have is that it is doing > a match by name for the TI DM365 EVM board I am using. If I have the old > NAND chip (MT29F16G08FAA) plugged in then I can see platform_match going > through the list and it finds the davinci_nand driver. If I plug my new > NAND chip (MT29F8G08ABABA) in then I can see the same platform_match > occurring but this time it does not find the driver so no match occurs. > > I know this particular chip is supported on this EVM as I have managed to > get it working correctly with uBoot but it obviously initialises and defines > things differently to the kernel. So what I do not understand or know is > what decides which drivers should be loaded? Something must be doing a > check based on the fact that I have enabled the driver in the board config > but it is not available for the platform_match to succeed. > You are right, the platform_match() does not succeed based on a simple string comparison. platform_match() defined in platform.c drivers/base, does a string comparison of the driver and device name variable. If there is a name mismatch platform_match() bails out and the probe fails. Try setting the ".name" variable in your platform driver and device to be the same. Regards, Philby From seanp at pfk.co.za Thu Jul 8 05:37:47 2010 From: seanp at pfk.co.za (Sean Kelvin Preston) Date: Thu, 8 Jul 2010 12:37:47 +0200 Subject: Driver probe functionality In-Reply-To: <1278583742.23958.1.camel@localhost.localdomain> References: <000a01cb1dd3$95aba470$c102ed50$@pfk.co.za> <000301cb1e7f$99a7c520$ccf74f60$@pfk.co.za> <1278583742.23958.1.camel@localhost.localdomain> Message-ID: <000901cb1e89$a324c580$e96e5080$@pfk.co.za> Hi Philby > You are right, the platform_match() does not succeed based on a simple > string comparison. platform_match() defined in platform.c drivers/base, > does a string comparison of the driver and device name variable. If there is a > name mismatch platform_match() bails out and the probe fails. > > Try setting the ".name" variable in your platform driver and device to be the > same. The names are the same as I have not changed that code at all. As I was just testing the new NAND I did not change the drivers except to add an additional ID to the drivers/mtd/nand/nand_ids.c file. Otherwise I just replaced the actual chip on the EVM board. This is why I was wondering if there was something else going on when the platform_probe is done or maybe before that which is failing because I need to change or add something elsewhere to identify the new chip. Thanks for the info. Regards Sean -- Sean Preston Email: seanp at pfk.co.za From pjohn at mvista.com Thu Jul 8 05:53:10 2010 From: pjohn at mvista.com (Philby John) Date: Thu, 08 Jul 2010 16:23:10 +0530 Subject: Driver probe functionality In-Reply-To: <000901cb1e89$a324c580$e96e5080$@pfk.co.za> References: <000a01cb1dd3$95aba470$c102ed50$@pfk.co.za> <000301cb1e7f$99a7c520$ccf74f60$@pfk.co.za> <1278583742.23958.1.camel@localhost.localdomain> <000901cb1e89$a324c580$e96e5080$@pfk.co.za> Message-ID: <1278586390.24238.3.camel@localhost.localdomain> On Thu, 2010-07-08 at 12:37 +0200, Sean Kelvin Preston wrote: > Hi Philby > > > You are right, the platform_match() does not succeed based on a simple > > string comparison. platform_match() defined in platform.c drivers/base, > > does a string comparison of the driver and device name variable. If there > is a > > name mismatch platform_match() bails out and the probe fails. > > > > Try setting the ".name" variable in your platform driver and device to be > the > > same. > > The names are the same as I have not changed that code at all. As I was > just testing the new NAND I did not change the drivers except to add an > additional ID to the drivers/mtd/nand/nand_ids.c file. Otherwise I just > replaced the actual chip on the EVM board. This is why I was wondering if > there was something else going on when the platform_probe is done or maybe > before that which is failing because I need to change or add something > elsewhere to identify the new chip. > Okay, then how about here, where a check is first done to see if there is a match between the device and driver id if (drv->bus->match && !drv->bus->match(dev, drv)) Regards, Philby From seanp at pfk.co.za Thu Jul 8 06:28:50 2010 From: seanp at pfk.co.za (Sean Kelvin Preston) Date: Thu, 8 Jul 2010 13:28:50 +0200 Subject: Driver probe functionality In-Reply-To: <1278586390.24238.3.camel@localhost.localdomain> References: <000a01cb1dd3$95aba470$c102ed50$@pfk.co.za> <000301cb1e7f$99a7c520$ccf74f60$@pfk.co.za> <1278583742.23958.1.camel@localhost.localdomain> <000901cb1e89$a324c580$e96e5080$@pfk.co.za> <1278586390.24238.3.camel@localhost.localdomain> Message-ID: <001001cb1e90$c462e310$4d28a930$@pfk.co.za> Hi > > The names are the same as I have not changed that code at all. As I > > was just testing the new NAND I did not change the drivers except to > > add an additional ID to the drivers/mtd/nand/nand_ids.c file. > > Otherwise I just replaced the actual chip on the EVM board. This is > > why I was wondering if there was something else going on when the > > platform_probe is done or maybe before that which is failing because I > > need to change or add something elsewhere to identify the new chip. > > > > Okay, then how about here, where a check is first done to see if there is a > match between the device and driver id > > if (drv->bus->match && !drv->bus->match(dev, drv)) Sorry I am struggling to find this line of code. I am using version 2.6.32-rc2 of the kernel. Where would I look to find this entry? Regards Sean -- Sean Preston Email: seanp at pfk.co.za From pjohn at mvista.com Thu Jul 8 06:45:47 2010 From: pjohn at mvista.com (Philby John) Date: Thu, 08 Jul 2010 17:15:47 +0530 Subject: Driver probe functionality In-Reply-To: <001001cb1e90$c462e310$4d28a930$@pfk.co.za> References: <000a01cb1dd3$95aba470$c102ed50$@pfk.co.za> <000301cb1e7f$99a7c520$ccf74f60$@pfk.co.za> <1278583742.23958.1.camel@localhost.localdomain> <000901cb1e89$a324c580$e96e5080$@pfk.co.za> <1278586390.24238.3.camel@localhost.localdomain> <001001cb1e90$c462e310$4d28a930$@pfk.co.za> Message-ID: <1278589547.24560.1.camel@localhost.localdomain> On Thu, 2010-07-08 at 13:28 +0200, Sean Kelvin Preston wrote: > Hi > > > > The names are the same as I have not changed that code at all. As I > > > was just testing the new NAND I did not change the drivers except to > > > add an additional ID to the drivers/mtd/nand/nand_ids.c file. > > > Otherwise I just replaced the actual chip on the EVM board. This is > > > why I was wondering if there was something else going on when the > > > platform_probe is done or maybe before that which is failing because I > > > need to change or add something elsewhere to identify the new chip. > > > > > > > Okay, then how about here, where a check is first done to see if there is > a > > match between the device and driver id > > > > if (drv->bus->match && !drv->bus->match(dev, drv)) > > Sorry I am struggling to find this line of code. I am using version > 2.6.32-rc2 of the kernel. Where would I look to find this entry? > Sorry about that, I was looking at an older kernel version :-) In the function driver_match_device() Regards, Philby From seanp at pfk.co.za Thu Jul 8 07:20:38 2010 From: seanp at pfk.co.za (Sean Kelvin Preston) Date: Thu, 8 Jul 2010 14:20:38 +0200 Subject: Driver probe functionality In-Reply-To: <1278589547.24560.1.camel@localhost.localdomain> References: <000a01cb1dd3$95aba470$c102ed50$@pfk.co.za> <000301cb1e7f$99a7c520$ccf74f60$@pfk.co.za> <1278583742.23958.1.camel@localhost.localdomain> <000901cb1e89$a324c580$e96e5080$@pfk.co.za> <1278586390.24238.3.camel@localhost.localdomain> <001001cb1e90$c462e310$4d28a930$@pfk.co.za> <1278589547.24560.1.camel@localhost.localdomain> Message-ID: <001401cb1e98$01b9b0c0$052d1240$@pfk.co.za> Hi > Sorry about that, I was looking at an older kernel version :-) In the function > driver_match_device() Thanks for the suggestions and help so far but as I am new to this and I am really not understanding what the problem is. From what I have understood is that the platform_probe and platform_register functions are not loading the driver. I have not changed anything about the driver except to add the actual chip id to the nand_ids.c file but by looking at the original NAND boot sequence I have observed that this is only used later once the davinci_nand driver is loaded. So when the kernel boots and it needs to determine what hardware is there. How is it doing this? How does it know that a particular driver should be loaded? In my board configuration file for the TO DM365 EVM board it has an option to enable the davinci_nand and this is definitely being compiled in as the kernel work with the old NAND but not the new one. Except for me physically changing the NAND chip nothing else has changed so surely the driver should load anyway? Sorry for all the newbie questions but I am new and digging around worked for getting the NAND working with uBoot but is not for getting it to work with the Linux Kernel. Regards Sean -- Sean Preston Email: seanp at pfk.co.za From pjohn at mvista.com Thu Jul 8 07:46:19 2010 From: pjohn at mvista.com (Philby John) Date: Thu, 08 Jul 2010 18:16:19 +0530 Subject: Driver probe functionality In-Reply-To: <001401cb1e98$01b9b0c0$052d1240$@pfk.co.za> References: <000a01cb1dd3$95aba470$c102ed50$@pfk.co.za> <000301cb1e7f$99a7c520$ccf74f60$@pfk.co.za> <1278583742.23958.1.camel@localhost.localdomain> <000901cb1e89$a324c580$e96e5080$@pfk.co.za> <1278586390.24238.3.camel@localhost.localdomain> <001001cb1e90$c462e310$4d28a930$@pfk.co.za> <1278589547.24560.1.camel@localhost.localdomain> <001401cb1e98$01b9b0c0$052d1240$@pfk.co.za> Message-ID: <1278593179.24807.14.camel@localhost.localdomain> On Thu, 2010-07-08 at 14:20 +0200, Sean Kelvin Preston wrote: > Hi > > > Sorry about that, I was looking at an older kernel version :-) In the > function > > driver_match_device() > > Thanks for the suggestions and help so far but as I am new to this and I am > really not understanding what the problem is. From what I have understood > is that the platform_probe and platform_register functions are not loading > the driver. You need to identify exactly where the code fails. Like previously mentioned I could think of two such places, can't think of any other. > I have not changed anything about the driver except to add the > actual chip id to the nand_ids.c file but by looking at the original NAND > boot sequence I have observed that this is only used later once the > davinci_nand driver is loaded. > > So when the kernel boots and it needs to determine what hardware is there. > How is it doing this? How does it know that a particular driver should be > loaded? After a match is found using the id and name variable, the function driver_probe_device() calls really_probe(dev, drv). This is the function that actually calls your driver specific probe function. But you can verify all this by putting printk's in your code. Regards, Philby From jp.francois at cynove.com Thu Jul 8 08:28:34 2010 From: jp.francois at cynove.com (jean-philippe francois) Date: Thu, 8 Jul 2010 15:28:34 +0200 Subject: Driver probe functionality In-Reply-To: <001e01cb1e9a$7ddd67d0$79983770$@pfk.co.za> References: <000a01cb1dd3$95aba470$c102ed50$@pfk.co.za> <000301cb1e7f$99a7c520$ccf74f60$@pfk.co.za> <1278583742.23958.1.camel@localhost.localdomain> <000901cb1e89$a324c580$e96e5080$@pfk.co.za> <001e01cb1e9a$7ddd67d0$79983770$@pfk.co.za> Message-ID: 2010/7/8 Sean Kelvin Preston : > Hi > >> I guess it is not a platform_match problem then, but a driver_probe > problem. >> >> Did you try using it as a module ? > > No I have not tried it as a module. ?The TI DM365 EVM board does not have > any modules built by default from what I can see so will need to see how to > get it working with the build environment to test. ?The old NAND works > perfectly with this kernel. > > When the driver_probe is run how does it determine if a piece of hardware > exists or which driver a piece of hardware should be using. ?At this stage > nothing has been changed from a hardware point of view except the physical > NAND chip. ?As best as I can tell the interfacing is working correctly > because I can get the chip working with uBoot. The board code registers the device, if it is not compiled out by config options Then the nand driver init function register the driver. Since nothing changed, I assume the platform bus code matches the driver and the device. Then the driver code probe function is called. Then you have to dig in nand_scan_idents, which in turns calls nand_get_flash_type (in drivers/mtd/nand_base.c) Happy printk debugging ! Jean-Philippe Fran?ois From tharma at e-consystems.com Thu Jul 8 10:10:06 2010 From: tharma at e-consystems.com (Tharmarajan Ganeshan) Date: Thu, 08 Jul 2010 20:40:06 +0530 Subject: DM355 Auto Focus Message-ID: <1278601806.3821.42.camel@tharma-laptop> Hi All, I am working on a DM355 processor based Development board and the kernel version is 2.6.10. I need auto focus value that is sharpness of the image. I found an example application for autofocus in DM355 EVM package and the output of the sample example is as follows 2974 : Green Sum (Paxel 0 Data) 122 : FV Sum for IIR filter 0 (Paxel 0 Data) 1496 : FV Sum for IIR filter 1 (Paxel 0 Data) 0 : Zero (Paxel 0 Data) 1022 : Red/Blue Sum (Paxel 0 Data) 62 : FV Sum for IIR filter 0 (Paxel 0 Data) 831 : FV Sum for IIR filter 1 (Paxel 0 Data) 0 : Zero (Paxel 0 Data) 1122 : Red/Blue Sum (Paxel 0 Data) 115 : FV Sum for IIR filter 0 (Paxel 0 Data) 881 : FV Sum for IIR filter 1 (Paxel 0 Data) 0 : Zero (Paxel 0 Data) I could not understand this output format. Please can anyone clarify my doubts. I need a single focus value. How does I know that the object is focused properly using the H3A engine in DM355 ? Can I give a static frame data (instead of the frame captured from sensor) to this Auto Focus engine ? My configuration: int iir0[12] = { 64, 0, 0, 21, 22, 21, 0, 0, -16, 32, -16 }; int iir1[12] = { 64, 0, 0, 21, 22, 21, 0, -29, -16,32, -16 }; /* Enable Alaw */ config.alaw_enable = H3A_AF_DISABLE; /*Set Horizontal Median filter*/ config.hmf_config.enable = H3A_AF_DISABLE; config.hmf_config.threshold = 100; /* Set paxel Parmateres */ config.iir_config.hz_start_pos = 2; config.paxel_config.height = 8; config.paxel_config.width = 8; config.paxel_config.line_incr = 4; config.paxel_config.vt_start = 4; config.paxel_config.hz_start = 4; config.paxel_config.hz_cnt = 1; config.paxel_config.vt_cnt = 1; /* Set Accumulator mode */ //config.mode = ACCUMULATOR_SUMMED; config.mode = ACCUMULATOR_PEAK; /* Set IIR Filter Parameters */ for (index = 0; index < 11; index++) { config.iir_config.coeff_set0[index] = iir0[index]; config.iir_config.coeff_set1[index] = iir1[index]; } /* Set RGBPOSITION */ config.rgb_pos = RG_GB_BAYER; Thanks Dinesh -------------- next part -------------- An HTML attachment was scrubbed... URL: From bniebuhr3 at gmail.com Thu Jul 8 14:23:22 2010 From: bniebuhr3 at gmail.com (Brian Niebuhr) Date: Thu, 8 Jul 2010 14:23:22 -0500 Subject: [PATCH v3 0/1] davinci: spi: replace existing driver Message-ID: <1278617003-10295-1-git-send-email-bniebuhr@efjohnson.com> Fixed in this version: - Got rid of the incorrect IORESOURCE flags. DMA resources are now selected by index. - Added a third SPI controller version to differentiate the version on DM355 with no Tx interrupt and the version on DM365 and DM6467 with a Tx interrupt. This should fix the interrupt-mode issues on DM365. ** NOTE ** This patch requires the EDMA patch at: http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-March/018022.html which is queued waiting on another driver fix, for DMA mode to work correctly. Brian Niebuhr (1): davinci: spi: replace existing driver arch/arm/mach-davinci/board-dm355-evm.c | 10 + arch/arm/mach-davinci/board-dm355-leopard.c | 10 + arch/arm/mach-davinci/board-dm365-evm.c | 10 + arch/arm/mach-davinci/dm355.c | 8 +- arch/arm/mach-davinci/dm365.c | 6 - arch/arm/mach-davinci/include/mach/spi.h | 35 +- drivers/spi/davinci_spi.c | 1329 ++++++++++++--------------- 7 files changed, 640 insertions(+), 768 deletions(-) From bniebuhr3 at gmail.com Thu Jul 8 14:23:23 2010 From: bniebuhr3 at gmail.com (Brian Niebuhr) Date: Thu, 8 Jul 2010 14:23:23 -0500 Subject: [PATCH v3 1/1] davinci: spi: replace existing driver In-Reply-To: <1278617003-10295-1-git-send-email-bniebuhr@efjohnson.com> References: <1278617003-10295-1-git-send-email-bniebuhr@efjohnson.com> Message-ID: <1278617003-10295-2-git-send-email-bniebuhr@efjohnson.com> INTRODUCTION I have been working on a custom OMAP-L138 board that has multiple spi devices (seven) on one controller. These devices have a wide range of transfer parameters (speed, phase, polarity, internal and gpio chip selects). During my testing I found multiple errors in the davinci spi driver as a result of this complex setup. The primary issues were: 1. There is a race condition due to the SPIBUF read busy-waits for slow devices 2. I found some DMA transfer length errors under some conditions 3. The chip select code caused extra byte transfers (with no chip select active) due to writes to SPIDAT1 4. Several issues prevented using multiple SPI devices, especially the DMA code, as disucussed previously on the davinci list. The fixes to these problems were not simple. I ended up making fairly large changes to the driver, and those changes are contained in these patches. The full list of changes follows. CHANGE LIST 1. davinci_spi_chipelect() now performs both activation and deactivation of chip selects. This lets spi_bitbang fully control chip select activation, as intended by the SPI API. 2. Chip select activation does not cause extra writes to the SPI bus 3. Chip select activation does not use SPIDEF for control. This change will also allow for implementation of inverted (active high) chip selects in the future. 4. Added back gpio chip select capability from the old driver 5. Fixed prescale calculation for non-integer fractions of spi clock 6. Allow specification of SPI transfer parameters on a per-device (instead of per-controller) basis 7. Allow specification of polled, interrupt-based, or DMA operation on a per-device basis 8. Allow DMA with when more than one device is connected 9. Combined pio and dma txrx_bufs functions into one since they share large parts of their functionality, and to simplify item (8). 10. Use only SPIFMT0 to allow more than 4 devices TESTING I have tested the driver using a custom SPI stress test on my OMAP-L138-based board with three devices connected. I have tested configurations with all three devices polled, all three interrupt-based, all three DMA, and a mixture. I have compiled with the davinci_all_defconfig, but I don't have EVMs for the other davinci platforms to test with. Signed-off-by: Brian Niebuhr --- arch/arm/mach-davinci/board-dm355-evm.c | 10 + arch/arm/mach-davinci/board-dm355-leopard.c | 10 + arch/arm/mach-davinci/board-dm365-evm.c | 10 + arch/arm/mach-davinci/dm355.c | 8 +- arch/arm/mach-davinci/dm365.c | 6 - arch/arm/mach-davinci/include/mach/spi.h | 35 +- drivers/spi/davinci_spi.c | 1329 ++++++++++++--------------- 7 files changed, 640 insertions(+), 768 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index a319101..d2e9f20 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -32,6 +32,7 @@ #include #include #include +#include /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you @@ -300,10 +301,19 @@ static struct spi_eeprom at25640a = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640a_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm355_evm_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640a, + .controller_data = &at25640a_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index f1d8132..63078dc 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -29,6 +29,7 @@ #include #include #include +#include /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you @@ -222,10 +223,19 @@ static struct spi_eeprom at25640a = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640a_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm355_leopard_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640a, + .controller_data = &at25640a_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 5bb86b2..5bc3622 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -39,6 +39,7 @@ #include #include #include +#include #include @@ -579,10 +580,19 @@ static struct spi_eeprom at25640 = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm365_evm_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640, + .controller_data = &at25640_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 3834781..f747c05 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -410,14 +410,8 @@ static struct resource dm355_spi0_resources[] = { }; static struct davinci_spi_platform_data dm355_spi0_pdata = { - .version = SPI_VERSION_1, + .version = SPI_VERSION_0, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, }; static struct platform_device dm355_spi0_device = { .name = "spi_davinci", diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 652f4b6..4aea346 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); static struct davinci_spi_platform_data dm365_spi0_pdata = { .version = SPI_VERSION_1, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, }; static struct resource dm365_spi0_resources[] = { diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h index 910efbf..b57ca9b 100644 --- a/arch/arm/mach-davinci/include/mach/spi.h +++ b/arch/arm/mach-davinci/include/mach/spi.h @@ -19,26 +19,35 @@ #ifndef __ARCH_ARM_DAVINCI_SPI_H #define __ARCH_ARM_DAVINCI_SPI_H +#define SPI_INTERN_CS 0xFF + enum { - SPI_VERSION_1, /* For DM355/DM365/DM6467 */ + SPI_VERSION_0, /* For DM355 (reduced features, no Tx interrupt) */ + SPI_VERSION_1, /* For DM365/DM6467 (reduced features) */ SPI_VERSION_2, /* For DA8xx */ }; struct davinci_spi_platform_data { u8 version; - u8 num_chipselect; - u8 wdelay; - u8 odd_parity; - u8 parity_enable; - u8 wait_enable; - u8 timer_disable; - u8 clk_internal; - u8 cs_hold; + u16 num_chipselect; + u8 *chip_sel; +}; + +struct davinci_spi_config { + bool odd_parity; + bool parity_enable; u8 intr_level; - u8 poll_mode; - u8 use_dma; - u8 c2tdelay; - u8 t2cdelay; + u8 io_type; +#define SPI_IO_TYPE_INTR 0 +#define SPI_IO_TYPE_POLL 1 +#define SPI_IO_TYPE_DMA 2 + u8 bytes_per_word; + u8 wdelay; + bool timer_disable; + u8 c2t_delay; + u8 t2c_delay; + u8 t2e_delay; + u8 c2e_delay; }; #endif /* __ARCH_ARM_DAVINCI_SPI_H */ diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index b85090c..9ed9b20 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2009 Texas Instruments. + * Copyright (C) 2010 EF Johnson Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,197 +28,222 @@ #include #include #include -#include #include #include -#define SPI_NO_RESOURCE ((resource_size_t)-1) - -#define SPI_MAX_CHIPSELECT 2 - -#define CS_DEFAULT 0xFF - -#define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 - -#define SPIFMT_PHASE_MASK BIT(16) -#define SPIFMT_POLARITY_MASK BIT(17) -#define SPIFMT_DISTIMER_MASK BIT(18) -#define SPIFMT_SHIFTDIR_MASK BIT(20) -#define SPIFMT_WAITENA_MASK BIT(21) -#define SPIFMT_PARITYENA_MASK BIT(22) -#define SPIFMT_ODD_PARITY_MASK BIT(23) -#define SPIFMT_WDELAY_MASK 0x3f000000u -#define SPIFMT_WDELAY_SHIFT 24 -#define SPIFMT_CHARLEN_MASK 0x0000001Fu +#define CS_DEFAULT 0xFF +#define SCS0_SELECT 0x01 +#define SCS1_SELECT 0x02 +#define SCS2_SELECT 0x04 +#define SCS3_SELECT 0x08 +#define SCS4_SELECT 0x10 +#define SCS5_SELECT 0x20 +#define SCS6_SELECT 0x40 +#define SCS7_SELECT 0x80 + +#define RX_DMA_INDEX 0 +#define TX_DMA_INDEX 1 +#define EVENTQ_DMA_INDEX 2 + +#define SPIFMT_PHASE_MASK BIT(16) +#define SPIFMT_POLARITY_MASK BIT(17) +#define SPIFMT_DISTIMER_MASK BIT(18) +#define SPIFMT_SHIFTDIR_MASK BIT(20) +#define SPIFMT_WAITENA_MASK BIT(21) +#define SPIFMT_PARITYENA_MASK BIT(22) +#define SPIFMT_ODD_PARITY_MASK BIT(23) +#define SPIFMT_WDELAY_MASK 0x3f000000u +#define SPIFMT_WDELAY_SHIFT 24 +#define SPIFMT_CHARLEN_MASK 0x0000001Fu +#define SPIFMT_PRESCALE_SHIFT 8 /* SPIGCR1 */ -#define SPIGCR1_SPIENA_MASK 0x01000000u +#define SPIGCR1_SPIENA_MASK BIT(24) +#define SPIGCR1_POWERDOWN_MASK BIT(8) /* SPIPC0 */ -#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ -#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ -#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ -#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ -#define SPIPC0_EN1FUN_MASK BIT(1) -#define SPIPC0_EN0FUN_MASK BIT(0) - -#define SPIINT_MASKALL 0x0101035F -#define SPI_INTLVL_1 0x000001FFu -#define SPI_INTLVL_0 0x00000000u +#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ +#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ +#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ +#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ +#define SPIPC0_EN1FUN_MASK BIT(1) +#define SPIPC0_EN0FUN_MASK BIT(0) + +#define SPIINT_MASKALL 0x0101035Fu +#define SPIINT_MASKINT 0x0000035Fu +#define SPI_INTLVL_1 0x000001FFu +#define SPI_INTLVL_0 0x00000000u /* SPIDAT1 */ +#define SPIDAT1_CSHOLD_MASK BIT(28) #define SPIDAT1_CSHOLD_SHIFT 28 +#define SPIDAT1_WDEL_MASK BIT(26) +#define SPIDAT1_CSNR_MASK 0x00FF0000u #define SPIDAT1_CSNR_SHIFT 16 +#define SPIDAT1_DFSEL_MASK (BIT(24 | BIT(25)) #define SPIGCR1_CLKMOD_MASK BIT(1) -#define SPIGCR1_MASTER_MASK BIT(0) +#define SPIGCR1_MASTER_MASK BIT(0) #define SPIGCR1_LOOPBACK_MASK BIT(16) /* SPIBUF */ -#define SPIBUF_TXFULL_MASK BIT(29) -#define SPIBUF_RXEMPTY_MASK BIT(31) +#define SPIBUF_TXFULL_MASK BIT(29) +#define SPIBUF_RXEMPTY_MASK BIT(31) + +/* SPIDELAY */ +#define SPIDELAY_C2TDELAY_MASK 0xFF000000u +#define SPIDELAY_C2TDELAY_SHIFT 24 +#define SPIDELAY_T2CDELAY_MASK 0x00FF0000u +#define SPIDELAY_T2CDELAY_SHIFT 16 +#define SPIDELAY_T2EDELAY_MASK 0x0000FF00u +#define SPIDELAY_T2EDELAY_SHIFT 8 +#define SPIDELAY_C2EDELAY_MASK 0x000000FFu +#define SPIDELAY_C2EDELAY_SHIFT 0 + +/* SPIDEF */ +#define SPIDEF_CSDEF_MASK 0x000000FFu /* Error Masks */ -#define SPIFLG_DLEN_ERR_MASK BIT(0) -#define SPIFLG_TIMEOUT_MASK BIT(1) -#define SPIFLG_PARERR_MASK BIT(2) -#define SPIFLG_DESYNC_MASK BIT(3) -#define SPIFLG_BITERR_MASK BIT(4) -#define SPIFLG_OVRRUN_MASK BIT(6) -#define SPIFLG_RX_INTR_MASK BIT(8) -#define SPIFLG_TX_INTR_MASK BIT(9) -#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) -#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \ - | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ - | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ - | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \ - | SPIFLG_TX_INTR_MASK \ - | SPIFLG_BUF_INIT_ACTIVE_MASK) - -#define SPIINT_DLEN_ERR_INTR BIT(0) -#define SPIINT_TIMEOUT_INTR BIT(1) -#define SPIINT_PARERR_INTR BIT(2) -#define SPIINT_DESYNC_INTR BIT(3) -#define SPIINT_BITERR_INTR BIT(4) -#define SPIINT_OVRRUN_INTR BIT(6) -#define SPIINT_RX_INTR BIT(8) -#define SPIINT_TX_INTR BIT(9) -#define SPIINT_DMA_REQ_EN BIT(16) -#define SPIINT_ENABLE_HIGHZ BIT(24) - -#define SPI_T2CDELAY_SHIFT 16 -#define SPI_C2TDELAY_SHIFT 24 - +#define SPIFLG_DLEN_ERR_MASK BIT(0) +#define SPIFLG_TIMEOUT_MASK BIT(1) +#define SPIFLG_PARERR_MASK BIT(2) +#define SPIFLG_DESYNC_MASK BIT(3) +#define SPIFLG_BITERR_MASK BIT(4) +#define SPIFLG_OVRRUN_MASK BIT(6) +#define SPIFLG_RX_INTR_MASK BIT(8) +#define SPIFLG_TX_INTR_MASK BIT(9) +#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) +#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ + | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ + | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ + | SPIFLG_OVRRUN_MASK) +#define SPIFLG_MASK (SPIFLG_ERROR_MASK \ + | SPIFLG_RX_INTR_MASK | SPIFLG_TX_INTR_MASK \ + | SPIFLG_BUF_INIT_ACTIVE_MASK) + +#define SPIINT_DLEN_ERR_INTR BIT(0) +#define SPIINT_TIMEOUT_INTR BIT(1) +#define SPIINT_PARERR_INTR BIT(2) +#define SPIINT_DESYNC_INTR BIT(3) +#define SPIINT_BITERR_INTR BIT(4) +#define SPIINT_OVRRUN_INTR BIT(6) +#define SPIINT_RX_INTR BIT(8) +#define SPIINT_TX_INTR BIT(9) +#define SPIINT_DMA_REQ_EN BIT(16) +#define SPIINT_ENABLE_HIGHZ BIT(24) + +#define SPI_T2CDELAY_SHIFT 16 +#define SPI_C2TDELAY_SHIFT 24 /* SPI Controller registers */ -#define SPIGCR0 0x00 -#define SPIGCR1 0x04 -#define SPIINT 0x08 -#define SPILVL 0x0c -#define SPIFLG 0x10 -#define SPIPC0 0x14 -#define SPIPC1 0x18 -#define SPIPC2 0x1c -#define SPIPC3 0x20 -#define SPIPC4 0x24 -#define SPIPC5 0x28 -#define SPIPC6 0x2c -#define SPIPC7 0x30 -#define SPIPC8 0x34 -#define SPIDAT0 0x38 -#define SPIDAT1 0x3c -#define SPIBUF 0x40 -#define SPIEMU 0x44 -#define SPIDELAY 0x48 -#define SPIDEF 0x4c -#define SPIFMT0 0x50 -#define SPIFMT1 0x54 -#define SPIFMT2 0x58 -#define SPIFMT3 0x5c -#define TGINTVEC0 0x60 -#define TGINTVEC1 0x64 - -struct davinci_spi_slave { - u32 cmd_to_write; - u32 clk_ctrl_to_write; - u32 bytes_per_word; - u8 active_cs; +#define SPIGCR0 0x00 +#define SPIGCR1 0x04 +#define SPIINT 0x08 +#define SPILVL 0x0c +#define SPIFLG 0x10 +#define SPIPC0 0x14 +#define SPIPC1 0x18 +#define SPIPC2 0x1c +#define SPIPC3 0x20 +#define SPIPC4 0x24 +#define SPIPC5 0x28 +#define SPIPC6 0x2c +#define SPIPC7 0x30 +#define SPIPC8 0x34 +#define SPIDAT0 0x38 +#define SPIDAT1 0x3c +#define SPIBUF 0x40 +#define SPIEMU 0x44 +#define SPIDELAY 0x48 +#define SPIDEF 0x4c +#define SPIFMT0 0x50 +#define SPIFMT1 0x54 +#define SPIFMT2 0x58 +#define SPIFMT3 0x5c +#define TGINTVEC0 0x60 +#define TGINTVEC1 0x64 + +#define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) + +const char * const io_type_names[] = { + [SPI_IO_TYPE_INTR] = "Interrupt", + [SPI_IO_TYPE_POLL] = "Polled", + [SPI_IO_TYPE_DMA] = "DMA", }; /* We have 2 DMA channels per CS, one for RX and one for TX */ struct davinci_spi_dma { - int dma_tx_channel; - int dma_rx_channel; - int dma_tx_sync_dev; - int dma_rx_sync_dev; - enum dma_event_q eventq; - - struct completion dma_tx_completion; - struct completion dma_rx_completion; + int dma_tx_channel; + int dma_rx_channel; + int dma_tx_sync_dev; + int dma_rx_sync_dev; + int dummy_param_slot; + enum dma_event_q eventq; }; /* SPI Controller driver's private data. */ struct davinci_spi { - struct spi_bitbang bitbang; - struct clk *clk; - - u8 version; - resource_size_t pbase; - void __iomem *base; - size_t region_size; - u32 irq; - struct completion done; - - const void *tx; - void *rx; - u8 *tmp_buf; - int count; - struct davinci_spi_dma *dma_channels; - struct davinci_spi_platform_data *pdata; - - void (*get_rx)(u32 rx_data, struct davinci_spi *); - u32 (*get_tx)(struct davinci_spi *); - - struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT]; + struct spi_bitbang bitbang; + struct clk *clk; + + u8 version; + resource_size_t pbase; + void __iomem *base; + size_t region_size; + u32 irq; + struct completion done; + + const void *tx; + void *rx; + u8 *tmp_buf; + int rcount; + int wcount; + u32 errors; + struct davinci_spi_dma dma_channels; + struct davinci_spi_platform_data *pdata; + + void (*get_rx)(u32 rx_data, struct davinci_spi *); + u32 (*get_tx)(struct davinci_spi *); }; -static unsigned use_dma; +#define DAVINCI_SPI_NO_RESOURCE ((resource_size_t)-1) static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) { - u8 *rx = davinci_spi->rx; - - *rx++ = (u8)data; - davinci_spi->rx = rx; + if (davinci_spi->rx) { + u8 *rx = davinci_spi->rx; + *rx++ = (u8)data; + davinci_spi->rx = rx; + } } static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) { - u16 *rx = davinci_spi->rx; - - *rx++ = (u16)data; - davinci_spi->rx = rx; + if (davinci_spi->rx) { + u16 *rx = davinci_spi->rx; + *rx++ = (u16)data; + davinci_spi->rx = rx; + } } static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) { - u32 data; - const u8 *tx = davinci_spi->tx; - - data = *tx++; - davinci_spi->tx = tx; + u32 data = 0; + if (davinci_spi->tx) { + const u8 *tx = davinci_spi->tx; + data = *tx++; + davinci_spi->tx = tx; + } return data; } static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) { - u32 data; - const u16 *tx = davinci_spi->tx; - - data = *tx++; - davinci_spi->tx = tx; + u32 data = 0; + if (davinci_spi->tx) { + const u16 *tx = davinci_spi->tx; + data = *tx++; + davinci_spi->tx = tx; + } return data; } @@ -237,26 +263,6 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits) iowrite32(v, addr); } -static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num) -{ - set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); -} - -static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num) -{ - clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); -} - -static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) -{ - struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); - - if (enable) - set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); - else - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); -} - /* * Interface to control the chip select signal */ @@ -264,28 +270,57 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) { struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; - u32 data1_reg_val = 0; + u8 i, chip_sel = spi->chip_select; + u32 spidat1; + u16 spidat1_cfg; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; - /* - * Board specific chip select logic decides the polarity and cs - * line for the controller - */ - if (value == BITBANG_CS_INACTIVE) { - set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT); - - data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT; - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); + spidat1 = SPIDAT1_CSNR_MASK; + if (value == BITBANG_CS_ACTIVE) + spidat1 |= SPIDAT1_CSHOLD_MASK; + else + spidat1 |= SPIDAT1_WDEL_MASK; - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); + if (pdata->chip_sel == NULL) { + if (value == BITBANG_CS_ACTIVE) + spidat1 &= ~((0x1 << chip_sel) << SPIDAT1_CSNR_SHIFT); + } else { + for (i = 0; i < pdata->num_chipselect; i++) { + if (pdata->chip_sel[i] == SPI_INTERN_CS) { + if ((i == chip_sel) && + (value == BITBANG_CS_ACTIVE)) { + spidat1 &= ~((0x1 << chip_sel) + << SPIDAT1_CSNR_SHIFT); + } + } else { + if (value == BITBANG_CS_INACTIVE) + gpio_set_value(pdata->chip_sel[i], 1); + else if (i == chip_sel) + gpio_set_value(pdata->chip_sel[i], 0); + } + } } + + spidat1_cfg = spidat1 >> SPIDAT1_CSNR_SHIFT; + iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); +} + +/* + * davinci_spi_get_prescale - Calculates the correct prescale value + * @max_speed_hz: the maximum rate the SPI clock can run at + * + * This function calculates the prescale value that generates a clock rate + * less than or equal to the specified maximum + */ +static inline u32 davinci_spi_get_prescale(struct davinci_spi *davinci_spi, + u32 max_speed_hz) +{ + return ((clk_get_rate(davinci_spi->clk) - 1) / max_speed_hz) & 0xff; } -/** +/* * davinci_spi_setup_transfer - This functions will determine transfer method * @spi: spi device on which data transfer to be done * @t: spi transfer in which transfer info is filled @@ -297,14 +332,15 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) static int davinci_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { - struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; + struct davinci_spi_config *spi_cfg; u8 bits_per_word = 0; - u32 hz = 0, prescale = 0, clkspeed; + u32 hz = 0, spifmt = 0, prescale, delay = 0; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; + spi_cfg = spi->controller_data; if (t) { bits_per_word = t->bits_per_word; @@ -322,76 +358,112 @@ static int davinci_spi_setup_transfer(struct spi_device *spi, if (bits_per_word <= 8 && bits_per_word >= 2) { davinci_spi->get_rx = davinci_spi_rx_buf_u8; davinci_spi->get_tx = davinci_spi_tx_buf_u8; - davinci_spi->slave[spi->chip_select].bytes_per_word = 1; + spi_cfg->bytes_per_word = 1; } else if (bits_per_word <= 16 && bits_per_word >= 2) { davinci_spi->get_rx = davinci_spi_rx_buf_u16; davinci_spi->get_tx = davinci_spi_tx_buf_u16; - davinci_spi->slave[spi->chip_select].bytes_per_word = 2; + spi_cfg->bytes_per_word = 2; } else return -EINVAL; if (!hz) hz = spi->max_speed_hz; - clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK, - spi->chip_select); - set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f, - spi->chip_select); + prescale = davinci_spi_get_prescale(davinci_spi, hz); + spifmt |= (prescale << SPIFMT_PRESCALE_SHIFT); + + spifmt |= (bits_per_word & 0x1f); + + if (spi->mode & SPI_LSB_FIRST) + spifmt |= SPIFMT_SHIFTDIR_MASK; - clkspeed = clk_get_rate(davinci_spi->clk); - if (hz > clkspeed / 2) - prescale = 1 << 8; - if (hz < clkspeed / 256) - prescale = 255 << 8; - if (!prescale) - prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00; + if (spi->mode & SPI_CPOL) + spifmt |= SPIFMT_POLARITY_MASK; - clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select); - set_fmt_bits(davinci_spi->base, prescale, spi->chip_select); + if (!(spi->mode & SPI_CPHA)) + spifmt |= SPIFMT_PHASE_MASK; + + if (davinci_spi->version == SPI_VERSION_2) { + spifmt |= ((spi_cfg->wdelay << SPIFMT_WDELAY_SHIFT) + & SPIFMT_WDELAY_MASK); + + if (spi_cfg->odd_parity) + spifmt |= SPIFMT_ODD_PARITY_MASK; + + if (spi_cfg->parity_enable) + spifmt |= SPIFMT_PARITYENA_MASK; + + if (spi->mode & SPI_READY) { + spifmt |= SPIFMT_WAITENA_MASK; + delay |= (spi_cfg->t2e_delay + << SPIDELAY_T2EDELAY_SHIFT) + & SPIDELAY_T2EDELAY_MASK; + delay |= (spi_cfg->c2e_delay + << SPIDELAY_C2EDELAY_SHIFT) + & SPIDELAY_C2EDELAY_MASK; + } + + if (spi_cfg->timer_disable) { + spifmt |= SPIFMT_DISTIMER_MASK; + } else { + delay |= (spi_cfg->c2t_delay + << SPIDELAY_C2TDELAY_SHIFT) + & SPIDELAY_C2TDELAY_MASK; + delay |= (spi_cfg->t2c_delay + << SPIDELAY_T2CDELAY_SHIFT) + & SPIDELAY_T2CDELAY_MASK; + } + + iowrite32(delay, davinci_spi->base + SPIDELAY); + } + + iowrite32(spifmt, davinci_spi->base + SPIFMT0); + + if (spi_cfg->intr_level) + iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); + else + iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); + + if (spi->mode & SPI_LOOP) + set_io_bits(davinci_spi->base + SPIGCR1, + SPIGCR1_LOOPBACK_MASK); + else + clear_io_bits(davinci_spi->base + SPIGCR1, + SPIGCR1_LOOPBACK_MASK); return 0; } static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) { - struct spi_device *spi = (struct spi_device *)data; - struct davinci_spi *davinci_spi; + struct davinci_spi *davinci_spi = (struct davinci_spi *)data; struct davinci_spi_dma *davinci_spi_dma; struct davinci_spi_platform_data *pdata; - davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); + davinci_spi_dma = &(davinci_spi->dma_channels); pdata = davinci_spi->pdata; + edma_stop(davinci_spi_dma->dma_rx_channel); + if (ch_status == DMA_COMPLETE) - edma_stop(davinci_spi_dma->dma_rx_channel); - else - edma_clean_channel(davinci_spi_dma->dma_rx_channel); + davinci_spi->rcount = 0; - complete(&davinci_spi_dma->dma_rx_completion); - /* We must disable the DMA RX request */ - davinci_spi_set_dma_req(spi, 0); + complete(&davinci_spi->done); } static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) { - struct spi_device *spi = (struct spi_device *)data; - struct davinci_spi *davinci_spi; + struct davinci_spi *davinci_spi = (struct davinci_spi *)data; struct davinci_spi_dma *davinci_spi_dma; struct davinci_spi_platform_data *pdata; - davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); + davinci_spi_dma = &(davinci_spi->dma_channels); pdata = davinci_spi->pdata; - if (ch_status == DMA_COMPLETE) - edma_stop(davinci_spi_dma->dma_tx_channel); - else - edma_clean_channel(davinci_spi_dma->dma_tx_channel); + edma_stop(davinci_spi_dma->dma_tx_channel); - complete(&davinci_spi_dma->dma_tx_completion); - /* We must disable the DMA TX request */ - davinci_spi_set_dma_req(spi, 0); + if (ch_status == DMA_COMPLETE) + davinci_spi->wcount = 0; } static int davinci_spi_request_dma(struct spi_device *spi) @@ -403,33 +475,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) int r; davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; + davinci_spi_dma = &davinci_spi->dma_channels; pdata = davinci_spi->pdata; sdev = davinci_spi->bitbang.master->dev.parent; r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, - davinci_spi_dma_rx_callback, spi, + davinci_spi_dma_rx_callback, davinci_spi, davinci_spi_dma->eventq); if (r < 0) { - dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); - return -EAGAIN; + dev_dbg(sdev, "Unable to request DMA channel for MibSPI RX\n"); + r = -EAGAIN; + goto rx_dma_failed; } davinci_spi_dma->dma_rx_channel = r; + r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, - davinci_spi_dma_tx_callback, spi, + davinci_spi_dma_tx_callback, davinci_spi, davinci_spi_dma->eventq); if (r < 0) { - edma_free_channel(davinci_spi_dma->dma_rx_channel); - davinci_spi_dma->dma_rx_channel = -1; - dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); - return -EAGAIN; + dev_dbg(sdev, "Unable to request DMA channel for MibSPI TX\n"); + r = -EAGAIN; + goto tx_dma_failed; } davinci_spi_dma->dma_tx_channel = r; + r = edma_alloc_slot(EDMA_CTLR(davinci_spi_dma->dma_tx_sync_dev), + EDMA_SLOT_ANY); + if (r < 0) { + dev_dbg(sdev, "Unable to request SPI DMA param slot\n"); + r = -EAGAIN; + goto param_failed; + } + davinci_spi_dma->dummy_param_slot = r; + edma_link(davinci_spi_dma->dummy_param_slot, + davinci_spi_dma->dummy_param_slot); + return 0; + +param_failed: + edma_free_channel(davinci_spi_dma->dma_tx_channel); + davinci_spi_dma->dma_tx_channel = -1; +tx_dma_failed: + edma_free_channel(davinci_spi_dma->dma_rx_channel); + davinci_spi_dma->dma_rx_channel = -1; +rx_dma_failed: + return r; } -/** +/* * davinci_spi_setup - This functions will set default transfer method * @spi: spi device on which data transfer to be done * @@ -438,129 +531,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) static int davinci_spi_setup(struct spi_device *spi) { - int retval; + int retval = 0; struct davinci_spi *davinci_spi; - struct davinci_spi_dma *davinci_spi_dma; - struct device *sdev; + struct davinci_spi_dma *davinci_dma; + struct davinci_spi_platform_data *pdata; + struct davinci_spi_config *spi_cfg; + u32 prescale; davinci_spi = spi_master_get_devdata(spi->master); - sdev = davinci_spi->bitbang.master->dev.parent; + pdata = davinci_spi->pdata; + spi_cfg = (struct davinci_spi_config *)spi->controller_data; + davinci_dma = &(davinci_spi->dma_channels); /* if bits per word length is zero then set it default 8 */ if (!spi->bits_per_word) spi->bits_per_word = 8; - davinci_spi->slave[spi->chip_select].cmd_to_write = 0; - - if (use_dma && davinci_spi->dma_channels) { - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if ((davinci_spi_dma->dma_rx_channel == -1) - || (davinci_spi_dma->dma_tx_channel == -1)) { - retval = davinci_spi_request_dma(spi); - if (retval < 0) - return retval; - } - } + if (!(spi->mode & SPI_NO_CS)) { + if ((pdata->chip_sel == NULL) || + (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) + set_io_bits(davinci_spi->base + SPIPC0, + 1 << spi->chip_select); - /* - * SPI in DaVinci and DA8xx operate between - * 600 KHz and 50 MHz - */ - if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) { - dev_dbg(sdev, "Operating frequency is not in acceptable " - "range\n"); - return -EINVAL; } - /* - * Set up SPIFMTn register, unique to this chipselect. - * - * NOTE: we could do all of these with one write. Also, some - * of the "version 2" features are found in chips that don't - * support all of them... - */ - if (spi->mode & SPI_LSB_FIRST) - set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, - spi->chip_select); + if (spi->mode & SPI_READY) + set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); - if (spi->mode & SPI_CPOL) - set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, - spi->chip_select); + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + davinci_dma = &(davinci_spi->dma_channels); - if (!(spi->mode & SPI_CPHA)) - set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, - spi->chip_select); + if ((davinci_dma->dma_tx_sync_dev == DAVINCI_SPI_NO_RESOURCE) || + (davinci_dma->dma_rx_sync_dev == DAVINCI_SPI_NO_RESOURCE) || + (davinci_dma->eventq == DAVINCI_SPI_NO_RESOURCE)) + spi_cfg->io_type = SPI_IO_TYPE_INTR; + else if ((davinci_dma->dma_rx_channel == -1) || + (davinci_dma->dma_tx_channel == -1)) + retval = davinci_spi_request_dma(spi); + } /* - * Version 1 hardware supports two basic SPI modes: - * - Standard SPI mode uses 4 pins, with chipselect - * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) - * (distinct from SPI_3WIRE, with just one data wire; - * or similar variants without MOSI or without MISO) - * - * Version 2 hardware supports an optional handshaking signal, - * so it can support two more modes: - * - 5 pin SPI variant is standard SPI plus SPI_READY - * - 4 pin with enable is (SPI_READY | SPI_NO_CS) + * Validate desired clock rate */ + prescale = davinci_spi_get_prescale(davinci_spi, spi->max_speed_hz); + if ((prescale < 2) || (prescale > 255)) + return -EINVAL; - if (davinci_spi->version == SPI_VERSION_2) { - clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK, - spi->chip_select); - set_fmt_bits(davinci_spi->base, - (davinci_spi->pdata->wdelay - << SPIFMT_WDELAY_SHIFT) - & SPIFMT_WDELAY_MASK, - spi->chip_select); - - if (davinci_spi->pdata->odd_parity) - set_fmt_bits(davinci_spi->base, - SPIFMT_ODD_PARITY_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_ODD_PARITY_MASK, - spi->chip_select); - - if (davinci_spi->pdata->parity_enable) - set_fmt_bits(davinci_spi->base, - SPIFMT_PARITYENA_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_PARITYENA_MASK, - spi->chip_select); - - if (davinci_spi->pdata->wait_enable) - set_fmt_bits(davinci_spi->base, - SPIFMT_WAITENA_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_WAITENA_MASK, - spi->chip_select); - - if (davinci_spi->pdata->timer_disable) - set_fmt_bits(davinci_spi->base, - SPIFMT_DISTIMER_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_DISTIMER_MASK, - spi->chip_select); - } - - retval = davinci_spi_setup_transfer(spi, NULL); + dev_info(&spi->dev, "DaVinci SPI driver in %s mode\n", + io_type_names[spi_cfg->io_type]); return retval; } @@ -569,50 +587,19 @@ static void davinci_spi_cleanup(struct spi_device *spi) { struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); struct davinci_spi_dma *davinci_spi_dma; + struct davinci_spi_platform_data *pdata; - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if (use_dma && davinci_spi->dma_channels) { - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if ((davinci_spi_dma->dma_rx_channel != -1) - && (davinci_spi_dma->dma_tx_channel != -1)) { - edma_free_channel(davinci_spi_dma->dma_tx_channel); - edma_free_channel(davinci_spi_dma->dma_rx_channel); - } - } -} - -static int davinci_spi_bufs_prep(struct spi_device *spi, - struct davinci_spi *davinci_spi) -{ - int op_mode = 0; - - /* - * REVISIT unless devices disagree about SPI_LOOP or - * SPI_READY (SPI_NO_CS only allows one device!), this - * should not need to be done before each message... - * optimize for both flags staying cleared. - */ - - op_mode = SPIPC0_DIFUN_MASK - | SPIPC0_DOFUN_MASK - | SPIPC0_CLKFUN_MASK; - if (!(spi->mode & SPI_NO_CS)) - op_mode |= 1 << spi->chip_select; - if (spi->mode & SPI_READY) - op_mode |= SPIPC0_SPIENA_MASK; + davinci_spi_dma = &davinci_spi->dma_channels; + pdata = davinci_spi->pdata; - iowrite32(op_mode, davinci_spi->base + SPIPC0); + if (davinci_spi_dma->dma_rx_channel != -1) + edma_free_channel(davinci_spi_dma->dma_rx_channel); - if (spi->mode & SPI_LOOP) - set_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_LOOPBACK_MASK); - else - clear_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_LOOPBACK_MASK); + if (davinci_spi_dma->dma_tx_channel != -1) + edma_free_channel(davinci_spi_dma->dma_tx_channel); - return 0; + if (davinci_spi_dma->dummy_param_slot != -1) + edma_free_slot(davinci_spi_dma->dummy_param_slot); } static int davinci_spi_check_error(struct davinci_spi *davinci_spi, @@ -659,356 +646,243 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi, return 0; } -/** - * davinci_spi_bufs - functions which will handle transfer data - * @spi: spi device on which data transfer to be done - * @t: spi transfer in which transfer info is filled +/* + * davinci_spi_process_events - check for and handle any SPI controller events + * @davinci_spi - the controller data * - * This function will put data to be transferred into data register - * of SPI controller and then wait until the completion will be marked - * by the IRQ Handler. + * This function will check the SPIFLG register and handle any events that are + * detected there */ -static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) +static int davinci_spi_process_events(struct davinci_spi *davinci_spi) { - struct davinci_spi *davinci_spi; - int int_status, count, ret; - u8 conv, tmp; - u32 tx_data, data1_reg_val; - u32 buf_val, flg_val; - struct davinci_spi_platform_data *pdata; - - davinci_spi = spi_master_get_devdata(spi->master); - pdata = davinci_spi->pdata; - - davinci_spi->tx = t->tx_buf; - davinci_spi->rx = t->rx_buf; - - /* convert len to words based on bits_per_word */ - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; - davinci_spi->count = t->len / conv; - - INIT_COMPLETION(davinci_spi->done); - - ret = davinci_spi_bufs_prep(spi, davinci_spi); - if (ret) - return ret; - - /* Enable SPI */ - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), - davinci_spi->base + SPIDELAY); - - count = davinci_spi->count; - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; - tmp = ~(0x1 << spi->chip_select); - - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); - - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; - - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); - - /* Determine the command to execute READ or WRITE */ - if (t->tx_buf) { - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); - - while (1) { - tx_data = davinci_spi->get_tx(davinci_spi); - - data1_reg_val &= ~(0xFFFF); - data1_reg_val |= (0xFFFF & tx_data); - - buf_val = ioread32(davinci_spi->base + SPIBUF); - if ((buf_val & SPIBUF_TXFULL_MASK) == 0) { - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - count--; - } - while (ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) - cpu_relax(); - - /* getting the returned byte */ - if (t->rx_buf) { - buf_val = ioread32(davinci_spi->base + SPIBUF); - davinci_spi->get_rx(buf_val, davinci_spi); - } - if (count <= 0) - break; - } - } else { - if (pdata->poll_mode) { - while (1) { - /* keeps the serial clock going */ - if ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_TXFULL_MASK) == 0) - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - while (ioread32(davinci_spi->base + SPIBUF) & - SPIBUF_RXEMPTY_MASK) - cpu_relax(); - - flg_val = ioread32(davinci_spi->base + SPIFLG); - buf_val = ioread32(davinci_spi->base + SPIBUF); - - davinci_spi->get_rx(buf_val, davinci_spi); - - count--; - if (count <= 0) - break; - } - } else { /* Receive in Interrupt mode */ - int i; - - for (i = 0; i < davinci_spi->count; i++) { - set_io_bits(davinci_spi->base + SPIINT, - SPIINT_BITERR_INTR - | SPIINT_OVRRUN_INTR - | SPIINT_RX_INTR); - - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - while (ioread32(davinci_spi->base + SPIINT) & - SPIINT_RX_INTR) - cpu_relax(); - } - iowrite32((data1_reg_val & 0x0ffcffff), - davinci_spi->base + SPIDAT1); - } + u32 status, tx_data, rx_data, spidat1; + u8 tx_word = 0; + + status = ioread32(davinci_spi->base + SPIFLG); + + if ((davinci_spi->version != SPI_VERSION_0) && + (likely(status & SPIFLG_TX_INTR_MASK)) && + (likely(davinci_spi->wcount > 0))) + tx_word = 1; + + if (likely(status & SPIFLG_RX_INTR_MASK)) { + rx_data = ioread32(davinci_spi->base + SPIBUF) & 0xFFFF; + davinci_spi->get_rx(rx_data, davinci_spi); + davinci_spi->rcount--; + if ((davinci_spi->version == SPI_VERSION_0) && + (likely(davinci_spi->wcount > 0))) + tx_word = 1; } - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - int_status = ioread32(davinci_spi->base + SPIFLG); - - ret = davinci_spi_check_error(davinci_spi, int_status); - if (ret != 0) - return ret; + if (unlikely(status & SPIFLG_ERROR_MASK)) { + davinci_spi->errors = (status & SPIFLG_ERROR_MASK); + return -1; + } - /* SPI Framework maintains the count only in bytes so convert back */ - davinci_spi->count *= conv; + if (likely(tx_word)) { + spidat1 = ioread32(davinci_spi->base + SPIDAT1); + davinci_spi->wcount--; + tx_data = davinci_spi->get_tx(davinci_spi); + spidat1 &= 0xFFFF0000; + spidat1 |= (tx_data & 0xFFFF); + iowrite32(spidat1, davinci_spi->base + SPIDAT1); + } - return t->len; + return 0; } -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 - -static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) +/* + * davinci_spi_txrx_bufs - function which will handle transfer data + * @spi: spi device on which data transfer to be done + * @t: spi transfer in which transfer info is filled + * + * This function will put data to be transferred into data register + * of SPI controller and then wait until the completion will be marked + * by the IRQ Handler. + */ +static int davinci_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) { struct davinci_spi *davinci_spi; - int int_status = 0; - int count, temp_count; - u8 conv = 1; - u8 tmp; - u32 data1_reg_val; - struct davinci_spi_dma *davinci_spi_dma; - int word_len, data_type, ret; - unsigned long tx_reg, rx_reg; + int data_type, ret = 0; + u32 tx_data, spidat1; + u16 tx_buf_count = 0, rx_buf_count = 0; + struct davinci_spi_config *spi_cfg; struct davinci_spi_platform_data *pdata; + struct davinci_spi_dma *davinci_dma; struct device *sdev; + dma_addr_t tx_reg, rx_reg; + void *tx_buf, *rx_buf; + struct edmacc_param rx_param, tx_param; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; - sdev = davinci_spi->bitbang.master->dev.parent; - - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; - rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; + spi_cfg = (struct davinci_spi_config *)spi->controller_data; + davinci_dma = &(davinci_spi->dma_channels); davinci_spi->tx = t->tx_buf; davinci_spi->rx = t->rx_buf; + davinci_spi->wcount = t->len / spi_cfg->bytes_per_word; + davinci_spi->rcount = davinci_spi->wcount; + davinci_spi->errors = 0; - /* convert len to words based on bits_per_word */ - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; - davinci_spi->count = t->len / conv; - - INIT_COMPLETION(davinci_spi->done); + spidat1 = ioread32(davinci_spi->base + SPIDAT1); - init_completion(&davinci_spi_dma->dma_rx_completion); - init_completion(&davinci_spi_dma->dma_tx_completion); - - word_len = conv * 8; - - if (word_len <= 8) - data_type = DAVINCI_DMA_DATA_TYPE_S8; - else if (word_len <= 16) - data_type = DAVINCI_DMA_DATA_TYPE_S16; - else if (word_len <= 32) - data_type = DAVINCI_DMA_DATA_TYPE_S32; - else - return -EINVAL; - - ret = davinci_spi_bufs_prep(spi, davinci_spi); - if (ret) - return ret; - - /* Put delay val if required */ - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), - davinci_spi->base + SPIDELAY); - - count = davinci_spi->count; /* the number of elements */ - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; - - /* CS default = 0xFF */ - tmp = ~(0x1 << spi->chip_select); - - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); - - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; - - /* disable all interrupts for dma transfers */ - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); - /* Disable SPI to write configuration bits in SPIDAT */ - clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); - /* Enable SPI */ + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); - + INIT_COMPLETION(davinci_spi->done); - if (t->tx_buf) { - t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, - DMA_TO_DEVICE); - if (dma_mapping_error(&spi->dev, t->tx_dma)) { - dev_dbg(sdev, "Unable to DMA map a %d bytes" - " TX buffer\n", count); - return -ENOMEM; + if ((spi_cfg->io_type == SPI_IO_TYPE_INTR) || + (spi_cfg->io_type == SPI_IO_TYPE_POLL)) { + + if (spi_cfg->io_type == SPI_IO_TYPE_INTR) + set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); + + /* start the transfer */ + davinci_spi->wcount--; + tx_data = davinci_spi->get_tx(davinci_spi); + spidat1 &= 0xFFFF0000; + spidat1 |= (tx_data & 0xFFFF); + iowrite32(spidat1, davinci_spi->base + SPIDAT1); + + } else if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + data_type = spi_cfg->bytes_per_word; + tx_reg = (dma_addr_t)davinci_spi->pbase + SPIDAT1; + rx_reg = (dma_addr_t)davinci_spi->pbase + SPIBUF; + + if (t->tx_buf) { + tx_buf = ((void *)t->tx_buf); + tx_buf_count = davinci_spi->wcount; + } else { + tx_buf = (void *)davinci_spi->tmp_buf; + tx_buf_count = SPI_BUFSIZ; } - temp_count = count; - } else { - /* We need TX clocking for RX transaction */ - t->tx_dma = dma_map_single(&spi->dev, - (void *)davinci_spi->tmp_buf, count + 1, - DMA_TO_DEVICE); - if (dma_mapping_error(&spi->dev, t->tx_dma)) { - dev_dbg(sdev, "Unable to DMA map a %d bytes" - " TX tmp buffer\n", count); - return -ENOMEM; + if (t->rx_buf) { + rx_buf = (void *)t->rx_buf; + rx_buf_count = davinci_spi->rcount; + } else { + rx_buf = (void *)davinci_spi->tmp_buf; + rx_buf_count = SPI_BUFSIZ; } - temp_count = count + 1; + + t->tx_dma = dma_map_single(&spi->dev, tx_buf, + tx_buf_count, DMA_TO_DEVICE); + t->rx_dma = dma_map_single(&spi->dev, rx_buf, + rx_buf_count, DMA_FROM_DEVICE); + + tx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_tx_channel); + tx_param.src = t->tx_buf ? t->tx_dma : tx_reg; + tx_param.a_b_cnt = davinci_spi->wcount << 16 | data_type; + tx_param.dst = tx_reg; + tx_param.src_dst_bidx = t->tx_buf ? data_type : 0; + tx_param.link_bcntrld = 0xffff; + tx_param.src_dst_cidx = 0; + tx_param.ccnt = 1; + edma_write_slot(davinci_dma->dma_tx_channel, &tx_param); + edma_link(davinci_dma->dma_tx_channel, + davinci_dma->dummy_param_slot); + + rx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_rx_channel); + rx_param.src = rx_reg; + rx_param.a_b_cnt = davinci_spi->rcount << 16 | data_type; + rx_param.dst = t->rx_dma; + rx_param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; + rx_param.link_bcntrld = 0xffff; + rx_param.src_dst_cidx = 0; + rx_param.ccnt = 1; + edma_write_slot(davinci_dma->dma_rx_channel, &rx_param); + + iowrite16(spidat1 >> SPIDAT1_CSNR_SHIFT, + davinci_spi->base + SPIDAT1 + 2); + + edma_start(davinci_dma->dma_rx_channel); + edma_start(davinci_dma->dma_tx_channel); + set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); } - edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, - data_type, temp_count, 1, 0, ASYNC); - edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); - edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT); - edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0); - edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); - - if (t->rx_buf) { - /* initiate transaction */ - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); - - t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, - DMA_FROM_DEVICE); - if (dma_mapping_error(&spi->dev, t->rx_dma)) { - dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", - count); - if (t->tx_buf != NULL) - dma_unmap_single(NULL, t->tx_dma, - count, DMA_TO_DEVICE); - return -ENOMEM; + /* Wait for the transfer to complete */ + if (spi_cfg->io_type != SPI_IO_TYPE_POLL) { + wait_for_completion_interruptible(&(davinci_spi->done)); + } else { + while ((davinci_spi->rcount > 0) && (ret == 0)) { + ret = davinci_spi_process_events(davinci_spi); + cpu_relax(); } - edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, - data_type, count, 1, 0, ASYNC); - edma_set_src(davinci_spi_dma->dma_rx_channel, - rx_reg, INCR, W8BIT); - edma_set_dest(davinci_spi_dma->dma_rx_channel, - t->rx_dma, INCR, W8BIT); - edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); - edma_set_dest_index(davinci_spi_dma->dma_rx_channel, - data_type, 0); } - if ((t->tx_buf) || (t->rx_buf)) - edma_start(davinci_spi_dma->dma_tx_channel); - - if (t->rx_buf) - edma_start(davinci_spi_dma->dma_rx_channel); - - if ((t->rx_buf) || (t->tx_buf)) - davinci_spi_set_dma_req(spi, 1); - - if (t->tx_buf) - wait_for_completion_interruptible( - &davinci_spi_dma->dma_tx_completion); - - if (t->rx_buf) - wait_for_completion_interruptible( - &davinci_spi_dma->dma_rx_completion); - - dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE); - - if (t->rx_buf) - dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); - - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - int_status = ioread32(davinci_spi->base + SPIFLG); + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + dma_unmap_single(NULL, t->tx_dma, tx_buf_count, + DMA_TO_DEVICE); + dma_unmap_single(NULL, t->rx_dma, rx_buf_count, + DMA_FROM_DEVICE); + } - ret = davinci_spi_check_error(davinci_spi, int_status); - if (ret != 0) - return ret; + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - /* SPI Framework maintains the count only in bytes so convert back */ - davinci_spi->count *= conv; + if (davinci_spi->errors) { + ret = davinci_spi_check_error(davinci_spi, davinci_spi->errors); + if (ret != 0) + return ret; + } + if ((davinci_spi->rcount != 0) || (davinci_spi->wcount != 0)) { + sdev = davinci_spi->bitbang.master->dev.parent; + dev_info(sdev, "SPI data transfer error\n"); + return -EIO; + } return t->len; } -/** - * davinci_spi_irq - IRQ handler for DaVinci SPI +/* + * davinci_spi_irq - probe function for SPI Master Controller * @irq: IRQ number for this SPI Master * @context_data: structure for SPI Master controller davinci_spi + * + * ISR will determine that interrupt arrives either for READ or WRITE command. + * According to command it will do the appropriate action. It will check + * transfer length and if it is not zero then dispatch transfer command again. + * If transfer length is zero then it will indicate the COMPLETION so that + * davinci_spi_bufs function can go ahead. */ static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) { struct davinci_spi *davinci_spi = context_data; - u32 int_status, rx_data = 0; - irqreturn_t ret = IRQ_NONE; + int status; - int_status = ioread32(davinci_spi->base + SPIFLG); + status = davinci_spi_process_events(davinci_spi); + if (unlikely(status != 0)) + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); - while ((int_status & SPIFLG_RX_INTR_MASK)) { - if (likely(int_status & SPIFLG_RX_INTR_MASK)) { - ret = IRQ_HANDLED; + if ((davinci_spi->rcount == 0) || (status != 0)) + complete(&(davinci_spi->done)); - rx_data = ioread32(davinci_spi->base + SPIBUF); - davinci_spi->get_rx(rx_data, davinci_spi); + return IRQ_HANDLED; +} - /* Disable Receive Interrupt */ - iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR), - davinci_spi->base + SPIINT); - } else - (void)davinci_spi_check_error(davinci_spi, int_status); +resource_size_t davinci_spi_get_dma_by_index(struct platform_device *dev, + unsigned long index) +{ + struct resource *r; - int_status = ioread32(davinci_spi->base + SPIFLG); - } + r = platform_get_resource(dev, IORESOURCE_DMA, index); + if (r != NULL) + return r->start; - return ret; + return DAVINCI_SPI_NO_RESOURCE; } -/** +/* * davinci_spi_probe - probe function for SPI Master Controller * @pdev: platform_device structure which contains plateform specific data + * + * According to Linux Device Model this function will be invoked by Linux + * with platform_device struct which contains the device specific info. + * This function will map the SPI controller's memory, register IRQ, + * Reset SPI controller and setting its registers to default value. + * It will invoke spi_bitbang_start to create work queue so that client driver + * can register transfer method to work queue. */ static int davinci_spi_probe(struct platform_device *pdev) { @@ -1016,10 +890,11 @@ static int davinci_spi_probe(struct platform_device *pdev) struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; struct resource *r, *mem; - resource_size_t dma_rx_chan = SPI_NO_RESOURCE; - resource_size_t dma_tx_chan = SPI_NO_RESOURCE; - resource_size_t dma_eventq = SPI_NO_RESOURCE; + resource_size_t dma_rx_chan = DAVINCI_SPI_NO_RESOURCE; + resource_size_t dma_tx_chan = DAVINCI_SPI_NO_RESOURCE; + resource_size_t dma_eventq = DAVINCI_SPI_NO_RESOURCE; int i = 0, ret = 0; + u32 spipc0; pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -1071,16 +946,18 @@ static int davinci_spi_probe(struct platform_device *pdev) goto unmap_io; } - ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED, + ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev), davinci_spi); - if (ret) + if (ret != 0) { + ret = -EAGAIN; goto unmap_io; + } /* Allocate tmp_buf for tx_buf */ davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); if (davinci_spi->tmp_buf == NULL) { ret = -ENOMEM; - goto irq_free; + goto err1; } davinci_spi->bitbang.master = spi_master_get(master); @@ -1104,55 +981,23 @@ static int davinci_spi_probe(struct platform_device *pdev) davinci_spi->bitbang.chipselect = davinci_spi_chipselect; davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; + davinci_spi->bitbang.txrx_bufs = davinci_spi_txrx_bufs; davinci_spi->version = pdata->version; - use_dma = pdata->use_dma; davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; if (davinci_spi->version == SPI_VERSION_2) davinci_spi->bitbang.flags |= SPI_READY; - if (use_dma) { - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (r) - dma_rx_chan = r->start; - r = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (r) - dma_tx_chan = r->start; - r = platform_get_resource(pdev, IORESOURCE_DMA, 2); - if (r) - dma_eventq = r->start; - } - - if (!use_dma || - dma_rx_chan == SPI_NO_RESOURCE || - dma_tx_chan == SPI_NO_RESOURCE || - dma_eventq == SPI_NO_RESOURCE) { - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; - use_dma = 0; - } else { - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; - davinci_spi->dma_channels = kzalloc(master->num_chipselect - * sizeof(struct davinci_spi_dma), GFP_KERNEL); - if (davinci_spi->dma_channels == NULL) { - ret = -ENOMEM; - goto free_clk; - } - - for (i = 0; i < master->num_chipselect; i++) { - davinci_spi->dma_channels[i].dma_rx_channel = -1; - davinci_spi->dma_channels[i].dma_rx_sync_dev = - dma_rx_chan; - davinci_spi->dma_channels[i].dma_tx_channel = -1; - davinci_spi->dma_channels[i].dma_tx_sync_dev = - dma_tx_chan; - davinci_spi->dma_channels[i].eventq = dma_eventq; - } - dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" - "Using RX channel = %d , TX channel = %d and " - "event queue = %d", dma_rx_chan, dma_tx_chan, - dma_eventq); - } + dma_rx_chan = davinci_spi_get_dma_by_index(pdev, RX_DMA_INDEX); + dma_tx_chan = davinci_spi_get_dma_by_index(pdev, TX_DMA_INDEX); + dma_eventq = davinci_spi_get_dma_by_index(pdev, EVENTQ_DMA_INDEX); + davinci_spi->dma_channels.dma_rx_channel = -1; + davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan; + davinci_spi->dma_channels.dma_tx_channel = -1; + davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan; + davinci_spi->dma_channels.dummy_param_slot = -1; + davinci_spi->dma_channels.eventq = dma_eventq; davinci_spi->get_rx = davinci_spi_rx_buf_u8; davinci_spi->get_tx = davinci_spi_tx_buf_u8; @@ -1164,32 +1009,29 @@ static int davinci_spi_probe(struct platform_device *pdev) udelay(100); iowrite32(1, davinci_spi->base + SPIGCR0); - /* Clock internal */ - if (davinci_spi->pdata->clk_internal) - set_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_CLKMOD_MASK); - else - clear_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_CLKMOD_MASK); + /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ + spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; + iowrite32(spipc0, davinci_spi->base + SPIPC0); - /* master mode default */ - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + /* initialize chip selects */ + if (pdata->chip_sel != NULL) { + for (i = 0; i < pdata->num_chipselect; i++) { + if (pdata->chip_sel[i] != SPI_INTERN_CS) + gpio_direction_output(pdata->chip_sel[i], 1); + } + } + iowrite32(SPIDEF_CSDEF_MASK, davinci_spi->base + SPIDEF); - if (davinci_spi->pdata->intr_level) - iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); - else - iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); ret = spi_bitbang_start(&davinci_spi->bitbang); - if (ret) + if (ret != 0) goto free_clk; dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base); - if (!pdata->poll_mode) - dev_info(&pdev->dev, "Operating in interrupt mode" - " using IRQ %d\n", davinci_spi->irq); - return ret; free_clk: @@ -1199,7 +1041,7 @@ put_master: spi_master_put(master); free_tmp_buf: kfree(davinci_spi->tmp_buf); -irq_free: +err1: free_irq(davinci_spi->irq, davinci_spi); unmap_io: iounmap(davinci_spi->base); @@ -1211,7 +1053,7 @@ err: return ret; } -/** +/* * davinci_spi_remove - remove function for SPI Master Controller * @pdev: platform_device structure which contains plateform specific data * @@ -1220,7 +1062,7 @@ err: * It will also call spi_bitbang_stop to destroy the work queue which was * created by spi_bitbang_start. */ -static int __exit davinci_spi_remove(struct platform_device *pdev) +static int __devexit davinci_spi_remove(struct platform_device *pdev) { struct davinci_spi *davinci_spi; struct spi_master *master; @@ -1242,8 +1084,11 @@ static int __exit davinci_spi_remove(struct platform_device *pdev) } static struct platform_driver davinci_spi_driver = { - .driver.name = "spi_davinci", - .remove = __exit_p(davinci_spi_remove), + .driver = { + .name = "spi_davinci", + .owner = THIS_MODULE, + }, + .remove = __devexit_p(davinci_spi_remove), }; static int __init davinci_spi_init(void) -- 1.6.3.3 From grant.likely at secretlab.ca Thu Jul 8 14:34:02 2010 From: grant.likely at secretlab.ca (Grant Likely) Date: Thu, 8 Jul 2010 13:34:02 -0600 Subject: [PATCH v3 1/1] davinci: spi: replace existing driver In-Reply-To: <1278617003-10295-2-git-send-email-bniebuhr@efjohnson.com> References: <1278617003-10295-1-git-send-email-bniebuhr@efjohnson.com> <1278617003-10295-2-git-send-email-bniebuhr@efjohnson.com> Message-ID: On Thu, Jul 8, 2010 at 1:23 PM, Brian Niebuhr wrote: > INTRODUCTION > > I have been working on a custom OMAP-L138 board that has multiple spi > devices (seven) on one controller. ?These devices have a wide range of > transfer parameters (speed, phase, polarity, internal and gpio chip > selects). ?During my testing I found multiple errors in the davinci spi > driver as a result of this complex setup. ?The primary issues were: Nack. Sorry for being abrupt, but the patch still is full of unrelated whitespace changes (tabs converted to spaces) which makes the patch very difficult to review. This needs to be fixed. Let me know if you need help with how to do this. g. From bniebuhr3 at gmail.com Thu Jul 8 17:39:04 2010 From: bniebuhr3 at gmail.com (Brian Niebuhr) Date: Thu, 8 Jul 2010 17:39:04 -0500 Subject: [PATCH v4 0/1] davinci: spi: replace existing driver Message-ID: <1278628745-18502-1-git-send-email-bniebuhr@efjohnson.com> Fixed in this version: -Fixed whitespace mangling ** NOTE ** This patch requires the EDMA patch at: http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-March/018022.html which is queued waiting on another driver fix, for DMA mode to work correctly. Brian Niebuhr (1): davinci: spi: replace existing driver arch/arm/mach-davinci/board-dm355-evm.c | 10 + arch/arm/mach-davinci/board-dm355-leopard.c | 10 + arch/arm/mach-davinci/board-dm365-evm.c | 10 + arch/arm/mach-davinci/dm355.c | 8 +- arch/arm/mach-davinci/dm365.c | 6 - arch/arm/mach-davinci/include/mach/spi.h | 35 +- drivers/spi/davinci_spi.c | 1112 ++++++++++++--------------- 7 files changed, 528 insertions(+), 663 deletions(-) From bniebuhr3 at gmail.com Thu Jul 8 17:39:05 2010 From: bniebuhr3 at gmail.com (Brian Niebuhr) Date: Thu, 8 Jul 2010 17:39:05 -0500 Subject: [PATCH v4 1/1] davinci: spi: replace existing driver In-Reply-To: <1278628745-18502-1-git-send-email-bniebuhr@efjohnson.com> References: <1278628745-18502-1-git-send-email-bniebuhr@efjohnson.com> Message-ID: <1278628745-18502-2-git-send-email-bniebuhr@efjohnson.com> INTRODUCTION I have been working on a custom OMAP-L138 board that has multiple spi devices (seven) on one controller. These devices have a wide range of transfer parameters (speed, phase, polarity, internal and gpio chip selects). During my testing I found multiple errors in the davinci spi driver as a result of this complex setup. The primary issues were: 1. There is a race condition due to the SPIBUF read busy-waits for slow devices 2. I found some DMA transfer length errors under some conditions 3. The chip select code caused extra byte transfers (with no chip select active) due to writes to SPIDAT1 4. Several issues prevented using multiple SPI devices, especially the DMA code, as disucussed previously on the davinci list. The fixes to these problems were not simple. I ended up making fairly large changes to the driver, and those changes are contained in these patches. The full list of changes follows. CHANGE LIST 1. davinci_spi_chipelect() now performs both activation and deactivation of chip selects. This lets spi_bitbang fully control chip select activation, as intended by the SPI API. 2. Chip select activation does not cause extra writes to the SPI bus 3. Chip select activation does not use SPIDEF for control. This change will also allow for implementation of inverted (active high) chip selects in the future. 4. Added back gpio chip select capability from the old driver 5. Fixed prescale calculation for non-integer fractions of spi clock 6. Allow specification of SPI transfer parameters on a per-device (instead of per-controller) basis 7. Allow specification of polled, interrupt-based, or DMA operation on a per-device basis 8. Allow DMA with when more than one device is connected 9. Combined pio and dma txrx_bufs functions into one since they share large parts of their functionality, and to simplify item (8). 10. Use only SPIFMT0 to allow more than 4 devices TESTING I have tested the driver using a custom SPI stress test on my OMAP-L138-based board with three devices connected. I have tested configurations with all three devices polled, all three interrupt-based, all three DMA, and a mixture. I have compiled with the davinci_all_defconfig, but I don't have EVMs for the other davinci platforms to test with. Signed-off-by: Brian Niebuhr --- arch/arm/mach-davinci/board-dm355-evm.c | 10 + arch/arm/mach-davinci/board-dm355-leopard.c | 10 + arch/arm/mach-davinci/board-dm365-evm.c | 10 + arch/arm/mach-davinci/dm355.c | 8 +- arch/arm/mach-davinci/dm365.c | 6 - arch/arm/mach-davinci/include/mach/spi.h | 35 +- drivers/spi/davinci_spi.c | 1112 ++++++++++++--------------- 7 files changed, 528 insertions(+), 663 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index a319101..ad8779b 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -32,6 +32,7 @@ #include #include #include +#include /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you @@ -300,10 +301,19 @@ static struct spi_eeprom at25640a = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640a_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm355_evm_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640a, + .controller_data = &at25640a_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index f1d8132..b2d8d48 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -29,6 +29,7 @@ #include #include #include +#include /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you @@ -222,10 +223,19 @@ static struct spi_eeprom at25640a = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640a_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm355_leopard_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640a, + .controller_data = &at25640a_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 5bb86b2..db85372 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -39,6 +39,7 @@ #include #include #include +#include #include @@ -579,10 +580,19 @@ static struct spi_eeprom at25640 = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm365_evm_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640, + .controller_data = &at25640_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 3834781..f747c05 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -410,14 +410,8 @@ static struct resource dm355_spi0_resources[] = { }; static struct davinci_spi_platform_data dm355_spi0_pdata = { - .version = SPI_VERSION_1, + .version = SPI_VERSION_0, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, }; static struct platform_device dm355_spi0_device = { .name = "spi_davinci", diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 652f4b6..4aea346 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); static struct davinci_spi_platform_data dm365_spi0_pdata = { .version = SPI_VERSION_1, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, }; static struct resource dm365_spi0_resources[] = { diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h index 910efbf..3f77dab 100644 --- a/arch/arm/mach-davinci/include/mach/spi.h +++ b/arch/arm/mach-davinci/include/mach/spi.h @@ -19,26 +19,35 @@ #ifndef __ARCH_ARM_DAVINCI_SPI_H #define __ARCH_ARM_DAVINCI_SPI_H +#define SPI_INTERN_CS 0xFF + enum { - SPI_VERSION_1, /* For DM355/DM365/DM6467 */ + SPI_VERSION_0, /* For DM355 (reduced features, no Tx interrupt) */ + SPI_VERSION_1, /* For DM365/DM6467 (reduced features) */ SPI_VERSION_2, /* For DA8xx */ }; struct davinci_spi_platform_data { u8 version; - u8 num_chipselect; - u8 wdelay; - u8 odd_parity; - u8 parity_enable; - u8 wait_enable; - u8 timer_disable; - u8 clk_internal; - u8 cs_hold; + u16 num_chipselect; + u8 *chip_sel; +}; + +struct davinci_spi_config { + bool odd_parity; + bool parity_enable; u8 intr_level; - u8 poll_mode; - u8 use_dma; - u8 c2tdelay; - u8 t2cdelay; + u8 io_type; +#define SPI_IO_TYPE_INTR 0 +#define SPI_IO_TYPE_POLL 1 +#define SPI_IO_TYPE_DMA 2 + u8 bytes_per_word; + u8 wdelay; + bool timer_disable; + u8 c2t_delay; + u8 t2c_delay; + u8 t2e_delay; + u8 c2e_delay; }; #endif /* __ARCH_ARM_DAVINCI_SPI_H */ diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index b85090c..931130a 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2009 Texas Instruments. + * Copyright (C) 2010 EF Johnson Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,21 +28,19 @@ #include #include #include -#include #include #include #define SPI_NO_RESOURCE ((resource_size_t)-1) -#define SPI_MAX_CHIPSELECT 2 - #define CS_DEFAULT 0xFF #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 + +#define RX_DMA_INDEX 0 +#define TX_DMA_INDEX 1 +#define EVENTQ_DMA_INDEX 2 #define SPIFMT_PHASE_MASK BIT(16) #define SPIFMT_POLARITY_MASK BIT(17) @@ -53,9 +52,11 @@ #define SPIFMT_WDELAY_MASK 0x3f000000u #define SPIFMT_WDELAY_SHIFT 24 #define SPIFMT_CHARLEN_MASK 0x0000001Fu +#define SPIFMT_PRESCALE_SHIFT 8 /* SPIGCR1 */ -#define SPIGCR1_SPIENA_MASK 0x01000000u +#define SPIGCR1_SPIENA_MASK BIT(24) +#define SPIGCR1_POWERDOWN_MASK BIT(8) /* SPIPC0 */ #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ @@ -66,20 +67,38 @@ #define SPIPC0_EN0FUN_MASK BIT(0) #define SPIINT_MASKALL 0x0101035F +#define SPIINT_MASKINT 0x0000035F #define SPI_INTLVL_1 0x000001FFu #define SPI_INTLVL_0 0x00000000u /* SPIDAT1 */ +#define SPIDAT1_CSHOLD_MASK BIT(28) #define SPIDAT1_CSHOLD_SHIFT 28 +#define SPIDAT1_WDEL_MASK BIT(26) +#define SPIDAT1_CSNR_MASK 0x00FF0000u #define SPIDAT1_CSNR_SHIFT 16 +#define SPIDAT1_DFSEL_MASK (BIT(24 | BIT(25)) #define SPIGCR1_CLKMOD_MASK BIT(1) -#define SPIGCR1_MASTER_MASK BIT(0) +#define SPIGCR1_MASTER_MASK BIT(0) #define SPIGCR1_LOOPBACK_MASK BIT(16) /* SPIBUF */ #define SPIBUF_TXFULL_MASK BIT(29) #define SPIBUF_RXEMPTY_MASK BIT(31) +/* SPIDELAY */ +#define SPIDELAY_C2TDELAY_MASK 0xFF000000u +#define SPIDELAY_C2TDELAY_SHIFT 24 +#define SPIDELAY_T2CDELAY_MASK 0x00FF0000u +#define SPIDELAY_T2CDELAY_SHIFT 16 +#define SPIDELAY_T2EDELAY_MASK 0x0000FF00u +#define SPIDELAY_T2EDELAY_SHIFT 8 +#define SPIDELAY_C2EDELAY_MASK 0x000000FFu +#define SPIDELAY_C2EDELAY_SHIFT 0 + +/* SPIDEF */ +#define SPIDEF_CSDEF_MASK 0x000000FFu + /* Error Masks */ #define SPIFLG_DLEN_ERR_MASK BIT(0) #define SPIFLG_TIMEOUT_MASK BIT(1) @@ -90,11 +109,12 @@ #define SPIFLG_RX_INTR_MASK BIT(8) #define SPIFLG_TX_INTR_MASK BIT(9) #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) -#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \ +#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ - | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \ - | SPIFLG_TX_INTR_MASK \ + | SPIFLG_OVRRUN_MASK) +#define SPIFLG_MASK (SPIFLG_ERROR_MASK \ + | SPIFLG_RX_INTR_MASK | SPIFLG_TX_INTR_MASK \ | SPIFLG_BUF_INIT_ACTIVE_MASK) #define SPIINT_DLEN_ERR_INTR BIT(0) @@ -139,11 +159,10 @@ #define TGINTVEC0 0x60 #define TGINTVEC1 0x64 -struct davinci_spi_slave { - u32 cmd_to_write; - u32 clk_ctrl_to_write; - u32 bytes_per_word; - u8 active_cs; +const char * const io_type_names[] = { + [SPI_IO_TYPE_INTR] = "Interrupt", + [SPI_IO_TYPE_POLL] = "Polled", + [SPI_IO_TYPE_DMA] = "DMA", }; /* We have 2 DMA channels per CS, one for RX and one for TX */ @@ -152,10 +171,8 @@ struct davinci_spi_dma { int dma_rx_channel; int dma_tx_sync_dev; int dma_rx_sync_dev; + int dummy_param_slot; enum dma_event_q eventq; - - struct completion dma_tx_completion; - struct completion dma_rx_completion; }; /* SPI Controller driver's private data. */ @@ -173,51 +190,53 @@ struct davinci_spi { const void *tx; void *rx; u8 *tmp_buf; - int count; - struct davinci_spi_dma *dma_channels; - struct davinci_spi_platform_data *pdata; + int rcount; + int wcount; + u32 errors; + struct davinci_spi_dma dma_channels; + struct davinci_spi_platform_data *pdata; void (*get_rx)(u32 rx_data, struct davinci_spi *); u32 (*get_tx)(struct davinci_spi *); - - struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT]; }; -static unsigned use_dma; - static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) { - u8 *rx = davinci_spi->rx; - - *rx++ = (u8)data; - davinci_spi->rx = rx; + if (davinci_spi->rx) { + u8 *rx = davinci_spi->rx; + *rx++ = (u8)data; + davinci_spi->rx = rx; + } } static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) { - u16 *rx = davinci_spi->rx; - - *rx++ = (u16)data; - davinci_spi->rx = rx; + if (davinci_spi->rx) { + u16 *rx = davinci_spi->rx; + *rx++ = (u16)data; + davinci_spi->rx = rx; + } } static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) { - u32 data; - const u8 *tx = davinci_spi->tx; - - data = *tx++; - davinci_spi->tx = tx; + u32 data = 0; + if (davinci_spi->tx) { + const u8 *tx = davinci_spi->tx; + data = *tx++; + davinci_spi->tx = tx; + } return data; } static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) { - u32 data; - const u16 *tx = davinci_spi->tx; - - data = *tx++; - davinci_spi->tx = tx; + u32 data = 0; + if (davinci_spi->tx) { + const u16 *tx = davinci_spi->tx; + data = *tx++; + davinci_spi->tx = tx; + } return data; } @@ -237,26 +256,6 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits) iowrite32(v, addr); } -static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num) -{ - set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); -} - -static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num) -{ - clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); -} - -static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) -{ - struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); - - if (enable) - set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); - else - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); -} - /* * Interface to control the chip select signal */ @@ -264,28 +263,57 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) { struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; - u32 data1_reg_val = 0; + u8 i, chip_sel = spi->chip_select; + u32 spidat1; + u16 spidat1_cfg; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; - /* - * Board specific chip select logic decides the polarity and cs - * line for the controller - */ - if (value == BITBANG_CS_INACTIVE) { - set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT); - - data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT; - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); + spidat1 = SPIDAT1_CSNR_MASK; + if (value == BITBANG_CS_ACTIVE) + spidat1 |= SPIDAT1_CSHOLD_MASK; + else + spidat1 |= SPIDAT1_WDEL_MASK; - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); + if (pdata->chip_sel == NULL) { + if (value == BITBANG_CS_ACTIVE) + spidat1 &= ~((0x1 << chip_sel) << SPIDAT1_CSNR_SHIFT); + } else { + for (i = 0; i < pdata->num_chipselect; i++) { + if (pdata->chip_sel[i] == SPI_INTERN_CS) { + if ((i == chip_sel) && + (value == BITBANG_CS_ACTIVE)) { + spidat1 &= ~((0x1 << chip_sel) + << SPIDAT1_CSNR_SHIFT); + } + } else { + if (value == BITBANG_CS_INACTIVE) + gpio_set_value(pdata->chip_sel[i], 1); + else if (i == chip_sel) + gpio_set_value(pdata->chip_sel[i], 0); + } + } } + + spidat1_cfg = spidat1 >> SPIDAT1_CSNR_SHIFT; + iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); } -/** +/* + * davinci_spi_get_prescale - Calculates the correct prescale value + * @max_speed_hz: the maximum rate the SPI clock can run at + * + * This function calculates the prescale value that generates a clock rate + * less than or equal to the specified maximum + */ +static inline u32 davinci_spi_get_prescale(struct davinci_spi *davinci_spi, + u32 max_speed_hz) +{ + return ((clk_get_rate(davinci_spi->clk) - 1) / max_speed_hz) & 0xff; +} + +/* * davinci_spi_setup_transfer - This functions will determine transfer method * @spi: spi device on which data transfer to be done * @t: spi transfer in which transfer info is filled @@ -297,14 +325,15 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) static int davinci_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { - struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; + struct davinci_spi_config *spi_cfg; u8 bits_per_word = 0; - u32 hz = 0, prescale = 0, clkspeed; + u32 hz = 0, spifmt = 0, prescale, delay = 0; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; + spi_cfg = spi->controller_data; if (t) { bits_per_word = t->bits_per_word; @@ -322,76 +351,112 @@ static int davinci_spi_setup_transfer(struct spi_device *spi, if (bits_per_word <= 8 && bits_per_word >= 2) { davinci_spi->get_rx = davinci_spi_rx_buf_u8; davinci_spi->get_tx = davinci_spi_tx_buf_u8; - davinci_spi->slave[spi->chip_select].bytes_per_word = 1; + spi_cfg->bytes_per_word = 1; } else if (bits_per_word <= 16 && bits_per_word >= 2) { davinci_spi->get_rx = davinci_spi_rx_buf_u16; davinci_spi->get_tx = davinci_spi_tx_buf_u16; - davinci_spi->slave[spi->chip_select].bytes_per_word = 2; + spi_cfg->bytes_per_word = 2; } else return -EINVAL; if (!hz) hz = spi->max_speed_hz; - clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK, - spi->chip_select); - set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f, - spi->chip_select); + prescale = davinci_spi_get_prescale(davinci_spi, hz); + spifmt |= (prescale << SPIFMT_PRESCALE_SHIFT); - clkspeed = clk_get_rate(davinci_spi->clk); - if (hz > clkspeed / 2) - prescale = 1 << 8; - if (hz < clkspeed / 256) - prescale = 255 << 8; - if (!prescale) - prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00; + spifmt |= (bits_per_word & 0x1f); + + if (spi->mode & SPI_LSB_FIRST) + spifmt |= SPIFMT_SHIFTDIR_MASK; + + if (spi->mode & SPI_CPOL) + spifmt |= SPIFMT_POLARITY_MASK; - clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select); - set_fmt_bits(davinci_spi->base, prescale, spi->chip_select); + if (!(spi->mode & SPI_CPHA)) + spifmt |= SPIFMT_PHASE_MASK; + + if (davinci_spi->version == SPI_VERSION_2) { + spifmt |= ((spi_cfg->wdelay << SPIFMT_WDELAY_SHIFT) + & SPIFMT_WDELAY_MASK); + + if (spi_cfg->odd_parity) + spifmt |= SPIFMT_ODD_PARITY_MASK; + + if (spi_cfg->parity_enable) + spifmt |= SPIFMT_PARITYENA_MASK; + + if (spi->mode & SPI_READY) { + spifmt |= SPIFMT_WAITENA_MASK; + delay |= (spi_cfg->t2e_delay + << SPIDELAY_T2EDELAY_SHIFT) + & SPIDELAY_T2EDELAY_MASK; + delay |= (spi_cfg->c2e_delay + << SPIDELAY_C2EDELAY_SHIFT) + & SPIDELAY_C2EDELAY_MASK; + } + + if (spi_cfg->timer_disable) { + spifmt |= SPIFMT_DISTIMER_MASK; + } else { + delay |= (spi_cfg->c2t_delay + << SPIDELAY_C2TDELAY_SHIFT) + & SPIDELAY_C2TDELAY_MASK; + delay |= (spi_cfg->t2c_delay + << SPIDELAY_T2CDELAY_SHIFT) + & SPIDELAY_T2CDELAY_MASK; + } + + iowrite32(delay, davinci_spi->base + SPIDELAY); + } + + iowrite32(spifmt, davinci_spi->base + SPIFMT0); + + if (spi_cfg->intr_level) + iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); + else + iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); + + if (spi->mode & SPI_LOOP) + set_io_bits(davinci_spi->base + SPIGCR1, + SPIGCR1_LOOPBACK_MASK); + else + clear_io_bits(davinci_spi->base + SPIGCR1, + SPIGCR1_LOOPBACK_MASK); return 0; } static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) { - struct spi_device *spi = (struct spi_device *)data; - struct davinci_spi *davinci_spi; + struct davinci_spi *davinci_spi = (struct davinci_spi *)data; struct davinci_spi_dma *davinci_spi_dma; struct davinci_spi_platform_data *pdata; - davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); + davinci_spi_dma = &(davinci_spi->dma_channels); pdata = davinci_spi->pdata; + edma_stop(davinci_spi_dma->dma_rx_channel); + if (ch_status == DMA_COMPLETE) - edma_stop(davinci_spi_dma->dma_rx_channel); - else - edma_clean_channel(davinci_spi_dma->dma_rx_channel); + davinci_spi->rcount = 0; - complete(&davinci_spi_dma->dma_rx_completion); - /* We must disable the DMA RX request */ - davinci_spi_set_dma_req(spi, 0); + complete(&davinci_spi->done); } static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) { - struct spi_device *spi = (struct spi_device *)data; - struct davinci_spi *davinci_spi; + struct davinci_spi *davinci_spi = (struct davinci_spi *)data; struct davinci_spi_dma *davinci_spi_dma; struct davinci_spi_platform_data *pdata; - davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); + davinci_spi_dma = &(davinci_spi->dma_channels); pdata = davinci_spi->pdata; - if (ch_status == DMA_COMPLETE) - edma_stop(davinci_spi_dma->dma_tx_channel); - else - edma_clean_channel(davinci_spi_dma->dma_tx_channel); + edma_stop(davinci_spi_dma->dma_tx_channel); - complete(&davinci_spi_dma->dma_tx_completion); - /* We must disable the DMA TX request */ - davinci_spi_set_dma_req(spi, 0); + if (ch_status == DMA_COMPLETE) + davinci_spi->wcount = 0; } static int davinci_spi_request_dma(struct spi_device *spi) @@ -403,33 +468,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) int r; davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; + davinci_spi_dma = &davinci_spi->dma_channels; pdata = davinci_spi->pdata; sdev = davinci_spi->bitbang.master->dev.parent; r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, - davinci_spi_dma_rx_callback, spi, + davinci_spi_dma_rx_callback, davinci_spi, davinci_spi_dma->eventq); if (r < 0) { - dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); - return -EAGAIN; + dev_dbg(sdev, "Unable to request DMA channel for MibSPI RX\n"); + r = -EAGAIN; + goto rx_dma_failed; } davinci_spi_dma->dma_rx_channel = r; + r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, - davinci_spi_dma_tx_callback, spi, + davinci_spi_dma_tx_callback, davinci_spi, davinci_spi_dma->eventq); if (r < 0) { - edma_free_channel(davinci_spi_dma->dma_rx_channel); - davinci_spi_dma->dma_rx_channel = -1; - dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); - return -EAGAIN; + dev_dbg(sdev, "Unable to request DMA channel for MibSPI TX\n"); + r = -EAGAIN; + goto tx_dma_failed; } davinci_spi_dma->dma_tx_channel = r; + r = edma_alloc_slot(EDMA_CTLR(davinci_spi_dma->dma_tx_sync_dev), + EDMA_SLOT_ANY); + if (r < 0) { + dev_dbg(sdev, "Unable to request SPI DMA param slot\n"); + r = -EAGAIN; + goto param_failed; + } + davinci_spi_dma->dummy_param_slot = r; + edma_link(davinci_spi_dma->dummy_param_slot, + davinci_spi_dma->dummy_param_slot); + return 0; + +param_failed: + edma_free_channel(davinci_spi_dma->dma_tx_channel); + davinci_spi_dma->dma_tx_channel = -1; +tx_dma_failed: + edma_free_channel(davinci_spi_dma->dma_rx_channel); + davinci_spi_dma->dma_rx_channel = -1; +rx_dma_failed: + return r; } -/** +/* * davinci_spi_setup - This functions will set default transfer method * @spi: spi device on which data transfer to be done * @@ -438,129 +524,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) static int davinci_spi_setup(struct spi_device *spi) { - int retval; + int retval = 0; struct davinci_spi *davinci_spi; - struct davinci_spi_dma *davinci_spi_dma; - struct device *sdev; + struct davinci_spi_dma *davinci_dma; + struct davinci_spi_platform_data *pdata; + struct davinci_spi_config *spi_cfg; + u32 prescale; davinci_spi = spi_master_get_devdata(spi->master); - sdev = davinci_spi->bitbang.master->dev.parent; + pdata = davinci_spi->pdata; + spi_cfg = (struct davinci_spi_config *)spi->controller_data; + davinci_dma = &(davinci_spi->dma_channels); /* if bits per word length is zero then set it default 8 */ if (!spi->bits_per_word) spi->bits_per_word = 8; - davinci_spi->slave[spi->chip_select].cmd_to_write = 0; + if (!(spi->mode & SPI_NO_CS)) { + if ((pdata->chip_sel == NULL) || + (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) + set_io_bits(davinci_spi->base + SPIPC0, + 1 << spi->chip_select); - if (use_dma && davinci_spi->dma_channels) { - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if ((davinci_spi_dma->dma_rx_channel == -1) - || (davinci_spi_dma->dma_tx_channel == -1)) { - retval = davinci_spi_request_dma(spi); - if (retval < 0) - return retval; - } - } - - /* - * SPI in DaVinci and DA8xx operate between - * 600 KHz and 50 MHz - */ - if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) { - dev_dbg(sdev, "Operating frequency is not in acceptable " - "range\n"); - return -EINVAL; } - /* - * Set up SPIFMTn register, unique to this chipselect. - * - * NOTE: we could do all of these with one write. Also, some - * of the "version 2" features are found in chips that don't - * support all of them... - */ - if (spi->mode & SPI_LSB_FIRST) - set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, - spi->chip_select); + if (spi->mode & SPI_READY) + set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); - if (spi->mode & SPI_CPOL) - set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, - spi->chip_select); + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + davinci_dma = &(davinci_spi->dma_channels); - if (!(spi->mode & SPI_CPHA)) - set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, - spi->chip_select); + if ((davinci_dma->dma_tx_sync_dev == SPI_NO_RESOURCE) || + (davinci_dma->dma_rx_sync_dev == SPI_NO_RESOURCE) || + (davinci_dma->eventq == SPI_NO_RESOURCE)) + spi_cfg->io_type = SPI_IO_TYPE_INTR; + else if ((davinci_dma->dma_rx_channel == -1) || + (davinci_dma->dma_tx_channel == -1)) + retval = davinci_spi_request_dma(spi); + } /* - * Version 1 hardware supports two basic SPI modes: - * - Standard SPI mode uses 4 pins, with chipselect - * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) - * (distinct from SPI_3WIRE, with just one data wire; - * or similar variants without MOSI or without MISO) - * - * Version 2 hardware supports an optional handshaking signal, - * so it can support two more modes: - * - 5 pin SPI variant is standard SPI plus SPI_READY - * - 4 pin with enable is (SPI_READY | SPI_NO_CS) + * Validate desired clock rate */ + prescale = davinci_spi_get_prescale(davinci_spi, spi->max_speed_hz); + if ((prescale < 2) || (prescale > 255)) + return -EINVAL; - if (davinci_spi->version == SPI_VERSION_2) { - clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK, - spi->chip_select); - set_fmt_bits(davinci_spi->base, - (davinci_spi->pdata->wdelay - << SPIFMT_WDELAY_SHIFT) - & SPIFMT_WDELAY_MASK, - spi->chip_select); - - if (davinci_spi->pdata->odd_parity) - set_fmt_bits(davinci_spi->base, - SPIFMT_ODD_PARITY_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_ODD_PARITY_MASK, - spi->chip_select); - - if (davinci_spi->pdata->parity_enable) - set_fmt_bits(davinci_spi->base, - SPIFMT_PARITYENA_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_PARITYENA_MASK, - spi->chip_select); - - if (davinci_spi->pdata->wait_enable) - set_fmt_bits(davinci_spi->base, - SPIFMT_WAITENA_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_WAITENA_MASK, - spi->chip_select); - - if (davinci_spi->pdata->timer_disable) - set_fmt_bits(davinci_spi->base, - SPIFMT_DISTIMER_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_DISTIMER_MASK, - spi->chip_select); - } - - retval = davinci_spi_setup_transfer(spi, NULL); + dev_info(&spi->dev, "DaVinci SPI driver in %s mode\n", + io_type_names[spi_cfg->io_type]); return retval; } @@ -569,50 +580,19 @@ static void davinci_spi_cleanup(struct spi_device *spi) { struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); struct davinci_spi_dma *davinci_spi_dma; + struct davinci_spi_platform_data *pdata; - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if (use_dma && davinci_spi->dma_channels) { - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if ((davinci_spi_dma->dma_rx_channel != -1) - && (davinci_spi_dma->dma_tx_channel != -1)) { - edma_free_channel(davinci_spi_dma->dma_tx_channel); - edma_free_channel(davinci_spi_dma->dma_rx_channel); - } - } -} - -static int davinci_spi_bufs_prep(struct spi_device *spi, - struct davinci_spi *davinci_spi) -{ - int op_mode = 0; - - /* - * REVISIT unless devices disagree about SPI_LOOP or - * SPI_READY (SPI_NO_CS only allows one device!), this - * should not need to be done before each message... - * optimize for both flags staying cleared. - */ - - op_mode = SPIPC0_DIFUN_MASK - | SPIPC0_DOFUN_MASK - | SPIPC0_CLKFUN_MASK; - if (!(spi->mode & SPI_NO_CS)) - op_mode |= 1 << spi->chip_select; - if (spi->mode & SPI_READY) - op_mode |= SPIPC0_SPIENA_MASK; + davinci_spi_dma = &davinci_spi->dma_channels; + pdata = davinci_spi->pdata; - iowrite32(op_mode, davinci_spi->base + SPIPC0); + if (davinci_spi_dma->dma_rx_channel != -1) + edma_free_channel(davinci_spi_dma->dma_rx_channel); - if (spi->mode & SPI_LOOP) - set_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_LOOPBACK_MASK); - else - clear_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_LOOPBACK_MASK); + if (davinci_spi_dma->dma_tx_channel != -1) + edma_free_channel(davinci_spi_dma->dma_tx_channel); - return 0; + if (davinci_spi_dma->dummy_param_slot != -1) + edma_free_slot(davinci_spi_dma->dummy_param_slot); } static int davinci_spi_check_error(struct davinci_spi *davinci_spi, @@ -659,356 +639,243 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi, return 0; } -/** - * davinci_spi_bufs - functions which will handle transfer data - * @spi: spi device on which data transfer to be done - * @t: spi transfer in which transfer info is filled +/* + * davinci_spi_process_events - check for and handle any SPI controller events + * @davinci_spi - the controller data * - * This function will put data to be transferred into data register - * of SPI controller and then wait until the completion will be marked - * by the IRQ Handler. + * This function will check the SPIFLG register and handle any events that are + * detected there */ -static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) +static int davinci_spi_process_events(struct davinci_spi *davinci_spi) { - struct davinci_spi *davinci_spi; - int int_status, count, ret; - u8 conv, tmp; - u32 tx_data, data1_reg_val; - u32 buf_val, flg_val; - struct davinci_spi_platform_data *pdata; - - davinci_spi = spi_master_get_devdata(spi->master); - pdata = davinci_spi->pdata; - - davinci_spi->tx = t->tx_buf; - davinci_spi->rx = t->rx_buf; - - /* convert len to words based on bits_per_word */ - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; - davinci_spi->count = t->len / conv; - - INIT_COMPLETION(davinci_spi->done); - - ret = davinci_spi_bufs_prep(spi, davinci_spi); - if (ret) - return ret; - - /* Enable SPI */ - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), - davinci_spi->base + SPIDELAY); - - count = davinci_spi->count; - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; - tmp = ~(0x1 << spi->chip_select); - - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); - - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; - - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); - - /* Determine the command to execute READ or WRITE */ - if (t->tx_buf) { - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); - - while (1) { - tx_data = davinci_spi->get_tx(davinci_spi); - - data1_reg_val &= ~(0xFFFF); - data1_reg_val |= (0xFFFF & tx_data); - - buf_val = ioread32(davinci_spi->base + SPIBUF); - if ((buf_val & SPIBUF_TXFULL_MASK) == 0) { - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - count--; - } - while (ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) - cpu_relax(); - - /* getting the returned byte */ - if (t->rx_buf) { - buf_val = ioread32(davinci_spi->base + SPIBUF); - davinci_spi->get_rx(buf_val, davinci_spi); - } - if (count <= 0) - break; - } - } else { - if (pdata->poll_mode) { - while (1) { - /* keeps the serial clock going */ - if ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_TXFULL_MASK) == 0) - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - while (ioread32(davinci_spi->base + SPIBUF) & - SPIBUF_RXEMPTY_MASK) - cpu_relax(); - - flg_val = ioread32(davinci_spi->base + SPIFLG); - buf_val = ioread32(davinci_spi->base + SPIBUF); - - davinci_spi->get_rx(buf_val, davinci_spi); - - count--; - if (count <= 0) - break; - } - } else { /* Receive in Interrupt mode */ - int i; - - for (i = 0; i < davinci_spi->count; i++) { - set_io_bits(davinci_spi->base + SPIINT, - SPIINT_BITERR_INTR - | SPIINT_OVRRUN_INTR - | SPIINT_RX_INTR); - - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - while (ioread32(davinci_spi->base + SPIINT) & - SPIINT_RX_INTR) - cpu_relax(); - } - iowrite32((data1_reg_val & 0x0ffcffff), - davinci_spi->base + SPIDAT1); - } + u32 status, tx_data, rx_data, spidat1; + u8 tx_word = 0; + + status = ioread32(davinci_spi->base + SPIFLG); + + if ((davinci_spi->version != SPI_VERSION_0) && + (likely(status & SPIFLG_TX_INTR_MASK)) && + (likely(davinci_spi->wcount > 0))) + tx_word = 1; + + if (likely(status & SPIFLG_RX_INTR_MASK)) { + rx_data = ioread32(davinci_spi->base + SPIBUF) & 0xFFFF; + davinci_spi->get_rx(rx_data, davinci_spi); + davinci_spi->rcount--; + if ((davinci_spi->version == SPI_VERSION_0) && + (likely(davinci_spi->wcount > 0))) + tx_word = 1; } - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - int_status = ioread32(davinci_spi->base + SPIFLG); - - ret = davinci_spi_check_error(davinci_spi, int_status); - if (ret != 0) - return ret; + if (unlikely(status & SPIFLG_ERROR_MASK)) { + davinci_spi->errors = (status & SPIFLG_ERROR_MASK); + return -1; + } - /* SPI Framework maintains the count only in bytes so convert back */ - davinci_spi->count *= conv; + if (likely(tx_word)) { + spidat1 = ioread32(davinci_spi->base + SPIDAT1); + davinci_spi->wcount--; + tx_data = davinci_spi->get_tx(davinci_spi); + spidat1 &= 0xFFFF0000; + spidat1 |= (tx_data & 0xFFFF); + iowrite32(spidat1, davinci_spi->base + SPIDAT1); + } - return t->len; + return 0; } -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 - -static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) +/* + * davinci_spi_txrx_bufs - function which will handle transfer data + * @spi: spi device on which data transfer to be done + * @t: spi transfer in which transfer info is filled + * + * This function will put data to be transferred into data register + * of SPI controller and then wait until the completion will be marked + * by the IRQ Handler. + */ +static int davinci_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) { struct davinci_spi *davinci_spi; - int int_status = 0; - int count, temp_count; - u8 conv = 1; - u8 tmp; - u32 data1_reg_val; - struct davinci_spi_dma *davinci_spi_dma; - int word_len, data_type, ret; - unsigned long tx_reg, rx_reg; + int data_type, ret = 0; + u32 tx_data, spidat1; + u16 tx_buf_count = 0, rx_buf_count = 0; + struct davinci_spi_config *spi_cfg; struct davinci_spi_platform_data *pdata; + struct davinci_spi_dma *davinci_dma; struct device *sdev; + dma_addr_t tx_reg, rx_reg; + void *tx_buf, *rx_buf; + struct edmacc_param rx_param, tx_param; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; - sdev = davinci_spi->bitbang.master->dev.parent; - - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; - rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; + spi_cfg = (struct davinci_spi_config *)spi->controller_data; + davinci_dma = &(davinci_spi->dma_channels); davinci_spi->tx = t->tx_buf; davinci_spi->rx = t->rx_buf; + davinci_spi->wcount = t->len / spi_cfg->bytes_per_word; + davinci_spi->rcount = davinci_spi->wcount; + davinci_spi->errors = 0; - /* convert len to words based on bits_per_word */ - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; - davinci_spi->count = t->len / conv; - - INIT_COMPLETION(davinci_spi->done); - - init_completion(&davinci_spi_dma->dma_rx_completion); - init_completion(&davinci_spi_dma->dma_tx_completion); - - word_len = conv * 8; - - if (word_len <= 8) - data_type = DAVINCI_DMA_DATA_TYPE_S8; - else if (word_len <= 16) - data_type = DAVINCI_DMA_DATA_TYPE_S16; - else if (word_len <= 32) - data_type = DAVINCI_DMA_DATA_TYPE_S32; - else - return -EINVAL; - - ret = davinci_spi_bufs_prep(spi, davinci_spi); - if (ret) - return ret; - - /* Put delay val if required */ - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), - davinci_spi->base + SPIDELAY); - - count = davinci_spi->count; /* the number of elements */ - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; + spidat1 = ioread32(davinci_spi->base + SPIDAT1); - /* CS default = 0xFF */ - tmp = ~(0x1 << spi->chip_select); - - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); - - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; - - /* disable all interrupts for dma transfers */ - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); - /* Disable SPI to write configuration bits in SPIDAT */ - clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); - /* Enable SPI */ + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); - + INIT_COMPLETION(davinci_spi->done); - if (t->tx_buf) { - t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, - DMA_TO_DEVICE); - if (dma_mapping_error(&spi->dev, t->tx_dma)) { - dev_dbg(sdev, "Unable to DMA map a %d bytes" - " TX buffer\n", count); - return -ENOMEM; + if ((spi_cfg->io_type == SPI_IO_TYPE_INTR) || + (spi_cfg->io_type == SPI_IO_TYPE_POLL)) { + + if (spi_cfg->io_type == SPI_IO_TYPE_INTR) + set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); + + /* start the transfer */ + davinci_spi->wcount--; + tx_data = davinci_spi->get_tx(davinci_spi); + spidat1 &= 0xFFFF0000; + spidat1 |= (tx_data & 0xFFFF); + iowrite32(spidat1, davinci_spi->base + SPIDAT1); + + } else if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + data_type = spi_cfg->bytes_per_word; + tx_reg = (dma_addr_t)davinci_spi->pbase + SPIDAT1; + rx_reg = (dma_addr_t)davinci_spi->pbase + SPIBUF; + + if (t->tx_buf) { + tx_buf = ((void *)t->tx_buf); + tx_buf_count = davinci_spi->wcount; + } else { + tx_buf = (void *)davinci_spi->tmp_buf; + tx_buf_count = SPI_BUFSIZ; } - temp_count = count; - } else { - /* We need TX clocking for RX transaction */ - t->tx_dma = dma_map_single(&spi->dev, - (void *)davinci_spi->tmp_buf, count + 1, - DMA_TO_DEVICE); - if (dma_mapping_error(&spi->dev, t->tx_dma)) { - dev_dbg(sdev, "Unable to DMA map a %d bytes" - " TX tmp buffer\n", count); - return -ENOMEM; + if (t->rx_buf) { + rx_buf = (void *)t->rx_buf; + rx_buf_count = davinci_spi->rcount; + } else { + rx_buf = (void *)davinci_spi->tmp_buf; + rx_buf_count = SPI_BUFSIZ; } - temp_count = count + 1; + + t->tx_dma = dma_map_single(&spi->dev, tx_buf, + tx_buf_count, DMA_TO_DEVICE); + t->rx_dma = dma_map_single(&spi->dev, rx_buf, + rx_buf_count, DMA_FROM_DEVICE); + + tx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_tx_channel); + tx_param.src = t->tx_buf ? t->tx_dma : tx_reg; + tx_param.a_b_cnt = davinci_spi->wcount << 16 | data_type; + tx_param.dst = tx_reg; + tx_param.src_dst_bidx = t->tx_buf ? data_type : 0; + tx_param.link_bcntrld = 0xffff; + tx_param.src_dst_cidx = 0; + tx_param.ccnt = 1; + edma_write_slot(davinci_dma->dma_tx_channel, &tx_param); + edma_link(davinci_dma->dma_tx_channel, + davinci_dma->dummy_param_slot); + + rx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_rx_channel); + rx_param.src = rx_reg; + rx_param.a_b_cnt = davinci_spi->rcount << 16 | data_type; + rx_param.dst = t->rx_dma; + rx_param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; + rx_param.link_bcntrld = 0xffff; + rx_param.src_dst_cidx = 0; + rx_param.ccnt = 1; + edma_write_slot(davinci_dma->dma_rx_channel, &rx_param); + + iowrite16(spidat1 >> SPIDAT1_CSNR_SHIFT, + davinci_spi->base + SPIDAT1 + 2); + + edma_start(davinci_dma->dma_rx_channel); + edma_start(davinci_dma->dma_tx_channel); + set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); } - edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, - data_type, temp_count, 1, 0, ASYNC); - edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); - edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT); - edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0); - edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); - - if (t->rx_buf) { - /* initiate transaction */ - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); - - t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, - DMA_FROM_DEVICE); - if (dma_mapping_error(&spi->dev, t->rx_dma)) { - dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", - count); - if (t->tx_buf != NULL) - dma_unmap_single(NULL, t->tx_dma, - count, DMA_TO_DEVICE); - return -ENOMEM; + /* Wait for the transfer to complete */ + if (spi_cfg->io_type != SPI_IO_TYPE_POLL) { + wait_for_completion_interruptible(&(davinci_spi->done)); + } else { + while ((davinci_spi->rcount > 0) && (ret == 0)) { + ret = davinci_spi_process_events(davinci_spi); + cpu_relax(); } - edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, - data_type, count, 1, 0, ASYNC); - edma_set_src(davinci_spi_dma->dma_rx_channel, - rx_reg, INCR, W8BIT); - edma_set_dest(davinci_spi_dma->dma_rx_channel, - t->rx_dma, INCR, W8BIT); - edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); - edma_set_dest_index(davinci_spi_dma->dma_rx_channel, - data_type, 0); } - if ((t->tx_buf) || (t->rx_buf)) - edma_start(davinci_spi_dma->dma_tx_channel); - - if (t->rx_buf) - edma_start(davinci_spi_dma->dma_rx_channel); - - if ((t->rx_buf) || (t->tx_buf)) - davinci_spi_set_dma_req(spi, 1); - - if (t->tx_buf) - wait_for_completion_interruptible( - &davinci_spi_dma->dma_tx_completion); - - if (t->rx_buf) - wait_for_completion_interruptible( - &davinci_spi_dma->dma_rx_completion); - - dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE); - - if (t->rx_buf) - dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); - - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - int_status = ioread32(davinci_spi->base + SPIFLG); + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + dma_unmap_single(NULL, t->tx_dma, tx_buf_count, + DMA_TO_DEVICE); + dma_unmap_single(NULL, t->rx_dma, rx_buf_count, + DMA_FROM_DEVICE); + } - ret = davinci_spi_check_error(davinci_spi, int_status); - if (ret != 0) - return ret; + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - /* SPI Framework maintains the count only in bytes so convert back */ - davinci_spi->count *= conv; + if (davinci_spi->errors) { + ret = davinci_spi_check_error(davinci_spi, davinci_spi->errors); + if (ret != 0) + return ret; + } + if ((davinci_spi->rcount != 0) || (davinci_spi->wcount != 0)) { + sdev = davinci_spi->bitbang.master->dev.parent; + dev_info(sdev, "SPI data transfer error\n"); + return -EIO; + } return t->len; } -/** - * davinci_spi_irq - IRQ handler for DaVinci SPI +/* + * davinci_spi_irq - probe function for SPI Master Controller * @irq: IRQ number for this SPI Master * @context_data: structure for SPI Master controller davinci_spi + * + * ISR will determine that interrupt arrives either for READ or WRITE command. + * According to command it will do the appropriate action. It will check + * transfer length and if it is not zero then dispatch transfer command again. + * If transfer length is zero then it will indicate the COMPLETION so that + * davinci_spi_bufs function can go ahead. */ static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) { struct davinci_spi *davinci_spi = context_data; - u32 int_status, rx_data = 0; - irqreturn_t ret = IRQ_NONE; + int status; - int_status = ioread32(davinci_spi->base + SPIFLG); + status = davinci_spi_process_events(davinci_spi); + if (unlikely(status != 0)) + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); - while ((int_status & SPIFLG_RX_INTR_MASK)) { - if (likely(int_status & SPIFLG_RX_INTR_MASK)) { - ret = IRQ_HANDLED; + if ((davinci_spi->rcount == 0) || (status != 0)) + complete(&(davinci_spi->done)); - rx_data = ioread32(davinci_spi->base + SPIBUF); - davinci_spi->get_rx(rx_data, davinci_spi); + return IRQ_HANDLED; +} - /* Disable Receive Interrupt */ - iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR), - davinci_spi->base + SPIINT); - } else - (void)davinci_spi_check_error(davinci_spi, int_status); +resource_size_t davinci_spi_get_dma_by_index(struct platform_device *dev, + unsigned long index) +{ + struct resource *r; - int_status = ioread32(davinci_spi->base + SPIFLG); - } + r = platform_get_resource(dev, IORESOURCE_DMA, index); + if (r != NULL) + return r->start; - return ret; + return SPI_NO_RESOURCE; } -/** +/* * davinci_spi_probe - probe function for SPI Master Controller * @pdev: platform_device structure which contains plateform specific data + * + * According to Linux Device Model this function will be invoked by Linux + * with platform_device struct which contains the device specific info. + * This function will map the SPI controller's memory, register IRQ, + * Reset SPI controller and setting its registers to default value. + * It will invoke spi_bitbang_start to create work queue so that client driver + * can register transfer method to work queue. */ static int davinci_spi_probe(struct platform_device *pdev) { @@ -1020,6 +887,7 @@ static int davinci_spi_probe(struct platform_device *pdev) resource_size_t dma_tx_chan = SPI_NO_RESOURCE; resource_size_t dma_eventq = SPI_NO_RESOURCE; int i = 0, ret = 0; + u32 spipc0; pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -1071,16 +939,18 @@ static int davinci_spi_probe(struct platform_device *pdev) goto unmap_io; } - ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED, + ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev), davinci_spi); - if (ret) + if (ret != 0) { + ret = -EAGAIN; goto unmap_io; + } /* Allocate tmp_buf for tx_buf */ davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); if (davinci_spi->tmp_buf == NULL) { ret = -ENOMEM; - goto irq_free; + goto err1; } davinci_spi->bitbang.master = spi_master_get(master); @@ -1104,55 +974,23 @@ static int davinci_spi_probe(struct platform_device *pdev) davinci_spi->bitbang.chipselect = davinci_spi_chipselect; davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; + davinci_spi->bitbang.txrx_bufs = davinci_spi_txrx_bufs; davinci_spi->version = pdata->version; - use_dma = pdata->use_dma; davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; if (davinci_spi->version == SPI_VERSION_2) davinci_spi->bitbang.flags |= SPI_READY; - if (use_dma) { - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (r) - dma_rx_chan = r->start; - r = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (r) - dma_tx_chan = r->start; - r = platform_get_resource(pdev, IORESOURCE_DMA, 2); - if (r) - dma_eventq = r->start; - } - - if (!use_dma || - dma_rx_chan == SPI_NO_RESOURCE || - dma_tx_chan == SPI_NO_RESOURCE || - dma_eventq == SPI_NO_RESOURCE) { - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; - use_dma = 0; - } else { - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; - davinci_spi->dma_channels = kzalloc(master->num_chipselect - * sizeof(struct davinci_spi_dma), GFP_KERNEL); - if (davinci_spi->dma_channels == NULL) { - ret = -ENOMEM; - goto free_clk; - } - - for (i = 0; i < master->num_chipselect; i++) { - davinci_spi->dma_channels[i].dma_rx_channel = -1; - davinci_spi->dma_channels[i].dma_rx_sync_dev = - dma_rx_chan; - davinci_spi->dma_channels[i].dma_tx_channel = -1; - davinci_spi->dma_channels[i].dma_tx_sync_dev = - dma_tx_chan; - davinci_spi->dma_channels[i].eventq = dma_eventq; - } - dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" - "Using RX channel = %d , TX channel = %d and " - "event queue = %d", dma_rx_chan, dma_tx_chan, - dma_eventq); - } + dma_rx_chan = davinci_spi_get_dma_by_index(pdev, RX_DMA_INDEX); + dma_tx_chan = davinci_spi_get_dma_by_index(pdev, TX_DMA_INDEX); + dma_eventq = davinci_spi_get_dma_by_index(pdev, EVENTQ_DMA_INDEX); + davinci_spi->dma_channels.dma_rx_channel = -1; + davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan; + davinci_spi->dma_channels.dma_tx_channel = -1; + davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan; + davinci_spi->dma_channels.dummy_param_slot = -1; + davinci_spi->dma_channels.eventq = dma_eventq; davinci_spi->get_rx = davinci_spi_rx_buf_u8; davinci_spi->get_tx = davinci_spi_tx_buf_u8; @@ -1164,32 +1002,29 @@ static int davinci_spi_probe(struct platform_device *pdev) udelay(100); iowrite32(1, davinci_spi->base + SPIGCR0); - /* Clock internal */ - if (davinci_spi->pdata->clk_internal) - set_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_CLKMOD_MASK); - else - clear_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_CLKMOD_MASK); + /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ + spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; + iowrite32(spipc0, davinci_spi->base + SPIPC0); - /* master mode default */ - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + /* initialize chip selects */ + if (pdata->chip_sel != NULL) { + for (i = 0; i < pdata->num_chipselect; i++) { + if (pdata->chip_sel[i] != SPI_INTERN_CS) + gpio_direction_output(pdata->chip_sel[i], 1); + } + } + iowrite32(SPIDEF_CSDEF_MASK, davinci_spi->base + SPIDEF); - if (davinci_spi->pdata->intr_level) - iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); - else - iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); ret = spi_bitbang_start(&davinci_spi->bitbang); - if (ret) + if (ret != 0) goto free_clk; dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base); - if (!pdata->poll_mode) - dev_info(&pdev->dev, "Operating in interrupt mode" - " using IRQ %d\n", davinci_spi->irq); - return ret; free_clk: @@ -1199,7 +1034,7 @@ put_master: spi_master_put(master); free_tmp_buf: kfree(davinci_spi->tmp_buf); -irq_free: +err1: free_irq(davinci_spi->irq, davinci_spi); unmap_io: iounmap(davinci_spi->base); @@ -1211,7 +1046,7 @@ err: return ret; } -/** +/* * davinci_spi_remove - remove function for SPI Master Controller * @pdev: platform_device structure which contains plateform specific data * @@ -1220,7 +1055,7 @@ err: * It will also call spi_bitbang_stop to destroy the work queue which was * created by spi_bitbang_start. */ -static int __exit davinci_spi_remove(struct platform_device *pdev) +static int __devexit davinci_spi_remove(struct platform_device *pdev) { struct davinci_spi *davinci_spi; struct spi_master *master; @@ -1242,8 +1077,11 @@ static int __exit davinci_spi_remove(struct platform_device *pdev) } static struct platform_driver davinci_spi_driver = { - .driver.name = "spi_davinci", - .remove = __exit_p(davinci_spi_remove), + .driver = { + .name = "spi_davinci", + .owner = THIS_MODULE, + }, + .remove = __devexit_p(davinci_spi_remove), }; static int __init davinci_spi_init(void) -- 1.6.3.3 From lamiaposta71 at gmail.com Fri Jul 9 00:28:38 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Fri, 9 Jul 2010 07:28:38 +0200 Subject: Rif: Re: [PATCH 3/3] ASoC: DaVinci: More accurate calculation for clock divider for McBSP (I2S) In-Reply-To: <20100707041727.GA12335@opensource.wolfsonmicro.com> References: <4C337770.3070007@boundarydevices.com> <20100707041727.GA12335@opensource.wolfsonmicro.com> Message-ID: 2010/7/7 Mark Brown > On Tue, Jul 06, 2010 at 11:35:28AM -0700, Troy Kisky wrote: > > > Indeed, your algorithm may produce more accurate results for the specific > rate > > that you tested for. However, that seems more luck than anything. How do > you > > know that a frame size of 33 will always give more accurate results than > a frame > > size of 32? If your going to loop, you need to calculate the error and > minimize that > > and not just stop when framesize finally reaches your minimum size of 33. > > Yes, this is pretty much the algorithm I was trying to suggest earlier. > Iterate up until you hit either an exact match or decide that the frame > size is getting too big. > Mark and Troy, yes, it is wrong to say that a faster clock is automatically better approximated. But we did measurements and it was better. Sorry, no data available. The setup was difficult due to very thin wires solded to the I2S bus. Now we don't have the setup. At the moment is for me impossible to enhance the algorithm. I'm sorry. During september or october I'll work again on it and it is possible I could do some improvements. I hope anyway that the three patches are accepted. I don't know exactly how this procedure works, can you explain to me? I should see the patches in the mainline kernel, or in a special linux-next or other? Thanks, Raffaele -------------- next part -------------- An HTML attachment was scrubbed... URL: From sudhakar.raj at ti.com Fri Jul 9 00:29:49 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Fri, 9 Jul 2010 10:59:49 +0530 Subject: [PATCH] mtd-nand: davinci: correct 4-bit error correction Message-ID: <1278653389-12019-1-git-send-email-sudhakar.raj@ti.com> On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the 4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and before waiting for the NAND Flash status register to be equal to 1, 2 or 3, we have to wait till the ECC HW goes to correction state. Without this wait, ECC correction calculations will not be proper. This has been tested on DA830/OMAP-L137, DA850/OMAP-L138, DM355 and DM365 EVMs. Signed-off-by: Sudhakar Rajashekhara Acked-by: Sneha Narnakaje Cc: David Woodhouse Signed-off-by: Andrew Morton --- This patch applies on top of Linus's master. This patch was present in -mm tree and was dropped because it was merged into mainline. But now this patch is not present neither in Linus's tree nor in linux-next. Hence resending it again. drivers/mtd/nand/davinci_nand.c | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 9c9d893..2ac7367 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -311,7 +311,9 @@ static int nand_davinci_correct_4bit(struct mtd_info *mtd, unsigned short ecc10[8]; unsigned short *ecc16; u32 syndrome[4]; + u32 ecc_state; unsigned num_errors, corrected; + unsigned long timeo = jiffies + msecs_to_jiffies(100); /* All bytes 0xff? It's an erased page; ignore its ECC. */ for (i = 0; i < 10; i++) { @@ -361,6 +363,21 @@ compare: */ davinci_nand_writel(info, NANDFCR_OFFSET, davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13)); + + /* + * ECC_STATE field reads 0x3 (Error correction complete) immediately + * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately + * begin trying to poll for the state, you may fall right out of your + * loop without any of the correction calculations having taken place. + * The recommendation from the hardware team is to wait till ECC_STATE + * reads less than 4, which means ECC HW has entered correction state. + */ + do { + ecc_state = (davinci_nand_readl(info, + NANDFSR_OFFSET) >> 8) & 0x0f; + cpu_relax(); + } while ((ecc_state < 4) && time_before(jiffies, timeo)); + for (;;) { u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET); -- 1.5.6 From chris-meng at ti.com Fri Jul 9 02:27:34 2010 From: chris-meng at ti.com (Meng, Chris) Date: Fri, 9 Jul 2010 15:27:34 +0800 Subject: DM365: Problem of using filesystem made by own Message-ID: Hi, We are facing problem to using filesystem made by own. When the DM365 system boots up with new FS by NFS, /dev/video0, /dev/video2, /dev/video3 can be generated. And /dev/video2, /dev/video3 can be opened correctly. But if open video0, there is error as below. kobject_add failed for (-13) Failed to register TVP7002 I2C client. vpfe ccdc capture vpfe ccdc capture.1: Error in initializing channel open fd is error The busybox version used is 1.2.2.1. Using the FS provided in DVSDK2.1 is ok. Would you pls kindly advise what is missed? Have you ever made FS for DM365? Would you pls share with me the configuration file for busybox? We suspected the problem is due to the configuration. The filesystem made by own can't use below inittab which is in the FS provided in DVSDK2.1 (See detail below). Why? Is this due to the configuration of busybox? Any comment is appreciated! # /etc/inittab: init(8) configuration. 2 # $Id: inittab,v 1.91 2002/01/25 13:35:21 miquels Exp $ 3 4 # The default runlevel. 5 id:3:initdefault: 6 7 # Boot-time system configuration/initialization script. 8 # This is run first except when booting in emergency (-b) mode. 9 si::sysinit:/etc/init.d/rcS 10 11 # What to do in single-user mode. 12 ~~:S:wait:/sbin/sulogin 13 14 # /etc/init.d executes the S and K scripts upon change 15 # of runlevel. 16 # 17 # Runlevel 0 is halt. 18 # Runlevel 1 is single-user. 19 # Runlevels 2-5 are multi-user. 20 # Runlevel 6 is reboot. 21 22 l0:0:wait:/etc/init.d/rc 0 23 l1:1:wait:/etc/init.d/rc 1 24 l2:2:wait:/etc/init.d/rc 2 25 l3:3:wait:/etc/init.d/rc 3 26 l4:4:wait:/etc/init.d/rc 4 27 l5:5:wait:/etc/init.d/rc 5 28 l6:6:wait:/etc/init.d/rc 6 Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: From spoulsen at css-design.com Fri Jul 9 07:11:13 2010 From: spoulsen at css-design.com (Steve Poulsen) Date: Fri, 09 Jul 2010 07:11:13 -0500 Subject: pwrite in mtd In-Reply-To: <316378.87035.qm@web38806.mail.mud.yahoo.com> References: <316378.87035.qm@web38806.mail.mud.yahoo.com> Message-ID: <4C3711E1.7060300@css-design.com> Can you replace the pwrite with calls to write() and seek()? This would help determine which part is causing the error. Steve On 07/06/2010 11:47 PM, Vijay Soni wrote: > The write to mtd > > pwrite(fd, writebuf, size, mtdoffset) > > returns error Num 22, Invalid Arguments > > Any clue? > > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. From akpm at linux-foundation.org Fri Jul 9 17:39:32 2010 From: akpm at linux-foundation.org (Andrew Morton) Date: Fri, 9 Jul 2010 15:39:32 -0700 Subject: [PATCH] mtd-nand: davinci: correct 4-bit error correction In-Reply-To: <1278653389-12019-1-git-send-email-sudhakar.raj@ti.com> References: <1278653389-12019-1-git-send-email-sudhakar.raj@ti.com> Message-ID: <20100709153932.0a6cdbcd.akpm@linux-foundation.org> On Fri, 9 Jul 2010 10:59:49 +0530 Sudhakar Rajashekhara wrote: > + > + /* > + * ECC_STATE field reads 0x3 (Error correction complete) immediately > + * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately > + * begin trying to poll for the state, you may fall right out of your > + * loop without any of the correction calculations having taken place. > + * The recommendation from the hardware team is to wait till ECC_STATE > + * reads less than 4, which means ECC HW has entered correction state. > + */ > + do { > + ecc_state = (davinci_nand_readl(info, > + NANDFSR_OFFSET) >> 8) & 0x0f; > + cpu_relax(); > + } while ((ecc_state < 4) && time_before(jiffies, timeo)); An up-to-100-milliseond busy wait is pretty bad. For how long do you expect this to spin in practice? From tharma at e-consystems.com Sat Jul 10 10:35:29 2010 From: tharma at e-consystems.com (Tharmarajan Ganeshan) Date: Sat, 10 Jul 2010 21:05:29 +0530 Subject: DM355 - 256MB RAM memory issue In-Reply-To: <1278428415.14942.19703.camel@sax-lx> References: <1278339242.18556.10.camel@tharma-laptop> <1278428415.14942.19703.camel@sax-lx> Message-ID: <1278776129.3931.225.camel@tharma-laptop> Hi Todd and Chris, Thank for your suggestion. We tried the option 'hole in the kernel memory space'. But that is not solving our issue. We tried to reserve memory 30MB at various place in RAM. But these trials does not help us to solve this issue. And also we tried to get the memory for this 5MP image capturing from the CMEM driver. For this we allocated 86MB to CMEM driver. But the kernel is hanging while loading this CMEM driver. Is there any limitation in CMEM driver ? Regards, Tharmarajan G On Tue, 2010-07-06 at 09:00 -0600, Todd Fischer wrote: > Tharmarajan, > > I believe you need to rebuild your codec server with a different > memory map. Another idea is to have a hole in the kernel memory space > (specify mem= in the kernel command line twice). I am not sure if the > kernel version you are using for dm355 supports a hole in the kernel > memory space. > > Todd > > On Mon, 2010-07-05 at 19:44 +0530, Tharmarajan Ganeshan wrote: > > > Hi All, > > We are working on a DM355 processor based Development > > board. The Board has 256MB mDDR RAM and 5MP image sensor MT9P031. > > > > We are using the kernel version 2.6.10 > > > > We have modified the driver code for capturing 5MP raw > > image and converting this 5MP raw into YUV. For this 5MP image > > capturing , we have reserved 30MB. > > > > We have allocated 56MB to the CMEM driver. > > > > The reserved memory 30MB and the 56MB memory for CMEM > > are at top of the RAM. > > > > We are passing the remaining memory size to the kernel > > in bootargs as mem=170M. And we are using the NFS rootfilesystem. > > > > But we are getting kernel hanging issues while testing > > the IPNC_APP applications and 5MP still image capturing. Sometimes > > the kernel is hanging while booting itself. > > > > > > If we reserve the 30MB from the address region > > 0x83200000 - 0x84FFFFFF and pass the memory size to kernel in > > bootargs as mem=50M, then we are NOT having any issues in running > > the applications. But we want to use the exact remaining memory. > > > > And also we are not able to program the NAND flash > > memory in kernel level if we are not passing the mem=50M in > > bootargs. > > > > What could be the cause for this kernel hanging issue ? > > > > Are we missing any configurations while building the > > kernel image ? > > > > Our Bootargs is : > > mem=50M console=ttyS1,115200n8 root=/dev/nfs rootwait rw > > ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 > > nfsroot=192.168.1.99:/tftpboot/bellatrix_rootfilesystem,nolock > > eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 > > > > > > > > Regards, > > Tharmarajan G > > > > > > _______________________________________________ > > Davinci-linux-open-source mailing list > > Davinci-linux-open-source at linux.davincidsp.com > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -------------- next part -------------- An HTML attachment was scrubbed... URL: From rohan_javed at yahoo.co.uk Sun Jul 11 23:15:13 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Mon, 12 Jul 2010 04:15:13 +0000 (GMT) Subject: jffs2 question Message-ID: <340203.57591.qm@web24106.mail.ird.yahoo.com> I am using jffs2 filesystem got alot of these messages and then increase each time i boot JFFS2 notice: (1) check_node_data: wrong data CRC in data node at 0x0047dce8: read 0x9b72523b, calculated 0x2d0a05f4 CRC messages how what these messages area for? they add latency to my system Regard's -------------- next part -------------- An HTML attachment was scrubbed... URL: From rohan_javed at yahoo.co.uk Mon Jul 12 01:30:36 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Mon, 12 Jul 2010 06:30:36 +0000 (GMT) Subject: YAFFS2 not in git???? Message-ID: <7198.61536.qm@web24103.mail.ird.yahoo.com> How to use yaffs with git kernel there is no support for it? Regard's Rohan Tabish -------------- next part -------------- An HTML attachment was scrubbed... URL: From sudhakar.raj at ti.com Mon Jul 12 01:28:18 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Mon, 12 Jul 2010 11:58:18 +0530 Subject: [PATCH] mtd-nand: davinci: correct 4-bit error correction In-Reply-To: <20100709153932.0a6cdbcd.akpm@linux-foundation.org> References: <1278653389-12019-1-git-send-email-sudhakar.raj@ti.com> <20100709153932.0a6cdbcd.akpm@linux-foundation.org> Message-ID: <00c701cb218b$6e4d6dd0$4ae84970$@raj@ti.com> On Sat, Jul 10, 2010 at 04:09:32, Andrew Morton wrote: > On Fri, 9 Jul 2010 10:59:49 +0530 > Sudhakar Rajashekhara wrote: > > > + > > + /* > > + * ECC_STATE field reads 0x3 (Error correction complete) immediately > > + * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately > > + * begin trying to poll for the state, you may fall right out of your > > + * loop without any of the correction calculations having taken place. > > + * The recommendation from the hardware team is to wait till ECC_STATE > > + * reads less than 4, which means ECC HW has entered correction state. > > + */ > > + do { > > + ecc_state = (davinci_nand_readl(info, > > + NANDFSR_OFFSET) >> 8) & 0x0f; > > + cpu_relax(); > > + } while ((ecc_state < 4) && time_before(jiffies, timeo)); > > An up-to-100-milliseond busy wait is pretty bad. For how long do you > expect this to spin in practice? On the hardware, I have never seen this taking 100 msec to come out of the loop. I'll check with the hardware folks on the maximum time to wait for, before the ECC engine is ready. Thanks, Sudhakar From nsekhar at ti.com Mon Jul 12 05:34:46 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Mon, 12 Jul 2010 16:04:46 +0530 Subject: [PATCH 1/2] regulator: tps6507x: allow driver to use DEFDCDC{2, 3}_HIGH register Message-ID: <1278930888-26810-1-git-send-email-nsekhar@ti.com> From: Anuj Aggarwal In TPS6507x, depending on the status of DEFDCDC{2,3} pin either DEFDCDC{2,3}_LOW or DEFDCDC{2,3}_HIGH register needs to be read or programmed to change the output voltage. The current driver assumes DEFDCDC{2,3} pins are always tied low and thus operates only on DEFDCDC{2,3}_LOW register. This need not always be the case (as is found on OMAP-L138 EVM). Unfortunately, software cannot read the status of DEFDCDC{2,3} pins. So, this information is passed through platform data depending on how the board is wired. Signed-off-by: Anuj Aggarwal Signed-off-by: Sekhar Nori --- drivers/regulator/tps6507x-regulator.c | 36 +++++++++++++++++++++++++------ include/linux/regulator/tps6507x.h | 32 ++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 7 deletions(-) create mode 100644 include/linux/regulator/tps6507x.h diff --git a/drivers/regulator/tps6507x-regulator.c b/drivers/regulator/tps6507x-regulator.c index 14b4576..fc1c33c 100644 --- a/drivers/regulator/tps6507x-regulator.c +++ b/drivers/regulator/tps6507x-regulator.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -101,9 +102,12 @@ struct tps_info { unsigned max_uV; u8 table_len; const u16 *table; + + /* Does DCDC high or the low register defines output voltage? */ + bool defdcdc_high; }; -static const struct tps_info tps6507x_pmic_regs[] = { +static struct tps_info tps6507x_pmic_regs[] = { { .name = "VDCDC1", .min_uV = 725000, @@ -145,7 +149,7 @@ struct tps6507x_pmic { struct regulator_desc desc[TPS6507X_NUM_REGULATOR]; struct tps6507x_dev *mfd; struct regulator_dev *rdev[TPS6507X_NUM_REGULATOR]; - const struct tps_info *info[TPS6507X_NUM_REGULATOR]; + struct tps_info *info[TPS6507X_NUM_REGULATOR]; struct mutex io_lock; }; static inline int tps6507x_pmic_read(struct tps6507x_pmic *tps, u8 reg) @@ -341,10 +345,16 @@ static int tps6507x_pmic_dcdc_get_voltage(struct regulator_dev *dev) reg = TPS6507X_REG_DEFDCDC1; break; case TPS6507X_DCDC_2: - reg = TPS6507X_REG_DEFDCDC2_LOW; + if (tps->info[dcdc]->defdcdc_high) + reg = TPS6507X_REG_DEFDCDC2_HIGH; + else + reg = TPS6507X_REG_DEFDCDC2_LOW; break; case TPS6507X_DCDC_3: - reg = TPS6507X_REG_DEFDCDC3_LOW; + if (tps->info[dcdc]->defdcdc_high) + reg = TPS6507X_REG_DEFDCDC3_HIGH; + else + reg = TPS6507X_REG_DEFDCDC3_LOW; break; default: return -EINVAL; @@ -370,10 +380,16 @@ static int tps6507x_pmic_dcdc_set_voltage(struct regulator_dev *dev, reg = TPS6507X_REG_DEFDCDC1; break; case TPS6507X_DCDC_2: - reg = TPS6507X_REG_DEFDCDC2_LOW; + if (tps->info[dcdc]->defdcdc_high) + reg = TPS6507X_REG_DEFDCDC2_HIGH; + else + reg = TPS6507X_REG_DEFDCDC2_LOW; break; case TPS6507X_DCDC_3: - reg = TPS6507X_REG_DEFDCDC3_LOW; + if (tps->info[dcdc]->defdcdc_high) + reg = TPS6507X_REG_DEFDCDC3_HIGH; + else + reg = TPS6507X_REG_DEFDCDC3_LOW; break; default: return -EINVAL; @@ -532,7 +548,7 @@ int tps6507x_pmic_probe(struct platform_device *pdev) { struct tps6507x_dev *tps6507x_dev = dev_get_drvdata(pdev->dev.parent); static int desc_id; - const struct tps_info *info = &tps6507x_pmic_regs[0]; + struct tps_info *info = &tps6507x_pmic_regs[0]; struct regulator_init_data *init_data; struct regulator_dev *rdev; struct tps6507x_pmic *tps; @@ -569,6 +585,12 @@ int tps6507x_pmic_probe(struct platform_device *pdev) for (i = 0; i < TPS6507X_NUM_REGULATOR; i++, info++, init_data++) { /* Register the regulators */ tps->info[i] = info; + if (init_data->driver_data) { + struct tps6507x_reg_platform_data *data = + init_data->driver_data; + tps->info[i]->defdcdc_high = data->defdcdc_high; + } + tps->desc[i].name = info->name; tps->desc[i].id = desc_id++; tps->desc[i].n_voltages = num_voltages[i]; diff --git a/include/linux/regulator/tps6507x.h b/include/linux/regulator/tps6507x.h new file mode 100644 index 0000000..33d91cd --- /dev/null +++ b/include/linux/regulator/tps6507x.h @@ -0,0 +1,32 @@ +/* + * tps6507x.h -- Voltage regulation for the Texas Instruments TPS6507X + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef REGULATOR_TPS6507X +#define REGULATOR_TPS6507X + +/** + * tps6507x_reg_platform_data - platform data for tps6507x + * @defdcdc_high: Defines whether DCDC high or the low register controls + * output voltage. Valid for DCDC2 and DCDC3 outputs only. + */ +struct tps6507x_reg_platform_data { + bool defdcdc_high; +}; + +#endif -- 1.6.2.4 From nsekhar at ti.com Mon Jul 12 05:39:32 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Mon, 12 Jul 2010 16:09:32 +0530 Subject: [PATCH 2/2] davinci: da850/omap-l138 evm: account for DEFDCDC{2, 3} being tied high Message-ID: <1278931172-5379-1-git-send-email-nsekhar@ti.com> Per the da850/omap-l138 Beta EVM SOM schematic, the DEFDCDC2 and DEFDCDC3 lines are tied high. This leads to a 3.3V IO and 1.2V CVDD voltage. Pass the right platform data to the TPS6507x driver so it can operate on the DEFDCDC{2,3}_HIGH register to read and change voltage levels. Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/board-da850-evm.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 2ec3095..0c436c9 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -469,6 +470,11 @@ struct regulator_consumer_supply tps65070_ldo2_consumers[] = { }, }; +/* We take advantage of the fact that both defdcdc{2,3} are tied high */ +static struct tps6507x_reg_platform_data tps6507x_platform_data = { + .defdcdc_high = false, +}; + struct regulator_init_data tps65070_regulator_data[] = { /* dcdc1 */ { @@ -494,6 +500,7 @@ struct regulator_init_data tps65070_regulator_data[] = { }, .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers), .consumer_supplies = tps65070_dcdc2_consumers, + .driver_data = &tps6507x_platform_data, }, /* dcdc3 */ @@ -507,6 +514,7 @@ struct regulator_init_data tps65070_regulator_data[] = { }, .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers), .consumer_supplies = tps65070_dcdc3_consumers, + .driver_data = &tps6507x_platform_data, }, /* ldo1 */ -- 1.6.2.4 From broonie at opensource.wolfsonmicro.com Mon Jul 12 05:40:45 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Mon, 12 Jul 2010 11:40:45 +0100 Subject: [PATCH 1/2] regulator: tps6507x: allow driver to use DEFDCDC{2,3}_HIGH register In-Reply-To: <1278930888-26810-1-git-send-email-nsekhar@ti.com> References: <1278930888-26810-1-git-send-email-nsekhar@ti.com> Message-ID: <20100712104045.GE21840@rakim.wolfsonmicro.main> On Mon, Jul 12, 2010 at 04:04:46PM +0530, Sekhar Nori wrote: > + > + /* Does DCDC high or the low register defines output voltage? */ > + bool defdcdc_high; This should probably be "defdcdc_default" or something. Presumably the line can also be wired to a GPIO and changed at runtime (otherwise the feature seems at best odd) and if support for that is implemented then this will change from being a static configuration in the platform data to something configured dynamically so the name would no longer make sense. From nsekhar at ti.com Mon Jul 12 05:43:47 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Mon, 12 Jul 2010 16:13:47 +0530 Subject: [PATCH 2/2] davinci: da850/omap-l138 evm: account for DEFDCDC{2,3} being tied high In-Reply-To: <1278931172-5379-1-git-send-email-nsekhar@ti.com> References: <1278931172-5379-1-git-send-email-nsekhar@ti.com> Message-ID: On Mon, Jul 12, 2010 at 16:09:32, Nori, Sekhar wrote: > Per the da850/omap-l138 Beta EVM SOM schematic, the DEFDCDC2 and > DEFDCDC3 lines are tied high. This leads to a 3.3V IO and 1.2V CVDD > voltage. > > Pass the right platform data to the TPS6507x driver so it can operate > on the DEFDCDC{2,3}_HIGH register to read and change voltage levels. > > Signed-off-by: Sekhar Nori > --- > arch/arm/mach-davinci/board-da850-evm.c | 8 ++++++++ > 1 files changed, 8 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c > index 2ec3095..0c436c9 100644 > --- a/arch/arm/mach-davinci/board-da850-evm.c > +++ b/arch/arm/mach-davinci/board-da850-evm.c > @@ -25,6 +25,7 @@ > #include > #include > #include > +#include > #include > #include > > @@ -469,6 +470,11 @@ struct regulator_consumer_supply tps65070_ldo2_consumers[] = { > }, > }; > > +/* We take advantage of the fact that both defdcdc{2,3} are tied high */ > +static struct tps6507x_reg_platform_data tps6507x_platform_data = { > + .defdcdc_high = false, Oops, changed this to false for some testing and looks like I ended-up committing it! Will resubmit. Thanks, Sekhar From nsekhar at ti.com Mon Jul 12 05:49:03 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Mon, 12 Jul 2010 16:19:03 +0530 Subject: [PATCH 1/2] regulator: tps6507x: allow driver to use DEFDCDC{2,3}_HIGH register In-Reply-To: <20100712104045.GE21840@rakim.wolfsonmicro.main> References: <1278930888-26810-1-git-send-email-nsekhar@ti.com> <20100712104045.GE21840@rakim.wolfsonmicro.main> Message-ID: Hi Mark, On Mon, Jul 12, 2010 at 16:10:45, Mark Brown wrote: > On Mon, Jul 12, 2010 at 04:04:46PM +0530, Sekhar Nori wrote: > > > + > > + /* Does DCDC high or the low register defines output voltage? */ > > + bool defdcdc_high; > > This should probably be "defdcdc_default" or something. Presumably the > line can also be wired to a GPIO and changed at runtime (otherwise the > feature seems at best odd) and if support for that is implemented then > this will change from being a static configuration in the platform data > to something configured dynamically so the name would no longer make > sense. Quite right, it should be possible to change that line at runtime - though none of the existing boards use that flexibility. Will change the name as you have suggested. Thanks, Sekhar From nsekhar at ti.com Mon Jul 12 07:24:06 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Mon, 12 Jul 2010 17:54:06 +0530 Subject: [PATCH v2 1/2] regulator: tps6507x: allow driver to use DEFDCDC{2, 3}_HIGH register Message-ID: <1278937448-32404-1-git-send-email-nsekhar@ti.com> From: Anuj Aggarwal In TPS6507x, depending on the status of DEFDCDC{2,3} pin either DEFDCDC{2,3}_LOW or DEFDCDC{2,3}_HIGH register needs to be read or programmed to change the output voltage. The current driver assumes DEFDCDC{2,3} pins are always tied low and thus operates only on DEFDCDC{2,3}_LOW register. This need not always be the case (as is found on OMAP-L138 EVM). Unfortunately, software cannot read the status of DEFDCDC{2,3} pins. So, this information is passed through platform data depending on how the board is wired. Signed-off-by: Anuj Aggarwal Signed-off-by: Sekhar Nori --- v2: changed defdcdc_high to defdcdc_default to reflect the fact that it only takes care of reset default - not runtime change in defdcdc pin. drivers/regulator/tps6507x-regulator.c | 36 +++++++++++++++++++++++++------ include/linux/regulator/tps6507x.h | 32 ++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 7 deletions(-) create mode 100644 include/linux/regulator/tps6507x.h diff --git a/drivers/regulator/tps6507x-regulator.c b/drivers/regulator/tps6507x-regulator.c index 14b4576..8152d65 100644 --- a/drivers/regulator/tps6507x-regulator.c +++ b/drivers/regulator/tps6507x-regulator.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -101,9 +102,12 @@ struct tps_info { unsigned max_uV; u8 table_len; const u16 *table; + + /* Does DCDC high or the low register defines output voltage? */ + bool defdcdc_default; }; -static const struct tps_info tps6507x_pmic_regs[] = { +static struct tps_info tps6507x_pmic_regs[] = { { .name = "VDCDC1", .min_uV = 725000, @@ -145,7 +149,7 @@ struct tps6507x_pmic { struct regulator_desc desc[TPS6507X_NUM_REGULATOR]; struct tps6507x_dev *mfd; struct regulator_dev *rdev[TPS6507X_NUM_REGULATOR]; - const struct tps_info *info[TPS6507X_NUM_REGULATOR]; + struct tps_info *info[TPS6507X_NUM_REGULATOR]; struct mutex io_lock; }; static inline int tps6507x_pmic_read(struct tps6507x_pmic *tps, u8 reg) @@ -341,10 +345,16 @@ static int tps6507x_pmic_dcdc_get_voltage(struct regulator_dev *dev) reg = TPS6507X_REG_DEFDCDC1; break; case TPS6507X_DCDC_2: - reg = TPS6507X_REG_DEFDCDC2_LOW; + if (tps->info[dcdc]->defdcdc_default) + reg = TPS6507X_REG_DEFDCDC2_HIGH; + else + reg = TPS6507X_REG_DEFDCDC2_LOW; break; case TPS6507X_DCDC_3: - reg = TPS6507X_REG_DEFDCDC3_LOW; + if (tps->info[dcdc]->defdcdc_default) + reg = TPS6507X_REG_DEFDCDC3_HIGH; + else + reg = TPS6507X_REG_DEFDCDC3_LOW; break; default: return -EINVAL; @@ -370,10 +380,16 @@ static int tps6507x_pmic_dcdc_set_voltage(struct regulator_dev *dev, reg = TPS6507X_REG_DEFDCDC1; break; case TPS6507X_DCDC_2: - reg = TPS6507X_REG_DEFDCDC2_LOW; + if (tps->info[dcdc]->defdcdc_default) + reg = TPS6507X_REG_DEFDCDC2_HIGH; + else + reg = TPS6507X_REG_DEFDCDC2_LOW; break; case TPS6507X_DCDC_3: - reg = TPS6507X_REG_DEFDCDC3_LOW; + if (tps->info[dcdc]->defdcdc_default) + reg = TPS6507X_REG_DEFDCDC3_HIGH; + else + reg = TPS6507X_REG_DEFDCDC3_LOW; break; default: return -EINVAL; @@ -532,7 +548,7 @@ int tps6507x_pmic_probe(struct platform_device *pdev) { struct tps6507x_dev *tps6507x_dev = dev_get_drvdata(pdev->dev.parent); static int desc_id; - const struct tps_info *info = &tps6507x_pmic_regs[0]; + struct tps_info *info = &tps6507x_pmic_regs[0]; struct regulator_init_data *init_data; struct regulator_dev *rdev; struct tps6507x_pmic *tps; @@ -569,6 +585,12 @@ int tps6507x_pmic_probe(struct platform_device *pdev) for (i = 0; i < TPS6507X_NUM_REGULATOR; i++, info++, init_data++) { /* Register the regulators */ tps->info[i] = info; + if (init_data->driver_data) { + struct tps6507x_reg_platform_data *data = + init_data->driver_data; + tps->info[i]->defdcdc_default = data->defdcdc_default; + } + tps->desc[i].name = info->name; tps->desc[i].id = desc_id++; tps->desc[i].n_voltages = num_voltages[i]; diff --git a/include/linux/regulator/tps6507x.h b/include/linux/regulator/tps6507x.h new file mode 100644 index 0000000..4892f59 --- /dev/null +++ b/include/linux/regulator/tps6507x.h @@ -0,0 +1,32 @@ +/* + * tps6507x.h -- Voltage regulation for the Texas Instruments TPS6507X + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef REGULATOR_TPS6507X +#define REGULATOR_TPS6507X + +/** + * tps6507x_reg_platform_data - platform data for tps6507x + * @defdcdc_default: Defines whether DCDC high or the low register controls + * output voltage by default. Valid for DCDC2 and DCDC3 outputs only. + */ +struct tps6507x_reg_platform_data { + bool defdcdc_default; +}; + +#endif -- 1.6.2.4 From nsekhar at ti.com Mon Jul 12 07:26:21 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Mon, 12 Jul 2010 17:56:21 +0530 Subject: [PATCH v2 2/2] davinci: da850/omap-l138 evm: account for DEFDCDC{2, 3} being tied high Message-ID: <1278937581-867-1-git-send-email-nsekhar@ti.com> Per the da850/omap-l138 Beta EVM SOM schematic, the DEFDCDC2 and DEFDCDC3 lines are tied high. This leads to a 3.3V IO and 1.2V CVDD voltage. Pass the right platform data to the TPS6507x driver so it can operate on the DEFDCDC{2,3}_HIGH register to read and change voltage levels. Signed-off-by: Sekhar Nori --- v2: set the defdcdc_default to true to match the patch description. Other change done in line with the change in patch 1/2. arch/arm/mach-davinci/board-da850-evm.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 2ec3095..b280efb 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -469,6 +470,11 @@ struct regulator_consumer_supply tps65070_ldo2_consumers[] = { }, }; +/* We take advantage of the fact that both defdcdc{2,3} are tied high */ +static struct tps6507x_reg_platform_data tps6507x_platform_data = { + .defdcdc_default = true, +}; + struct regulator_init_data tps65070_regulator_data[] = { /* dcdc1 */ { @@ -494,6 +500,7 @@ struct regulator_init_data tps65070_regulator_data[] = { }, .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers), .consumer_supplies = tps65070_dcdc2_consumers, + .driver_data = &tps6507x_platform_data, }, /* dcdc3 */ @@ -507,6 +514,7 @@ struct regulator_init_data tps65070_regulator_data[] = { }, .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers), .consumer_supplies = tps65070_dcdc3_consumers, + .driver_data = &tps6507x_platform_data, }, /* ldo1 */ -- 1.6.2.4 From broonie at opensource.wolfsonmicro.com Mon Jul 12 07:27:07 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Mon, 12 Jul 2010 13:27:07 +0100 Subject: [PATCH v2 2/2] davinci: da850/omap-l138 evm: account for DEFDCDC{2,3} being tied high In-Reply-To: <1278937581-867-1-git-send-email-nsekhar@ti.com> References: <1278937581-867-1-git-send-email-nsekhar@ti.com> Message-ID: <20100712122707.GA22701@rakim.wolfsonmicro.main> On Mon, Jul 12, 2010 at 05:56:21PM +0530, Sekhar Nori wrote: > Per the da850/omap-l138 Beta EVM SOM schematic, the DEFDCDC2 and > DEFDCDC3 lines are tied high. This leads to a 3.3V IO and 1.2V CVDD > voltage. > > Pass the right platform data to the TPS6507x driver so it can operate > on the DEFDCDC{2,3}_HIGH register to read and change voltage levels. > > Signed-off-by: Sekhar Nori Acked-by: Mark Brown From broonie at opensource.wolfsonmicro.com Mon Jul 12 07:28:35 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Mon, 12 Jul 2010 13:28:35 +0100 Subject: [PATCH v2 1/2] regulator: tps6507x: allow driver to use DEFDCDC{2,3}_HIGH register In-Reply-To: <1278937448-32404-1-git-send-email-nsekhar@ti.com> References: <1278937448-32404-1-git-send-email-nsekhar@ti.com> Message-ID: <20100712122835.GB22701@rakim.wolfsonmicro.main> On Mon, Jul 12, 2010 at 05:54:06PM +0530, Sekhar Nori wrote: > From: Anuj Aggarwal > > In TPS6507x, depending on the status of DEFDCDC{2,3} pin either > DEFDCDC{2,3}_LOW or DEFDCDC{2,3}_HIGH register needs to be read or > programmed to change the output voltage. > > The current driver assumes DEFDCDC{2,3} pins are always tied low > and thus operates only on DEFDCDC{2,3}_LOW register. This need > not always be the case (as is found on OMAP-L138 EVM). > > Unfortunately, software cannot read the status of DEFDCDC{2,3} pins. > So, this information is passed through platform data depending on > how the board is wired. > > Signed-off-by: Anuj Aggarwal > Signed-off-by: Sekhar Nori Acked-by: Mark Brown From lrg at slimlogic.co.uk Mon Jul 12 07:52:26 2010 From: lrg at slimlogic.co.uk (Liam Girdwood) Date: Mon, 12 Jul 2010 13:52:26 +0100 Subject: [PATCH v2 2/2] davinci: da850/omap-l138 evm: account for DEFDCDC{2,3} being tied high In-Reply-To: <20100712122707.GA22701@rakim.wolfsonmicro.main> References: <1278937581-867-1-git-send-email-nsekhar@ti.com> <20100712122707.GA22701@rakim.wolfsonmicro.main> Message-ID: <1278939146.3072.50.camel@odin> On Mon, 2010-07-12 at 13:27 +0100, Mark Brown wrote: > On Mon, Jul 12, 2010 at 05:56:21PM +0530, Sekhar Nori wrote: > > Per the da850/omap-l138 Beta EVM SOM schematic, the DEFDCDC2 and > > DEFDCDC3 lines are tied high. This leads to a 3.3V IO and 1.2V CVDD > > voltage. > > > > Pass the right platform data to the TPS6507x driver so it can operate > > on the DEFDCDC{2,3}_HIGH register to read and change voltage levels. > > > > Signed-off-by: Sekhar Nori > > Acked-by: Mark Brown Kevin, I can take this through regulator (to reduce dependencies) if you want ? Liam From nsekhar at ti.com Mon Jul 12 07:59:02 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Mon, 12 Jul 2010 18:29:02 +0530 Subject: [PATCH 01/14] ASoC: DaVinci: Added support for stereo I2S In-Reply-To: <87aaqovwyr.fsf@deeprootsystems.com> References: <1276251594-5936-1-git-send-email-lamiaposta71@gmail.com> <87aaqovwyr.fsf@deeprootsystems.com> Message-ID: On Tue, Jun 22, 2010 at 04:01:56, Kevin Hilman wrote: > > To find out the right mailing lists for each of these subsystems, > please consult the MAINTAINERS file. A really useful tool is the > scripts/get_maintainer.pl script. Running that on a patch will > suggest the right audience for that patch using the MAINTAINERS file. > Since I gathered you're now using git-send-email, you can use this script > in combination with git-send-email's --cc-cmd option. e.g. > > git-send-email --to --cc-cmd=scripts/get_maintainer.pl [...] For DaVinci architecture patches, by default get_maintainer.pl is including Russell, linux-arm-kernel and LKML in the CC list. That I guess is too much for each DaVinci patch. To limit the CC list please use: --cc-cmd="scripts/get_maintainer.pl --pattern-depth=1" Not sure how well this works for other subsystem patches, but if it does, the option can also be placed in the .get_maintainer.conf file in kernel topdir. Thanks, Sekhar From nsekhar at ti.com Mon Jul 12 08:23:55 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Mon, 12 Jul 2010 18:53:55 +0530 Subject: BSD on davinci In-Reply-To: <664283.89475.qm@web24105.mail.ird.yahoo.com> References: <664283.89475.qm@web24105.mail.ird.yahoo.com> Message-ID: Hi rohan, On Fri, Jul 02, 2010 at 11:35:39, rohan tabish wrote: > anyone having any idea of porting BSD on davinci platform > Nope. Never heard of BSD port on DaVinci. Any specific reasons why you are looking for a BSD port? Thanks, Sekhar From mrechberger at gmail.com Mon Jul 12 08:34:34 2010 From: mrechberger at gmail.com (Markus Rechberger) Date: Mon, 12 Jul 2010 15:34:34 +0200 Subject: BSD on davinci In-Reply-To: References: <664283.89475.qm@web24105.mail.ird.yahoo.com> Message-ID: On Mon, Jul 12, 2010 at 3:23 PM, Nori, Sekhar wrote: > Hi rohan, > > On Fri, Jul 02, 2010 at 11:35:39, rohan tabish wrote: >> anyone having any idea of porting BSD on davinci platform >> > > Nope. Never heard of BSD port on DaVinci. Any specific reasons > why you are looking for a BSD port? > better commercial use (or easier legal integration of restricted 3rd party code). BR, Markus > Thanks, > Sekhar > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > From luna.id at gmail.com Mon Jul 12 09:10:07 2010 From: luna.id at gmail.com (Nicolas Luna) Date: Mon, 12 Jul 2010 10:10:07 -0400 Subject: YAFFS2 not in git???? In-Reply-To: <7198.61536.qm@web24103.mail.ird.yahoo.com> References: <7198.61536.qm@web24103.mail.ird.yahoo.com> Message-ID: Patch it : http://www.yaffs.net/ Regards, Nicolas On Mon, Jul 12, 2010 at 2:30 AM, rohan tabish wrote: > How to use yaffs with git kernel there is no support for it? > > > Regard's > Rohan Tabish > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From rtivy at ti.com Mon Jul 12 16:32:13 2010 From: rtivy at ti.com (Tivy, Robert) Date: Mon, 12 Jul 2010 16:32:13 -0500 Subject: DM355 - 256MB RAM memory issue In-Reply-To: <1278776129.3931.225.camel@tharma-laptop> References: <1278339242.18556.10.camel@tharma-laptop> <1278428415.14942.19703.camel@sax-lx> <1278776129.3931.225.camel@tharma-laptop> Message-ID: <6B8224E84039B140AA662F0BB0361643012BC33E26@dlee04.ent.ti.com> ________________________________ From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Tharmarajan Ganeshan Sent: Saturday, July 10, 2010 8:35 AM To: todd.fischer at ridgerun.com; Ring, Chris Cc: davinci-linux-open-source at linux.davincidsp.com; dhineshkumar; Mohamed Thalib H; maharajan Subject: Re: DM355 - 256MB RAM memory issue Hi Todd and Chris, Thank for your suggestion. We tried the option 'hole in the kernel memory space'. But that is not solving our issue. We tried to reserve memory 30MB at various place in RAM. But these trials does not help us to solve this issue. And also we tried to get the memory for this 5MP image capturing from the CMEM driver. For this we allocated 86MB to CMEM driver. But the kernel is hanging while loading this CMEM driver. Is there any limitation in CMEM driver ? As far as we know there is no limitation on the size of the physical block granted to CMEM. If you'd like to pursue this approach (getting your 5MP image memory from CMEM) then I could help, but would need to see the debug output of the CMEMK kernel module that you say is "hanging while loading this CMEM driver." To produce debug output, build the "debug" version by: % cd /ti/sdo/linuxutils/cmem/src/module % make debug Then 'insmod' this cmemk.ko and observe CMEMK debug output on the Linux console. Regards, - Rob Regards, Tharmarajan G On Tue, 2010-07-06 at 09:00 -0600, Todd Fischer wrote: Tharmarajan, I believe you need to rebuild your codec server with a different memory map. Another idea is to have a hole in the kernel memory space (specify mem= in the kernel command line twice). I am not sure if the kernel version you are using for dm355 supports a hole in the kernel memory space. Todd On Mon, 2010-07-05 at 19:44 +0530, Tharmarajan Ganeshan wrote: Hi All, We are working on a DM355 processor based Development board. The Board has 256MB mDDR RAM and 5MP image sensor MT9P031. We are using the kernel version 2.6.10 We have modified the driver code for capturing 5MP raw image and converting this 5MP raw into YUV. For this 5MP image capturing , we have reserved 30MB. We have allocated 56MB to the CMEM driver. The reserved memory 30MB and the 56MB memory for CMEM are at top of the RAM. We are passing the remaining memory size to the kernel in bootargs as mem=170M. And we are using the NFS rootfilesystem. But we are getting kernel hanging issues while testing the IPNC_APP applications and 5MP still image capturing. Sometimes the kernel is hanging while booting itself. If we reserve the 30MB from the address region 0x83200000 - 0x84FFFFFF and pass the memory size to kernel in bootargs as mem=50M, then we are NOT having any issues in running the applications. But we want to use the exact remaining memory. And also we are not able to program the NAND flash memory in kernel level if we are not passing the mem=50M in bootargs. What could be the cause for this kernel hanging issue ? Are we missing any configurations while building the kernel image ? Our Bootargs is : mem=50M console=ttyS1,115200n8 root=/dev/nfs rootwait rw ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 nfsroot=192.168.1.99:/tftpboot/bellatrix_rootfilesystem,nolock eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 Regards, Tharmarajan G _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -------------- next part -------------- An HTML attachment was scrubbed... URL: From schen at mvista.com Tue Jul 13 00:11:20 2010 From: schen at mvista.com (Steve Chen) Date: Tue, 13 Jul 2010 00:11:20 -0500 Subject: BSD on davinci In-Reply-To: References: <664283.89475.qm@web24105.mail.ird.yahoo.com> Message-ID: On Mon, Jul 12, 2010 at 8:34 AM, Markus Rechberger wrote: > On Mon, Jul 12, 2010 at 3:23 PM, Nori, Sekhar wrote: >> Hi rohan, >> >> On Fri, Jul 02, 2010 at 11:35:39, rohan tabish wrote: >>> anyone having any idea of porting BSD on davinci platform >>> >> >> Nope. Never heard of BSD port on DaVinci. Any specific reasons >> why you are looking for a BSD port? >> > > better commercial use (or easier legal integration of restricted 3rd > party code). > Since this is the *Linux* Davinci mailing list probably not too many BSD folks hangs out here :) May want to try BSD mailing if you haven't already. Steve From rohan_javed at yahoo.co.uk Tue Jul 13 00:59:59 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Tue, 13 Jul 2010 05:59:59 +0000 (GMT) Subject: yaffs Message-ID: <833440.75064.qm@web24103.mail.ird.yahoo.com> i have enable yaffs support in the kernl it gives following error when i mount using yaffs2 mount -t yaffs2 /dev/mtdblock3 /mnt/yaffs: dev is 32505859 name is "mtdblock3"???????????????????????????????????????????????????????????? ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? yaffs: passed flags ""?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? =============================================================================??????????????????????????????????????????????????????????????? BUG yaffs_o_1: Objects remaining on kmem_cache_close()?????????????????????????????????????????????????????????????????????????????????????? -----------------------------------------------------------------------------??????????????????????????????????????????????????????????????? ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? INFO: Slab 0xc0435e60 objects=32 used=4 fp=0xc6873f80 flags=0x0080?????????????????????????????????????????????????????????????????????????? Backtrace:?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? [] (dump_backtrace+0x0/0x110) from [] (dump_stack+0x18/0x1c)???????????????????????????????????????????????????????????? ?r6:c0435e60 r5:c688b3c0 r4:c7075c38???????????????????????????????????????????????????????????????????????????????????????????????????????? [] (dump_stack+0x0/0x1c) from [] (slab_err+0x58/0x64)??????????????????????????????????????????????????????????????????? [] (slab_err+0x0/0x64) from [] (list_slab_objects+0x80/0x164)??????????????????????????????????????????????????????????? ?r3:c02e253c r2:c02d90c4???????????????????????????????????????????????????????????????????????????????????????????????????????????????????? ?r6:c6873000 r5:c688b3c0 r4:c02e253c???????????????????????????????????????????????????????????????????????????????????????????????????????? [] (list_slab_objects+0x0/0x164) from [] (kmem_cache_destroy+0xe0/0x1b0)???????????????????????????????????????????????? [] (kmem_cache_destroy+0x0/0x1b0) from [] (yaffs_DeinitialiseRawTnodesAndObjects+0x78/0xe4)????????????????????????????? [] (yaffs_DeinitialiseRawTnodesAndObjects+0x0/0xe4) from [] (yaffs_DeinitialiseTnodesAndObjects+0x18/0x28)?????????????? ?r5:c33ab800 r4:c7014000???????????????????????????????????????????????????????????????????????????????????????????????????????????????????? [] (yaffs_DeinitialiseTnodesAndObjects+0x0/0x28) from [] (yaffs_GutsInitialise+0x594/0x870)????????????????????????????? ?r4:c68e3efc???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? [] (yaffs_GutsInitialise+0x0/0x870) from [] (yaffs_internal_read_super+0x8b4/0xb3c)????????????????????????????????????? [] (yaffs_internal_read_super+0x0/0xb3c) from [] (yaffs2_internal_read_super_mtd+0x24/0x34)????????????????????????????? [] (yaffs2_internal_read_super_mtd+0x0/0x34) from [] (get_sb_bdev+0x11c/0x174)?????????????????????????????????????????? [] (get_sb_bdev+0x0/0x174) from [] (yaffs2_read_super+0x24/0x30)???????????????????????????????????????????????????????? [] (yaffs2_read_super+0x0/0x30) from [] (vfs_kern_mount+0x58/0xdc)?????????????????????????????????????????????????????? [] (vfs_kern_mount+0x0/0xdc) from [] (do_kern_mount+0x40/0xe4)?????????????????????????????????????????????????????????? ?r8:c03337b8 r7:c767d660 r6:c6870000 r5:c767d680 r4:00008000???????????????????????????????????????????????????????????????????????????????? [] (do_kern_mount+0x0/0xe4) from [] (do_mount+0x6b4/0x720)?????????????????????????????????????????????????????????????? ?r8:00008000 r7:c767d680 r6:00000020 r5:00000000 r4:00000000???????????????????????????????????????????????????????????????????????????????? [] (do_mount+0x0/0x720) from [] (sys_mount+0x8c/0xcc)??????????????????????????????????????????????????????????????????? [] (sys_mount+0x0/0xcc) from [] (ret_fast_syscall+0x0/0x28)????????????????????????????????????????????????????????????? ?r7:00000015 r6:bec7af87 r5:bec7af78 r4:001fafb8???????????????????????????????????????????????????????????????????????????????????????????? INFO: Object 0xc6873000 @offset=0??????????????????????????????????????????????????????????????????????????????????????????????????????????? INFO: Object 0xc6873080 @offset=128????????????????????????????????????????????????????????????????????????????????????????????????????????? INFO: Object 0xc6873100 @offset=256????????????????????????????????????????????????????????????????????????????????????????????????????????? INFO: Object 0xc6873180 @offset=384????????????????????????????????????????????????????????????????????????????????????????????????????????? SLUB yaffs_o_1: kmem_cache_destroy called for cache that still has objects.????????????????????????????????????????????????????????????????? Backtrace:?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? [] (dump_backtrace+0x0/0x110) from [] (dump_stack+0x18/0x1c)???????????????????????????????????????????????????????????? ?r6:c688b3c0 r5:c688b3d8 r4:c0435e60???????????????????????????????????????????????????????????????????????????????????????????????????????? [] (dump_stack+0x0/0x1c) from [] (kmem_cache_destroy+0x194/0x1b0)??????????????????????????????????????????????????????? [] (kmem_cache_destroy+0x0/0x1b0) from [] (yaffs_DeinitialiseRawTnodesAndObjects+0x78/0xe4)????????????????????????????? [] (yaffs_DeinitialiseRawTnodesAndObjects+0x0/0xe4) from [] (yaffs_DeinitialiseTnodesAndObjects+0x18/0x28)?????????????? ?r5:c33ab800 r4:c7014000???????????????????????????????????????????????????????????????????????????????????????????????????????????????????? [] (yaffs_DeinitialiseTnodesAndObjects+0x0/0x28) from [] (yaffs_GutsInitialise+0x594/0x870)????????????????????????????? ?r4:c68e3efc???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? [] (yaffs_GutsInitialise+0x0/0x870) from [] (yaffs_internal_read_super+0x8b4/0xb3c)????????????????????????????????????? [] (yaffs_internal_read_super+0x0/0xb3c) from [] (yaffs2_internal_read_super_mtd+0x24/0x34)????????????????????????????? [] (yaffs2_internal_read_super_mtd+0x0/0x34) from [] (get_sb_bdev+0x11c/0x174)?????????????????????????????????????????? [] (get_sb_bdev+0x0/0x174) from [] (yaffs2_read_super+0x24/0x30)???????????????????????????????????????????????????????? [] (yaffs2_read_super+0x0/0x30) from [] (vfs_kern_mount+0x58/0xdc)?????????????????????????????????????????????????????? [] (vfs_kern_mount+0x0/0xdc) from [] (do_kern_mount+0x40/0xe4)?????????????????????????????????????????????????????????? ?r8:c03337b8 r7:c767d660 r6:c6870000 r5:c767d680 r4:00008000???????????????????????????????????????????????????????????????????????????????? [] (do_kern_mount+0x0/0xe4) from [] (do_mount+0x6b4/0x720)?????????????????????????????????????????????????????????????? ?r8:00008000 r7:c767d680 r6:00000020 r5:00000000 r4:00000000???????????????????????????????????????????????????????????????????????????????? [] (do_mount+0x0/0x720) from [] (sys_mount+0x8c/0xcc)??????????????????????????????????????????????????????????????????? [] (sys_mount+0x0/0xcc) from [] (ret_fast_syscall+0x0/0x28)????????????????????????????????????????????????????????????? ?r7:00000015 r6:bec7af87 r5:bec7af78 r4:001fafb8???? RT -------------- next part -------------- An HTML attachment was scrubbed... URL: From david-b at pacbell.net Tue Jul 13 01:35:44 2010 From: david-b at pacbell.net (David Brownell) Date: Mon, 12 Jul 2010 23:35:44 -0700 (PDT) Subject: yaffs Message-ID: <514789.39887.qm@web180302.mail.gq1.yahoo.com> > i have enable yaffs support in the kernl it >?gives following error when i mount using yaffs2 Try asking YAFFS questions on a YAFFS mailing list; that's not standard Linux stuff. And for that matter, UBI and UBIFS are still the preferred approaches for NAND in Linux ... with the MTD lists ready to help, since that tech is standard in mainline. - Dave From sudhakar.raj at ti.com Tue Jul 13 04:32:59 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Tue, 13 Jul 2010 15:02:59 +0530 Subject: [PATCH] mtd-nand: davinci: correct 4-bit error correction In-Reply-To: <00c701cb218b$6e4d6dd0$4ae84970$@raj@ti.com> References: <1278653389-12019-1-git-send-email-sudhakar.raj@ti.com> <20100709153932.0a6cdbcd.akpm@linux-foundation.org> <00c701cb218b$6e4d6dd0$4ae84970$@raj@ti.com> Message-ID: <012f01cb226e$61ac9b80$2505d280$@raj@ti.com> Hi, On Mon, Jul 12, 2010 at 11:58:18, Sudhakar Rajashekhara wrote: > On Sat, Jul 10, 2010 at 04:09:32, Andrew Morton wrote: > > On Fri, 9 Jul 2010 10:59:49 +0530 > > Sudhakar Rajashekhara wrote: > > > > > + > > > + /* > > > + * ECC_STATE field reads 0x3 (Error correction complete) immediately > > > + * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately > > > + * begin trying to poll for the state, you may fall right out of your > > > + * loop without any of the correction calculations having taken place. > > > + * The recommendation from the hardware team is to wait till ECC_STATE > > > + * reads less than 4, which means ECC HW has entered correction state. > > > + */ > > > + do { > > > + ecc_state = (davinci_nand_readl(info, > > > + NANDFSR_OFFSET) >> 8) & 0x0f; > > > + cpu_relax(); > > > + } while ((ecc_state < 4) && time_before(jiffies, timeo)); > > > > An up-to-100-milliseond busy wait is pretty bad. For how long do you > > expect this to spin in practice? > > On the hardware, I have never seen this taking 100 msec to come out of > the loop. I'll check with the hardware folks on the maximum time to wait > for, before the ECC engine is ready. I checked this with the hardware team but no one is sure about the exact time one should wait before the ECC engine becomes ready. But everyone is of the opinion that 100 loop cycles should be enough. To be on the safer side, I'll be changing the timeout to 10 milliseconds in the next version of this patch. Thanks, Sudhakar From nsekhar at ti.com Tue Jul 13 06:00:46 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Tue, 13 Jul 2010 16:30:46 +0530 Subject: [PATCH 4/4] ASoC: DaVinci: pcm, fix underrun by using sram In-Reply-To: <1258415554-31069-4-git-send-email-troy.kisky@boundarydevices.com> References: <1258415554-31069-1-git-send-email-troy.kisky@boundarydevices.com> <1258415554-31069-2-git-send-email-troy.kisky@boundarydevices.com> <1258415554-31069-3-git-send-email-troy.kisky@boundarydevices.com> <1258415554-31069-4-git-send-email-troy.kisky@boundarydevices.com> Message-ID: Hi Troy, On Tue, Nov 17, 2009 at 05:22:34, Troy Kisky wrote: > Fix underruns by using dma to copy 1st to sram > in a ping/pong buffer style and then copying from > the sram to the ASP. This also has the advantage > of tolerating very long interrupt latency on dma > completion. > > Signed-off-by: Troy Kisky [...] > +static int request_ping_pong(struct snd_pcm_substream *substream, > + struct davinci_runtime_data *prtd, > + struct snd_dma_buffer *iram_dma) > +{ > + dma_addr_t asp_src_ping; > + dma_addr_t asp_dst_ping; > + int link; > + struct davinci_pcm_dma_params *dma_data = prtd->params; > + > + /* Request ram master channel */ > + link = prtd->ram_channel = edma_alloc_channel(EDMA_CHANNEL_ANY, > + davinci_pcm_dma_irq, substream, > + EVENTQ_1); What is the reason for choosing EVENTQ_1 for this channel? EVENTQ_0 is already being used for ASP channel. I imagine it will be much easier to tune the queue usage in the system if all of audio data was using the same queue. I am working on a patch which lets platform specify the event queues for audio DMA. I am not sure if I really need to make a provision for two different queues to be specified - that's why I ask. Thanks, Sekhar From akpm at linux-foundation.org Tue Jul 13 12:41:26 2010 From: akpm at linux-foundation.org (Andrew Morton) Date: Tue, 13 Jul 2010 10:41:26 -0700 Subject: [PATCH] mtd-nand: davinci: correct 4-bit error correction In-Reply-To: <012f01cb226e$61ac9b80$2505d280$@raj@ti.com> References: <1278653389-12019-1-git-send-email-sudhakar.raj@ti.com> <20100709153932.0a6cdbcd.akpm@linux-foundation.org> <00c701cb218b$6e4d6dd0$4ae84970$@raj@ti.com> <012f01cb226e$61ac9b80$2505d280$@raj@ti.com> Message-ID: <20100713104126.95891684.akpm@linux-foundation.org> On Tue, 13 Jul 2010 15:02:59 +0530 "Sudhakar Rajashekhara" wrote: > Hi, > > On Mon, Jul 12, 2010 at 11:58:18, Sudhakar Rajashekhara wrote: > > On Sat, Jul 10, 2010 at 04:09:32, Andrew Morton wrote: > > > On Fri, 9 Jul 2010 10:59:49 +0530 > > > Sudhakar Rajashekhara wrote: > > > > > > > + > > > > + /* > > > > + * ECC_STATE field reads 0x3 (Error correction complete) immediately > > > > + * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately > > > > + * begin trying to poll for the state, you may fall right out of your > > > > + * loop without any of the correction calculations having taken place. > > > > + * The recommendation from the hardware team is to wait till ECC_STATE > > > > + * reads less than 4, which means ECC HW has entered correction state. > > > > + */ > > > > + do { > > > > + ecc_state = (davinci_nand_readl(info, > > > > + NANDFSR_OFFSET) >> 8) & 0x0f; > > > > + cpu_relax(); > > > > + } while ((ecc_state < 4) && time_before(jiffies, timeo)); > > > > > > An up-to-100-milliseond busy wait is pretty bad. For how long do you > > > expect this to spin in practice? > > > > On the hardware, I have never seen this taking 100 msec to come out of > > the loop. I'll check with the hardware folks on the maximum time to wait > > for, before the ECC engine is ready. > > I checked this with the hardware team but no one is sure about the exact > time one should wait before the ECC engine becomes ready. But everyone is > of the opinion that 100 loop cycles should be enough. To be on the safer > side, I'll be changing the timeout to 10 milliseconds in the next version > of this patch. Going from 100ms down to 10ms sounds a bit risky. It'd be better to retain the 100ms and to make the kernel spend most of that time sleeping, rather than busywaiting, IMO. From troy.kisky at boundarydevices.com Tue Jul 13 14:01:00 2010 From: troy.kisky at boundarydevices.com (troy.kisky at boundarydevices.com) Date: Tue, 13 Jul 2010 14:01:00 -0500 Subject: [PATCH 4/4] ASoC: DaVinci: pcm, fix underrun by using sram Message-ID: <51883.1279047660@boundarydevices.com> BODY { font-family:Arial, Helvetica, sans-serif;font-size:12px; } On Tue 13/07/10 6:00 AM , "Nori, Sekhar" nsekhar at ti.com sent: Hi Troy, On Tue, Nov 17, 2009 at 05:22:34, Troy Kisky wrote: > Fix underruns by using dma to copy 1st to sram > in a ping/pong buffer style and then copying from > the sram to the ASP. This also has the advantage > of tolerating very long interrupt latency on dma > completion. > > Signed-off-by: Troy Kisky [...] > +static int request_ping_pong(struct snd_pcm_substream *substream, > + struct davinci_runtime_data *prtd, > + struct snd_dma_buffer *iram_dma) > +{ > + dma_addr_t asp_src_ping; > + dma_addr_t asp_dst_ping; > + int link; > + struct davinci_pcm_dma_params *dma_data = prtd->params; > + > + /* Request ram master channel */ > + link = prtd->ram_channel = edma_alloc_channel(EDMA_CHANNEL_ANY, > + davinci_pcm_dma_irq, substream, > + EVENTQ_1); What is the reason for choosing EVENTQ_1 for this channel? EVENTQ_0 is already being used for ASP channel. I imagine it will be much easier to tune the queue usage in the system if all of audio data was using the same queue. I am working on a patch which lets platform specify the event queues for audio DMA. I am not sure if I really need to make a provision for two different queues to be specified - that's why I ask. Thanks, Sekhar The reason is so that the IRAM data can be fetched and used while EVENTQ_1 fetches the next buffer of data from sdram into IRAM. Troy -------------- next part -------------- An HTML attachment was scrubbed... URL: From hankm at mtinet.com Tue Jul 13 16:05:31 2010 From: hankm at mtinet.com (Hank Magnuski) Date: Tue, 13 Jul 2010 14:05:31 -0700 (PDT) Subject: DM368 Support Message-ID: Can someone clue me in on how support for the DM368 will be handled? First, have any patches been developed for this chip and if so, where? How will the chip be handled in the code? Will it have its own identity: is_a_dm368() or will it have an identity as some type of DM365 variant? Has anybody patched the clock code to take advantage of the faster speeds available with this chip? Thanks, Hank From hankm at ncast.com Tue Jul 13 08:58:53 2010 From: hankm at ncast.com (Hank Magnuski) Date: Tue, 13 Jul 2010 06:58:53 -0700 (PDT) Subject: DM368 Support Message-ID: Can someone clue me in on how support for the DM368 will be handled? First, have any patches been developed for this chip and if so, where? How will the chip be handled in the code? Will it have its own identity: is_a_dm368() or will it have an identity as some type of DM365 variant? Has anybody patched the clock code to take advantage of the faster speeds available with this chip? Thanks, Hank From nsekhar at ti.com Wed Jul 14 06:00:41 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Wed, 14 Jul 2010 16:30:41 +0530 Subject: DM368 Support In-Reply-To: References: Message-ID: Hi Hank, On Tue, Jul 13, 2010 at 19:28:53, Hank Magnuski wrote: > > Can someone clue me in on how support for the DM368 will be handled? > > First, have any patches been developed for this chip and if so, where? > > How will the chip be handled in the code? Will it have its own identity: > > is_a_dm368() I don't think there is a way to differentiate DM365 from DM368 except the changed PLL settings. > > or will it have an identity as some type of DM365 variant? > Yes, cpu_is_dm365() will be true for DM368. > Has anybody patched the clock code to take advantage of the faster speeds > available with this chip? > The clock code reads the settings done by UBL and configures itself. So you slip in an updated UBL, and that should be it. I believe some changes are required in the video drivers from what has been shipping in TI releases so far, but those drivers are not upstream so the upstream kernel should not require any changes per se. Thanks, Sekhar From sudhakar.raj at ti.com Wed Jul 14 06:25:34 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Wed, 14 Jul 2010 16:55:34 +0530 Subject: [PATCH] mtd-nand: davinci: correct 4-bit error correction In-Reply-To: <20100713104126.95891684.akpm@linux-foundation.org> References: <1278653389-12019-1-git-send-email-sudhakar.raj@ti.com> <20100709153932.0a6cdbcd.akpm@linux-foundation.org> <00c701cb218b$6e4d6dd0$4ae84970$@raj@ti.com> <012f01cb226e$61ac9b80$2505d280$@raj@ti.com> <20100713104126.95891684.akpm@linux-foundation.org> Message-ID: <025e01cb2347$46817310$d3845930$@raj@ti.com> Hi, On Tue, Jul 13, 2010 at 23:11:26, Andrew Morton wrote: > On Tue, 13 Jul 2010 15:02:59 +0530 "Sudhakar Rajashekhara" wrote: > > > Hi, > > > > On Mon, Jul 12, 2010 at 11:58:18, Sudhakar Rajashekhara wrote: > > > On Sat, Jul 10, 2010 at 04:09:32, Andrew Morton wrote: > > > > On Fri, 9 Jul 2010 10:59:49 +0530 > > > > Sudhakar Rajashekhara wrote: > > > > > > > > > + > > > > > + /* > > > > > + * ECC_STATE field reads 0x3 (Error correction complete) immediately > > > > > + * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately > > > > > + * begin trying to poll for the state, you may fall right out of your > > > > > + * loop without any of the correction calculations having taken place. > > > > > + * The recommendation from the hardware team is to wait till ECC_STATE > > > > > + * reads less than 4, which means ECC HW has entered correction state. > > > > > + */ > > > > > + do { > > > > > + ecc_state = (davinci_nand_readl(info, > > > > > + NANDFSR_OFFSET) >> 8) & 0x0f; > > > > > + cpu_relax(); > > > > > + } while ((ecc_state < 4) && time_before(jiffies, timeo)); > > > > > > > > An up-to-100-milliseond busy wait is pretty bad. For how long do you > > > > expect this to spin in practice? > > > > > > On the hardware, I have never seen this taking 100 msec to come out of > > > the loop. I'll check with the hardware folks on the maximum time to wait > > > for, before the ECC engine is ready. > > > > I checked this with the hardware team but no one is sure about the exact > > time one should wait before the ECC engine becomes ready. But everyone is > > of the opinion that 100 loop cycles should be enough. To be on the safer > > side, I'll be changing the timeout to 10 milliseconds in the next version > > of this patch. > > Going from 100ms down to 10ms sounds a bit risky. It'd be better to > retain the 100ms and to make the kernel spend most of that time > sleeping, rather than busywaiting, IMO. > I chose 100ms timeout randomly, but today I did some calculation using do_gettimeofday() to find out the actual time spent inside the loop. I found that, control is coming out of loop within 5 microseconds. So I'll go ahead and use usecs_to_jiffies(100) as timeout. Busywaiting for such a short duration may not be a problem. Regards, Sudhakar From nsekhar at ti.com Wed Jul 14 06:38:17 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Wed, 14 Jul 2010 17:08:17 +0530 Subject: [PATCH] davinci: dm365: disable pulldowns for all MMC/SD1 pins. Message-ID: <1279107497-22729-1-git-send-email-nsekhar@ti.com> This patch disables internal pulldowns for all MMC/SD1 pins. Presently only MMCSD1_CMD pin's pull down is disabled, but with this some MMC/SD cards do not get detected on MMC/SD1 slot of the EVM. The problem was reproducible with SanDisk 4GB SDHC card. Reported-by: Stephane Bovagne Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/devices.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 8b7201e..2a9a252 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -213,7 +213,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c); /* Configure pull down control */ - __raw_writel((__raw_readl(pupdctl1) & ~0x400), + __raw_writel((__raw_readl(pupdctl1) & ~0xfc0), pupdctl1); mmcsd1_resources[0].start = DM365_MMCSD1_BASE; -- 1.6.2.4 From nsekhar at ti.com Wed Jul 14 06:39:45 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Wed, 14 Jul 2010 17:09:45 +0530 Subject: [PATCH] davinci: dm365: disable pulldowns for all MMC/SD1 pins. Message-ID: <1279107585-23521-1-git-send-email-nsekhar@ti.com> This patch disables internal pulldowns for all MMC/SD1 pins. Presently only MMCSD1_CMD pin's pull down is disabled, but with this some MMC/SD cards do not get detected on MMC/SD1 slot of the EVM. The problem was reproducible with SanDisk 4GB SDHC card. Reported-by: Stephane Bovagne Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/devices.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 8b7201e..2a9a252 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -213,7 +213,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c); /* Configure pull down control */ - __raw_writel((__raw_readl(pupdctl1) & ~0x400), + __raw_writel((__raw_readl(pupdctl1) & ~0xfc0), pupdctl1); mmcsd1_resources[0].start = DM365_MMCSD1_BASE; -- 1.6.2.4 From nsekhar at ti.com Wed Jul 14 08:05:28 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Wed, 14 Jul 2010 18:35:28 +0530 Subject: [PATCH 4/4] ASoC: DaVinci: pcm, fix underrun by using sram In-Reply-To: <51883.1279047660@boundarydevices.com> References: <51883.1279047660@boundarydevices.com> Message-ID: On Wed, Jul 14, 2010 at 00:31:00, troy.kisky at boundarydevices.com wrote: > > On Tue 13/07/10 6:00 AM , "Nori, Sekhar" nsekhar at ti.com sent: > > [...] > > > +static int request_ping_pong(struct snd_pcm_substream > *substream, > > + struct davinci_runtime_data *prtd, > > + struct snd_dma_buffer *iram_dma) > > +{ > > + dma_addr_t asp_src_ping; > > + dma_addr_t asp_dst_ping; > > + int link; > > + struct davinci_pcm_dma_params *dma_data = prtd->params; > > + > > + /* Request ram master channel */ > > + link = prtd->ram_channel = > edma_alloc_channel(EDMA_CHANNEL_ANY, > > + davinci_pcm_dma_irq, substream, > > + EVENTQ_1); > > What is the reason for choosing EVENTQ_1 for this channel? > EVENTQ_0 > is already being used for ASP channel. > > I imagine it will be much easier to tune the queue usage in the > system > if all of audio data was using the same queue. > > I am working on a patch which lets platform specify the event > queues > for audio DMA. I am not sure if I really need to make a > provision for > two different queues to be specified - that's why I ask. > > Thanks, > Sekhar > > The reason is so that the IRAM data can be fetched and used > while > > EVENTQ_1 fetches the next buffer of data from sdram into IRAM. Thanks for the explanation. That sounds reasonable. Just curious as to whether you actually faced an issue when using the same event queue for both transfers? I just tested this on DM365 with both transfers on EDMAQ_0 with 16K each of capture and playback IRAM at 48KHz sampling rate and did not find any issue. Anyway it makes sense to make provision for platform to choose different queues for both transfers so will implement my patch that way. Thanks, Sekhar From tharma at e-consystems.com Wed Jul 14 10:16:43 2010 From: tharma at e-consystems.com (Tharmarajan Ganeshan) Date: Wed, 14 Jul 2010 20:46:43 +0530 Subject: DM355 - 256MB RAM memory issue In-Reply-To: <6B8224E84039B140AA662F0BB0361643012BC33E26@dlee04.ent.ti.com> References: <1278339242.18556.10.camel@tharma-laptop> <1278428415.14942.19703.camel@sax-lx> <1278776129.3931.225.camel@tharma-laptop> <6B8224E84039B140AA662F0BB0361643012BC33E26@dlee04.ent.ti.com> Message-ID: <1279120603.4033.63.camel@tharma-laptop> Hi Robert, I have built the cmemk.ko by running the command 'make debug'. But I could not find any extra messages while loading this cmemk driver. Here I have attached two log files when mem=50M and mem=168M to the kernel. CMEM is reserved with 88M. Regards, Tharmarajan G On Mon, 2010-07-12 at 16:32 -0500, Tivy, Robert wrote: > > > > > > ______________________________________________________________ > From: davinci-linux-open-source-bounces at linux.davincidsp.com > [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Tharmarajan Ganeshan > Sent: Saturday, July 10, 2010 8:35 AM > To: todd.fischer at ridgerun.com; Ring, Chris > Cc: davinci-linux-open-source at linux.davincidsp.com; > dhineshkumar; Mohamed Thalib H; maharajan > Subject: Re: DM355 - 256MB RAM memory issue > > > > Hi Todd and Chris, > > Thank for your suggestion. We tried the option > 'hole in the kernel memory space'. But that is not solving our > issue. > We tried to reserve memory 30MB at various > place in RAM. But these trials does not help us to solve this > issue. > > And also we tried to get the memory for this > 5MP image capturing from the CMEM driver. For this we > allocated 86MB to CMEM driver. But the kernel is hanging while > loading this CMEM driver. > > Is there any limitation in CMEM driver ? > > As far as we know there is no limitation on the size of the physical > block granted to CMEM. > > If you'd like to pursue this approach (getting your 5MP image memory > from CMEM) then I could help, but would need to see the debug output > of the CMEMK kernel module that you say is "hanging while loading this > CMEM driver." To produce debug output, build the "debug" version by: > % cd /ti/sdo/linuxutils/cmem/src/module > % make debug > Then 'insmod' this cmemk.ko and observe CMEMK debug output on the > Linux console. > > Regards, > > - Rob > > > > Regards, > Tharmarajan G > > On Tue, 2010-07-06 at 09:00 -0600, Todd Fischer wrote: > > > > > Tharmarajan, > > > > I believe you need to rebuild your codec server with a > > different memory map. Another idea is to have a hole in the > > kernel memory space (specify mem= in the kernel command line > > twice). I am not sure if the kernel version you are using > > for dm355 supports a hole in the kernel memory space. > > > > Todd > > > > On Mon, 2010-07-05 at 19:44 +0530, Tharmarajan Ganeshan > > wrote: > > > > > Hi All, > > > We are working on a DM355 processor based > > > Development board. The Board has 256MB mDDR RAM and 5MP > > > image sensor MT9P031. > > > > > > We are using the kernel version 2.6.10 > > > > > > We have modified the driver code for capturing > > > 5MP raw image and converting this 5MP raw into YUV. For > > > this 5MP image capturing , we have reserved 30MB. > > > > > > We have allocated 56MB to the CMEM driver. > > > > > > The reserved memory 30MB and the 56MB memory > > > for CMEM are at top of the RAM. > > > > > > We are passing the remaining memory size to > > > the kernel in bootargs as mem=170M. And we are using the > > > NFS rootfilesystem. > > > > > > But we are getting kernel hanging issues while > > > testing the IPNC_APP applications and 5MP still image > > > capturing. Sometimes the kernel is hanging while booting > > > itself. > > > > > > > > > If we reserve the 30MB from the address region > > > 0x83200000 - 0x84FFFFFF and pass the memory size to kernel > > > in bootargs as mem=50M, then we are NOT having any issues > > > in running the applications. But we want to use the exact > > > remaining memory. > > > > > > And also we are not able to program the NAND > > > flash memory in kernel level if we are not passing the > > > mem=50M in bootargs. > > > > > > What could be the cause for this kernel > > > hanging issue ? > > > > > > Are we missing any configurations while > > > building the kernel image ? > > > > > > Our Bootargs is : > > > mem=50M console=ttyS1,115200n8 root=/dev/nfs rootwait rw > > > ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 > > > nfsroot=192.168.1.99:/tftpboot/bellatrix_rootfilesystem,nolock eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 > > > > > > > > > > > > Regards, > > > Tharmarajan G > > > > > > > > > _______________________________________________ > > > Davinci-linux-open-source mailing list > > > Davinci-linux-open-source at linux.davincidsp.com > > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- U-Boot 1.2.0-gbef31061-dirty (Jun 30 2010 - 17:14:02) Bellatrix DRAM: 256 MB NAND: NAND device: Manufacturer ID: 0x20, Chip ID: 0x76 (ST Micro NAND 64MiB 3,3V 8-bit) Bad block table found at page 130976, version 0x01 Bad block table found at page 130944, version 0x01 nand_read_bbt: Bad block at 0x000b4000 nand_read_bbt: Bad block at 0x03ff8000 nand_read_bbt: Bad block at 0x03ffc000 64 MiB In: serial Out: serial Err: serial ARM Clock :- 216MHz DDR Clock :- 133MHz Hit any key to stop autoboot: 0 => pri baudrate=115200 ethaddr=00:0C:0C:A0:01:FE bootfile="uImage" ramargs=setenv bootargs mem=50M console=ttyS1,115200n8 root=/dev/ram0 rw initrd=0x82000000,40M nfsboot=tftp 0x80700000 uImage;run nfsargs; bootm 0x80700000 ramboot=tftp 0x80700000 uImage; tftp 0x82000000 ramdisk.gz;bootm 0x80700000 jffsargs=setenv bootargs mem=50M console=ttyS1,115200n8 root=/dev/mtdblock4 noinitrd rootfstype=jffs2 ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 bootdelay=2 bootargs=mem=50M console=ttyS1,115200n8 root=/dev/mtdblock4 noinitrd rootfstype=jffs2 ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 eth=00:0C:0C:A0:01:FE v4l2_video_c apture=:device=MT9P031 nfsargs=set bootargs mem=50M console=ttyS1,115200n8 root=/dev/nfs rootwait rw ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 nfsroot=192.168.1.99:/tftpboot/bellatrix_r ootfilesystem,nolock eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 filesize=ea0c9c fileaddr=82000000 netmask=255.255.255.0 ipaddr=192.168.1.90 serverip=192.168.1.99 jffsboot=nand read 0x80700000 0xc8000 0x144000; bootm 0x80700000 bootcmd=run jffsboot stdin=serial stdout=serial stderr=serial videostd=pal ver=U-Boot 1.2.0-gbef31061-dirty (Jun 30 2010 - 17:14:02) Bellatrix Environment size: 1218/16380 bytes => run nfsboot The media mode is autosense. TFTP from server 192.168.1.99; our IP address is 192.168.1.90 Filename 'uImage'. Load address: 0x80700000 Loading: LINK DOWN. LINK DOWN. LINK UP. Link mode : 100 Mb/s Full Duplex. T ################################################################# ################################################################# ################################################################# ################################################################ done Bytes transferred = 1321560 (142a58 hex) ## Booting image at 80700000 ... Image Name: Linux-2.6.10_mvl401_BELLATRIX-2. Created: 2010-07-14 14:13:08 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 1321496 Bytes = 1.3 MB Load Address: 80008000 Entry Point: 80008000 Verifying Checksum ... OK OK Starting kernel ... ?Linux version 2.6.10_mvl401_BELLATRIX-2.1.0 (dinesh at dell-desktop) (gcc version 3.4.3 (MontaVista 3.4.3-25.0.104.0600975 2006-07-06)) #2 Wed Jul 14 19:43:05 IST 2010 CPU: ARM926EJ-Sid(wb) [41069265] revision 5 (ARMv5TEJ) CPU0: D VIVT write-back cache CPU0: I cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets CPU0: D cache: 8192 bytes, associativity 4, 32 byte lines, 64 sets Machine: DaVinci DM355 Bellatrix Memory policy: ECC disabled, Data cache writeback DM0350 TCM: Mapped pa 0x00000000 to va 0xfea00000 size: 0x100000 Built 1 zonelists Kernel command line: mem=50M console=ttyS1,115200n8 root=/dev/nfs rootwait rw ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 nfsroot=192.168.1.99:/tftpboot/bellatrix_r ootfilesystem,nolock eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 PID hash table entries: 256 (order: 8, 4096 bytes) Console: colour dummy device 80x30 Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 50MB = 50MB total Memory: 47628KB available (2285K code, 559K data, 156K init) Mount-cache hash table entries: 512 (order: 0, 4096 bytes) CPU: Testing write buffer coherency: ok spawn_desched_task(00000000) desched cpu_callback 3/00000000 ksoftirqd started up. desched cpu_callback 2/00000000 desched thread 0 started up. NET: Registered protocol family 16 Registering platform device 'serial8250.0'. Parent at platform Registering platform device 'nand_davinci.0'. Parent at platform Registering platform device 'mmc.0'. Parent at platform DaVinci I2C DEBUG: 19:37:30 Jul 14 2010 Registering platform device 'i2c'. Parent at platform SCSI subsystem initialized musb_hdrc: version 2.2a/db-0.4.8 [cppi-dma] [peripheral] [debug=0] Registering platform device 'musb_hdrc'. Parent at platform musb_hdrc: USB Peripheral mode controller at c3800000 using DMA, IRQ 12 NetWinder Floating Point Emulator V0.97 (double precision) JFFS2 version 2.2. (NAND) (C) 2001-2003 Red Hat, Inc. Initializing Cryptographic API Registering platform device 'dm355fb.0'. Parent at platform Console: switching to colour frame buffer device 90x30 watchdog: TI DaVinci Watchdog Timer: timer margin 64 sec Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled Registering platform device 'serial8250'. Parent at platform ttyS0 at MMIO 0x1c20000 (irq = 40) is a 16550A ttyS1 at MMIO 0x1c20400 (irq = 41) is a 16550A ttyS2 at MMIO 0x1e06000 (irq = 14) is a 16550A io scheduler noop registered io scheduler anticipatory registered RAMDISK driver initialized: 1 RAM disks of 46080K size 1024 blocksize loop: loaded (max 8 devices) AX88796B Ethernet Driver FUNC bellatrix_ax88796b_init_module() : LINE 382 : Driver for AX88796B Non-PCI Fast Ethernet Chip Physical address of EMIF CE1 is 0x04000000 ioremaped address is 0xC3870000 FUNC ax_probe() : LINE 592 : Reading data from Page0 FUNC ax_probe() : LINE 593: Address is 0x00 . Data is 0x22 FUNC ax_probe() : LINE 594: Address is 0x02 . Data is 0x4C FUNC ax_probe() : LINE 595: Address is 0x04 . Data is 0x80 FUNC ax_probe() : LINE 596: Address is 0x06 . Data is 0x7D FUNC ax_probe() : LINE 597: Address is 0x08 . Data is 0x01 FUNC ax_probe() : LINE 598: Address is 0x0A . Data is 0x00 FUNC ax_probe() : LINE 599: Address is 0x0C . Data is 0x7F FUNC ax_probe() : LINE 600: Address is 0x0E . Data is 0x03 FUNC ax_probe() : LINE 601: Address is 0x10 . Data is 0x3C FUNC ax_probe() : LINE 602: Address is 0x12 . Data is 0x43 FUNC ax_probe() : LINE 603: Address is 0x14 . Data is 0xFF Func: ax_probe Line: 606 Interrup status reg content is 0x00000003 Func: ax_probe Line: 607 Boundary Pointer Reg is 0x0000007d ASIX AX88796B Ethernet Adapter:v1.2.0 19:37:42 Jul 14 2010 http://www.asix.com.tw FUNC ax_probe(): LINE 628: Reset card. Who knows what brain-damaged state it was left in. Func: ax_probe Line: 643 Interrup status reg content is 0x00000080 Func: ax_probe Line: 644 Boundary Pointer Reg is 0x0000004c AX88796B: MAC ADDRESS 00 88 88 77 99 66 eth0: AX88796B found at 0x4000000, using IRQ 53. i2c /dev entries driver Dallas 32B35 RTC Driver for Bellatrix RTC: Maxim DS32B35 Registeration successfull Dallas 32B35/32C35 FRAM Driver for Bellatrix Attaching Slave Address 0x50 Attaching Slave Address 0x51 Attaching Slave Address 0x52 Attaching Slave Address 0x53 Attaching Slave Address 0x54 Attaching Slave Address 0x55 Attaching Slave Address 0x56 Attaching Slave Address 0x57 DS32B35 2K FRAM Device Detected Linux video capture interface: v1.00 Registering platform device 'vpfe.1'. Parent at platform vpfe vpfe.1: DaVinci v4l2 capture driver V1.0 loaded ipipe major#: 254, minor# 0 Registering platform device 'dm355_ipipe.2'. Parent at platform ipipe driver registered af major#: 253, minor# 0 Registering platform device 'dm355_af.2'. Parent at platform aew major#: 252, minor# 0 Registering platform device 'dm355_aew.2'. Parent at platform elevator: using anticipatory as default io scheduler Registering Davinci NAND driver nand_davinci nand_davinci.0: Using 4-bit hardware ECC NAND device: Manufacturer ID: 0x20, Chip ID: 0x76 (ST Micro NAND 64MiB 3,3V 8-bit) Creating 6 MTD partitions on "nand_davinci.0": 0x00000000-0x00004000 : "UBL - User Boot Loader (RO)" 0x00004000-0x00050000 : "U-Boot (RO)" 0x00050000-0x000c8000 : "Env Parameters (RO)" 0x000c8000-0x004c8000 : "Kernel - 4MB (RW)" 0x004c8000-0x024c8000 : "Filesystem (RW)" 0x024c8000-0x04000000 : "Camera Settings (RW)" nand_davinci nand_davinci.0: hardware revision: 2.3 mmc mmc.0: Supporting 4-bit mode mmc mmc.0: Using DMA mode NET: Registered protocol family 2 IP: routing cache hash table of 512 buckets, 4Kbytes TCP: Hash tables configured (established 4096 bind 8192) NET: Registered protocol family 1 MMC cmd.resp[0] = aa orc=0 NET: Registered protocol family 17 Power Management for DaVinci initializing Enable interrupt generation from GPIO Bank 0 (GPIO0-GPIO15) Register ISR for GPIO 0, 2 & 6 Start Sync Sequence MMC cmd.resp[0] = aa orc=300000 MMC: selected 50.000MHz transfer rate MMC: selected 25.000MHz transfer rate mmcblk0: mmc0:b368 SD 1981440KiB mmcblk0: AX88796B: The media mode is autosense. IP-Config: Complete: device=eth0, addr=192.168.1.90, mask=255.255.255.0, gw=192.168.1.1, host=192.168.1.90, domain=, nis-domain=(none), bootserver=192.168.1.99, rootserver=192.168.1.99, rootpath= Looking up port of RPC 100003/2 on 192.168.1.99 Looking up port of RPC 100005/1 on 192.168.1.99 VFS: Mounted root (nfs filesystem). Freeing init memory: 156K INIT: version 2.85 booting eth0 Link mode : 100 Mb/s Full Duplex. 0 mknod: /dev/ptmx: File exists Mounting a tmpfs over /dev...done. Creating initial device nodes...done. 0 Mounting local filesystems: mount none on /dev/shm type tmpfs (rw,size=5M) mount: mount point /var/run does not exist none on /tmp type tmpfs (rw,sync) failed (96: ). Starting hotplug subsystem: pci pci [success] usb usb [success] isapnp isapnp [success] ide ide [success] input input [success] scsi scsi [success] done. Starting portmap daemon: portmap/etc/rc.d/rcS.d/S41portmap: 156: nice: not found pidof: invalid option -- x BusyBox v1.01 (2005.12.18-04:57+0000) multi-call binary No help available. /etc/rc.d/rcS.d/S41portmap: 156: cannot create /var/run/portmap.pid: Directory nonexistent failed (2: ). cmemk: no version for "struct_module" found: kernel tainted. ioremap_nocache(0x89800000, 109051904)=0xc3880000 allocated heap buffer 0xc3880000 of size 0x3204000 cmem initialized 14 pools between 0x89800000 and 0x90000000 insmod: cannot insert `dm350mmap.ko': Bad address (-1): Bad address BusyBox v1.01 (2005.12.18-04:57+0000) multi-call binary Usage: mknod [OPTIONS] NAME TYPE MAJOR MINOR Create a special file (block, character, or pipe). Options: -m create the special file using the specified mode (default a=rw) TYPEs include: b: Make a block (buffered) device. c or u: Make a character (un-buffered) device. p: Make a named pipe. MAJOR and MINOR are ignored for named pipes. insmod: cannot insert `sbull.ko': Bad address (-1): Bad address insmod: cannot insert `musb_hdrc.ko': Bad address (-1): Bad address mkdosfs 2.11 (12 Mar 2005) /dev/sbulla: No such file or directory mount: you must specify the filesystem type ln: /var/www/sdcard/mmc: File exists func StartNetwork() [line 894] : no need to take the DHCP enabling status from the GPIO. It will be taken through the NetWork Page Settings net_get_hwaddr: ioctl SIOCGIFHWADDR: No such device Error: Error on get MAC address Error: Network Init Fail UDPString=uuid:Upnp-TVEmulator-1_0-00_0016980517 Unable to handle kernel NULL pointer dereference at virtual address 00000004 pgd = c20c0000 [00000004] *pgd=80fc9031, *pte=00000000, *ppte=00000000 Internal error: Oops: 817 [#1] Modules linked in: cmemk CPU: 0 PC is at cache_alloc_refill+0x148/0x57c LR is at 0xc03c996c pc : [] lr : [] Tainted: GF sp : c0bd3ab8 ip : 00000006 fp : c0bd3aec r10: 00000050 r9 : 00000005 r8 : c0bd2000 r7 : c0bd2000 r6 : c03c9960 r5 : c30268c0 r4 : c3021900 r3 : 00000000 r2 : c03c996c r1 : c303f018 r0 : c303f000 Flags: nZCv IRQs off FIQs on Mode SVC_32 Segment user Control: 5317F Table: 820C0000 DAC: 00000015 Process encode_stream (pid: 998, stack limit = 0xc0bd21a0) Stack: (0xc0bd3ab8 to 0xc0bd4000) 3aa0: c02163f4 00000200 3ac0: c303ffb8 c30268d0 40000013 c30218e0 c0bd2000 c0bd3b28 00000005 00000050 3ae0: c0bd3b04 c0bd3af0 c0073fc0 c00741cc c0bd3b20 c0bd3c00 c0bd3b6c c0bd3b08 3b00: c006ea84 c0073f84 c303ffd8 00000000 00000000 c31d5a80 c0063da8 c0bd3b34 3b20: c0bd3b34 00000000 00000000 c31d5a80 c0063da8 c0bd3b34 c0bd3b34 c0bd3b48 3b40: c0215730 00000000 c0bd3c00 c0bd3bc0 c0bd3bc0 00001000 c0fae340 c05c6e00 3b60: c0bd3b84 c0bd3b70 c00da14c c006ea10 00000000 00000000 c0bd3bbc c0bd3b88 3b80: c00da764 c00da13c c00d8ac8 c00d87a4 c00732fc 00000000 c0bd3c00 c0bd3bc0 3ba0: 0000000e 00000001 c0fae340 c05c6e00 c0bd3bec c0bd3bc0 c00da8e0 c00da58c 3bc0: c002a120 c002a120 c0fae340 00000000 c0fae340 c0bd3c00 c202567c c0bd3ca0 3be0: c0bd3c2c c0bd3bf0 c00db2cc c00da88c 00000000 00000002 c0bd3c00 c06679a0 3c00: c002a1a0 c002a1a0 c0bd2000 00000000 c202567c 00000000 c202567c 0000000f 3c20: c0bd3c8c c0bd3c30 c0073350 c00db20c c0272658 c0bd3ca0 c0bd2000 c31d5a80 3c40: c0bd3c8c c0bd3c50 c0070130 c006fd48 00000000 00000000 00000010 c02d3af4 3c60: c0bd2000 c0bd2000 00000000 000000e5 0000000f c202567c c0bd3ca0 0000000f 3c80: c0bd3cd4 c0bd3c90 c00738d8 c0073320 0000012e 0000000f 000000d7 c0fae340 3ca0: c0bd3ca0 c0bd3ca0 c0073bd8 00000000 c0bd2000 0012edf9 00000000 000000de 3cc0: c0fae340 c202567c c0bd3d1c c0bd3cd8 c006c308 c00736f0 00000002 00000001 3ce0: c20255e0 c0fae38c c0bd3d2c c0aeb1d0 00000000 00000000 c0bd2000 c0bd2000 3d00: c0aeb1d0 000ee000 00000800 c202567c c0bd3d5c c0bd3d20 c007bfc8 c006c17c 3d20: 00000000 00000000 c002b6a0 00000001 c006fc60 00000000 c0bd2000 c0fc9bb8 3d40: c0aeb1d0 000ee000 c20c0000 c002b6a0 c0bd3da4 c0bd3d60 c007c414 c007bd44 3d60: c0fc9bb8 c20c0000 60000013 c20c0000 00000000 00000800 c0072da8 ffffffeb 3d80: c0aeb1d0 c31d5a80 c002b6a0 c002b6d0 00000805 000ee8a0 c0bd3de4 c0bd3da8 3da0: c0037e50 c007c2f8 c0bd3dcc c0bd3db8 c007d77c c0bd3e10 000000ef 00000805 3dc0: c0bd3e44 000ee8a0 c026f3fc c0bd3e10 60000013 00000009 c0bd3e0c c0bd3de8 3de0: c00380d8 c0037db0 c0bd3e4c ffffffff c0bd3e44 c0bd2000 00000000 00000000 3e00: c0bd3e6c c0bd3e10 c002f728 c00380a8 000ee8a0 00000758 00000000 00000000 3e20: 000c1000 c067f320 c0bd2000 00000000 00000000 00000000 00000009 c0bd3e6c 3e40: 00000000 c0bd3e58 c00b37a0 c0123d28 20000013 ffffffff 00000760 c00b37a0 3e60: c0bd3f2c c0bd3e70 c00b4238 c00b3764 00001812 c0bd3e80 c006ff30 c006f380 3e80: 60000093 00000003 60000013 00000000 c002b824 0000011b 00000001 c067f200 3ea0: c0bc5b20 00000000 000ee8a0 000c1000 000b8cc8 00008000 c0070130 00000004 3ec0: 001ec544 000ee8a0 00000002 c07a85c0 00000001 00008000 c05c5800 c0bd3fb0 3ee0: c067f400 00000000 00000018 00000018 00000018 00000018 c0668000 c2024ea0 3f00: 00000018 c0bd2000 c0273744 c067f400 fffffffe c00b386c c0bd3fb0 00000000 3f20: c0bd3f5c c0bd3f30 c0094ee8 c00b387c c0bd2000 c067f400 c0668000 00000000 3f40: befffe2c 0004983c c0bd2000 c0bd3fb0 c0bd3f84 c0bd3f60 c009526c c0094dd8 3f60: c0668000 befffe2c c0bd3fb0 c0668000 c00302f4 0090000b c0bd3fa4 c0bd3f88 3f80: c0034c50 c0095144 00000000 0004983c 00000000 0000000b 00000000 c0bd3fa8 3fa0: c002fb60 c0034c24 00000000 0004983c befffae0 0004983c befffe2c 0000010c 3fc0: 00000000 0004983c 00000000 0003a190 befffae0 00049644 00049820 00000000 3fe0: 401b0fb4 befffa9c 0001c470 401294c0 60000010 befffae0 ffffffff dfe5ffff Backtrace: [] (cache_alloc_refill+0x0/0x57c) from [] (kmem_cache_alloc+0x4c/0x54) [] (kmem_cache_alloc+0x0/0x54) from [] (mempool_alloc+0x84/0x19c) r5 = C0BD3C00 r4 = C0BD3B20 [] (mempool_alloc+0x0/0x19c) from [] (nfs_readdata_alloc+0x20/0x40) [] (nfs_readdata_alloc+0x0/0x40) from [] (nfs_pagein_one+0x1e8/0x300) r4 = 00000000 [] (nfs_pagein_one+0x0/0x300) from [] (nfs_pagein_list+0x64/0x98) [] (nfs_pagein_list+0x0/0x98) from [] (nfs_readpages+0xd0/0xfc) r8 = C0BD3CA0 r7 = C202567C r6 = C0BD3C00 r5 = C0FAE340 r4 = 00000000 [] (nfs_readpages+0x0/0xfc) from [] (read_pages+0x40/0x160) [] (read_pages+0x0/0x160) from [] (do_page_cache_readahead+0x1f8/0x224) [] (do_page_cache_readahead+0x0/0x224) from [] (filemap_nopage+0x19c/0x450) [] (filemap_nopage+0x0/0x450) from [] (do_no_page+0x294/0x5b4) [] (do_no_page+0x0/0x5b4) from [] (handle_mm_fault+0x12c/0x310) [] (handle_mm_fault+0x0/0x310) from [] (do_page_fault+0xb0/0x1ec) [] (do_page_fault+0x0/0x1ec) from [] (do_DataAbort+0x40/0xa4) [] (do_DataAbort+0x0/0xa4) from [] (__dabt_svc+0x48/0x60) r8 = 00000000 r7 = 00000000 r6 = C0BD2000 r5 = C0BD3E44 r4 = FFFFFFFF [] (padzero+0x0/0x50) from [] (load_elf_binary+0x9cc/0x15e0) [] (load_elf_binary+0x0/0x15e0) from [] (search_binary_handler+0x120/0x36c) [] (search_binary_handler+0x0/0x36c) from [] (do_execve+0x138/0x1f0) [] (do_execve+0x0/0x1f0) from [] (sys_execve+0x3c/0x5c) [] (sys_execve+0x0/0x5c) from [] (ret_fast_syscall+0x0/0x2c) r7 = 0000000B r6 = 00000000 r5 = 0004983C r4 = 00000000 Code: 3affffea e5903000 e5902004 e5823000 (e5832004) <6>note: encode_stream[998] exited with preempt_count 1 BUG: scheduling while atomic: encode_stream/0x40000001/998 caller is __cond_resched+0x60/0x80 CMEMK Debug: open: called. CMEMK Debug: GETVERSION ioctl received, returning 0x2000000. BUG: scheduling while atomic: encode_stream/0x00000001/998 caller is do_exit+0xd3c/0xda0 Unable to handle kernel NULL pointer dereference at virtual address 00000004 pgd = c0004000 [00000004] *pgd=00000000 Internal error: Oops: 817 [#2] Modules linked in: cmemk CPU: 0 PC is at free_block+0x60/0x124 LR is at drain_array_locked+0x88/0xa8 pc : [] lr : [] Tainted: GF sp : c03a1ed0 ip : c03a1ef8 fp : c03a1ef4 r10: c02d644c r9 : c02d645c r8 : c30268d0 r7 : 00000000 r6 : 00000004 r5 : c03c9960 r4 : c303f000 r3 : 00000000 r2 : c03c996c r1 : c30268d0 r0 : c303f200 Flags: Nzcv IRQs off FIQs on Mode SVC_32 Segment kernel Control: 5317F Table: 80018000 DAC: 00000017 Process events/0 (pid: 4, stack limit = 0xc03a01a0) Stack: (0xc03a1ed0 to 0xc03a2000) 1ec0: c02ce610 00000004 c30268c0 0000000b 1ee0: c30268d0 c03c9960 c03a1f1c c03a1ef8 c0074a70 c00748d4 00000000 00000000 1f00: c03c9960 c03a0000 c03c99d0 00000001 c03a1f54 c03a1f20 c0075880 c00749f8 1f20: c3096c00 c0371f28 c03a1f54 c02d646c c02d6468 c03a0000 00000000 c0371f20 1f40: 00000000 c0371f28 c03a1fc4 c03a1f58 c005e10c c00757e4 c0387f2c c00757d4 1f60: ffffffff ffffffff 00000001 00000000 c00483e4 00010000 00000000 c03a0000 1f80: 00000000 c036f540 c00483e4 00100100 00200200 00000000 c03a1fc4 c0371f20 1fa0: c03a0000 c0387f28 c005df08 fffffffc 00000000 00000000 c03a1ff4 c03a1fc8 1fc0: c006382c c005df18 ffffffff ffffffff 00000000 00000000 00000000 00000000 1fe0: 00000000 00000000 00000000 c03a1ff8 c004e9f0 c0063754 6e552072 38397869 Backtrace: [] (free_block+0x0/0x124) from [] (drain_array_locked+0x88/0xa8) r8 = C03C9960 r7 = C30268D0 r6 = 0000000B r5 = C30268C0 r4 = 00000004 [] (drain_array_locked+0x0/0xa8) from [] (cache_reap+0xac/0x248) r8 = 00000001 r7 = C03C99D0 r6 = C03A0000 r5 = C03C9960 r4 = 00000000 [] (cache_reap+0x0/0x248) from [] (worker_thread+0x204/0x2c0) [] (worker_thread+0x0/0x2c0) from [] (kthread+0xe8/0x11c) [] (kthread+0x0/0x11c) from [] (do_exit+0x0/0xda0) r8 = 00000000 r7 = 00000000 r6 = 00000000 r5 = 00000000 r4 = 00000000 Code: e592401c e5942004 e5943000 e5823000 (e5832004) <6>note: events/0[4] exited with preempt_count 1 BUG: scheduling while atomic: events/0/0x00000001/4 caller is do_exit+0xd3c/0xda0 -------------- next part -------------- U-Boot 1.2.0-gbef31061-dirty (Jun 30 2010 - 17:14:02) Bellatrix DRAM: 256 MB NAND: NAND device: Manufacturer ID: 0x20, Chip ID: 0x76 (ST Micro NAND 64MiB 3,3V 8-bit) Bad block table found at page 130976, version 0x01 Bad block table found at page 130944, version 0x01 nand_read_bbt: Bad block at 0x000b4000 nand_read_bbt: Bad block at 0x03ff8000 nand_read_bbt: Bad block at 0x03ffc000 64 MiB In: serial Out: serial Err: serial ARM Clock :- 216MHz DDR Clock :- 133MHz Hit any key to stop autoboot: 0 => pri baudrate=115200 ethaddr=00:0C:0C:A0:01:FE bootfile="uImage" ramargs=setenv bootargs mem=50M console=ttyS1,115200n8 root=/dev/ram0 rw initrd=0x82000000,40M nfsboot=tftp 0x80700000 uImage;run nfsargs; bootm 0x80700000 ramboot=tftp 0x80700000 uImage; tftp 0x82000000 ramdisk.gz;bootm 0x80700000 jffsargs=setenv bootargs mem=50M console=ttyS1,115200n8 root=/dev/mtdblock4 noinitrd rootfstype=jffs2 ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 bootdelay=2 bootargs=mem=50M console=ttyS1,115200n8 root=/dev/mtdblock4 noinitrd rootfstype=jffs2 ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 eth=00:0C:0C:A0:01:FE v4l2_video_c apture=:device=MT9P031 filesize=ea0c9c fileaddr=82000000 netmask=255.255.255.0 ipaddr=192.168.1.90 serverip=192.168.1.99 jffsboot=nand read 0x80700000 0xc8000 0x144000; bootm 0x80700000 bootcmd=run jffsboot stdin=serial stdout=serial stderr=serial videostd=pal ver=U-Boot 1.2.0-gbef31061-dirty (Jun 30 2010 - 17:14:02) Bellatrix nfsargs=set bootargs mem=168M console=ttyS1,115200n8 root=/dev/nfs rootwait rw ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 nfsroot=192.168.1.99:/tftpboot/bellatrix_ rootfilesystem,nolock eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 Environment size: 1219/16380 bytes => run nfsboot The media mode is autosense. TFTP from server 192.168.1.99; our IP address is 192.168.1.90 Filename 'uImage'. Load address: 0x80700000 Loading: LINK DOWN. LINK DOWN. LINK UP. Link mode : 100 Mb/s Full Duplex. ################################################################# ################################################################# ################################################################# ################################################################ done Bytes transferred = 1321560 (142a58 hex) ## Booting image at 80700000 ... Image Name: Linux-2.6.10_mvl401_BELLATRIX-2. Created: 2010-07-14 14:13:08 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 1321496 Bytes = 1.3 MB Load Address: 80008000 Entry Point: 80008000 Verifying Checksum ... OK OK Starting kernel ... ?Linux version 2.6.10_mvl401_BELLATRIX-2.1.0 (dinesh at dell-desktop) (gcc version 3.4.3 (MontaVista 3.4.3-25.0.104.0600975 2006-07-06)) #2 Wed Jul 14 19:43:05 IST 2010 CPU: ARM926EJ-Sid(wb) [41069265] revision 5 (ARMv5TEJ) CPU0: D VIVT write-back cache CPU0: I cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets CPU0: D cache: 8192 bytes, associativity 4, 32 byte lines, 64 sets Machine: DaVinci DM355 Bellatrix Memory policy: ECC disabled, Data cache writeback DM0350 TCM: Mapped pa 0x00000000 to va 0xfea00000 size: 0x100000 Built 1 zonelists Kernel command line: mem=168M console=ttyS1,115200n8 root=/dev/nfs rootwait rw ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 nfsroot=192.168.1.99:/tftpboot/bellatrix_ rootfilesystem,nolock eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 PID hash table entries: 1024 (order: 10, 16384 bytes) Console: colour dummy device 80x30 Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) Memory: 168MB = 168MB total Memory: 167296KB available (2285K code, 559K data, 156K init) Mount-cache hash table entries: 512 (order: 0, 4096 bytes) CPU: Testing write buffer coherency: ok spawn_desched_task(00000000) desched cpu_callback 3/00000000 ksoftirqd started up. desched cpu_callback 2/00000000 desched thread 0 started up. NET: Registered protocol family 16 Registering platform device 'serial8250.0'. Parent at platform Registering platform device 'nand_davinci.0'. Parent at platform Registering platform device 'mmc.0'. Parent at platform DaVinci I2C DEBUG: 19:37:30 Jul 14 2010 Registering platform device 'i2c'. Parent at platform SCSI subsystem initialized musb_hdrc: version 2.2a/db-0.4.8 [cppi-dma] [peripheral] [debug=0] Registering platform device 'musb_hdrc'. Parent at platform musb_hdrc: USB Peripheral mode controller at cb000000 using DMA, IRQ 12 NetWinder Floating Point Emulator V0.97 (double precision) JFFS2 version 2.2. (NAND) (C) 2001-2003 Red Hat, Inc. Initializing Cryptographic API Registering platform device 'dm355fb.0'. Parent at platform Console: switching to colour frame buffer device 90x30 watchdog: TI DaVinci Watchdog Timer: timer margin 64 sec Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled Registering platform device 'serial8250'. Parent at platform ttyS0 at MMIO 0x1c20000 (irq = 40) is a 16550A ttyS1 at MMIO 0x1c20400 (irq = 41) is a 16550A ttyS2 at MMIO 0x1e06000 (irq = 14) is a 16550A io scheduler noop registered io scheduler anticipatory registered RAMDISK driver initialized: 1 RAM disks of 46080K size 1024 blocksize loop: loaded (max 8 devices) AX88796B Ethernet Driver FUNC bellatrix_ax88796b_init_module() : LINE 382 : Driver for AX88796B Non-PCI Fast Ethernet Chip Physical address of EMIF CE1 is 0x04000000 ioremaped address is 0xCB070000 FUNC ax_probe() : LINE 592 : Reading data from Page0 FUNC ax_probe() : LINE 593: Address is 0x00 . Data is 0x22 FUNC ax_probe() : LINE 594: Address is 0x02 . Data is 0x4C FUNC ax_probe() : LINE 595: Address is 0x04 . Data is 0x80 FUNC ax_probe() : LINE 596: Address is 0x06 . Data is 0x7D FUNC ax_probe() : LINE 597: Address is 0x08 . Data is 0x01 FUNC ax_probe() : LINE 598: Address is 0x0A . Data is 0x00 FUNC ax_probe() : LINE 599: Address is 0x0C . Data is 0x7F FUNC ax_probe() : LINE 600: Address is 0x0E . Data is 0x03 FUNC ax_probe() : LINE 601: Address is 0x10 . Data is 0x3C FUNC ax_probe() : LINE 602: Address is 0x12 . Data is 0x43 FUNC ax_probe() : LINE 603: Address is 0x14 . Data is 0xFF Func: ax_probe Line: 606 Interrup status reg content is 0x00000003 Func: ax_probe Line: 607 Boundary Pointer Reg is 0x0000007d ASIX AX88796B Ethernet Adapter:v1.2.0 19:37:42 Jul 14 2010 http://www.asix.com.tw FUNC ax_probe(): LINE 628: Reset card. Who knows what brain-damaged state it was left in. Func: ax_probe Line: 643 Interrup status reg content is 0x00000080 Func: ax_probe Line: 644 Boundary Pointer Reg is 0x0000004c AX88796B: MAC ADDRESS 00 88 88 77 99 66 eth0: AX88796B found at 0x4000000, using IRQ 53. i2c /dev entries driver Dallas 32B35 RTC Driver for Bellatrix RTC: Maxim DS32B35 Registeration successfull Dallas 32B35/32C35 FRAM Driver for Bellatrix Attaching Slave Address 0x50 Attaching Slave Address 0x51 Attaching Slave Address 0x52 Attaching Slave Address 0x53 Attaching Slave Address 0x54 Attaching Slave Address 0x55 Attaching Slave Address 0x56 Attaching Slave Address 0x57 DS32B35 2K FRAM Device Detected Linux video capture interface: v1.00 Registering platform device 'vpfe.1'. Parent at platform vpfe vpfe.1: DaVinci v4l2 capture driver V1.0 loaded ipipe major#: 254, minor# 0 Registering platform device 'dm355_ipipe.2'. Parent at platform ipipe driver registered af major#: 253, minor# 0 Registering platform device 'dm355_af.2'. Parent at platform aew major#: 252, minor# 0 Registering platform device 'dm355_aew.2'. Parent at platform elevator: using anticipatory as default io scheduler Registering Davinci NAND driver nand_davinci nand_davinci.0: Using 4-bit hardware ECC NAND device: Manufacturer ID: 0x20, Chip ID: 0x76 (ST Micro NAND 64MiB 3,3V 8-bit) Creating 6 MTD partitions on "nand_davinci.0": 0x00000000-0x00004000 : "UBL - User Boot Loader (RO)" 0x00004000-0x00050000 : "U-Boot (RO)" 0x00050000-0x000c8000 : "Env Parameters (RO)" 0x000c8000-0x004c8000 : "Kernel - 4MB (RW)" 0x004c8000-0x024c8000 : "Filesystem (RW)" 0x024c8000-0x04000000 : "Camera Settings (RW)" nand_davinci nand_davinci.0: hardware revision: 2.3 mmc mmc.0: Supporting 4-bit mode mmc mmc.0: Using DMA mode NET: Registered protocol family 2 MMC cmd.resp[0] = aa orc=0 IP: routing cache hash table of 1024 buckets, 8Kbytes TCP: Hash tables configured (established 16384 bind 32768) NET: Registered protocol family 1 NET: Registered protocol family 17 Power Management for DaVinci initializing Enable interrupt generation from GPIO Bank 0 (GPIO0-GPIO15) Register ISR for GPIO 0, 2 & 6 Start Sync Sequence MMC cmd.resp[0] = aa orc=300000 MMC: selected 50.000MHz transfer rate MMC: selected 25.000MHz transfer rate mmcblk0: mmc0:b368 SD 1981440KiB mmcblk0: AX88796B: The media mode is autosense. IP-Config: Complete: device=eth0, addr=192.168.1.90, mask=255.255.255.0, gw=192.168.1.1, host=192.168.1.90, domain=, nis-domain=(none), bootserver=192.168.1.99, rootserver=192.168.1.99, rootpath= Looking up port of RPC 100003/2 on 192.168.1.99 Looking up port of RPC 100005/1 on 192.168.1.99 VFS: Mounted root (nfs filesystem). Freeing init memory: 156K INIT: version 2.85 booting eth0 Link mode : 100 Mb/s Full Duplex. 0 mknod: /dev/ptmx: File exists Mounting a tmpfs over /dev...done. Creating initial device nodes...done. 0 Mounting local filesystems: mount none on /dev/shm type tmpfs (rw,size=5M) mount: mount point /var/run does not exist none on /tmp type tmpfs (rw,sync) failed (96: ). Starting hotplug subsystem: pci pci [success] usb usb [success] isapnp isapnp [success] ide ide [success] input input [success] scsi scsi [success] done. Starting portmap daemon: portmap/etc/rc.d/rcS.d/S41portmap: 156: nice: not found pidof: invalid option -- x BusyBox v1.01 (2005.12.18-04:57+0000) multi-call binary No help available. /etc/rc.d/rcS.d/S41portmap: 156: cannot create /var/run/portmap.pid: Directory nonexistent failed (2: ). cmemk: no version for "struct_module" found: kernel tainted. ioremap_nocache(0x8a800000, 92274688)=0xcb080000 allocated heap buffer 0xcb080000 of size 0x2204000 cmem initialized 14 pools between 0x8a800000 and 0x90000000 sbulla: unknown partition table musb_hdrc: version 2.2a/db-0.4.8 [cppi-dma] [peripheral] [debug=0] Registering platform device 'musb_hdrc'. Parent at platform kobject_register failed for musb_hdrc (-17) insmod: cannot insert `musb_hdrc.ko': File exists (-1): File exists mkdosfs 2.11 (12 Mar 2005) /dev/sbulla has 4 heads and 16 sectors per track, logical sector size is 512, using 0xf8 media descriptor, with 1024 sectors; file system has 2 12-bit FATs and 4 sectors per cluster. FAT size is 1 sector, and provides 247 clusters. Root directory contains 512 slots. Volume ID is 00000015, no volume label. ln: /var/www/sdcard/mmc: File exists modprobe: FATAL: Could not load /lib/modules/2.6.10_mvl401_BELLATRIX-2.1.0/modules.dep: No such file or directory INIT: Entering runlevel: 3 UDPString=uuid:Upnp-TVEmulator-1_0-00_0008421557 func StartNetwork() [line 894] : no need to take the DHCP enabling status from the GPIO. It will be taken through the NetWork Page Settings Upnp port is 0 UPnP Initialized OK ip=192.168.1.90, port=49152 desc_doc_url = http://192.168.1.90/tvdevicedesc.xml UpnpRegisterRootDevice failure. error code = -204 device advertisement failure. killall: dhcpcd: no process killed rm: cannot remove `/var/run/dhcpcd-eth0.pid': No such file or directory net_search_gateway:eth0, 1A8C0, 0, 1 net_search_gateway:eth0, 0, 101A8C0, 3 dns=192.168.1.1 Starting internet superserver: inetd. pgd = c9438000 [40ad1000] *pgd=896e0031, *pte=00000000, *ppte=00000000 pgd = c9438000 [40ad2000] *pgd=896e0031, *pte=00000000, *ppte=00000000 pgd = c9438000 [40ad3000] *pgd=896e0031, *pte=00000000, *ppte=00000000 pgd = c9438000 [40ae2000] *pgd=896e0031, *pte=00000000, *ppte=00000000 pgd = c9438000 [40ae3000] *pgd=896e0031, *pte=00000000, *ppte=00000000 pgd = c9438000 [40ae4000] *pgd=896e0031, *pte=00000000, *ppte=00000000 pgd = c9438000 [40ae5000] *pgd=896e0031, *pte=00000000, *ppte=00000000 pgd = c9438000 [4434b000] *pgd=89709031, *pte=00000000, *ppte=00000000 pgd = c9408000 [43a07000] *pgd=894f7031, *pte=00000000, *ppte=00000000 pgd = c9438000 [48380000] *pgd=89784031, *pte=00000000, *ppte=00000000 pgd = c9438000 [48383000] *pgd=89784031, *pte=00000000, *ppte=00000000 pgd = c9438000 [48384000] *pgd=89784031, *pte=00000000, *ppte=00000000 pgd = c9438000 [48708000] *pgd=89787031, *pte=00000000, *ppte=00000000 pgd = c9438000 [48717000] *pgd=89787031, *pte=00000000, *ppte=00000000 pgd = c9438000 [48718000] *pgd=89787031, *pte=00000000, *ppte=00000000 pgd = c9438000 [487c1000] *pgd=89787031, *pte=00000000, *ppte=00000000 pgd = c9438000 [487d0000] *pgd=89787031, *pte=00000000, *ppte=00000000 pgd = c9438000 [48bee000] *pgd=89789031, *pte=00000000, *ppte=00000000 pgd = c9438000 [4916e000] *pgd=8978f031, *pte=00000000, *ppte=00000000 pgd = c9438000 [4917d000] *pgd=8978f031, *pte=00000000, *ppte=00000000 pgd = c9438000 [466a7000] *pgd=894e1031, *pte=00000000, *ppte=00000000 pgd = c9438000 [4918c000] *pgd=8978f031, *pte=00000000, *ppte=00000000 pgd = c9438000 [49235000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [49236000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [49237000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [492e8000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [492e9000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [492ea000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [492eb000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [492fa000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [492fb000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [492fc000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [492fd000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [492fe000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [493c9000] *pgd=89790031, *pte=00000000, *ppte=00000000 pgd = c9438000 [49494000] *pgd=89792031, *pte=00000000, *ppte=00000000 pgd = c9438000 [4955f000] *pgd=89792031, *pte=00000000, *ppte=00000000 From david.kondrad at legrand.us Wed Jul 14 12:16:18 2010 From: david.kondrad at legrand.us (david.kondrad at legrand.us) Date: Wed, 14 Jul 2010 13:16:18 -0400 Subject: [PATCH 4/4] ASoC: DaVinci: pcm, fix underrun by using sram In-Reply-To: Message-ID: Troy, Sekhar: > On Wed, Jul 14, 2010 at 00:31:00, troy.kisky at boundarydevices.com wrote: > > > > On Tue 13/07/10 6:00 AM , "Nori, Sekhar" nsekhar at ti.com sent: > > > > [...] > > > > > +static int request_ping_pong(struct snd_pcm_substream > > *substream, > > > + struct davinci_runtime_data *prtd, > > > + struct snd_dma_buffer *iram_dma) > > > +{ > > > + dma_addr_t asp_src_ping; > > > + dma_addr_t asp_dst_ping; > > > + int link; > > > + struct davinci_pcm_dma_params *dma_data = prtd->params; > > > + > > > + /* Request ram master channel */ > > > + link = prtd->ram_channel = > > edma_alloc_channel(EDMA_CHANNEL_ANY, > > > + davinci_pcm_dma_irq, substream, > > > + EVENTQ_1); > > > > What is the reason for choosing EVENTQ_1 for this channel? > > EVENTQ_0 > > is already being used for ASP channel. > > > > I imagine it will be much easier to tune the queue usage in the > > system > > if all of audio data was using the same queue. > > > > I am working on a patch which lets platform specify the event > > queues > > for audio DMA. I am not sure if I really need to make a > > provision for > > two different queues to be specified - that's why I ask. > > > > Thanks, > > Sekhar > > > > The reason is so that the IRAM data can be fetched and used > > while > > > > EVENTQ_1 fetches the next buffer of data from sdram into IRAM. > > Thanks for the explanation. That sounds reasonable. > > Just curious as to whether you actually faced an issue > when using the same event queue for both transfers? > > I just tested this on DM365 with both transfers on EDMAQ_0 > with 16K each of capture and playback IRAM at 48KHz > sampling rate and did not find any issue. > > Anyway it makes sense to make provision for platform to choose > different queues for both transfers so will implement my patch > that way. I've also implemented a custom DSP-based audio driver (for DM6441) in the same fashion (Q0 for SRAM->ASP, Q1 from DDR->SRAM) and it works very well using both queues. When I used the same queue for both transfers we had many missed DMA events when the system was doing anything other than sitting idle (i.e. running a video codec/ application software / network transfers). I'm not sure if the DM365 has an errata on IRAM like DM644x, but we actually used ARM ram for our buffers since there existed a possibility that DMA to/from IRAM would cause a priority inversion (if i remember correctly) in the DMA controller. Regards, Dave -- David Kondrad Software Design Engineer Home Systems Division Legrand, North America 717.546.5442 david.kondrad at legrand.us www.legrand.us/onq This email, and any document attached hereto, may contain confidential and/or privileged information. If you are not the intended recipient (or have received this email in error) please notify the sender immediately and destroy this email. Any unauthorized, direct or indirect, copying, disclosure, distribution or other use of the material or parts thereof is strictly forbidden. From troy.kisky at boundarydevices.com Wed Jul 14 12:46:59 2010 From: troy.kisky at boundarydevices.com (Troy Kisky) Date: Wed, 14 Jul 2010 10:46:59 -0700 Subject: [PATCH 4/4] ASoC: DaVinci: pcm, fix underrun by using sram In-Reply-To: References: <51883.1279047660@boundarydevices.com> Message-ID: <4C3DF813.4050908@boundarydevices.com> Nori, Sekhar wrote: > On Wed, Jul 14, 2010 at 00:31:00, troy.kisky at boundarydevices.com wrote: >> On Tue 13/07/10 6:00 AM , "Nori, Sekhar" nsekhar at ti.com sent: >> > >> The reason is so that the IRAM data can be fetched and used >> while >> >> EVENTQ_1 fetches the next buffer of data from sdram into IRAM. > > Thanks for the explanation. That sounds reasonable. > > Just curious as to whether you actually faced an issue > when using the same event queue for both transfers? > > I just tested this on DM365 with both transfers on EDMAQ_0 > with 16K each of capture and playback IRAM at 48KHz > sampling rate and did not find any issue. > > Anyway it makes sense to make provision for platform to choose > different queues for both transfers so will implement my patch > that way. > > Thanks, > Sekhar > IIRC, the DM365 has a fifo, the 6443/6446 doesn't. So, the 365 doesn't need to use IRAM and shouldn't use it. Test using the same controller on a board without a fifo. Troy From sudhakar.raj at ti.com Thu Jul 15 00:10:41 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Thu, 15 Jul 2010 10:40:41 +0530 Subject: [PATCH v2] mtd-nand: davinci: correct 4-bit error correction Message-ID: <1279170641-24494-1-git-send-email-sudhakar.raj@ti.com> On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the 4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and before waiting for the NAND Flash status register to be equal to 1, 2 or 3, we have to wait till the ECC HW goes to correction state. Without this wait, ECC correction calculations will not be proper. This has been tested on DA830/OMAP-L137, DA850/OMAP-L138, DM355 and DM365 EVMs. Signed-off-by: Sudhakar Rajashekhara Acked-by: Sneha Narnakaje Cc: David Woodhouse Signed-off-by: Andrew Morton --- Since v1: a. Timeout has been changed from 100 msec to 100 usec. b. Comment above the do, while loop was not matching the code. This has been corrected. c. Initialization of 'timeo' variable has been moved down. d. It was observed that, while calculating the time in the loop, if there is a context switch between setting the 4BITECC_ADD_CALC_START bit and reading of ECC_STATE field, then the loop will not come out until the timeout happens. To prevent the context switch, spin_lock_irqsave and spin_unlock_irqrestore are used. drivers/mtd/nand/davinci_nand.c | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 9c9d893..1e2657c 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -311,7 +311,11 @@ static int nand_davinci_correct_4bit(struct mtd_info *mtd, unsigned short ecc10[8]; unsigned short *ecc16; u32 syndrome[4]; + u32 ecc_state; unsigned num_errors, corrected; + unsigned long timeo; + DEFINE_SPINLOCK(ecc_spin_lock); + unsigned long flags; /* All bytes 0xff? It's an erased page; ignore its ECC. */ for (i = 0; i < 10; i++) { @@ -355,12 +359,30 @@ compare: */ davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET); + spin_lock_irqsave(&ecc_spin_lock, flags); /* Start address calculation, and wait for it to complete. * We _could_ start reading more data while this is working, * to speed up the overall page read. */ davinci_nand_writel(info, NANDFCR_OFFSET, davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13)); + + /* + * ECC_STATE field reads 0x3 (Error correction complete) immediately + * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately + * begin trying to poll for the state, you may fall right out of your + * loop without any of the correction calculations having taken place. + * The recommendation from the hardware team is to wait till ECC_STATE + * reads >= 4, which means ECC HW has entered correction state. + */ + timeo = jiffies + usecs_to_jiffies(100); + do { + ecc_state = (davinci_nand_readl(info, + NANDFSR_OFFSET) >> 8) & 0x0f; + cpu_relax(); + } while ((ecc_state < 4) && time_before(jiffies, timeo)); + spin_unlock_irqrestore(&ecc_spin_lock, flags); + for (;;) { u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET); -- 1.5.6 From rohan_javed at yahoo.co.uk Thu Jul 15 01:00:17 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Thu, 15 Jul 2010 06:00:17 +0000 (GMT) Subject: Problem with UBIFS Message-ID: <972456.15235.qm@web24107.mail.ird.yahoo.com> I have used UBIFS as i have 256MB of FLASH but i have to save my changes to the flash when i do mkdir 123 the directory is created but when i reset the board the directory isn't there.however when i reset board after few seconds then the directory is dere after reset can anyone tell me what is the resaon i read UBIFS it says that it has write back support which makes its very fast ascompared to other but i want the data to be there i have to do fileoperation and when my data is changed and written to filei want it to me there after i reset the system i want that write to happen immediately. Regard's RT -------------- next part -------------- An HTML attachment was scrubbed... URL: From windlazio at gmail.com Thu Jul 15 01:04:25 2010 From: windlazio at gmail.com (Han Jun-peng) Date: Thu, 15 Jul 2010 14:04:25 +0800 Subject: the Lens Distortion module of DM36x Message-ID: Hi,all Is there any documents about the lens distortion of DM36x,I want to use DM368 to interface a fisheye lens, so I must use the lens distortion module to calibrate the image. Any tips or help will be appreciated! Thank you! btw:How can I perform AE and AWB opration on DM368,there is not a 3A module on the device! -------------- next part -------------- An HTML attachment was scrubbed... URL: From davide.bonfanti at bticino.it Thu Jul 15 01:09:04 2010 From: davide.bonfanti at bticino.it (davide.bonfanti at bticino.it) Date: Thu, 15 Jul 2010 08:09:04 +0200 Subject: Rif: Re: [PATCH] Asoc Davinci Voicecodec: Added support based on copy_from_user instead of DMA In-Reply-To: <20100714144414.GE31073@rakim.wolfsonmicro.main> References: <1279117691-5467-1-git-send-email-lamiaposta71@gmail.com>, <20100714144414.GE31073@rakim.wolfsonmicro.main> Message-ID: >Per:?Raffaele?Recalcati? >Da:?Mark?Brown? >Data:?14/07/2010?16.44 >Cc:?davinci-linux-open-source at linux.davincidsp.com,?Davide?Bonfanti >,?Raffaele?Recalcati >,?Chaithrika?U?S?,?Liam >Girdwood?,?Troy?Kisky?, >Barry?Song?<21cnbao at gmail.com>,?Peter?Ujfalusi?,?Eero >Nurkkala?,?alsa-devel at alsa-project.org >Oggetto:?Re:?[PATCH]?Asoc?Davinci?Voicecodec:?Added?support?based?on >copy_from_user?instead?of?DMA > >On?Wed,?Jul?14,?2010?at?04:28:10PM?+0200,?Raffaele?Recalcati?wrote: >>?From:?Davide?Bonfanti? > >>?????Since?DM365?has?the?same?DMA?event?for?McBSP?and?Voicecodec?this?two >>?????peripherals?cannot?be?used?at?the?same?time. > >Please?try?to?format?your?patches?as?documented?in?SubmittingPatches?- >you?don't?want?all?this?indentation?you're?introducing?in?the?start?of >the?changelog.??There's?also?other?stuff?with?regard?to?coding?style?and >so?on?that?it'd?be?useful?for?you?to?look?at. > Ok >>?????This?driver?implements?Voicecodec?without?the?use?of?a?DMA?but?with >>?????a?copy_from_user. > >Why?is?this?specific?to?the?voice?CODEC???Shouldn't?this?be?generally >usable,?and?wouldn't?it?be?better?if?the?DMA?driver?were?able?to?do?some >automatic?fallback?here?so?that?in?cases?where?DMA?can?be?used?it?will >be? The DMA can be dynamically allocated and I need to keep it free for I2S because it needs more throughput. I don't think it can be a good idea to copy 44KHz stereo data using a copy_from_user. What's your opinion about? > >I?had?thought?from?the?discussion?on?original?submission?that?the?two >devices?were?mutually?exclusive?for?other?reasons?anyway. The problem is that the event source for DMA is the same and can be configured to work for one peripheral or for the other. I need both peripheral working at the same time (not as an alternative one to the other) > >>?+/*?Timer?register?offsets?*/ >>?+#define?PID12???????????????????0x00 >>?+#define?TIM12???????????????????0x10 >>?+#define?TIM34???????????????????0x14 >>?+#define?PRD12???????????????????0x18 >>?+#define?PRD34???????????????????0x1c >>?+#define?TCR?????????????????????0x20 >>?+#define?TGCR????????????????????0x24 > >This?timer?stuff?all?looks?rather?like?it?should?be?in?whatever?other >code?manages?the?timers?-?as?it?stands?it'll?get?into?a?fight?with >anything?else?trying?to?use?them.??I'd?expect?something?like?this?to?use >hrtimers?to?get?high?resolution?time?rather?than?banging?the?timer >hardware?directly. > I'll try to do it >>?+int?pointer_sub; >>?+u16?local_buffer[BUF_SIZE/2]; > >Should?BUF_SIZE?not?be?a?configuration?option,?or?dynamically?configured >at?runtime? > You're right >>?+/* >>?+?*???? ppcm?=?(substream->stream?==?SNDRV_PCM_STREAM_PLAYBACK)?? >>?+?*???? ???? &pcm_hardware_playback?:?&pcm_hardware_capture; >>?+?*/ > >Remove?this?if?it's?not?used. > I've implemented only voice output using copy_from_user since I don't need input. This is an anchor to attach also input. Can I put a TODO or shall I remove everything? >>?+???? __raw_writel(0x0,?IO_ADDRESS(0x01D0C008)); >>?+???? __raw_writel(0x7400,?IO_ADDRESS(0x01D0C004)); > >This?could?do?with?being?substantially?clearer...??There's?quite?a?few >other?magic?numbers?in?the?code?which?need?fixing. You are right. I have to admit I sent the patch in order to understand if there is some interest on it... I will fix > >>?+static?int?davinci_pcm_close(struct?snd_pcm_substream?*substream) >>?+{ >>?+???? struct?snd_pcm_runtime?*runtime?=?substream->runtime; >>?+???? struct?clk?*clk; >>?+ >>?+???? clk?=?clk_get(NULL,?TIMER); >>?+???? if?(!IS_ERR(clk)) >>?+???? ???? clk_disable(clk); > >As?with?your?previous?patch?you're?going?to?be?leaking?clocks?all?over?- >you?should?be?balancing?your?clk_get()?with?clk_put(). > ops... >>?+struct?snd_soc_platform?davinci_soc_platform_copy?=?{ >>?+???? .name?=???? ???? "davinci-audio-copy", >>?+???? .pcm_ops?=???? &davinci_pcm_ops, >>?+???? .pcm_new?=???? davinci_pcm_new, >>?+};?EXPORT_SYMBOL_GPL(davinci_soc_platform_copy); > >Fix?your?formatting?here. > checkpatch didn't help me. >>?+++?b/sound/soc/soc-core.c >>?@@?-801,7?+801,7?@@?static?int?soc_pcm_trigger(struct?snd_pcm_substream >*substream,?int?cmd) >>?????? } >>?????? return?0; >>??} >>?- >>?+#if?0 >>??/*?ASoC?PCM?operations?*/ >>??static?struct?snd_pcm_ops?soc_pcm_ops?=?{ >>?????? .open???? ???? =?soc_pcm_open, >>?@@?-811,7?+811,7?@@?static?struct?snd_pcm_ops?soc_pcm_ops?=?{ >>?????? .prepare???? =?soc_pcm_prepare, >>?????? .trigger???? =?soc_pcm_trigger, >>??}; >>?- >>?+#endif > >Um....???I'm?not?entirely?sure?what?this?and?the?rest?of?the?changes?in >the?file?are?supposed?to?do?but?they?weren't?mentioned?at?all?in?the >changelog.??If?this?is?needed?it?should?be?a?separate?change?with?a >proper?changelog?explaining?what's?going?on. Of course I have to split the commit. here the problem is that soc_pcm_ops was statically instantiated so if one call more than one time soc_new_pcm the operations functions are overwritten. Ce message, ainsi que tous les fichiers joints ? ce message, peuvent contenir des informations sensibles et/ ou confidentielles ne devant pas ?tre divulgu?es. Si vous n'?tes pas le destinataire de ce message (ou que vous recevez ce message par erreur), nous vous remercions de le notifier imm?diatement ? son exp?diteur, et de d?truire ce message. Toute copie, divulgation, modification, utilisation ou diffusion, non autoris?e, directe ou indirecte, de tout ou partie de ce message, est strictement interdite. This e-mail, and any document attached hereby, may contain confidential and/or privileged information. If you are not the intended recipient (or have received this e-mail in error) please notify the sender immediately and destroy this e-mail. Any unauthorized, direct or indirect, copying, disclosure, distribution or other use of the material or parts thereof is strictly forbidden. From rohan_javed at yahoo.co.uk Thu Jul 15 02:32:48 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Thu, 15 Jul 2010 07:32:48 +0000 (GMT) Subject: Problem with UBIFS Message-ID: <79382.65490.qm@web24107.mail.ird.yahoo.com> Using sync option solves the problem but it is not recomended --- On Thu, 15/7/10, rohan tabish wrote: From: rohan tabish Subject: Problem with UBIFS To: davinci-linux-open-source at linux.davincidsp.com Date: Thursday, 15 July, 2010, 11:00 I have used UBIFS as i have 256MB of FLASH but i have to save my changes to the flash when i do mkdir 123 the directory is created but when i reset the board the directory isn't there.however when i reset board after few seconds then the directory is dere after reset can anyone tell me what is the resaon i read UBIFS it says that it has write back support which makes its very fast ascompared to other but i want the data to be there i have to do fileoperation and when my data is changed and written to filei want it to me there after i reset the system i want that write to happen immediately. Regard's RT -----Inline Attachment Follows----- _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -------------- next part -------------- An HTML attachment was scrubbed... URL: From a.auer at zydacron.com Thu Jul 15 02:47:43 2010 From: a.auer at zydacron.com (Andreas Auer) Date: Thu, 15 Jul 2010 09:47:43 +0200 Subject: [DM6446] How to figure out the reset source Message-ID: Hi, I'm searching for a possibility to figure out which reset source caused a system reset! Is there a way to do that? I don't know if there is a register or something like that which stores the reset condition. I would like to distinguish between a watchdog reset and a normal "reboot"! Is there any way to do that?? Or is it possible to trigger some action in case of a watchdog timeout? Thanks, Andreas From broonie at opensource.wolfsonmicro.com Thu Jul 15 04:21:39 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Thu, 15 Jul 2010 10:21:39 +0100 Subject: Rif: Re: [PATCH] Asoc Davinci Voicecodec: Added support based on copy_from_user instead of DMA In-Reply-To: References: <1279117691-5467-1-git-send-email-lamiaposta71@gmail.com> <20100714144414.GE31073@rakim.wolfsonmicro.main> Message-ID: <20100715092138.GD23529@rakim.wolfsonmicro.main> On Thu, Jul 15, 2010 at 08:09:04AM +0200, davide.bonfanti at bticino.it wrote: > >Per:?Raffaele?Recalcati? > >Da:?Mark?Brown? > >Data:?14/07/2010?16.44 You might want to look at your MUA configuration here - it's sending stuff with broken line endings which make things hard to read. > >>?????This?driver?implements?Voicecodec?without?the?use?of?a?DMA?but?with > >>?????a?copy_from_user. > >Why?is?this?specific?to?the?voice?CODEC???Shouldn't?this?be?generally > >usable,?and?wouldn't?it?be?better?if?the?DMA?driver?were?able?to?do?some > >automatic?fallback?here?so?that?in?cases?where?DMA?can?be?used?it?will > >be? > The DMA can be dynamically allocated and I need to keep it free for I2S > because it needs more throughput. I don't think it can be a good idea to > copy 44KHz stereo data using a copy_from_user. What's your opinion about? It's not ideal, no, but it can work and obviously people might choose to play 8kHz out of either interface. It could also come in handy if the CPUs get a new DMA controller while waiting for support for it. > >>?+/* > >>?+?*???? ppcm?=?(substream->stream?==?SNDRV_PCM_STREAM_PLAYBACK)?? > >>?+?*???? ???? &pcm_hardware_playback?:?&pcm_hardware_capture; > >>?+?*/ > >Remove?this?if?it's?not?used. > I've implemented only voice output using copy_from_user since I don't need > input. This is an anchor to attach also input. Can I put a TODO or shall I > remove everything? Remove it until it's implemented. > >>?+struct?snd_soc_platform?davinci_soc_platform_copy?=?{ > >>?+???? .name?=???? ???? "davinci-audio-copy", > >>?+???? .pcm_ops?=???? &davinci_pcm_ops, > >>?+???? .pcm_new?=???? davinci_pcm_new, > >>?+};?EXPORT_SYMBOL_GPL(davinci_soc_platform_copy); > > > >Fix?your?formatting?here. > checkpatch didn't help me. The export should be on a line by itself. > >Um....???I'm?not?entirely?sure?what?this?and?the?rest?of?the?changes?in > >the?file?are?supposed?to?do?but?they?weren't?mentioned?at?all?in?the > >changelog.??If?this?is?needed?it?should?be?a?separate?change?with?a > >proper?changelog?explaining?what's?going?on. > Of course I have to split the commit. here the problem is that soc_pcm_ops > was statically instantiated so if one call more than one time soc_new_pcm > the operations functions are overwritten. You're looking for the multi-CODEC work, due to be integrated very soon. From Jon.Povey at racelogic.co.uk Thu Jul 15 06:01:19 2010 From: Jon.Povey at racelogic.co.uk (Jon Povey) Date: Thu, 15 Jul 2010 12:01:19 +0100 Subject: [PATCH v2] mtd-nand: davinci: correct 4-bit error correction In-Reply-To: <1279170641-24494-1-git-send-email-sudhakar.raj@ti.com> Message-ID: <70E876B0EA86DD4BAF101844BC814DFE0903CBD539@Cloud.RL.local> Sudhakar Rajashekhara wrote: > On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the > 4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and > before waiting for the NAND Flash status register to be equal to 1, 2 > or 3, we have to wait till the ECC HW goes to correction state. > Without this wait, ECC correction calculations will not be proper. > > This has been tested on DA830/OMAP-L137, DA850/OMAP-L138, DM355 and > DM365 EVMs. > > Signed-off-by: Sudhakar Rajashekhara > Acked-by: Sneha Narnakaje > Cc: David Woodhouse > Signed-off-by: Andrew Morton Have these people acked and signed off this new version of the patch? > Since v1: > a. Timeout has been changed from 100 msec to 100 usec. > b. Comment above the do, while loop was not matching the code. > This has been corrected. > c. Initialization of 'timeo' variable has been moved down. > d. It was observed that, while calculating the time in the loop, > if there is a context switch between setting the > 4BITECC_ADD_CALC_START bit and reading of ECC_STATE field, then > the loop will not come out until the timeout happens. To prevent > the context switch, spin_lock_irqsave and spin_unlock_irqrestore > are used. d. means interrupts are disabled for up to 100us while waiting for ECC. Doesn't sound good if it can be avoided. How about instead of spinlock, set timeo first time inside the loop? >From this: + timeo = jiffies + usecs_to_jiffies(100); + do { + ecc_state = (davinci_nand_readl(info, + NANDFSR_OFFSET) >> 8) & 0x0f; + cpu_relax(); + } while ((ecc_state < 4) && time_before(jiffies, timeo)); + spin_unlock_irqrestore(&ecc_spin_lock, flags); To something like: + timeo = 0; + do { + ecc_state = (davinci_nand_readl(info, + NANDFSR_OFFSET) >> 8) & 0x0f; + if (!timeo) + timeo = jiffies + usecs_to_jiffies(100); + cpu_relax(); + } while ((ecc_state < 4) && time_before(jiffies, timeo)); Sorry if my mailer has messed up the formatting. Hopefuly readable. -- Jon Povey jon.povey at racelogic.co.uk Racelogic is a limited company registered in England. Registered number 2743719 . Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB . 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Please note that Racelogic reserves the right to monitor e-mail communications passing through its network From sudhakar.raj at ti.com Thu Jul 15 06:41:32 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Thu, 15 Jul 2010 17:11:32 +0530 Subject: [PATCH v2] mtd-nand: davinci: correct 4-bit error correction In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE0903CBD539@Cloud.RL.local> References: <1279170641-24494-1-git-send-email-sudhakar.raj@ti.com> <70E876B0EA86DD4BAF101844BC814DFE0903CBD539@Cloud.RL.local> Message-ID: <034101cb2412$ac5bcde0$051369a0$@raj@ti.com> Hi, On Thu, Jul 15, 2010 at 16:31:19, Jon Povey wrote: > Sudhakar Rajashekhara wrote: > > On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the > > 4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and > > before waiting for the NAND Flash status register to be equal to 1, 2 > > or 3, we have to wait till the ECC HW goes to correction state. > > Without this wait, ECC correction calculations will not be proper. > > > > This has been tested on DA830/OMAP-L137, DA850/OMAP-L138, DM355 and > > DM365 EVMs. > > > > Signed-off-by: Sudhakar Rajashekhara > > Acked-by: Sneha Narnakaje > > Cc: David Woodhouse > > Signed-off-by: Andrew Morton > > Have these people acked and signed off this new version of the patch? > No. Andrew Morton has not signed off this version. I'll remove Signed-off-by: Andrew Morton > > Since v1: > > a. Timeout has been changed from 100 msec to 100 usec. > > b. Comment above the do, while loop was not matching the code. > > This has been corrected. > > c. Initialization of 'timeo' variable has been moved down. > > d. It was observed that, while calculating the time in the loop, > > if there is a context switch between setting the > > 4BITECC_ADD_CALC_START bit and reading of ECC_STATE field, then > > the loop will not come out until the timeout happens. To prevent > > the context switch, spin_lock_irqsave and spin_unlock_irqrestore > > are used. > > d. means interrupts are disabled for up to 100us while waiting for ECC. > Doesn't sound good if it can be avoided. > I wanted to avoid context switching between setting 4BITECC_ADD_CALC_START bit: davinci_nand_writel(info, NANDFCR_OFFSET, davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13)); And reading of ECC_STATE field inside the loop: + ecc_state = (davinci_nand_readl(info, + NANDFSR_OFFSET) >> 8) & 0x0f; Because even if there was a slight delay after setting 4BITECC_ADD_CALC_START, ECC_STATE would read < 4(meaning ECC engine has completed Error correction) and I would wait in the loop for up to 100us. > How about instead of spinlock, set timeo first time inside the loop? I don't think this would also solve the problem which I stated above. Adding spinlock was a blunder as that would cause jiffies not to increment. I'll be removing the spinlocks and will be resubmitting the patch. Regards, Sudhakar From sudhakar.raj at ti.com Thu Jul 15 07:03:03 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Thu, 15 Jul 2010 17:33:03 +0530 Subject: [PATCH v2] mtd-nand: davinci: correct 4-bit error correction In-Reply-To: <034101cb2412$ac5bcde0$051369a0$@raj@ti.com> References: <1279170641-24494-1-git-send-email-sudhakar.raj@ti.com> <70E876B0EA86DD4BAF101844BC814DFE0903CBD539@Cloud.RL.local> <034101cb2412$ac5bcde0$051369a0$@raj@ti.com> Message-ID: <034501cb2415$ad54cc80$07fe6580$@raj@ti.com> On Thu, Jul 15, 2010 at 17:11:32, Sudhakar Rajashekhara wrote: > Hi, > > On Thu, Jul 15, 2010 at 16:31:19, Jon Povey wrote: > > Sudhakar Rajashekhara wrote: > > > On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the > > > 4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and > > > before waiting for the NAND Flash status register to be equal to 1, 2 > > > or 3, we have to wait till the ECC HW goes to correction state. > > > Without this wait, ECC correction calculations will not be proper. > > > > > > This has been tested on DA830/OMAP-L137, DA850/OMAP-L138, DM355 and > > > DM365 EVMs. > > > > > > Signed-off-by: Sudhakar Rajashekhara > > > Acked-by: Sneha Narnakaje > > > Cc: David Woodhouse > > > Signed-off-by: Andrew Morton > > > > Have these people acked and signed off this new version of the patch? > > > > No. Andrew Morton has not signed off this version. I'll remove > Signed-off-by: Andrew Morton > Andrew Morton had signed off an earlier version of this patch and it was present in -mm tree for a long time. He has not yet commented on v2 version of this patch. But I thought I can carry forward the Sign-offs from previous version to the next version. What's the common practice? Thanks, Sudhakar From nsekhar at ti.com Thu Jul 15 07:14:19 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Thu, 15 Jul 2010 17:44:19 +0530 Subject: [PATCH] asoc: davinci: let platform data define edma queue numbers Message-ID: <1279196059-6031-1-git-send-email-nsekhar@ti.com> Currently the EDMA queue to be used by for servicing ASP through internal RAM is fixed to EDMAQ_0 and that to service internal RAM from external RAM is fixed to EDMAQ_1. This may not be the desirable configuration on all platforms. For example, on DM365, queue 0 has large fifo size and is more suitable for video transfers. Having audio and video transfers on the same queue may lead to starvation on audio side. platform data as defined currently passes a queue number to the driver but that remains unused inside the driver. Fix this by defining one queue each for ASP and RAM transfers in the platform data and using it inside the driver. Since EDMAQ_0 maps to 0, thats the queue that will be used if the asp queue number is not initialized. None of the platforms currently utilize ping-pong transfers through internal RAM so that functionality remains unchanged too. This patch has been tested on DM644x and OMAP-L138 EVMs. Signed-off-by: Sekhar Nori --- This patch applies to latest of Linus's tree. arch/arm/mach-davinci/board-da830-evm.c | 2 +- arch/arm/mach-davinci/board-da850-evm.c | 2 +- arch/arm/mach-davinci/board-dm646x-evm.c | 4 ++-- arch/arm/mach-davinci/include/mach/asp.h | 3 ++- sound/soc/davinci/davinci-i2s.c | 10 ++++++++++ sound/soc/davinci/davinci-mcasp.c | 6 ++++-- sound/soc/davinci/davinci-pcm.c | 5 +++-- sound/soc/davinci/davinci-pcm.h | 3 ++- 8 files changed, 25 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 212d970..bc384d3 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -208,7 +208,7 @@ static struct snd_platform_data da830_evm_snd_data = { .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction), .tdm_slots = 2, .serial_dir = da830_iis_serializer_direction, - .eventq_no = EVENTQ_0, + .asp_chan_q = EVENTQ_0, .version = MCASP_VERSION_2, .txnumevt = 1, .rxnumevt = 1, diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 2ec3095..d4ec18d 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -342,7 +342,7 @@ static struct snd_platform_data da850_evm_snd_data = { .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), .tdm_slots = 2, .serial_dir = da850_iis_serializer_direction, - .eventq_no = EVENTQ_1, + .asp_chan_q = EVENTQ_1, .version = MCASP_VERSION_2, .txnumevt = 1, .rxnumevt = 1, diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 6d88893..87521f2 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -323,7 +323,7 @@ static struct snd_platform_data dm646x_evm_snd_data[] = { .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction), .tdm_slots = 2, .serial_dir = dm646x_iis_serializer_direction, - .eventq_no = EVENTQ_0, + .asp_chan_q = EVENTQ_0, }, { .tx_dma_offset = 0x400, @@ -332,7 +332,7 @@ static struct snd_platform_data dm646x_evm_snd_data[] = { .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction), .tdm_slots = 32, .serial_dir = dm646x_dit_serializer_direction, - .eventq_no = EVENTQ_0, + .asp_chan_q = EVENTQ_0, }, }; diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index 834725f..5d0a4c7 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -52,7 +52,8 @@ struct snd_platform_data { u32 tx_dma_offset; u32 rx_dma_offset; - enum dma_event_q eventq_no; /* event queue number */ + enum dma_event_q asp_chan_q; /* event queue number for ASP channel */ + enum dma_event_q ram_chan_q; /* event queue number for RAM channel */ unsigned int codec_fmt; /* * Allowing this is more efficient and eliminates left and right swaps diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c index adadcd3..4c1a7d2 100644 --- a/sound/soc/davinci/davinci-i2s.c +++ b/sound/soc/davinci/davinci-i2s.c @@ -526,6 +526,8 @@ static int davinci_i2s_probe(struct platform_device *pdev) struct snd_platform_data *pdata = pdev->dev.platform_data; struct davinci_mcbsp_dev *dev; struct resource *mem, *ioarea, *res; + enum dma_event_q asp_chan_q = EVENTQ_0; + enum dma_event_q ram_chan_q = EVENTQ_1; int ret; mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -552,7 +554,15 @@ static int davinci_i2s_probe(struct platform_device *pdev) pdata->sram_size_playback; dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size = pdata->sram_size_capture; + asp_chan_q = pdata->asp_chan_q; + ram_chan_q = pdata->ram_chan_q; } + + dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].asp_chan_q = asp_chan_q; + dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].ram_chan_q = ram_chan_q; + dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].asp_chan_q = asp_chan_q; + dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].ram_chan_q = ram_chan_q; + dev->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(dev->clk)) { ret = -ENODEV; diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c index d395509..b247208 100644 --- a/sound/soc/davinci/davinci-mcasp.c +++ b/sound/soc/davinci/davinci-mcasp.c @@ -890,7 +890,8 @@ static int davinci_mcasp_probe(struct platform_device *pdev) dev->rxnumevt = pdata->rxnumevt; dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; - dma_data->eventq_no = pdata->eventq_no; + dma_data->asp_chan_q = pdata->asp_chan_q; + dma_data->ram_chan_q = pdata->ram_chan_q; dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset + io_v2p(dev->base)); @@ -904,7 +905,8 @@ static int davinci_mcasp_probe(struct platform_device *pdev) dma_data->channel = res->start; dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]; - dma_data->eventq_no = pdata->eventq_no; + dma_data->asp_chan_q = pdata->asp_chan_q; + dma_data->ram_chan_q = pdata->ram_chan_q; dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset + io_v2p(dev->base)); diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c index 2dc406f..f026ac5 100644 --- a/sound/soc/davinci/davinci-pcm.c +++ b/sound/soc/davinci/davinci-pcm.c @@ -381,7 +381,7 @@ static int request_ping_pong(struct snd_pcm_substream *substream, /* Request ram master channel */ link = prtd->ram_channel = edma_alloc_channel(EDMA_CHANNEL_ANY, davinci_pcm_dma_irq, substream, - EVENTQ_1); + prtd->params->ram_chan_q); if (link < 0) goto exit1; @@ -477,7 +477,8 @@ static int davinci_pcm_dma_request(struct snd_pcm_substream *substream) /* Request asp master DMA channel */ link = prtd->asp_channel = edma_alloc_channel(params->channel, - davinci_pcm_dma_irq, substream, EVENTQ_0); + davinci_pcm_dma_irq, substream, + prtd->params->asp_chan_q); if (link < 0) goto exit1; diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h index 0764944..b799a02 100644 --- a/sound/soc/davinci/davinci-pcm.h +++ b/sound/soc/davinci/davinci-pcm.h @@ -21,7 +21,8 @@ struct davinci_pcm_dma_params { unsigned short acnt; dma_addr_t dma_addr; /* device physical address for DMA */ unsigned sram_size; - enum dma_event_q eventq_no; /* event queue number */ + enum dma_event_q asp_chan_q; /* event queue number for ASP channel */ + enum dma_event_q ram_chan_q; /* event queue number for RAM channel */ unsigned char data_type; /* xfer data type */ unsigned char convert_mono_stereo; unsigned int fifo_level; -- 1.6.2.4 From schen at mvista.com Thu Jul 15 07:57:00 2010 From: schen at mvista.com (Steve Chen) Date: Thu, 15 Jul 2010 07:57:00 -0500 Subject: Problem with UBIFS In-Reply-To: <79382.65490.qm@web24107.mail.ird.yahoo.com> References: <79382.65490.qm@web24107.mail.ird.yahoo.com> Message-ID: On Thu, Jul 15, 2010 at 2:32 AM, rohan tabish wrote: > Using sync option solves the problem but it is not recomended According to http://www.linux-mtd.infradead.org/doc/ubifs.html You can use fsync in the application to force write-through for specific files while having write-back as the default for performance. Steve -------------- next part -------------- An HTML attachment was scrubbed... URL: From lamiaposta71 at gmail.com Wed Jul 14 05:37:57 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Wed, 14 Jul 2010 12:37:57 +0200 Subject: [PATCH] DaVinci: dm365: Added clockout2 management and set_sysclk_rate Message-ID: <1279103878-3757-1-git-send-email-lamiaposta71@gmail.com> From: Davide Bonfanti Added also possibility to set sysclk frequency. Added possibility to set clockout2 frequency. Clockout2 is a child of pll1_sysclk9, because they have the same pll divisor. This patch has been developed against the http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git git tree and tested on bmx board. Signed-off-by: Davide Bonfanti Signed-off-by: Raffaele Recalcati --- arch/arm/mach-davinci/clock.c | 113 +++++++++++++++++++++++++++- arch/arm/mach-davinci/clock.h | 14 ++++ arch/arm/mach-davinci/dm365.c | 23 +++++- arch/arm/mach-davinci/include/mach/clock.h | 3 + 4 files changed, 146 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 054c303..464c289 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -144,6 +144,69 @@ int clk_set_rate(struct clk *clk, unsigned long rate) } EXPORT_SYMBOL(clk_set_rate); +int clkout2_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long flags; + int ret = -EINVAL; + int i, err, min_err, i_min_err; + u32 regval; + struct pll_data *pll; + struct clk *parent = clk; + + if (clk == NULL || IS_ERR(clk)) + return ret; + if (!cpu_is_davinci_dm365()) + return -ENODEV; + + while (parent->parent->parent) + parent = parent->parent; + + parent = clk->parent; + + if (parent == clk) + return -EPERM; + + pll = parent->pll_data; + regval = __raw_readl(IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + + PERI_CLKCTL)); + + i_min_err = min_err = INT_MAX; + for (i = 0x0F; i > 0; i--) { + if (clk->set_rate) { + ret = clk_set_rate(clk, rate * i) ; + err = clk_get_rate(clk) - rate * i; + if (abs(min_err) > abs(err)) { + min_err = err; + i_min_err = i; + } + } + } + i = i_min_err; + ret = clk->set_rate(clk, rate * i) ; + + regval &= ~(0x0F << 3); + regval |= (i-1) << 3; + regval |= 1 << CLOCKOUT2EN; + __raw_writel(regval, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + + PERI_CLKCTL)); + rate *= i; + + spin_lock_irqsave(&clockfw_lock, flags); + if (ret == 0) { + if (clk->recalc) + clk->rate = clk->recalc(clk); + propagate_rate(clk); + regval &= ~(1 << CLOCKOUT2EN); + __raw_writel(regval, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + + PERI_CLKCTL)); + } else + return -EINVAL; + spin_unlock_irqrestore(&clockfw_lock, flags); + + return ret; +} +EXPORT_SYMBOL(clkout2_set_rate); + int clk_set_parent(struct clk *clk, struct clk *parent) { unsigned long flags; @@ -254,7 +317,15 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) u32 v, plldiv; struct pll_data *pll; unsigned long rate = clk->rate; + struct clk *parent = clk; + + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + while (parent->parent->parent) + parent = parent->parent; + if (parent == clk) + return -EPERM; /* If this is the PLL base clock, no more calculations needed */ if (clk->pll_data) return rate; @@ -262,13 +333,13 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) if (WARN_ON(!clk->parent)) return rate; - rate = clk->parent->rate; + rate = parent->rate; + /* Otherwise, the parent must be a PLL */ - if (WARN_ON(!clk->parent->pll_data)) + if (WARN_ON(!parent->pll_data)) return rate; - - pll = clk->parent->pll_data; + pll = parent->pll_data; /* If pre-PLL, source clock is before the multiplier and divider(s) */ if (clk->flags & PRE_PLL) @@ -286,6 +357,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) return rate; } +EXPORT_SYMBOL(clk_sysclk_recalc); static unsigned long clk_leafclk_recalc(struct clk *clk) { @@ -433,6 +505,39 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, } EXPORT_SYMBOL(davinci_set_pllrate); +int set_sysclk_rate(struct clk *clk, unsigned long rate) +{ + u32 clk_freq_min, clk_freq_max, plldiv; + struct pll_data *pll; + struct clk *parent = clk; + + while (parent->parent->parent) + parent = parent->parent; + if (parent == clk) + return -EPERM; + + clk_freq_max = parent->rate; + pll = parent->pll_data; + if (clk->flags & PRE_PLL) + clk_freq_max = pll->input_rate; + + if (!clk->div_reg) + return -EPERM; + + clk_freq_min = clk_freq_max / 0x20; + if ((rate < clk_freq_min) || (rate > clk_freq_max)) + return -EINVAL; + + plldiv = clk_freq_max / rate ; + if ((clk_freq_max % rate) < (rate >> 1)) + plldiv--; + __raw_writel(plldiv & 0x1F, pll->base + clk->div_reg); + __raw_writel(plldiv | 0x8000, pll->base + clk->div_reg); + clk->rate = rate; + return 0; +} +EXPORT_SYMBOL(set_sysclk_rate); + int __init davinci_clk_init(struct clk_lookup *clocks) { struct clk_lookup *c; diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 01e3648..74ba65f 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -50,6 +50,11 @@ #define PLLDIV_EN BIT(15) #define PLLDIV_RATIO_MASK 0x1f +#define PERI_CLKCTL 0x48 +#define CLOCKOUT2EN 2 +#define CLOCKOUT1EN 1 +#define CLOCKOUT0EN 0 + /* * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us @@ -95,6 +100,14 @@ struct clk { struct list_head childnode; /* parent's child list node */ struct pll_data *pll_data; u32 div_reg; +/* + u32 sec_div_reg; + u32 sec_div_reg_max; + u32 sec_div_reg_shift; + u32 out_enable_reg; + u32 out_enable_bit; +*/ + unsigned long (*recalc) (struct clk *); int (*set_rate) (struct clk *clk, unsigned long rate); int (*round_rate) (struct clk *clk, unsigned long rate); @@ -121,6 +134,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, extern struct platform_device davinci_wdt_device; extern void davinci_watchdog_reset(struct platform_device *); +int set_sysclk_rate(struct clk *clk, unsigned long rate); #endif diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 42fd4a4..1e97c62 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -40,6 +40,15 @@ #include "mux.h" #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ +#define PINMUX0 0x00 +#define PINMUX1 0x04 +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 +#define INTMUX 0x18 +#define EVTMUX 0x1c + + static struct pll_data pll1_data = { .num = 1, @@ -124,6 +133,7 @@ static struct clk pll1_sysclk6 = { .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV6, + .set_rate = set_sysclk_rate, }; static struct clk pll1_sysclk7 = { @@ -147,6 +157,15 @@ static struct clk pll1_sysclk9 = { .div_reg = PLLDIV9, }; +static struct clk clkout2_clk = { + .name = "clkout2", + .parent = &pll1_sysclk9, + .flags = CLK_PLL, + .div_reg = PLLDIV9, + .set_rate = set_sysclk_rate, +}; + + static struct clk pll2_clk = { .name = "pll2", .parent = &ref_clk, @@ -421,6 +440,7 @@ static struct clk_lookup dm365_clks[] = { CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), + CLK(NULL, "clkout2", &clkout2_clk), CLK(NULL, "pll2", &pll2_clk), CLK(NULL, "pll2_aux", &pll2_aux_clk), CLK(NULL, "clkout1", &clkout1_clk), @@ -467,9 +487,6 @@ static struct clk_lookup dm365_clks[] = { /*----------------------------------------------------------------------*/ -#define INTMUX 0x18 -#define EVTMUX 0x1c - static const struct mux_config dm365_pins[] = { #ifdef CONFIG_DAVINCI_MUX diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h index a3b0402..4296080 100644 --- a/arch/arm/mach-davinci/include/mach/clock.h +++ b/arch/arm/mach-davinci/include/mach/clock.h @@ -18,4 +18,7 @@ struct clk; extern int clk_register(struct clk *clk); extern void clk_unregister(struct clk *clk); +int clkout2_set_rate(struct clk *clk, unsigned long rate); + + #endif -- 1.7.0.4 From lamiaposta71 at gmail.com Wed Jul 14 05:47:59 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Wed, 14 Jul 2010 12:47:59 +0200 Subject: [PATCH] DaVinci: dm365: Added clockout2 management and set_sysclk_rate In-Reply-To: <1279103878-3757-1-git-send-email-lamiaposta71@gmail.com> References: <1279103878-3757-1-git-send-email-lamiaposta71@gmail.com> Message-ID: Please not consider this patch. I have to re-check it. I'm sorry for the mistake. 2010/7/14 Raffaele Recalcati > From: Davide Bonfanti > > Added also possibility to set sysclk frequency. > > Added possibility to set clockout2 frequency. > Clockout2 is a child of pll1_sysclk9, because they have > the same pll divisor. > > This patch has been developed against the > > http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git > git tree and tested on bmx board. > > Signed-off-by: Davide Bonfanti > Signed-off-by: Raffaele Recalcati > --- > arch/arm/mach-davinci/clock.c | 113 > +++++++++++++++++++++++++++- > arch/arm/mach-davinci/clock.h | 14 ++++ > arch/arm/mach-davinci/dm365.c | 23 +++++- > arch/arm/mach-davinci/include/mach/clock.h | 3 + > 4 files changed, 146 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c > index 054c303..464c289 100644 > --- a/arch/arm/mach-davinci/clock.c > +++ b/arch/arm/mach-davinci/clock.c > @@ -144,6 +144,69 @@ int clk_set_rate(struct clk *clk, unsigned long rate) > } > EXPORT_SYMBOL(clk_set_rate); > > +int clkout2_set_rate(struct clk *clk, unsigned long rate) > +{ > + unsigned long flags; > + int ret = -EINVAL; > + int i, err, min_err, i_min_err; > + u32 regval; > + struct pll_data *pll; > + struct clk *parent = clk; > + > + if (clk == NULL || IS_ERR(clk)) > + return ret; > + if (!cpu_is_davinci_dm365()) > + return -ENODEV; > + > + while (parent->parent->parent) > + parent = parent->parent; > + > + parent = clk->parent; > + > + if (parent == clk) > + return -EPERM; > + > + pll = parent->pll_data; > + regval = __raw_readl(IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + > + PERI_CLKCTL)); > + > + i_min_err = min_err = INT_MAX; > + for (i = 0x0F; i > 0; i--) { > + if (clk->set_rate) { > + ret = clk_set_rate(clk, rate * i) ; > + err = clk_get_rate(clk) - rate * i; > + if (abs(min_err) > abs(err)) { > + min_err = err; > + i_min_err = i; > + } > + } > + } > + i = i_min_err; > + ret = clk->set_rate(clk, rate * i) ; > + > + regval &= ~(0x0F << 3); > + regval |= (i-1) << 3; > + regval |= 1 << CLOCKOUT2EN; > + __raw_writel(regval, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + > + PERI_CLKCTL)); > + rate *= i; > + > + spin_lock_irqsave(&clockfw_lock, flags); > + if (ret == 0) { > + if (clk->recalc) > + clk->rate = clk->recalc(clk); > + propagate_rate(clk); > + regval &= ~(1 << CLOCKOUT2EN); > + __raw_writel(regval, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE > + > + PERI_CLKCTL)); > + } else > + return -EINVAL; > + spin_unlock_irqrestore(&clockfw_lock, flags); > + > + return ret; > +} > +EXPORT_SYMBOL(clkout2_set_rate); > + > int clk_set_parent(struct clk *clk, struct clk *parent) > { > unsigned long flags; > @@ -254,7 +317,15 @@ static unsigned long clk_sysclk_recalc(struct clk > *clk) > u32 v, plldiv; > struct pll_data *pll; > unsigned long rate = clk->rate; > + struct clk *parent = clk; > + > + if (clk == NULL || IS_ERR(clk)) > + return -EINVAL; > + while (parent->parent->parent) > + parent = parent->parent; > > + if (parent == clk) > + return -EPERM; > /* If this is the PLL base clock, no more calculations needed */ > if (clk->pll_data) > return rate; > @@ -262,13 +333,13 @@ static unsigned long clk_sysclk_recalc(struct clk > *clk) > if (WARN_ON(!clk->parent)) > return rate; > > - rate = clk->parent->rate; > + rate = parent->rate; > + > > /* Otherwise, the parent must be a PLL */ > - if (WARN_ON(!clk->parent->pll_data)) > + if (WARN_ON(!parent->pll_data)) > return rate; > - > - pll = clk->parent->pll_data; > + pll = parent->pll_data; > > /* If pre-PLL, source clock is before the multiplier and divider(s) > */ > if (clk->flags & PRE_PLL) > @@ -286,6 +357,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) > > return rate; > } > +EXPORT_SYMBOL(clk_sysclk_recalc); > > static unsigned long clk_leafclk_recalc(struct clk *clk) > { > @@ -433,6 +505,39 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned > int prediv, > } > EXPORT_SYMBOL(davinci_set_pllrate); > > +int set_sysclk_rate(struct clk *clk, unsigned long rate) > +{ > + u32 clk_freq_min, clk_freq_max, plldiv; > + struct pll_data *pll; > + struct clk *parent = clk; > + > + while (parent->parent->parent) > + parent = parent->parent; > + if (parent == clk) > + return -EPERM; > + > + clk_freq_max = parent->rate; > + pll = parent->pll_data; > + if (clk->flags & PRE_PLL) > + clk_freq_max = pll->input_rate; > + > + if (!clk->div_reg) > + return -EPERM; > + > + clk_freq_min = clk_freq_max / 0x20; > + if ((rate < clk_freq_min) || (rate > clk_freq_max)) > + return -EINVAL; > + > + plldiv = clk_freq_max / rate ; > + if ((clk_freq_max % rate) < (rate >> 1)) > + plldiv--; > + __raw_writel(plldiv & 0x1F, pll->base + clk->div_reg); > + __raw_writel(plldiv | 0x8000, pll->base + clk->div_reg); > + clk->rate = rate; > + return 0; > +} > +EXPORT_SYMBOL(set_sysclk_rate); > + > int __init davinci_clk_init(struct clk_lookup *clocks) > { > struct clk_lookup *c; > diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h > index 01e3648..74ba65f 100644 > --- a/arch/arm/mach-davinci/clock.h > +++ b/arch/arm/mach-davinci/clock.h > @@ -50,6 +50,11 @@ > #define PLLDIV_EN BIT(15) > #define PLLDIV_RATIO_MASK 0x1f > > +#define PERI_CLKCTL 0x48 > +#define CLOCKOUT2EN 2 > +#define CLOCKOUT1EN 1 > +#define CLOCKOUT0EN 0 > + > /* > * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN > * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us > @@ -95,6 +100,14 @@ struct clk { > struct list_head childnode; /* parent's child list node > */ > struct pll_data *pll_data; > u32 div_reg; > +/* > + u32 sec_div_reg; > + u32 sec_div_reg_max; > + u32 sec_div_reg_shift; > + u32 out_enable_reg; > + u32 out_enable_bit; > +*/ > + > unsigned long (*recalc) (struct clk *); > int (*set_rate) (struct clk *clk, unsigned long rate); > int (*round_rate) (struct clk *clk, unsigned long rate); > @@ -121,6 +134,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned > int prediv, > > extern struct platform_device davinci_wdt_device; > extern void davinci_watchdog_reset(struct platform_device *); > +int set_sysclk_rate(struct clk *clk, unsigned long rate); > > #endif > > diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c > index 42fd4a4..1e97c62 100644 > --- a/arch/arm/mach-davinci/dm365.c > +++ b/arch/arm/mach-davinci/dm365.c > @@ -40,6 +40,15 @@ > #include "mux.h" > > #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM > */ > +#define PINMUX0 0x00 > +#define PINMUX1 0x04 > +#define PINMUX2 0x08 > +#define PINMUX3 0x0c > +#define PINMUX4 0x10 > +#define INTMUX 0x18 > +#define EVTMUX 0x1c > + > + > > static struct pll_data pll1_data = { > .num = 1, > @@ -124,6 +133,7 @@ static struct clk pll1_sysclk6 = { > .parent = &pll1_clk, > .flags = CLK_PLL, > .div_reg = PLLDIV6, > + .set_rate = set_sysclk_rate, > }; > > static struct clk pll1_sysclk7 = { > @@ -147,6 +157,15 @@ static struct clk pll1_sysclk9 = { > .div_reg = PLLDIV9, > }; > > +static struct clk clkout2_clk = { > + .name = "clkout2", > + .parent = &pll1_sysclk9, > + .flags = CLK_PLL, > + .div_reg = PLLDIV9, > + .set_rate = set_sysclk_rate, > +}; > + > + > static struct clk pll2_clk = { > .name = "pll2", > .parent = &ref_clk, > @@ -421,6 +440,7 @@ static struct clk_lookup dm365_clks[] = { > CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), > CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), > CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), > + CLK(NULL, "clkout2", &clkout2_clk), > CLK(NULL, "pll2", &pll2_clk), > CLK(NULL, "pll2_aux", &pll2_aux_clk), > CLK(NULL, "clkout1", &clkout1_clk), > @@ -467,9 +487,6 @@ static struct clk_lookup dm365_clks[] = { > > /*----------------------------------------------------------------------*/ > > -#define INTMUX 0x18 > -#define EVTMUX 0x1c > - > > static const struct mux_config dm365_pins[] = { > #ifdef CONFIG_DAVINCI_MUX > diff --git a/arch/arm/mach-davinci/include/mach/clock.h > b/arch/arm/mach-davinci/include/mach/clock.h > index a3b0402..4296080 100644 > --- a/arch/arm/mach-davinci/include/mach/clock.h > +++ b/arch/arm/mach-davinci/include/mach/clock.h > @@ -18,4 +18,7 @@ struct clk; > extern int clk_register(struct clk *clk); > extern void clk_unregister(struct clk *clk); > > +int clkout2_set_rate(struct clk *clk, unsigned long rate); > + > + > #endif > -- > 1.7.0.4 > > -- www.opensurf.it -------------- next part -------------- An HTML attachment was scrubbed... URL: From lamiaposta71 at gmail.com Wed Jul 14 09:21:09 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Wed, 14 Jul 2010 16:21:09 +0200 Subject: [PATCH] DaVinci: dm365: Added clockout2 management. Message-ID: <1279117269-5017-1-git-send-email-lamiaposta71@gmail.com> From: Davide Bonfanti Clockout2 is added as a child of pll1_sysclk9, because they have the same pll divisor. Added dm365_clkout2_set_rate to properly set clockout2 frequency. Modified the davinci_set_sysclk_rate function in order to get the right ancestor. This patch has been developed against the http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git git tree and tested on bmx board. Signed-off-by: Davide Bonfanti Signed-off-by: Raffaele Recalcati --- arch/arm/mach-davinci/clock.c | 32 ++++++++++++---- arch/arm/mach-davinci/clock.h | 5 ++ arch/arm/mach-davinci/dm365.c | 57 ++++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/dm365.h | 1 + 4 files changed, 87 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index f29a526..6e45808 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -254,7 +254,15 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) u32 v, plldiv; struct pll_data *pll; unsigned long rate = clk->rate; + struct clk *parent = clk; + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + while (parent->parent->parent) + parent = parent->parent; + + if (parent == clk) + return -EPERM; /* If this is the PLL base clock, no more calculations needed */ if (clk->pll_data) return rate; @@ -262,13 +270,13 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) if (WARN_ON(!clk->parent)) return rate; - rate = clk->parent->rate; + rate = parent->rate; + /* Otherwise, the parent must be a PLL */ - if (WARN_ON(!clk->parent->pll_data)) + if (WARN_ON(!parent->pll_data)) return rate; - - pll = clk->parent->pll_data; + pll = parent->pll_data; /* If pre-PLL, source clock is before the multiplier and divider(s) */ if (clk->flags & PRE_PLL) @@ -293,26 +301,33 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) struct pll_data *pll; unsigned long input; unsigned ratio = 0; + struct clk *parent = clk; + + /* searching the right ancestor (pll1_clk or pll2_clk) */ + while (parent->parent->parent) + parent = parent->parent; + if (parent == clk) + return -EPERM; /* If this is the PLL base clock, wrong function to call */ if (clk->pll_data) return 0; /* There must be a parent... */ - if (WARN_ON(!clk->parent)) + if (WARN_ON(!parent)) return 0; /* ... the parent must be a PLL... */ - if (WARN_ON(!clk->parent->pll_data)) + if (WARN_ON(!parent->pll_data)) return 0; /* ... and this clock must have a divider. */ if (WARN_ON(!clk->div_reg)) return 0; - pll = clk->parent->pll_data; + pll = parent->pll_data; - input = clk->parent->rate; + input = parent->rate; /* If pre-PLL, source clock is before the multiplier and divider(s) */ if (clk->flags & PRE_PLL) @@ -343,6 +358,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) return 0; } +EXPORT_SYMBOL(davinci_set_sysclk_rate); static unsigned long clk_leafclk_recalc(struct clk *clk) { diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index a717d98..df36d73 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -50,6 +50,11 @@ #define PLLDIV_EN BIT(15) #define PLLDIV_RATIO_MASK 0x1f +#define PERI_CLKCTL 0x48 +#define CLOCKOUT2EN 2 +#define CLOCKOUT1EN 1 +#define CLOCKOUT0EN 0 + /* * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 42fd4a4..56a425f 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -40,6 +40,11 @@ #include "mux.h" #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ +#define PINMUX0 0x00 +#define PINMUX1 0x04 +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 static struct pll_data pll1_data = { .num = 1, @@ -124,6 +129,7 @@ static struct clk pll1_sysclk6 = { .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV6, + .set_rate = davinci_set_sysclk_rate, }; static struct clk pll1_sysclk7 = { @@ -147,6 +153,14 @@ static struct clk pll1_sysclk9 = { .div_reg = PLLDIV9, }; +static struct clk clkout2_clk = { + .name = "clkout2", + .parent = &pll1_sysclk9, + .flags = CLK_PLL, + .div_reg = PLLDIV9, + .set_rate = davinci_set_sysclk_rate, +}; + static struct clk pll2_clk = { .name = "pll2", .parent = &ref_clk, @@ -421,6 +435,7 @@ static struct clk_lookup dm365_clks[] = { CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), + CLK(NULL, "clkout2", &clkout2_clk), CLK(NULL, "pll2", &pll2_clk), CLK(NULL, "pll2_aux", &pll2_aux_clk), CLK(NULL, "clkout1", &clkout1_clk), @@ -657,6 +672,48 @@ static struct resource dm365_spi0_resources[] = { }, }; +int dm365_clkout2_set_rate(unsigned long rate) +{ + int ret = -EINVAL; + int i, err, min_err, i_min_err; + u32 regval; + struct clk *clk; + static void __iomem *system_module_base; + + clk = &clkout2_clk; + system_module_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE, SZ_4K); + regval = __raw_readl(system_module_base + PERI_CLKCTL); + + /* check all possibilities to get best fitting for the required freq */ + i_min_err = min_err = INT_MAX; + for (i = 0x0F; i > 0; i--) { + if (clk->set_rate) { + ret = clk_set_rate(clk, rate * i) ; + err = clk_get_rate(clk) - rate * i; + if (min_err > abs(err)) { + min_err = abs(err); + i_min_err = i; + } + } + } + ret = clk_set_rate(clk, rate * i_min_err) ; + if (ret) + return ret; + + /* setup DIV1 value */ + regval &= ~(0x0F << 3); + regval |= (i_min_err - 1) << 3; + + /* to make changes work stop CLOCKOUT & start it again */ + regval |= 1 << CLOCKOUT2EN; + __raw_writel(regval, system_module_base + PERI_CLKCTL); + regval &= ~(1 << CLOCKOUT2EN); + __raw_writel(regval, system_module_base + PERI_CLKCTL); + + return ret; +} +EXPORT_SYMBOL(dm365_clkout2_set_rate); + static struct platform_device dm365_spi0_device = { .name = "spi_davinci", .id = 0, diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h index ea5df3b..f59741f 100644 --- a/arch/arm/mach-davinci/include/mach/dm365.h +++ b/arch/arm/mach-davinci/include/mach/dm365.h @@ -49,4 +49,5 @@ void dm365_init_spi0(unsigned chipselect_mask, struct spi_board_info *info, unsigned len); void dm365_set_vpfe_config(struct vpfe_config *cfg); +int dm365_clkout2_set_rate(unsigned long rate); #endif /* __ASM_ARCH_DM365_H */ -- 1.7.0.4 From lamiaposta71 at gmail.com Wed Jul 14 09:28:10 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Wed, 14 Jul 2010 16:28:10 +0200 Subject: [PATCH] Asoc Davinci Voicecodec: Added support based on copy_from_user instead of DMA Message-ID: <1279117691-5467-1-git-send-email-lamiaposta71@gmail.com> From: Davide Bonfanti Since DM365 has the same DMA event for McBSP and Voicecodec this two peripherals cannot be used at the same time. This driver implements Voicecodec without the use of a DMA but with a copy_from_user. There's a buffer of BUF_SIZE (tested with 2KB) bytes in the driver that is filled with davinci_pcm_copy. When pcm is running, a TIMER interrupt is activated each 1.36ms in order to fill HW FIFO (dm_vc_irq). BUG: It happens sometimes that the peripheral stops working so there's a trap. This driver was tested with timer1 and timer4. The measures made using a GPIO and scope give a time for copy_from_user about 8/10us (triggered by alsa layer) while TIMER interrupt takes 1.5us. This patch has been developed against the http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git git tree and tested on bmx board. Signed-off-by: Davide Bonfanti Signed-off-by: Raffaele Recalcati --- sound/soc/davinci/Makefile | 1 + sound/soc/davinci/davinci-pcm-copyfromuser.c | 333 ++++++++++++++++++++++++++ sound/soc/davinci/davinci-pcm.h | 1 + sound/soc/soc-core.c | 31 ++- 4 files changed, 354 insertions(+), 12 deletions(-) create mode 100644 sound/soc/davinci/davinci-pcm-copyfromuser.c diff --git a/sound/soc/davinci/Makefile b/sound/soc/davinci/Makefile index a93679d..7d6a9a1 100644 --- a/sound/soc/davinci/Makefile +++ b/sound/soc/davinci/Makefile @@ -1,5 +1,6 @@ # DAVINCI Platform Support snd-soc-davinci-objs := davinci-pcm.o +snd-soc-davinci-objs += davinci-pcm-copyfromuser.o snd-soc-davinci-i2s-objs := davinci-i2s.o snd-soc-davinci-mcasp-objs:= davinci-mcasp.o snd-soc-davinci-vcif-objs:= davinci-vcif.o diff --git a/sound/soc/davinci/davinci-pcm-copyfromuser.c b/sound/soc/davinci/davinci-pcm-copyfromuser.c new file mode 100644 index 0000000..df37873 --- /dev/null +++ b/sound/soc/davinci/davinci-pcm-copyfromuser.c @@ -0,0 +1,333 @@ +/* + * + * Copyright (C) 2010 Bticino S.p.a + * Author: Davide Bonfanti + * + * Contributors: + * Raffaele Recalcati + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "davinci-pcm.h" + +/* Timer register offsets */ +#define PID12 0x00 +#define TIM12 0x10 +#define TIM34 0x14 +#define PRD12 0x18 +#define PRD34 0x1c +#define TCR 0x20 +#define TGCR 0x24 + +/* Timer register bitfields */ +#define TCR_ENAMODE_DISABLE 0x0 +#define TCR_ENAMODE_ONESHOT 0x1 +#define TCR_ENAMODE_PERIODIC 0x2 +#define TCR_ENAMODE_MASK 0x3 + +#define TGCR_TIMMODE_SHIFT 2 +#define TGCR_TIMMODE_64BIT_GP 0x0 +#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 +#define TGCR_TIMMODE_64BIT_WDOG 0x2 +#define TGCR_TIMMODE_32BIT_CHAINED 0x3 + +#define TGCR_TIM12RS_SHIFT 0 +#define TGCR_TIM34RS_SHIFT 1 +#define TGCR_RESET 0x0 +#define TGCR_UNRESET 0x1 +#define TGCR_RESET_MASK 0x3 + +#define TIMER1_BASE 0x01C21800 +#define TIMER4_BASE 0x01C23800 + +/* choose the timer to use */ +#define TIMER_BASE TIMER4_BASE +/* driver buffer dimension */ +#define BUF_SIZE 2048 + +#if (TIMER_BASE == TIMER1_BASE) +#define TINT IRQ_TINT1_TINT12 +#define TIMER "timer1" +#elif (TIMER_BASE == TIMER4_BASE) +#define TINT IRQ_PWMINT2 +#define TIMER "timer4" +#endif + +int pointer_sub; +u16 local_buffer[BUF_SIZE/2]; + +static struct snd_pcm_hardware pcm_hardware_playback = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER), + .formats = (SNDRV_PCM_FMTBIT_S16_LE), + .rates = (SNDRV_PCM_RATE_8000), + .rate_min = 8000, + .rate_max = 8000, + .channels_min = 1, + .channels_max = 1, + .buffer_bytes_max = BUF_SIZE, + .period_bytes_min = 512, + .period_bytes_max = 512, + .periods_min = BUF_SIZE / 512, + .periods_max = BUF_SIZE / 512, + .fifo_size = 0, +}; + +/* + * How this driver works... + * + * Since DM365 have the same DMA event for I2S and Voicecodec this two + * peripheralscannot be used at the same time. + * This driver implements voicecodec without the use of a DMA but with + * a copy_from_user. + * There's a buffer of BUF_SIZE bytes in the driver that is filled with + * davinci_pcm_copy. + * When pcm is running, a TIMER interrupt is activated each 1.36ms in + * order to fill HW FIFO (dm_vc_irq). + * It happens that the peripheral stop working so there's a trap... + * Driver was proved with timer1 and timer4. if timer2 is used the device + * resets during power-up. Timer3 have a structure a bit different and, + * in fact, doesn't work. + * Measures using a GPIO and scope give a time for copy_from_user about + * 8/10us while interrupt takes 1.5us + */ + +static snd_pcm_uframes_t +davinci_pcm_pointer(struct snd_pcm_substream *substream) +{ + return pointer_sub; +} + +static int davinci_pcm_open(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct davinci_runtime_data *prtd; + struct snd_pcm_hardware *ppcm; + int ret = 0; + struct davinci_pcm_dma_params *pa; + struct davinci_pcm_dma_params *params; + struct clk *clk; + + pointer_sub = 0; + +/* + * ppcm = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? + * &pcm_hardware_playback : &pcm_hardware_capture; + */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + ppcm = &pcm_hardware_playback; + else + return -ENODEV; + + snd_soc_set_runtime_hwparams(substream, ppcm); + /* ensure that buffer size is a multiple of period size */ + ret = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) + return ret; + + __raw_writel(0x0, IO_ADDRESS(0x01D0C008)); + __raw_writel(0x7400, IO_ADDRESS(0x01D0C004)); + clk = clk_get(NULL, TIMER); + if (!IS_ERR(clk)) + clk_enable(clk); + return 0; +} + +static int davinci_pcm_close(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct clk *clk; + + clk = clk_get(NULL, TIMER); + if (!IS_ERR(clk)) + clk_disable(clk); + return 0; +} + +static int davinci_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params) +{ + return snd_pcm_lib_malloc_pages(substream, + params_buffer_bytes(hw_params)); +} + +static int davinci_pcm_hw_free(struct snd_pcm_substream *substream) +{ + return snd_pcm_lib_free_pages(substream); +} + +static int davinci_pcm_copy(struct snd_pcm_substream *substream, int channel, + snd_pcm_uframes_t hwoff, void __user *buf, snd_pcm_uframes_t frames) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + + if (copy_from_user(local_buffer + hwoff, buf, + frames_to_bytes(runtime, frames))) { + printk(KERN_ERR "ERROR COPY_FROM_USER\n"); + return -EFAULT; + } + return 0; +} + +static struct snd_pcm_ops davinci_pcm_ops = { + .open = davinci_pcm_open, + .close = davinci_pcm_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = davinci_pcm_hw_params, + .hw_free = davinci_pcm_hw_free, + .pointer = davinci_pcm_pointer, + .copy = davinci_pcm_copy, +}; + +static u64 davinci_pcm_dmamask = 0xffffffff; + +static irqreturn_t dm_vc_irq(int irq, void *sbst) +{ + struct snd_pcm_substream *substream = + (struct snd_pcm_substream *) sbst; + int fifo, diff, per_size, buf_size; + static int last_ptr; + + if (substream->runtime && substream->runtime->status && + snd_pcm_running(substream)) { + fifo = __raw_readl(IO_ADDRESS(0x01D0C028)); + fifo = (fifo & 0x1f00) >> 8; + if (fifo == 15) { + /* peripheral blocked! restart */ + __raw_writel(0, IO_ADDRESS(0x01D0C004)); + __raw_writel(0x5400, IO_ADDRESS(0x01D0C004)); + } + buf_size = substream->runtime->buffer_size; + per_size = substream->runtime->period_size; + for (; fifo < 0x10; fifo++) { + __raw_writew(local_buffer[pointer_sub++], + IO_ADDRESS(0x01D0C024)); + pointer_sub %= buf_size; + do { + diff = __raw_readl(IO_ADDRESS(0x01D0C00C)); + } while (!(diff & 0x8)); + } + if (last_ptr >= pointer_sub) + diff = buf_size + pointer_sub - last_ptr; + else + diff = pointer_sub - last_ptr; + if (diff >= per_size) { + snd_pcm_period_elapsed(substream); + last_ptr += per_size; + if (last_ptr >= buf_size) + last_ptr -= buf_size; + } + } else + last_ptr = 0; + return IRQ_HANDLED; +} + +static int davinci_pcm_new(struct snd_card *card, + struct snd_soc_dai *dai, struct snd_pcm *pcm) +{ + int tcr, tgcr; + struct snd_dma_buffer *buf; + struct snd_pcm_substream *substream; + struct clk *clk; + + if (!card->dev->dma_mask) + card->dev->dma_mask = &davinci_pcm_dmamask; + if (!card->dev->coherent_dma_mask) + card->dev->coherent_dma_mask = 0xffffffff; + + if (dai->playback.channels_min) { + substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; + buf = &substream->dma_buffer; + buf->dev.type = SNDRV_DMA_TYPE_DEV; + buf->dev.dev = pcm->card->dev; + buf->private_data = NULL; + buf->bytes = pcm_hardware_playback.buffer_bytes_max; + } + clk = clk_get(NULL, TIMER); + if (IS_ERR(clk)) + printk(KERN_ERR "ERROR getting timer\n"); + + /* Disabled, Internal clock source */ + __raw_writel(0, IO_ADDRESS(TIMER_BASE + TCR)); + + /* reset both timers, no pre-scaler for timer34 */ + tgcr = 0; + __raw_writel(tgcr, IO_ADDRESS(TIMER_BASE + TGCR)); + + /* Set both timers to unchained 32-bit */ + tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; + __raw_writel(tgcr, IO_ADDRESS(TIMER_BASE + TGCR)); + + /* Unreset timers */ + tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT); + __raw_writel(tgcr, IO_ADDRESS(TIMER_BASE + TGCR)); + + /* Init both counters to zero */ + __raw_writel(0, IO_ADDRESS(TIMER_BASE + TIM12)); + tcr = __raw_readl(IO_ADDRESS(TIMER_BASE + TCR)); + + /* disable timer */ + tcr &= ~(TCR_ENAMODE_MASK << 6); + __raw_writel(tcr, IO_ADDRESS(TIMER_BASE + TCR)); + + /* reset counter to zero, set new period */ + __raw_writel(0, IO_ADDRESS(TIMER_BASE + TIM12)); + __raw_writel(0x8000, IO_ADDRESS(TIMER_BASE + PRD12)); + + /* Set enable mode */ + tcr |= TCR_ENAMODE_PERIODIC << 6; + __raw_writel(tcr, IO_ADDRESS(TIMER_BASE + TCR)); + +#if (TIMER_BASE == TIMER4_BASE) + __raw_writel(__raw_readl(IO_ADDRESS(0x01c40018)) | + 0x1000, IO_ADDRESS(0x01c40018)); +#endif + if (request_irq(TINT, dm_vc_irq, IRQF_TIMER, "VOICE-TOUT", substream)) + printk(KERN_ERR "%s ERROR requesting Interrupt\n", __func__); + return 0; +} + +struct snd_soc_platform davinci_soc_platform_copy = { + .name = "davinci-audio-copy", + .pcm_ops = &davinci_pcm_ops, + .pcm_new = davinci_pcm_new, +}; EXPORT_SYMBOL_GPL(davinci_soc_platform_copy); + +static int __init davinci_soc_copy_platform_init(void) +{ + return snd_soc_register_platform(&davinci_soc_platform_copy); +} +module_init(davinci_soc_copy_platform_init); + +static void __exit davinci_soc_copy_platform_exit(void) +{ + snd_soc_unregister_platform(&davinci_soc_platform_copy); +} +module_exit(davinci_soc_copy_platform_exit); + +MODULE_AUTHOR("bticino s.p.a."); +MODULE_DESCRIPTION("TI DAVINCI PCM copy_from_user module"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h index 0764944..cb7c2aa 100644 --- a/sound/soc/davinci/davinci-pcm.h +++ b/sound/soc/davinci/davinci-pcm.h @@ -29,5 +29,6 @@ struct davinci_pcm_dma_params { extern struct snd_soc_platform davinci_soc_platform; +extern struct snd_soc_platform davinci_soc_platform_copy; #endif diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index ad7f952..696e8b3 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -801,7 +801,7 @@ static int soc_pcm_trigger(struct snd_pcm_substream *substream, int cmd) } return 0; } - +#if 0 /* ASoC PCM operations */ static struct snd_pcm_ops soc_pcm_ops = { .open = soc_pcm_open, @@ -811,7 +811,7 @@ static struct snd_pcm_ops soc_pcm_ops = { .prepare = soc_pcm_prepare, .trigger = soc_pcm_trigger, }; - +#endif #ifdef CONFIG_PM /* powers down audio subsystem for suspend */ static int soc_suspend(struct device *dev) @@ -1306,6 +1306,7 @@ static int soc_new_pcm(struct snd_soc_device *socdev, struct snd_pcm *pcm; char new_name[64]; int ret = 0, playback = 0, capture = 0; + struct snd_pcm_ops *soc_pcm_ops; rtd = kzalloc(sizeof(struct snd_soc_pcm_runtime), GFP_KERNEL); if (rtd == NULL) @@ -1335,19 +1336,25 @@ static int soc_new_pcm(struct snd_soc_device *socdev, dai_link->pcm = pcm; pcm->private_data = rtd; - soc_pcm_ops.mmap = platform->pcm_ops->mmap; - soc_pcm_ops.pointer = platform->pcm_ops->pointer; - soc_pcm_ops.ioctl = platform->pcm_ops->ioctl; - soc_pcm_ops.copy = platform->pcm_ops->copy; - soc_pcm_ops.silence = platform->pcm_ops->silence; - soc_pcm_ops.ack = platform->pcm_ops->ack; - soc_pcm_ops.page = platform->pcm_ops->page; + soc_pcm_ops = kmalloc(sizeof(struct snd_pcm_ops), GFP_KERNEL); + soc_pcm_ops->open = soc_pcm_open; + soc_pcm_ops->close = soc_codec_close; + soc_pcm_ops->hw_params = soc_pcm_hw_params; + soc_pcm_ops->hw_free = soc_pcm_hw_free; + soc_pcm_ops->prepare = soc_pcm_prepare; + soc_pcm_ops->trigger = soc_pcm_trigger; + soc_pcm_ops->mmap = platform->pcm_ops->mmap; + soc_pcm_ops->pointer = platform->pcm_ops->pointer; + soc_pcm_ops->ioctl = platform->pcm_ops->ioctl; + soc_pcm_ops->copy = platform->pcm_ops->copy; + soc_pcm_ops->silence = platform->pcm_ops->silence; + soc_pcm_ops->ack = platform->pcm_ops->ack; + soc_pcm_ops->page = platform->pcm_ops->page; if (playback) - snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &soc_pcm_ops); - + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, soc_pcm_ops); if (capture) - snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &soc_pcm_ops); + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, soc_pcm_ops); ret = platform->pcm_new(codec->card, codec_dai, pcm); if (ret < 0) { -- 1.7.0.4 From broonie at opensource.wolfsonmicro.com Wed Jul 14 09:44:14 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Wed, 14 Jul 2010 15:44:14 +0100 Subject: [PATCH] Asoc Davinci Voicecodec: Added support based on copy_from_user instead of DMA In-Reply-To: <1279117691-5467-1-git-send-email-lamiaposta71@gmail.com> References: <1279117691-5467-1-git-send-email-lamiaposta71@gmail.com> Message-ID: <20100714144414.GE31073@rakim.wolfsonmicro.main> On Wed, Jul 14, 2010 at 04:28:10PM +0200, Raffaele Recalcati wrote: > From: Davide Bonfanti > Since DM365 has the same DMA event for McBSP and Voicecodec this two > peripherals cannot be used at the same time. Please try to format your patches as documented in SubmittingPatches - you don't want all this indentation you're introducing in the start of the changelog. There's also other stuff with regard to coding style and so on that it'd be useful for you to look at. > This driver implements Voicecodec without the use of a DMA but with > a copy_from_user. Why is this specific to the voice CODEC? Shouldn't this be generally usable, and wouldn't it be better if the DMA driver were able to do some automatic fallback here so that in cases where DMA can be used it will be? I had thought from the discussion on original submission that the two devices were mutually exclusive for other reasons anyway. > +/* Timer register offsets */ > +#define PID12 0x00 > +#define TIM12 0x10 > +#define TIM34 0x14 > +#define PRD12 0x18 > +#define PRD34 0x1c > +#define TCR 0x20 > +#define TGCR 0x24 This timer stuff all looks rather like it should be in whatever other code manages the timers - as it stands it'll get into a fight with anything else trying to use them. I'd expect something like this to use hrtimers to get high resolution time rather than banging the timer hardware directly. > +int pointer_sub; > +u16 local_buffer[BUF_SIZE/2]; Should BUF_SIZE not be a configuration option, or dynamically configured at runtime? > +/* > + * ppcm = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? > + * &pcm_hardware_playback : &pcm_hardware_capture; > + */ Remove this if it's not used. > + __raw_writel(0x0, IO_ADDRESS(0x01D0C008)); > + __raw_writel(0x7400, IO_ADDRESS(0x01D0C004)); This could do with being substantially clearer... There's quite a few other magic numbers in the code which need fixing. > +static int davinci_pcm_close(struct snd_pcm_substream *substream) > +{ > + struct snd_pcm_runtime *runtime = substream->runtime; > + struct clk *clk; > + > + clk = clk_get(NULL, TIMER); > + if (!IS_ERR(clk)) > + clk_disable(clk); As with your previous patch you're going to be leaking clocks all over - you should be balancing your clk_get() with clk_put(). > +struct snd_soc_platform davinci_soc_platform_copy = { > + .name = "davinci-audio-copy", > + .pcm_ops = &davinci_pcm_ops, > + .pcm_new = davinci_pcm_new, > +}; EXPORT_SYMBOL_GPL(davinci_soc_platform_copy); Fix your formatting here. > +++ b/sound/soc/soc-core.c > @@ -801,7 +801,7 @@ static int soc_pcm_trigger(struct snd_pcm_substream *substream, int cmd) > } > return 0; > } > - > +#if 0 > /* ASoC PCM operations */ > static struct snd_pcm_ops soc_pcm_ops = { > .open = soc_pcm_open, > @@ -811,7 +811,7 @@ static struct snd_pcm_ops soc_pcm_ops = { > .prepare = soc_pcm_prepare, > .trigger = soc_pcm_trigger, > }; > - > +#endif Um....? I'm not entirely sure what this and the rest of the changes in the file are supposed to do but they weren't mentioned at all in the changelog. If this is needed it should be a separate change with a proper changelog explaining what's going on. From rtivy at ti.com Thu Jul 15 12:53:20 2010 From: rtivy at ti.com (Tivy, Robert) Date: Thu, 15 Jul 2010 12:53:20 -0500 Subject: DM355 - 256MB RAM memory issue In-Reply-To: <1279120603.4033.63.camel@tharma-laptop> References: <1278339242.18556.10.camel@tharma-laptop> <1278428415.14942.19703.camel@sax-lx> <1278776129.3931.225.camel@tharma-laptop> <6B8224E84039B140AA662F0BB0361643012BC33E26@dlee04.ent.ti.com> <1279120603.4033.63.camel@tharma-laptop> Message-ID: <6B8224E84039B140AA662F0BB0361643012BD48EB1@dlee04.ent.ti.com> ________________________________ From: Tharmarajan Ganeshan [mailto:tharma at e-consystems.com] Sent: Wednesday, July 14, 2010 8:17 AM To: Tivy, Robert Cc: davinci-linux-open-source at linux.davincidsp.com; maharajan; dhineshkumar Subject: RE: DM355 - 256MB RAM memory issue Hi Robert, I have built the cmemk.ko by running the command 'make debug'. But I could not find any extra messages while loading this cmemk driver. Here I have attached two log files when mem=50M and mem=168M to the kernel. CMEM is reserved with 88M. Regards, Tharmarajan G I don't know why you suspect CMEM here. Both your logs show CMEM being loaded properly - from your "50M" log: cmemk: no version for "struct_module" found: kernel tainted. ioremap_nocache(0x89800000, 109051904)=0xc3880000 allocated heap buffer 0xc3880000 of size 0x3204000 cmem initialized 14 pools between 0x89800000 and 0x90000000 The kernel "panics" don't show any CMEM-related function either. But you do seem to have other problems, here's just a sample of some from your 50M log: insmod: cannot insert `dm350mmap.ko': Bad address (-1): Bad address BusyBox v1.01 (2005.12.18-04:57+0000) multi-call binary Usage: mknod [OPTIONS] NAME TYPE MAJOR MINOR Create a special file (block, character, or pipe). Options: - m create the special file using the specified mode (default a=rw) TYPEs include: b: Make a block (buffered) device. c or u: Make a character (un-buffered) device. p: Make a named pipe. MAJOR and MINOR are ignored for named pipes. insmod: cannot insert `sbull.ko': Bad address (-1): Bad address insmod: cannot insert `musb_hdrc.ko': Bad address (-1): Bad address I don't know anything about those problems, I was just seeing if I could help with what I do know about - CMEM - but I don't see any problems related to CMEM in your logs. Regards, - Rob On Mon, 2010-07-12 at 16:32 -0500, Tivy, Robert wrote: ________________________________ From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Tharmarajan Ganeshan Sent: Saturday, July 10, 2010 8:35 AM To: todd.fischer at ridgerun.com; Ring, Chris Cc: davinci-linux-open-source at linux.davincidsp.com; dhineshkumar; Mohamed Thalib H; maharajan Subject: Re: DM355 - 256MB RAM memory issue Hi Todd and Chris, Thank for your suggestion. We tried the option 'hole in the kernel memory space'. But that is not solving our issue. We tried to reserve memory 30MB at various place in RAM. But these trials does not help us to solve this issue. And also we tried to get the memory for this 5MP image capturing from the CMEM driver. For this we allocated 86MB to CMEM driver. But the kernel is hanging while loading this CMEM driver. Is there any limitation in CMEM driver ? As far as we know there is no limitation on the size of the physical block granted to CMEM. If you'd like to pursue this approach (getting your 5MP image memory from CMEM) then I could help, but would need to see the debug output of the CMEMK kernel module that you say is "hanging while loading this CMEM driver." To produce debug output, build the "debug" version by: % cd /ti/sdo/linuxutils/cmem/src/module % make debug Then 'insmod' this cmemk.ko and observe CMEMK debug output on the Linux console. Regards, - Rob Regards, Tharmarajan G On Tue, 2010-07-06 at 09:00 -0600, Todd Fischer wrote: Tharmarajan, I believe you need to rebuild your codec server with a different memory map. Another idea is to have a hole in the kernel memory space (specify mem= in the kernel command line twice). I am not sure if the kernel version you are using for dm355 supports a hole in the kernel memory space. Todd On Mon, 2010-07-05 at 19:44 +0530, Tharmarajan Ganeshan wrote: Hi All, We are working on a DM355 processor based Development board. The Board has 256MB mDDR RAM and 5MP image sensor MT9P031. We are using the kernel version 2.6.10 We have modified the driver code for capturing 5MP raw image and converting this 5MP raw into YUV. For this 5MP image capturing , we have reserved 30MB. We have allocated 56MB to the CMEM driver. The reserved memory 30MB and the 56MB memory for CMEM are at top of the RAM. We are passing the remaining memory size to the kernel in bootargs as mem=170M. And we are using the NFS rootfilesystem. But we are getting kernel hanging issues while testing the IPNC_APP applications and 5MP still image capturing. Sometimes the kernel is hanging while booting itself. If we reserve the 30MB from the address region 0x83200000 - 0x84FFFFFF and pass the memory size to kernel in bootargs as mem=50M, then we are NOT having any issues in running the applications. But we want to use the exact remaining memory. And also we are not able to program the NAND flash memory in kernel level if we are not passing the mem=50M in bootargs. What could be the cause for this kernel hanging issue ? Are we missing any configurations while building the kernel image ? Our Bootargs is : mem=50M console=ttyS1,115200n8 root=/dev/nfs rootwait rw ip=192.168.1.90:192.168.1.99:192.168.1.1:255.255.255.0 nfsroot=192.168.1.99:/tftpboot/bellatrix_rootfilesystem,nolock eth=00:0C:0C:A0:01:FE v4l2_video_capture=:device=MT9P031 Regards, Tharmarajan G _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -------------- next part -------------- An HTML attachment was scrubbed... URL: From rohan_javed at yahoo.co.uk Fri Jul 16 01:23:05 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Fri, 16 Jul 2010 06:23:05 +0000 (GMT) Subject: Problem with UBIFS In-Reply-To: Message-ID: <929165.73146.qm@web24103.mail.ird.yahoo.com> yup that is right i read it its great thanks --- On Thu, 15/7/10, Steve Chen wrote: From: Steve Chen Subject: Re: Problem with UBIFS To: "rohan tabish" Cc: davinci-linux-open-source at linux.davincidsp.com Date: Thursday, 15 July, 2010, 17:57 On Thu, Jul 15, 2010 at 2:32 AM, rohan tabish wrote: Using sync option solves the problem but it is not recomended According to http://www.linux-mtd.infradead.org/doc/ubifs.html You can use fsync in the application to force write-through for specific files while having write-back as the default for performance. Steve -------------- next part -------------- An HTML attachment was scrubbed... URL: From rohan_javed at yahoo.co.uk Fri Jul 16 04:46:10 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Fri, 16 Jul 2010 09:46:10 +0000 (GMT) Subject: DSP/BIOS Message-ID: <305496.96594.qm@web24101.mail.ird.yahoo.com> Does Git kernel supports DSP/BIOS API from TI. Regard's RT -------------- next part -------------- An HTML attachment was scrubbed... URL: From rohan_javed at yahoo.co.uk Fri Jul 16 05:00:09 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Fri, 16 Jul 2010 10:00:09 +0000 (GMT) Subject: DSP/BIOS Link for GIT Kernel Message-ID: <790971.15697.qm@web24108.mail.ird.yahoo.com> Is there any source for DSP/BIOS/Link for git kernel Regard's RT -------------- next part -------------- An HTML attachment was scrubbed... URL: From nsekhar at ti.com Fri Jul 16 08:24:07 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Fri, 16 Jul 2010 18:54:07 +0530 Subject: [PATCH] DaVinci: dm365: Added clockout2 management. In-Reply-To: <1279117269-5017-1-git-send-email-lamiaposta71@gmail.com> References: <1279117269-5017-1-git-send-email-lamiaposta71@gmail.com> Message-ID: Hello Raffaele, When you submit an Nth version of a patch, can you please put a vN after PATH in the subject? That way it is easier for maintainer to find out the latest version of the patch. On Wed, Jul 14, 2010 at 19:51:09, Raffaele Recalcati wrote: > From: Davide Bonfanti > > Clockout2 is added as a child of pll1_sysclk9, because they have > the same pll divisor. > Added dm365_clkout2_set_rate to properly set clockout2 frequency. > Modified the davinci_set_sysclk_rate function in order > to get the right ancestor. > > This patch has been developed against the > http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git > git tree and tested on bmx board. > > Signed-off-by: Davide Bonfanti > Signed-off-by: Raffaele Recalcati [...] > +static struct clk clkout2_clk = { > + .name = "clkout2", > + .parent = &pll1_sysclk9, > + .flags = CLK_PLL, > + .div_reg = PLLDIV9, div_reg is for sysclks only. Since this is a child of sysclk and not sysclk itself, setting this here would be incorrect. > + .set_rate = davinci_set_sysclk_rate, Shouldn't you be using the newly introduced dm365_clkout2_set_rate here? Thanks, Sekhar From michael.williamson at criticallink.com Fri Jul 16 09:00:57 2010 From: michael.williamson at criticallink.com (Michael Williamson) Date: Fri, 16 Jul 2010 10:00:57 -0400 Subject: [PATCH] davinci: Add MityDSP-L138/MityARM-1808 SOM support Message-ID: This patch adds support for the MityDSP-L138 and MityARM-1808 system on module (SOM) under the registered machine "mityomapl138". These SOMs are based on the da850 davinci CPU architecture. Information on these SOMs may be found at http://www.mitydsp.com. Signed-off-by: Michael Williamson --- Adding ARM PORT list for requested ATAG_PERIPHERAL in /arch/arm/include/asm/setup.h diff --git a/arch/arm/configs/mityomapl138_defconfig b/arch/arm/configs/mityomapl138_defconfig new file mode 100644 index 0000000..513b851 --- /dev/null +++ b/arch/arm/configs/mityomapl138_defconfig @@ -0,0 +1,1764 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.34-rc1 +# Thu Apr 22 09:46:57 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +CONFIG_ARCH_DAVINCI=y +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_CP_INTC=y + +# +# TI DaVinci Implementations +# + +# +# DaVinci Core Type +# +# CONFIG_ARCH_DAVINCI_DM644x is not set +# CONFIG_ARCH_DAVINCI_DM355 is not set +# CONFIG_ARCH_DAVINCI_DM646x is not set +# CONFIG_ARCH_DAVINCI_DA830 is not set +CONFIG_ARCH_DAVINCI_DA850=y +CONFIG_DA8XX_MAX_SPEED_300=y +# CONFIG_DA8XX_MAX_SPEED_372 is not set +# CONFIG_DA8XX_MAX_SPEED_408 is not set +# CONFIG_DA8XX_MAX_SPEED_456 is not set +CONFIG_ARCH_DAVINCI_DA8XX=y +# CONFIG_ARCH_DAVINCI_DM365 is not set + +# +# DaVinci Board Type +# +# CONFIG_MACH_DAVINCI_DA850_EVM is not set +CONFIG_MACH_MITYOMAPL138=y +CONFIG_DAVINCI_MUX=y +CONFIG_DAVINCI_MUX_DEBUG=y +CONFIG_DAVINCI_MUX_WARNINGS=y +CONFIG_DAVINCI_RESET_CLOCKS=y +# CONFIG_DAVINCI_MCBSP is not set + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_CPU_DCACHE_WRITETHROUGH=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=m +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +CONFIG_MTD_DEBUG=y +CONFIG_MTD_DEBUG_VERBOSE=0 +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_FTL=y +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_CFI_AMDSTD is not set +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_DAVINCI_NOR is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_NAND_DAVINCI=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=32768 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_LXT_PHY=y +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +CONFIG_LSI_ET1011C_PHY=y +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +CONFIG_TI_DAVINCI_EMAC=y +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +CONFIG_KEYBOARD_XTKBD=m +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_DAVINCI=y +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_DAVINCI=y +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_PCA953X=y +# CONFIG_GPIO_PCA953X_IRQ is not set +CONFIG_GPIO_PCF857X=y +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_DAVINCI_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507x is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB4500_CORE is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +CONFIG_REGULATOR_TPS65023=y +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_DAVINCI is not set +# CONFIG_FB_VIRTUAL is not set +CONFIG_FB_DA8XX=y +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=m +CONFIG_BACKLIGHT_GENERIC=m + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +CONFIG_NOP_USB_XCEIV=y +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_OMAP=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=m +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=m +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index f392fb4..d6b1a47 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -143,6 +143,11 @@ struct tag_memclk { __u32 fmemclk; }; +/** MityDSP-L138 peripheral configuration info, + * see arch/arm/mach-davinci/include/mach/cb-mityomapl138.h + */ +#define ATAG_PERIPHERALS 0x42000101 + struct tag { struct tag_header hdr; union { diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 71f90f8..064b0e2 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -178,6 +178,13 @@ config DA850_UI_RMII endchoice +config MACH_MITYOMAPL138 + bool "Critical Link MityOMAPL138 SoM" + depends on ARCH_DAVINCI_DA850 + select GPIO_PCA953X + help + Say Y here to select the Critical Link MityOMAP-L138 System on Module. + config MACH_TNETV107X bool "TI TNETV107X Reference Platform" default ARCH_DAVINCI_TNETV107X diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index eab4c0f..dfc0fc4 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o +obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o # Power Management diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c new file mode 100644 index 0000000..c110daa --- /dev/null +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -0,0 +1,817 @@ +/* + * Critical Link MityOMAP-L138 SoM + * + * Copyright (C) 2010 Critical Link Incorporated - http://www.criticallink.com + * + * Derived from board-da850-evm.c + * Original Copyrights follow: + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from: arch/arm/mach-davinci/board-da830-evm.c + * Original Copyrights follow: + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct tag_peripherals peripheral_config = { + .Version = PERIPHERALS_VERSION, + .Manufacturer = "Critical Link", + .ENETConfig.EnetConfig = ENET_CONFIG_MII, + .ENETConfig.MACAddr = { 0x00, 0x50, 0xC2, 0x49, 0xDF, 0xFF }, + .UARTConfig[0] = { + .Enable = 0, + .IsConsole = 0, + .Baud = 115200, + }, + .UARTConfig[1] = { + .Enable = 1, + .IsConsole = 1, + .Baud = 115200, + }, + .UARTConfig[2] = { + .Enable = 0, + .IsConsole = 0, + .Baud = 115200, + }, + .SPIConfig[0] = { + .Enable = 0, + .CLKOut = 0, + .CSEnable = { 0, 0, 0, 0, 0, 0, 0, 0}, + .ENAEnable = 0, + .CLKRate = 0, + }, + .SPIConfig[1] = { + .Enable = 1, + .CLKOut = 1, + .CSEnable = { 1, 0, 0, 0, 0, 0, 0, 0}, + .ENAEnable = 0, + .CLKRate = 30000000, + }, + .LCDConfig = { + .Enable = 0, + .PanelName = "", + } +}; + + +#define MITYOMAPL138_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ + +#define MSTPRI2_LCD_MASK 0x70000000 +#define MSTPRI2_LCD_SHIFT 28 + +#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) +#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) + +/* MityDSP-L138 includes a 256 MByte large-page NAND flash + * (128K blocks). + */ +struct mtd_partition mityomapl138_nandflash_partition[] = { + { + .name = "rootfs", + .offset = 0, + .size = SZ_128M, + .mask_flags = 0, /* MTD_WRITEABLE, */ + }, + { + .name = "homefs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct davinci_nand_pdata mityomapl138_nandflash_data = { + .parts = mityomapl138_nandflash_partition, + .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16, + .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ +}; + +static struct resource mityomapl138_nandflash_resource[] = { + { + .start = DA8XX_AEMIF_CS3_BASE, + .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mityomapl138_nandflash_device = { + .name = "davinci_nand", + .id = 0, + .dev = { + .platform_data = &mityomapl138_nandflash_data, + }, + .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), + .resource = mityomapl138_nandflash_resource, +}; + +static struct platform_device *mityomapl138_devices[] __initdata = { + &mityomapl138_nandflash_device, +}; + +static __init void mityomapl138_setup_nand(void) +{ + + platform_add_devices(mityomapl138_devices, + ARRAY_SIZE(mityomapl138_devices)); +} + +static int mityomapl138_mmc_get_ro(int index) +{ + return gpio_get_value(DA850_MMCSD_WP_PIN); +} + +static int mityomapl138_mmc_get_cd(int index) +{ + return !gpio_get_value(DA850_MMCSD_CD_PIN); +} + +static struct davinci_mmc_config da850_mmc_config = { + .get_ro = mityomapl138_mmc_get_ro, + .get_cd = mityomapl138_mmc_get_cd, + .wires = 4, + .max_freq = 50000000, + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + .version = MMC_CTLR_VERSION_2, +}; + +static __init void mityomapl138_setup_mmc(void) +{ + int ret; + + ret = davinci_cfg_reg_list(da850_mmcsd0_pins); + if (ret) + pr_warning("mityomapl138_setup_mmc: mmcsd0 mux setup failed:" + " %d\n", ret); + + ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n"); + if (ret) + pr_warning("mityomapl138_setup_mmc: can not open GPIO %d\n", + DA850_MMCSD_CD_PIN); + gpio_direction_input(DA850_MMCSD_CD_PIN); + + ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n"); + if (ret) + pr_warning("mityomapl138_setup_mmc: can not open GPIO %d\n", + DA850_MMCSD_WP_PIN); + gpio_direction_input(DA850_MMCSD_WP_PIN); + + ret = da8xx_register_mmcsd0(&da850_mmc_config); + if (ret) + pr_warning("da850_evm_init: mmcsd0 registration failed:" + " %d\n", ret); +} + + +static struct davinci_uart_config mityomapl138_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static int __init mityomapl138_config_emac(void) +{ + void __iomem *cfg_chip3_base; + int ret; + u32 val; + struct davinci_soc_info *soc_info = &davinci_soc_info; + u8 rmii_en = 0; + + switch (peripheral_config.ENETConfig.EnetConfig) { + case ENET_CONFIG_RMII: + soc_info->emac_pdata->rmii_en = 1; + rmii_en = 1; + break; + case ENET_CONFIG_MII: + soc_info->emac_pdata->rmii_en = 0; + rmii_en = 0; + break; + case ENET_CONFIG_NONE: + default: + pr_info("EMAC: No Ethernet PHY Selected, EMAC disabled\n"); + return 0; /* no enet... */ + break; + } + memcpy(&soc_info->emac_pdata->mac_addr[0], + &peripheral_config.ENETConfig.MACAddr[0], 6); + + cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); + + val = __raw_readl(cfg_chip3_base); + + if (rmii_en) { + val |= BIT(8); + ret = davinci_cfg_reg_list(da850_rmii_pins); + pr_info("EMAC: RMII PHY configured, MII PHY will not be" + " functional\n"); + } else { + val &= ~BIT(8); + ret = davinci_cfg_reg_list(da850_cpgmac_pins); + pr_info("EMAC: MII PHY configured, RMII PHY will not be" + " functional\n"); + } + + if (ret) + pr_warning("mityomapl138_init: cpgmac/rmii mux setup failed: %d\n", + ret); + + /* configure the CFGCHIP3 register for RMII or MII */ + __raw_writel(val, cfg_chip3_base); + + soc_info->emac_pdata->phy_mask = peripheral_config.ENETConfig.PHYMask ? + peripheral_config.ENETConfig.PHYMask : 1; + pr_info("mityomapl138_init: setting phy_mask to %x\n", + soc_info->emac_pdata->phy_mask); + soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY; + + ret = da8xx_register_emac(); + if (ret) + pr_warning("mityomapl138_init: emac registration failed: %d\n", + ret); + + return 0; +} +device_initcall(mityomapl138_config_emac); + +static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { + .bus_freq = 100, /* kHz */ + .bus_delay = 0, /* usec */ +}; + +/* TPS65070 voltage regulator support */ + +/* 1.2V Core */ +struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { + { + .supply = "cvdd", + }, +}; + +/* 1.8V */ +struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { + { + .supply = "usb0_vdda18", + }, + { + .supply = "usb1_vdda18", + }, + { + .supply = "ddr_dvdd18", + }, + { + .supply = "sata_vddr", + }, +}; + +/* 1.2V */ +struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { + { + .supply = "sata_vdd", + }, + { + .supply = "usb_cvdd", + }, + { + .supply = "pll0_vdda", + }, + { + .supply = "pll1_vdda", + }, +}; + +/* 1.8V Aux LDO */ +struct regulator_consumer_supply tps65023_ldo1_consumers[] = { + { + .supply = "1.8v_aux", + }, +}; + +/* VCC Aux (1.8 or 3.3) LDO */ +struct regulator_consumer_supply tps65023_ldo2_consumers[] = { + { + .supply = "vccaux", + }, +}; + + +struct regulator_init_data tps65023_regulator_data[] = { + /* dcdc1 */ + { + .constraints = { + .min_uV = 1150000, + .max_uV = 1350000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers), + .consumer_supplies = tps65023_dcdc1_consumers, + }, + + /* dcdc2 */ + { + .constraints = { + .min_uV = 1710000, + .max_uV = 1910000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers), + .consumer_supplies = tps65023_dcdc2_consumers, + }, + + /* dcdc3 */ + { + .constraints = { + .min_uV = 1120000, + .max_uV = 1320000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers), + .consumer_supplies = tps65023_dcdc3_consumers, + }, + + /* ldo1 */ + { + .constraints = { + .min_uV = 1710000, + .max_uV = 1890000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers), + .consumer_supplies = tps65023_ldo1_consumers, + }, + + /* ldo2 */ + { + .constraints = { + .min_uV = 3140000, + .max_uV = 3420000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers), + .consumer_supplies = tps65023_ldo2_consumers, + }, +}; + + +static struct i2c_board_info __initdata mityomap_tps65023_info[] = { + { + I2C_BOARD_INFO("tps65023", 0x48), + .platform_data = &tps65023_regulator_data[0], + }, + { + I2C_BOARD_INFO("24c02", 0x50), + }, +}; + +static int __init pmic_tps65023_init(void) +{ + return i2c_register_board_info(1, mityomap_tps65023_info, + ARRAY_SIZE(mityomap_tps65023_info)); +} + +static struct davinci_spi_platform_data mityomap_spi1_pdata = { + .version = SPI_VERSION_2, + .num_chipselect = 1, + .wdelay = 0, + .odd_parity = 0, + .parity_enable = 0, + .wait_enable = 0, + .timer_disable = 0, + .clk_internal = 1, + .cs_hold = 1, + .intr_level = 0, + .poll_mode = 1, + .use_dma = 0, + .c2tdelay = 8, + .t2cdelay = 8, +}; + +static struct resource mityomap_spi1_resources[] = { + [0] = { + .start = 0x01F0E000, + .end = 0x01F0EFFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DA8XX_SPINT1, + .start = IRQ_DA8XX_SPINT1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = EDMA_CTLR_CHAN(0, 18), + .end = EDMA_CTLR_CHAN(0, 18), + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = EDMA_CTLR_CHAN(0, 19), + .end = EDMA_CTLR_CHAN(0, 19), + .flags = IORESOURCE_DMA, + }, + [4] = { + .start = 1, + .end = 1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device mityomap_spi1_device = { + .name = "spi_davinci", + .id = 1, + .dev = { + .platform_data = &mityomap_spi1_pdata, + }, + .num_resources = ARRAY_SIZE(mityomap_spi1_resources), + .resource = mityomap_spi1_resources, +}; + +/***************************************************************************** + * SPI Devices: + * SPI1_CS0: 8M Flash ST-M25P64-VME6G + ****************************************************************************/ +static struct mtd_partition spi_flash_partitions[] = { + [0] = { + .name = "UBL", + .offset = 0, + .size = SZ_64K, + .mask_flags = MTD_WRITEABLE + }, + [1] = { + .name = "U-Boot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = 0, + }, + [2] = { + .name = "Spare", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct flash_platform_data mityomap_spi_flash_data = { + .name = "m25p80", + .parts = spi_flash_partitions, + .nr_parts = ARRAY_SIZE(spi_flash_partitions), + .type = "m25p64", +}; + +static struct spi_board_info mityomap_spi_flash_info[] = { + { + .modalias = "m25p80", + .platform_data = &mityomap_spi_flash_data, + .mode = SPI_MODE_0, + .max_speed_hz = 30000000, + .bus_num = 1, + .chip_select = 0, + }, +}; + +void __init mityomap_init_spi1(unsigned chipselect_mask, + struct spi_board_info *info, unsigned len) +{ + int ret; + ret = platform_device_register(&mityomap_spi1_device); + if (ret) + pr_warning("mityomap_init_spi1 failed to register " + "spi device : %d\n", ret); + + ret = spi_register_board_info(info, len); + if (ret) + pr_warning("mityomap_init_spi1 failed to register " + "board info : %d\n", ret); +} + +/* davinci da850 evm audio machine driver */ +static u8 da850_iis_serializer_direction[] = { + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static struct snd_platform_data mityomapl138_snd_data = { + .tx_dma_offset = 0x2000, + .rx_dma_offset = 0x2000, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), + .tdm_slots = 0, + .serial_dir = da850_iis_serializer_direction, + .eventq_no = EVENTQ_1, + .version = MCASP_VERSION_2, + .txnumevt = 0, + .rxnumevt = 0, +}; + +short mityomapl138_mcasp_pins[24] __initdata = { + DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, + DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, + DA850_AMUTE, + -1, -1, -1, -1, + -1, -1, -1, -1, + -1, -1, -1, -1, + -1, -1, -1, -1, + -1 +}; + +static __init int mityomapl138_setup_mcasp(void) +{ + int ret; + + mityomapl138_mcasp_pins[7+0] = DA850_AXR_13; + da850_iis_serializer_direction[12] = TX_MODE; + + ret = davinci_cfg_reg_list(mityomapl138_mcasp_pins); + if (ret) + pr_warning("mityomapl138_setup_mcasp: mcasp mux setup failed:" + "%d\n", ret); + + mityomapl138_snd_data.tdm_slots = 2; + mityomapl138_snd_data.txnumevt = 1; + + da8xx_register_mcasp(0, &mityomapl138_snd_data); + + return ret; +} + +static const struct display_panel disp_panel = { + QVGA, + 16, + 16, + COLOR_ACTIVE, +}; + +static struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 255, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 0, + .invert_frm_clock = 0, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + +static struct da8xx_lcdc_platform_data sharp_lq035q7dh06_pdata = { + .manu_name = "sharp", + .controller_data = &lcd_cfg, + .type = "Sharp_LQ035Q7DH06", +}; + +static struct da8xx_lcdc_platform_data chimei_p0430wqlb_pdata = { + .manu_name = "ChiMei", + .controller_data = &lcd_cfg, + .type = "ChiMei_P0430WQLB", +}; + +static struct da8xx_lcdc_platform_data vga_640x480_pdata = { + .manu_name = "VGA", + .controller_data = &lcd_cfg, + .type = "vga_640x480", +}; + +static struct resource da8xx_lcdc_resources[] = { + [0] = { /* registers */ + .start = DA8XX_LCD_CNTRL_BASE, + .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { /* interrupt */ + .start = IRQ_DA8XX_LCDINT, + .end = IRQ_DA8XX_LCDINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_lcdc_device = { + .name = "da8xx_lcdc", + .id = 0, + .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), + .resource = da8xx_lcdc_resources, + .dev = { + .platform_data = &sharp_lq035q7dh06_pdata, + } +}; + +static __init void mityomapl138_setup_lcd(void) +{ + int ret; + + if (peripheral_config.LCDConfig.Enable) { + u32 prio; + + /* set peripheral master priority up to 1 */ + prio = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_MSTPRI2_REG)); + prio &= ~MSTPRI2_LCD_MASK; + prio |= 1<u.cmdline.cmdline[0]; + memcpy(&peripheral_config, ptag, sizeof(peripheral_config)); + pr_info("Peripheral Config Block Found\n"); + pr_info("Enet_Config = %d\n", peripheral_config.ENETConfig.EnetConfig); + pr_info("EMAC = %02X:%02X:%02X:%02X:%02X:%02X\n", + peripheral_config.ENETConfig.MACAddr[0], + peripheral_config.ENETConfig.MACAddr[1], + peripheral_config.ENETConfig.MACAddr[2], + peripheral_config.ENETConfig.MACAddr[3], + peripheral_config.ENETConfig.MACAddr[4], + peripheral_config.ENETConfig.MACAddr[5]); + pr_info("PHYMask = 0x%x\n", peripheral_config.ENETConfig.PHYMask); + if (peripheral_config.LCDConfig.Enable) + pr_info("LCD Configured : %s\n", + peripheral_config.LCDConfig.PanelName); + else + pr_info("No LCD Configured\n"); + + for (i = 0; i < 3; i++) { + pr_info("UART[%d] = %d, %d, %d, %d\n", i, + peripheral_config.UARTConfig[i].Enable, + peripheral_config.UARTConfig[i].IsConsole, + peripheral_config.UARTConfig[i].EnableHWFlowCtrl, + peripheral_config.UARTConfig[i].Baud); + } + for (i = 0; i < 2; i++) { + int mask = 0; + for (j = 0; j < 8; j++) + mask |= ((peripheral_config.SPIConfig[i].CSEnable[j]) ? + (1<> 18) & 0xfffc, + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = mityomapl138_map_io, + .init_irq = cp_intc_init, + .timer = &davinci_timer, + .init_machine = mityomapl138_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h new file mode 100644 index 0000000..7ba085a --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h @@ -0,0 +1,125 @@ +/** + * Factory / Peripheral Configuration Data as provided by ATAG_PERIPHERAL + * for the MityDSP-L138 SOMs. (mityomapl138 machines) + * + * Copyright (C) 2010 Critical Link LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef CONFIG_BLOCK_H_ +#define CONFIG_BLOCK_H_ + +#define CONFIG_MAGIC_WORD 0x00BD0138 +#define CONFIG_VERSION 0x00010000 + +#define ENET_CONFIG_NONE 1 +#define ENET_CONFIG_MII 2 +#define ENET_CONFIG_RMII 3 + +#define CONFIG_I2C_MAGIC_WORD 0x012C0138 +#define CONFIG_I2C_VERSION 0x00010001 + +/** + * Peripherals Version History + * 1.00 Baseline + * 1.01 Added McASP Configuration + * 1.02 Added ethernet phy mask + */ +#define PERIPHERALS_VERSION 0x00010002 + +#ifndef CONFIG_MITYDSP_ENV_SIZE +#define CONFIG_MITYDSP_ENV_SIZE (64 << 10) +#endif + +#define FPGATYPE_NONE 0 +#define FPGATYPE_XC6SLX9 1 +#define FPGATYPE_XC6SLX16 2 +#define FPGATYPE_XC6SLX25 3 +#define FPGATYPE_XC6SLX45 4 +#define FPGATYPE_UNKNOWN 10000 + +struct I2CFactoryConfig { + u32 ConfigMagicWord; /** CONFIG_I2C_MAGIC_WORD */ + u32 ConfigVersion; /** CONFIG_I2C_VERSION */ + u8 MACADDR[6]; /** mac address assigned to part */ + u32 FpgaType; /** fpga installed, see above */ + u32 Spare; /** Not Used */ + u32 SerialNumber; /** serial number of part */ + char PartNumber[32]; /** board part number */ +}; + +struct UARTConfig { + u8 Enable; /** enable Tx/Rx */ + u8 IsConsole; /** cfg as the console */ + u8 EnableHWFlowCtrl; /** cfg CTS/RTS */ + u32 Baud; /** default baud rate */ +}; + +struct SPIConfig { + u8 Enable; /** cfg dev+CLK, SIMO, SOMI pins */ + u8 CLKOut; /** drive the CLK */ + u8 CSEnable[8]; /** cfg the associated CS as output */ + u8 ENAEnable; /** cfg the ENA pin for SPI function */ + u32 CLKRate; /** default clock rate */ + u8 Spare[8]; +}; + +struct LCDConfig { + u8 Enable; + u8 PanelName[32]; +}; + +struct ENETConfig { + u32 EnetConfig; + u8 MACAddr[6]; + u32 PHYMask; + u8 Spare[8]; +}; + +#define MCASP_PINMODE_INACTIVE 0 +#define MCASP_PINMODE_TX 1 +#define MCASP_PINMODE_RX 2 + +struct MCASPConfig { + u8 Enable; + u8 Mode; + u8 PinMode[16]; +}; +/** + * struct tag_peripherals is passed in via kernel ATAG_PERIPHERALS + */ +struct tag_peripherals { + u32 Version; /** == PERIPHERALS_VERSION */ + u8 Manufacturer[64]; /** null terminated string indicating manufacturer */ + struct ENETConfig ENETConfig; /** Enable on-board ethernet */ + struct UARTConfig UARTConfig[3]; /** default UART 0,1,2 Configuration */ + struct SPIConfig SPIConfig[2]; + struct LCDConfig LCDConfig; + struct MCASPConfig MCASPConfig; +}; + +/** + * This structure can only be grown. You cannot make it smaller... + */ +struct MityDSPL138Config { + u32 ConfigMagicWord; /** == CONFIG_MAGIC_WORD */ + u32 ConfigVersion; /** version of the configuration block */ + u32 ConfigSizeBytes; /** configuration size, in bytes */ + struct tag_peripherals Peripherals; +}; + +struct MityDSPL138ConfigBlock { + union { + struct MityDSPL138Config config; + u8 space[CONFIG_MITYDSP_ENV_SIZE-sizeof(int)]; + } Data; + unsigned int CheckSum; /** summed bytes of ConfigSizeBytes */ +}; + +extern struct MityDSPL138Config config_block; +extern struct I2CFactoryConfig factory_config_block; +extern int get_config_block(void); +extern int get_factory_config_block(void); + +#endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 1b31a9a..1989316 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -41,6 +41,7 @@ extern void __iomem *da8xx_syscfg1_base; #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) #define DA8XX_JTAG_ID_REG 0x18 +#define DA8XX_MSTPRI2_REG 0x118 #define DA8XX_CFGCHIP0_REG 0x17c #define DA8XX_CFGCHIP2_REG 0x184 #define DA8XX_CFGCHIP3_REG 0x188 diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 15a6192..db6f1cd 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -88,6 +88,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* DA8xx boards */ DEBUG_LL_DA8XX(davinci_da830_evm, 2); DEBUG_LL_DA8XX(davinci_da850_evm, 2); + DEBUG_LL_DA8XX(mityomapl138, 1); /* TNETV107x boards */ DEBUG_LL_TNETV107X(tnetv107x, 1); From lamiaposta71 at gmail.com Fri Jul 16 09:46:57 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Fri, 16 Jul 2010 16:46:57 +0200 Subject: [PATCH 1/3] ASoC: soc-core: soc_pcm_ops dynamically allocated In-Reply-To: <1279291619-5081-1-git-send-email-lamiaposta71@gmail.com> References: <1279291619-5081-1-git-send-email-lamiaposta71@gmail.com> Message-ID: <1279291619-5081-2-git-send-email-lamiaposta71@gmail.com> From: Davide Bonfanti If soc_pcm_ops is statically allocated, more than one call to soc_new_pcm cause operations overwrite. The problem is overcome usyng dynamic allocation. Signed-off-by: Davide Bonfanti Signed-off-by: Raffaele Recalcati --- sound/soc/soc-core.c | 38 +++++++++++++++++--------------------- 1 files changed, 17 insertions(+), 21 deletions(-) diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index ad7f952..6500686 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -801,17 +801,6 @@ static int soc_pcm_trigger(struct snd_pcm_substream *substream, int cmd) } return 0; } - -/* ASoC PCM operations */ -static struct snd_pcm_ops soc_pcm_ops = { - .open = soc_pcm_open, - .close = soc_codec_close, - .hw_params = soc_pcm_hw_params, - .hw_free = soc_pcm_hw_free, - .prepare = soc_pcm_prepare, - .trigger = soc_pcm_trigger, -}; - #ifdef CONFIG_PM /* powers down audio subsystem for suspend */ static int soc_suspend(struct device *dev) @@ -1306,6 +1295,7 @@ static int soc_new_pcm(struct snd_soc_device *socdev, struct snd_pcm *pcm; char new_name[64]; int ret = 0, playback = 0, capture = 0; + struct snd_pcm_ops *soc_pcm_ops; rtd = kzalloc(sizeof(struct snd_soc_pcm_runtime), GFP_KERNEL); if (rtd == NULL) @@ -1335,19 +1325,25 @@ static int soc_new_pcm(struct snd_soc_device *socdev, dai_link->pcm = pcm; pcm->private_data = rtd; - soc_pcm_ops.mmap = platform->pcm_ops->mmap; - soc_pcm_ops.pointer = platform->pcm_ops->pointer; - soc_pcm_ops.ioctl = platform->pcm_ops->ioctl; - soc_pcm_ops.copy = platform->pcm_ops->copy; - soc_pcm_ops.silence = platform->pcm_ops->silence; - soc_pcm_ops.ack = platform->pcm_ops->ack; - soc_pcm_ops.page = platform->pcm_ops->page; + soc_pcm_ops = kmalloc(sizeof(struct snd_pcm_ops), GFP_KERNEL); + soc_pcm_ops->open = soc_pcm_open; + soc_pcm_ops->close = soc_codec_close; + soc_pcm_ops->hw_params = soc_pcm_hw_params; + soc_pcm_ops->hw_free = soc_pcm_hw_free; + soc_pcm_ops->prepare = soc_pcm_prepare; + soc_pcm_ops->trigger = soc_pcm_trigger; + soc_pcm_ops->mmap = platform->pcm_ops->mmap; + soc_pcm_ops->pointer = platform->pcm_ops->pointer; + soc_pcm_ops->ioctl = platform->pcm_ops->ioctl; + soc_pcm_ops->copy = platform->pcm_ops->copy; + soc_pcm_ops->silence = platform->pcm_ops->silence; + soc_pcm_ops->ack = platform->pcm_ops->ack; + soc_pcm_ops->page = platform->pcm_ops->page; if (playback) - snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &soc_pcm_ops); - + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, soc_pcm_ops); if (capture) - snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &soc_pcm_ops); + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, soc_pcm_ops); ret = platform->pcm_new(codec->card, codec_dai, pcm); if (ret < 0) { -- 1.7.0.4 From lamiaposta71 at gmail.com Fri Jul 16 09:46:58 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Fri, 16 Jul 2010 16:46:58 +0200 Subject: [PATCH 2/3] ASoC: DaVinci: Added support based on copy_from_user instead of DMA In-Reply-To: <1279291619-5081-1-git-send-email-lamiaposta71@gmail.com> References: <1279291619-5081-1-git-send-email-lamiaposta71@gmail.com> Message-ID: <1279291619-5081-3-git-send-email-lamiaposta71@gmail.com> From: Davide Bonfanti This driver implements a pcm interface without the use of a DMA but with a copy_from_user. There's a buffer in the driver that is filled with davinci_pcm_copy. When pcm is running, a TIMER interrupt is activated in order to fill HW FIFO. BUG: It happens sometimes that the peripheral stops working so there's a trap. This patch has been developed against the http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git git tree and tested on bmx board. Signed-off-by: Davide Bonfanti Signed-off-by: Raffaele Recalcati --- sound/soc/davinci/Makefile | 1 + sound/soc/davinci/davinci-pcm-copy.h | 52 +++++ sound/soc/davinci/davinci-pcm-copyfromuser.c | 278 ++++++++++++++++++++++++++ sound/soc/davinci/davinci-pcm.h | 1 + 4 files changed, 332 insertions(+), 0 deletions(-) create mode 100644 sound/soc/davinci/davinci-pcm-copy.h create mode 100644 sound/soc/davinci/davinci-pcm-copyfromuser.c diff --git a/sound/soc/davinci/Makefile b/sound/soc/davinci/Makefile index a93679d..7d6a9a1 100644 --- a/sound/soc/davinci/Makefile +++ b/sound/soc/davinci/Makefile @@ -1,5 +1,6 @@ # DAVINCI Platform Support snd-soc-davinci-objs := davinci-pcm.o +snd-soc-davinci-objs += davinci-pcm-copyfromuser.o snd-soc-davinci-i2s-objs := davinci-i2s.o snd-soc-davinci-mcasp-objs:= davinci-mcasp.o snd-soc-davinci-vcif-objs:= davinci-vcif.o diff --git a/sound/soc/davinci/davinci-pcm-copy.h b/sound/soc/davinci/davinci-pcm-copy.h new file mode 100644 index 0000000..c143fb3 --- /dev/null +++ b/sound/soc/davinci/davinci-pcm-copy.h @@ -0,0 +1,52 @@ +/* + * + * Copyright (C) 2010 Bticino S.p.a + * Author: Davide Bonfanti + * + * Contributors: + * Raffaele Recalcati + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _DAVINCI_PCM_COPY_H +#define _DAVINCI_PCM_COPY_H + +struct davinci_pcm_copy_ops { + /* called to perform initial settings - optional */ + void (*init)(void); + /* called to enable codec - mandatory */ + void (*enable)(void); + /* called to push one data into hw_fifo - mandatory */ + void (*write)(u16); + /* called to wait hw_fifo is ready for more data - optional */ + void (*wait_fifo_ready)(void); + /* called to get hw_fifo size - mandatory */ + int (*get_fifo_size)(void); + /* called to get number of samples already into the hw_fifo */ + int (*get_fifo_status)(void); +}; + +struct davinci_pcm_copy_platform_data { + /* length required for samples buffer in bytes */ + int buffer_size; + /* minimum time in ps between an interrupt and another */ + int min_interrupt_interval_ps; + /* + * margin between next interrupt occurrency and hw_fifo end_of_play + * using loaded samples + */ + int interrupt_margin_ps; + /* codec operations as explained above */ + struct davinci_pcm_copy_ops *ops; +}; + +#endif /* _DAVINCI_PCM_COPY_H */ diff --git a/sound/soc/davinci/davinci-pcm-copyfromuser.c b/sound/soc/davinci/davinci-pcm-copyfromuser.c new file mode 100644 index 0000000..7494afe --- /dev/null +++ b/sound/soc/davinci/davinci-pcm-copyfromuser.c @@ -0,0 +1,278 @@ +/* + * + * Copyright (C) 2010 Bticino S.p.a + * Author: Davide Bonfanti + * + * Contributors: + * Raffaele Recalcati + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "davinci-pcm.h" +#include "davinci-pcm-copy.h" + +#define DEF_BUF_SIZE 2048 +#define DEF_MIN_INT 500000 +#define DEF_INT_MARGIN 500000 + +int pointer_sub; +int hw_fifo_size; +u16 *local_buffer; +static struct hrtimer hrtimer; +struct snd_pcm_substream *substream_loc; +int ns_for_interrupt = 1500000; +int min_interrupt_ps; +int interrupt_margin; + +struct davinci_pcm_copy_ops *ops; + +static struct snd_pcm_hardware pcm_hardware_playback = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER), + .formats = (SNDRV_PCM_FMTBIT_S16_LE), + .rates = (SNDRV_PCM_RATE_8000), + .rate_min = 8000, + .rate_max = 8000, + .channels_min = 1, + .channels_max = 1, + .period_bytes_min = 512, + .period_bytes_max = 512, + .fifo_size = 0, +}; + +/* + * How this driver works... + * + * This driver implements a pcm interface without the use of a DMA but with + * a copy_from_user. + * There's a buffer of {platform_data->buffer_size} bytes in the driver + * that is filled with davinci_pcm_copy. + * When pcm is running, a TIMER interrupt is activated in order to fill + * HW FIFO. + * It happens that the peripheral stop working so there's a trap... + */ + +static snd_pcm_uframes_t +davinci_pcm_pointer(struct snd_pcm_substream *substream) +{ + return pointer_sub; +} + +static int davinci_pcm_open(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_pcm_hardware *ppcm; + static ktime_t wakeups_per_second; + int ret = 0; + + pointer_sub = 0; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + ppcm = &pcm_hardware_playback; + else + return -ENODEV; + + snd_soc_set_runtime_hwparams(substream, ppcm); + /* ensure that buffer size is a multiple of period size */ + ret = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) + return ret; + + hrtimer_start(&hrtimer, wakeups_per_second, HRTIMER_MODE_REL); + ops->enable(); + return 0; +} + +static int davinci_pcm_close(struct snd_pcm_substream *substream) +{ + hrtimer_cancel(&hrtimer); + return 0; +} + +static int davinci_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params) +{ + long rate; + + rate = hw_params->rate_num * hw_params->rate_den; + rate = hw_params->msbits * (1000000000 / rate); + + /* let's take some margin of */ + rate -= interrupt_margin; + + /* assure the interrupt doesn't occupy too many resources */ + ns_for_interrupt = rate > min_interrupt_ps ? rate : min_interrupt_ps; + + return snd_pcm_lib_malloc_pages(substream, + params_buffer_bytes(hw_params)); +} + +static int davinci_pcm_hw_free(struct snd_pcm_substream *substream) +{ + return snd_pcm_lib_free_pages(substream); +} + +static int davinci_pcm_copy(struct snd_pcm_substream *substream, int channel, + snd_pcm_uframes_t hwoff, void __user *buf, snd_pcm_uframes_t frames) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + + if (copy_from_user(local_buffer + hwoff, buf, + frames_to_bytes(runtime, frames))) { + printk(KERN_ERR "ERROR COPY_FROM_USER\n"); + return -EFAULT; + } + return 0; +} + +static struct snd_pcm_ops davinci_pcm_ops = { + .open = davinci_pcm_open, + .close = davinci_pcm_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = davinci_pcm_hw_params, + .hw_free = davinci_pcm_hw_free, + .pointer = davinci_pcm_pointer, + .copy = davinci_pcm_copy, +}; + +static u64 davinci_pcm_dmamask = 0xffffffff; + +static enum hrtimer_restart dm_vc_irq(struct hrtimer *handle) +{ + int fifo, diff, per_size, buf_size; + static int last_ptr; + gpio_set_value(69, 1); + + if (substream_loc->runtime && substream_loc->runtime->status && + snd_pcm_running(substream_loc)) { + fifo = ops->get_fifo_status(); + if (fifo >= (hw_fifo_size - 1)) + ops->enable(); + + buf_size = substream_loc->runtime->buffer_size; + per_size = substream_loc->runtime->period_size; + for (; fifo < hw_fifo_size; fifo++) { + ops->write(local_buffer[pointer_sub++]); + pointer_sub %= buf_size; + if (ops->wait_fifo_ready) + ops->wait_fifo_ready(); + } + if (last_ptr >= pointer_sub) + diff = buf_size + pointer_sub - last_ptr; + else + diff = pointer_sub - last_ptr; + if (diff >= per_size) { + snd_pcm_period_elapsed(substream_loc); + last_ptr += per_size; + if (last_ptr >= buf_size) + last_ptr -= buf_size; + } + } else + last_ptr = 0; + hrtimer_add_expires_ns(&hrtimer, ns_for_interrupt); + gpio_set_value(69, 0); + return HRTIMER_RESTART; +} + +static int davinci_pcm_new(struct snd_card *card, + struct snd_soc_dai *dai, struct snd_pcm *pcm) +{ + struct snd_dma_buffer *buf; + struct snd_pcm_substream *substream; + + if (!card->dev->dma_mask) + card->dev->dma_mask = &davinci_pcm_dmamask; + if (!card->dev->coherent_dma_mask) + card->dev->coherent_dma_mask = 0xffffffff; + + gpio_direction_output(69, 0); + + if (dai->playback.channels_min) { + substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; + buf = &substream->dma_buffer; + buf->dev.type = SNDRV_DMA_TYPE_DEV; + buf->dev.dev = pcm->card->dev; + buf->private_data = NULL; + buf->bytes = pcm_hardware_playback.buffer_bytes_max; + substream_loc = substream; + } + hrtimer_init(&hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + hrtimer.function = dm_vc_irq; + + return 0; +} + +int davinci_pcm_probe(struct platform_device *pdev) +{ + struct snd_soc_device *dev = platform_get_drvdata(pdev); + struct davinci_pcm_copy_platform_data *data; + + data = dev->codec_data; + ops = data->ops; + + if ((!ops) || (!ops->enable) || (!ops->write) || + (!ops->get_fifo_size) || (!ops->get_fifo_status)) + return -EINVAL; + min_interrupt_ps = data->min_interrupt_interval_ps ? + data->min_interrupt_interval_ps : DEF_MIN_INT; + interrupt_margin = data->interrupt_margin_ps ? + data->interrupt_margin_ps : DEF_INT_MARGIN; + pcm_hardware_playback.buffer_bytes_max = data->buffer_size ? + data->buffer_size : DEF_BUF_SIZE; + pcm_hardware_playback.periods_min = data->buffer_size / 512; + pcm_hardware_playback.periods_max = data->buffer_size / 512; + local_buffer = kmalloc(data->buffer_size, GFP_KERNEL); + if (ops->init) + ops->init(); + hw_fifo_size = ops->get_fifo_size(); + + return 0; +} + +struct snd_soc_platform davinci_soc_platform_copy = { + .name = "davinci-audio-copy", + .pcm_ops = &davinci_pcm_ops, + .pcm_new = davinci_pcm_new, + .probe = davinci_pcm_probe, +}; +EXPORT_SYMBOL_GPL(davinci_soc_platform_copy); + +static int __init davinci_soc_copy_platform_init(void) +{ + return snd_soc_register_platform(&davinci_soc_platform_copy); +} +module_init(davinci_soc_copy_platform_init); + +static void __exit davinci_soc_copy_platform_exit(void) +{ + snd_soc_unregister_platform(&davinci_soc_platform_copy); +} +module_exit(davinci_soc_copy_platform_exit); + +MODULE_AUTHOR("bticino s.p.a."); +MODULE_DESCRIPTION("TI DAVINCI PCM copy_from_user module"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h index 0764944..cb7c2aa 100644 --- a/sound/soc/davinci/davinci-pcm.h +++ b/sound/soc/davinci/davinci-pcm.h @@ -29,5 +29,6 @@ struct davinci_pcm_dma_params { extern struct snd_soc_platform davinci_soc_platform; +extern struct snd_soc_platform davinci_soc_platform_copy; #endif -- 1.7.0.4 From lamiaposta71 at gmail.com Fri Jul 16 09:46:59 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Fri, 16 Jul 2010 16:46:59 +0200 Subject: [PATCH 3/3] ASoC: DaVinci: Voicecodec: Added support based on davinci-pcm-copyfromuser In-Reply-To: <1279291619-5081-1-git-send-email-lamiaposta71@gmail.com> References: <1279291619-5081-1-git-send-email-lamiaposta71@gmail.com> Message-ID: <1279291619-5081-4-git-send-email-lamiaposta71@gmail.com> From: Davide Bonfanti The driver uses the pcm implementation without the use of DMA in order to support Voicecodec (cq93vc). Signed-off-by: Davide Bonfanti Signed-off-by: Raffaele Recalcati --- sound/soc/davinci/Makefile | 3 + sound/soc/davinci/cq93vc_copy.c | 130 +++++++++++++++++++++++++++++++++++++++ sound/soc/davinci/cq93vc_copy.h | 26 ++++++++ 3 files changed, 159 insertions(+), 0 deletions(-) create mode 100644 sound/soc/davinci/cq93vc_copy.c create mode 100644 sound/soc/davinci/cq93vc_copy.h diff --git a/sound/soc/davinci/Makefile b/sound/soc/davinci/Makefile index 7d6a9a1..44c17ad 100644 --- a/sound/soc/davinci/Makefile +++ b/sound/soc/davinci/Makefile @@ -1,6 +1,7 @@ # DAVINCI Platform Support snd-soc-davinci-objs := davinci-pcm.o snd-soc-davinci-objs += davinci-pcm-copyfromuser.o +snd-soc-davinci-objs += cq93vc_copy.o snd-soc-davinci-i2s-objs := davinci-i2s.o snd-soc-davinci-mcasp-objs:= davinci-mcasp.o snd-soc-davinci-vcif-objs:= davinci-vcif.o @@ -13,9 +14,11 @@ obj-$(CONFIG_SND_DAVINCI_SOC_VCIF) += snd-soc-davinci-vcif.o # DAVINCI Machine Support snd-soc-evm-objs := davinci-evm.o snd-soc-sffsdr-objs := davinci-sffsdr.o +snd-soc-bmx-objs := davinci-bmx.o obj-$(CONFIG_SND_DAVINCI_SOC_EVM) += snd-soc-evm.o obj-$(CONFIG_SND_DM6467_SOC_EVM) += snd-soc-evm.o obj-$(CONFIG_SND_DA830_SOC_EVM) += snd-soc-evm.o obj-$(CONFIG_SND_DA850_SOC_EVM) += snd-soc-evm.o obj-$(CONFIG_SND_DAVINCI_SOC_SFFSDR) += snd-soc-sffsdr.o +obj-$(CONFIG_SND_DAVINCI_SOC_BMX) += snd-soc-bmx.o diff --git a/sound/soc/davinci/cq93vc_copy.c b/sound/soc/davinci/cq93vc_copy.c new file mode 100644 index 0000000..41747dd --- /dev/null +++ b/sound/soc/davinci/cq93vc_copy.c @@ -0,0 +1,130 @@ +/* + * + * Copyright (C) 2010 Bticino S.p.a + * Author: Davide Bonfanti + * + * Contributors: + * Raffaele Recalcati + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "davinci-pcm-copy.h" +#include "cq93vc_copy.h" + +#define DAVINCI_VOICECODEC_MODULE_BASE 0x01D0C000 +#define VC_PID 0x00 +#define VC_CTRL 0x04 +#define VC_INTEN 0x08 +#define VC_INTSTATUS 0x0C +#define VC_INTCLR 0x10 +#define VC_EMUL_CTRL 0x14 +#define RFIFO 0x20 +#define WFIFO 0x24 +#define FIFOSTAT 0x28 +#define VC_REG00 0x80 +#define VC_REG01 0x84 +#define VC_REG02 0x88 +#define VC_REG03 0x8C +#define VC_REG04 0x90 +#define VC_REG05 0x94 +#define VC_REG06 0x98 +#define VC_REG09 0xA4 +#define VC_REG10 0xA8 +#define VC_REG12 0xB0 + +/* bit definitions */ +#define VC_CTRL_WFIFOMD BIT(14) +#define VC_CTRL_WFIFOCL BIT(13) +#define VC_CTRL_WFIFOEN BIT(12) +#define VC_CTRL_RFIFOMD BIT(10) +#define VC_CTRL_RFIFOCL BIT(9) +#define VC_CTRL_RFIFOEN BIT(8) +#define VC_CTRL_WDUNSIGNED BIT(7) +#define VC_CTRL_WDSIZE BIT(6) +#define VC_CTRL_RDUNSIGNED BIT(5) +#define VC_CTRL_RDSIZE BIT(4) +#define VC_CTRL_RSTDAC BIT(1) +#define VC_CTRL_RSTADC BIT(0) + +#define VC_INTSTATUS_WDREQ BIT(3) + +#define FIFOSTAT_WDATACOUNT_MASK 0x1F00 +#define FIFOSTAT_WDATACOUNT_OFFSET 8 + +#define HW_FIFO_SIZE 0x10 + +void __iomem *voice_codec_base; + +void cq93vc_enable(void) +{ + __raw_writel(0, voice_codec_base + VC_CTRL); + __raw_writel(0, voice_codec_base + VC_INTEN); + __raw_writel(VC_CTRL_RFIFOMD | VC_CTRL_WFIFOEN | + VC_CTRL_WFIFOMD, voice_codec_base + VC_CTRL); +} + +void cq93vc_write(u16 data) +{ + __raw_writew(data, voice_codec_base + WFIFO); +} + +void cq93vc_wait_fifo_ready(void) +{ + u32 diff; + do { + diff = __raw_readl(voice_codec_base + VC_INTSTATUS); + } while (!(diff & VC_INTSTATUS_WDREQ)); +} + +int cq93vc_get_fifo_size(void) +{ + return HW_FIFO_SIZE; +} + +int cq93vc_get_fifo_status(void) +{ + int fifo; + fifo = __raw_readl(voice_codec_base + FIFOSTAT); + fifo = (fifo & FIFOSTAT_WDATACOUNT_MASK) >> FIFOSTAT_WDATACOUNT_OFFSET; + return fifo; +} + +void cq93vc_init(void) +{ + voice_codec_base = ioremap(DAVINCI_VOICECODEC_MODULE_BASE, SZ_4K); + +} + +struct davinci_pcm_copy_ops cq93vc_pcm_copy_ops = { + .enable = cq93vc_enable, + .write = cq93vc_write, + .wait_fifo_ready = cq93vc_wait_fifo_ready, + .get_fifo_size = cq93vc_get_fifo_size, + .get_fifo_status = cq93vc_get_fifo_status, + .init = cq93vc_init, +}; +EXPORT_SYMBOL_GPL(cq93vc_pcm_copy_ops); diff --git a/sound/soc/davinci/cq93vc_copy.h b/sound/soc/davinci/cq93vc_copy.h new file mode 100644 index 0000000..bcc4458 --- /dev/null +++ b/sound/soc/davinci/cq93vc_copy.h @@ -0,0 +1,26 @@ +/* + * + * Copyright (C) 2010 Bticino S.p.a + * Author: Davide Bonfanti + * + * Contributors: + * Raffaele Recalcati + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _DAVINCI_CQ93VC_COPY_H +#define _DAVINCI_CQ93VC_COPY_H +#include "davinci-pcm-copy.h" + +extern struct davinci_pcm_copy_ops cq93vc_pcm_copy_ops; + +#endif /* _DAVINCI_CQ93VC_COPY_H */ -- 1.7.0.4 From broonie at opensource.wolfsonmicro.com Fri Jul 16 10:09:48 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Fri, 16 Jul 2010 16:09:48 +0100 Subject: [PATCH 1/3] ASoC: soc-core: soc_pcm_ops dynamically allocated In-Reply-To: <1279291619-5081-2-git-send-email-lamiaposta71@gmail.com> References: <1279291619-5081-1-git-send-email-lamiaposta71@gmail.com> <1279291619-5081-2-git-send-email-lamiaposta71@gmail.com> Message-ID: <20100716150948.GA23183@rakim.wolfsonmicro.main> On Fri, Jul 16, 2010 at 04:46:57PM +0200, Raffaele Recalcati wrote: > If soc_pcm_ops is statically allocated, more than one call to soc_new_pcm > cause operations overwrite. The problem is overcome usyng dynamic > allocation. As I said previously you're looking for Liam's multi-component work here rather than this (or at least should be basing your work off his). From lamiaposta71 at gmail.com Fri Jul 16 10:25:19 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Fri, 16 Jul 2010 17:25:19 +0200 Subject: [PATCH 1/3] ASoC: soc-core: soc_pcm_ops dynamically allocated In-Reply-To: <20100716150948.GA23183@rakim.wolfsonmicro.main> References: <1279291619-5081-1-git-send-email-lamiaposta71@gmail.com> <1279291619-5081-2-git-send-email-lamiaposta71@gmail.com> <20100716150948.GA23183@rakim.wolfsonmicro.main> Message-ID: 2010/7/16 Mark Brown > On Fri, Jul 16, 2010 at 04:46:57PM +0200, Raffaele Recalcati wrote: > > > If soc_pcm_ops is statically allocated, more than one call to > soc_new_pcm > > cause operations overwrite. The problem is overcome usyng dynamic > > allocation. > > As I said previously you're looking for Liam's multi-component work > here rather than this (or at least should be basing your work off his). > ok. For us it is better to have also more feedback from you about the other two patches. So the next patchset we'll submit shall be more complete. Thx -------------- next part -------------- An HTML attachment was scrubbed... URL: From broonie at opensource.wolfsonmicro.com Fri Jul 16 10:35:28 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Fri, 16 Jul 2010 16:35:28 +0100 Subject: [PATCH 1/3] ASoC: soc-core: soc_pcm_ops dynamically allocated In-Reply-To: References: <1279291619-5081-1-git-send-email-lamiaposta71@gmail.com> <1279291619-5081-2-git-send-email-lamiaposta71@gmail.com> <20100716150948.GA23183@rakim.wolfsonmicro.main> Message-ID: <20100716153528.GA23205@rakim.wolfsonmicro.main> On Fri, Jul 16, 2010 at 05:25:19PM +0200, Raffaele Recalcati wrote: > For us it is better to have also more feedback from you about the other two > patches. > So the next patchset we'll submit shall be more complete. Sure - those are bigger and take longer to read, should get to them by the end of the weekend at least. From lrg at slimlogic.co.uk Sat Jul 17 12:28:53 2010 From: lrg at slimlogic.co.uk (Liam Girdwood) Date: Sat, 17 Jul 2010 18:28:53 +0100 Subject: [PATCH] asoc: davinci: let platform data define edma queue numbers In-Reply-To: <1279196059-6031-1-git-send-email-nsekhar@ti.com> References: <1279196059-6031-1-git-send-email-nsekhar@ti.com> Message-ID: <1279387733.3070.0.camel@odin> On Thu, 2010-07-15 at 17:44 +0530, Sekhar Nori wrote: > Currently the EDMA queue to be used by for servicing ASP through > internal RAM is fixed to EDMAQ_0 and that to service internal RAM > from external RAM is fixed to EDMAQ_1. > > This may not be the desirable configuration on all platforms. For > example, on DM365, queue 0 has large fifo size and is more suitable > for video transfers. Having audio and video transfers on the same > queue may lead to starvation on audio side. > > platform data as defined currently passes a queue number to the driver > but that remains unused inside the driver. > > Fix this by defining one queue each for ASP and RAM transfers in the > platform data and using it inside the driver. > > Since EDMAQ_0 maps to 0, thats the queue that will be used if > the asp queue number is not initialized. None of the platforms > currently utilize ping-pong transfers through internal RAM so that > functionality remains unchanged too. > > This patch has been tested on DM644x and OMAP-L138 EVMs. > > Signed-off-by: Sekhar Nori Acked-by: Liam Girdwood -- Freelance Developer, SlimLogic Ltd ASoC and Voltage Regulator Maintainer. http://www.slimlogic.co.uk From broonie at opensource.wolfsonmicro.com Sat Jul 17 13:50:19 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Sat, 17 Jul 2010 19:50:19 +0100 Subject: [PATCH] asoc: davinci: let platform data define edma queue numbers In-Reply-To: <1279196059-6031-1-git-send-email-nsekhar@ti.com> References: <1279196059-6031-1-git-send-email-nsekhar@ti.com> Message-ID: <20100717185018.GC27456@rakim.wolfsonmicro.main> On Thu, Jul 15, 2010 at 05:44:19PM +0530, Sekhar Nori wrote: > This patch has been tested on DM644x and OMAP-L138 EVMs. > Signed-off-by: Sekhar Nori > This patch applies to latest of Linus's tree. ...so it doesn't apply against my for-2.6.36 branch (and obviously there's crossover with Kevin's tree as well which makes things possibly a bit interesting too). Could you please regenerate against for-2.6.36? You should generally always send patches against the latest version of code rather than Linus' tree, using other trees increases the chances that your patch will not apply. From amraldo at hotmail.com Sun Jul 18 02:31:20 2010 From: amraldo at hotmail.com (amr ali) Date: Sun, 18 Jul 2010 10:31:20 +0300 Subject: fb problem Message-ID: Hi All, I am trying to run angstrom file system with linux kernel 2.6.32. I do not see the start up screen and I can't get the ownership of the an osd window. This is the boot log related to the fb: " davincifb davincifb: dm_osd0_fb: 720x576x16 at 0,0 with framebuffer size 2025KB davincifb davincifb: dm_vid0_fb: 0x0x16 at 0,0 with framebuffer size 2500KB davincifb davincifb: dm_osd1_fb: 720x576x4 at 0,0 with framebuffer size 810KB davincifb davincifb: dm_vid1_fb: 720x576x16 at 0,0 with framebuffer size 2500KB davincifb davincifb.0: dm_osd0_fb: Failed to obtain ownership of OSD window. " -- Amr Ali Abdel-Naby Embedded Systems Developer www.embedded-tips.blogspot.com _________________________________________________________________ Hotmail: Free, trusted and rich email service. https://signup.live.com/signup.aspx?id=60969 -------------- next part -------------- An HTML attachment was scrubbed... URL: From caglarakyuz at gmail.com Sun Jul 18 12:19:07 2010 From: caglarakyuz at gmail.com (Caglar Akyuz) Date: Sun, 18 Jul 2010 20:19:07 +0300 Subject: fb problem In-Reply-To: References: Message-ID: <201007182019.07466.caglarakyuz@gmail.com> On Sunday 18 July 2010 10:31:20 am amr ali wrote: > Hi All, > I am trying to run angstrom file system with linux kernel 2.6.32. > I do not see the start up screen and I can't get the ownership of the an > osd window. This is the boot log related to the fb: > " > davincifb davincifb: dm_osd0_fb: 720x576x16 at 0,0 with framebuffer size > 2025KB davincifb davincifb: dm_vid0_fb: 0x0x16 at 0,0 with framebuffer size > 2500KB davincifb davincifb: dm_osd1_fb: 720x576x4 at 0,0 with framebuffer > size 810KB davincifb davincifb: dm_vid1_fb: 720x576x16 at 0,0 with > framebuffer size 2500KB davincifb davincifb.0: dm_osd0_fb: Failed to > obtain ownership of OSD window. " Hi, This is a false negative. I guess this is from the arago tree; driver at that tree is probes fb device twice for the reasons I don't know hence driver cannot take the ownership of the device for the second time. It is harmless. framebuffer driver is working at this stage. You have some other problem, probably display related. Regards, Caglar > -- > Amr Ali Abdel-Naby > Embedded Systems Developer > www.embedded-tips.blogspot.com > > > > _________________________________________________________________ > Hotmail: Free, trusted and rich email service. > https://signup.live.com/signup.aspx?id=60969 > From michael.williamson at criticallink.com Sun Jul 18 12:29:32 2010 From: michael.williamson at criticallink.com (Mike Williamson) Date: Sun, 18 Jul 2010 13:29:32 -0400 Subject: [PATCH] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: <1279324167.4526.85.camel@Joe-Laptop.home> References: <1279324167.4526.85.camel@Joe-Laptop.home> Message-ID: 2010/7/16 Joe Perches > On Fri, 2010-07-16 at 10:00 -0400, Michael Williamson wrote: > > +static __init void mityomapl138_setup_lcd(void) > > +{ > [] > > + pr_warning("mityomapl138_init: unknown LCD type : > %s\n", > > + peripheral_config.LCDConfig.PanelName); > > I think you'd be better off actually using the actual > function name rather than the caller name > > pr_warning("%s: unknown LCD type: %s\n", > __func__, > peripheral_config.LCDConfig.PanelName); > > Absolutely. Didn't catch those when shuffling around during cleanup / etc. I will clean these up and resubmit. Thank you for the feedback. -Mike -- Michael Williamson 315-425-4045x230 www.criticallink.com -------------- next part -------------- An HTML attachment was scrubbed... URL: From amraldo at hotmail.com Sun Jul 18 14:06:59 2010 From: amraldo at hotmail.com (amr ali) Date: Sun, 18 Jul 2010 22:06:59 +0300 Subject: fb problem In-Reply-To: <201007182019.07466.caglarakyuz@gmail.com> References: , <201007182019.07466.caglarakyuz@gmail.com> Message-ID: This is what I found out after sending the email. The fb device is probed twice: one from the device driver itself and the other from the board file under the arch file. What could be wrong with the display. I tried to start the xorg then run any gui program but no output on the screen. Any clues? -- Amr Ali Abdel-Naby Embedded Systems Developer www.embedded-tips.blogspot.com > From: caglarakyuz at gmail.com > To: davinci-linux-open-source at linux.davincidsp.com > Subject: Re: fb problem > Date: Sun, 18 Jul 2010 20:19:07 +0300 > CC: amraldo at hotmail.com > > On Sunday 18 July 2010 10:31:20 am amr ali wrote: > > Hi All, > > I am trying to run angstrom file system with linux kernel 2.6.32. > > I do not see the start up screen and I can't get the ownership of the an > > osd window. This is the boot log related to the fb: > > " > > davincifb davincifb: dm_osd0_fb: 720x576x16 at 0,0 with framebuffer size > > 2025KB davincifb davincifb: dm_vid0_fb: 0x0x16 at 0,0 with framebuffer size > > 2500KB davincifb davincifb: dm_osd1_fb: 720x576x4 at 0,0 with framebuffer > > size 810KB davincifb davincifb: dm_vid1_fb: 720x576x16 at 0,0 with > > framebuffer size 2500KB davincifb davincifb.0: dm_osd0_fb: Failed to > > obtain ownership of OSD window. " > > Hi, > > This is a false negative. I guess this is from the arago tree; driver at that > tree is probes fb device twice for the reasons I don't know hence driver > cannot take the ownership of the device for the second time. It is harmless. > framebuffer driver is working at this stage. > > You have some other problem, probably display related. > > Regards, > Caglar > > > -- > > Amr Ali Abdel-Naby > > Embedded Systems Developer > > www.embedded-tips.blogspot.com > > > > > > > > _________________________________________________________________ > > Hotmail: Free, trusted and rich email service. > > https://signup.live.com/signup.aspx?id=60969 > > _________________________________________________________________ Hotmail: Trusted email with Microsoft?s powerful SPAM protection. https://signup.live.com/signup.aspx?id=60969 -------------- next part -------------- An HTML attachment was scrubbed... URL: From caglarakyuz at gmail.com Sun Jul 18 14:35:01 2010 From: caglarakyuz at gmail.com (Caglar AKYUZ) Date: Sun, 18 Jul 2010 22:35:01 +0300 Subject: fb problem In-Reply-To: References: <201007182019.07466.caglarakyuz@gmail.com> Message-ID: 2010/7/18 amr ali > This is what I found out after sending the email. > The fb device is probed twice: one from the device driver itself and the > other from the board file under the arch file. > What could be wrong with the display. I tried to start the xorg then run > any gui program but no output on the screen. > Any clues? > > You can try enabling framebuffer console. What type of display are you using? Caglar -------------- next part -------------- An HTML attachment was scrubbed... URL: From david-b at pacbell.net Sun Jul 18 15:52:13 2010 From: david-b at pacbell.net (David Brownell) Date: Sun, 18 Jul 2010 13:52:13 -0700 (PDT) Subject: [PATCH v2] rtc: omap: let device wakeup capability be configured from chip init logic In-Reply-To: Message-ID: <389061.41765.qm@web180310.mail.gq1.yahoo.com> --- On Wed, 6/16/10, Nori, Sekhar wrote: > Date: Wednesday, June 16, 2010, 9:46 PM > Hi Dave, > > Any thoughts on my responses below? If you are > satisfied, would you please Ack my patch? I don't have time to properly review it. If it works, go for it ... bugs can be fixed later, and the principle behind the patch is fine. From grant.likely at secretlab.ca Mon Jul 19 00:09:34 2010 From: grant.likely at secretlab.ca (Grant Likely) Date: Sun, 18 Jul 2010 23:09:34 -0600 Subject: [PATCH v4 1/1] davinci: spi: replace existing driver In-Reply-To: <1278628745-18502-2-git-send-email-bniebuhr@efjohnson.com> References: <1278628745-18502-1-git-send-email-bniebuhr@efjohnson.com> <1278628745-18502-2-git-send-email-bniebuhr@efjohnson.com> Message-ID: <20100719050934.GA5949@angua.secretlab.ca> On Thu, Jul 08, 2010 at 05:39:05PM -0500, Brian Niebuhr wrote: > INTRODUCTION > > I have been working on a custom OMAP-L138 board that has multiple spi > devices (seven) on one controller. These devices have a wide range of > transfer parameters (speed, phase, polarity, internal and gpio chip > selects). During my testing I found multiple errors in the davinci spi > driver as a result of this complex setup. The primary issues were: > > 1. There is a race condition due to the SPIBUF read busy-waits for slow > devices > 2. I found some DMA transfer length errors under some conditions > 3. The chip select code caused extra byte transfers (with no chip > select active) due to writes to SPIDAT1 > 4. Several issues prevented using multiple SPI devices, especially > the DMA code, as disucussed previously on the davinci list. > > The fixes to these problems were not simple. I ended up making fairly > large changes to the driver, and those changes are contained in these > patches. The full list of changes follows. > > CHANGE LIST > > 1. davinci_spi_chipelect() now performs both activation and deactivation > of chip selects. This lets spi_bitbang fully control chip > select activation, as intended by the SPI API. > 2. Chip select activation does not cause extra writes to the SPI bus > 3. Chip select activation does not use SPIDEF for control. This change > will also allow for implementation of inverted (active high) > chip selects in the future. > 4. Added back gpio chip select capability from the old driver > 5. Fixed prescale calculation for non-integer fractions of spi clock > 6. Allow specification of SPI transfer parameters on a per-device > (instead of per-controller) basis > 7. Allow specification of polled, interrupt-based, or DMA operation on > a per-device basis > 8. Allow DMA with when more than one device is connected > 9. Combined pio and dma txrx_bufs functions into one since they share > large parts of their functionality, and to simplify item (8). > 10. Use only SPIFMT0 to allow more than 4 devices > > TESTING > > I have tested the driver using a custom SPI stress test on my > OMAP-L138-based board with three devices connected. I have tested > configurations with all three devices polled, all three interrupt-based, > all three DMA, and a mixture. > > I have compiled with the davinci_all_defconfig, but I don't have EVMs > for the other davinci platforms to test with. > > Signed-off-by: Brian Niebuhr Hi Brian, A couple of minor comments below, but overall the patch looks pretty sane, and I can probably pick it up after one more respin, and assuming I receive Acks for this version from the davinci folks. *However* the way this patch has been approached does make it very hard to know whether or not it is a good patch. Yes, I understand that a lot of the behaviour of the driver was rewritten, and yes I understand that it is easier to just do one big diff from the old and new (and don't get me wrong, this is still better than two patches; one to remove the old and one to add the new). That doesn't change the fact that there are still logical steps/changes to get from the old to the new. For instance, I can immediately see the following discrete changes that really belong in there own patches: a) the changes to spi_driver->driver, b) the __devinit/__devexit annotation changes, c) the prescale calculation fixes, d) the conditional usage of tx and rx buffers in davinci_spi_*_buf_*(). Probably the data structure changes could be handled separately too. By not keeping the discrete changes separate you are making it harder to get your code merged. Plus, when you keep things separate, I can merge the patches that look good while asking for rework on the others. The only reason I'm even considering picking it up is because it is for a driver with limited impact, and the primary users have been saying that it is a good thing. If this patch touched core or SPI infrastructure code, then I'd nack it out of hand because I cannot understand it. > --- > arch/arm/mach-davinci/board-dm355-evm.c | 10 + > arch/arm/mach-davinci/board-dm355-leopard.c | 10 + > arch/arm/mach-davinci/board-dm365-evm.c | 10 + > arch/arm/mach-davinci/dm355.c | 8 +- > arch/arm/mach-davinci/dm365.c | 6 - > arch/arm/mach-davinci/include/mach/spi.h | 35 +- > drivers/spi/davinci_spi.c | 1112 ++++++++++++--------------- > 7 files changed, 528 insertions(+), 663 deletions(-) > > diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c > index a319101..ad8779b 100644 > --- a/arch/arm/mach-davinci/board-dm355-evm.c > +++ b/arch/arm/mach-davinci/board-dm355-evm.c > @@ -32,6 +32,7 @@ > #include > #include > #include > +#include > > /* NOTE: this is geared for the standard config, with a socketed > * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you > @@ -300,10 +301,19 @@ static struct spi_eeprom at25640a = { > .flags = EE_ADDR2, > }; > > +static struct davinci_spi_config at25640a_spi_cfg = { > + .parity_enable = false, > + .intr_level = 0, > + .io_type = SPI_IO_TYPE_DMA, > + .wdelay = 0, > + .timer_disable = true, > +}; > + > static struct spi_board_info dm355_evm_spi_info[] __initconst = { > { > .modalias = "at25", > .platform_data = &at25640a, > + .controller_data = &at25640a_spi_cfg, > .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ > .bus_num = 0, > .chip_select = 0, > diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c > index f1d8132..b2d8d48 100644 > --- a/arch/arm/mach-davinci/board-dm355-leopard.c > +++ b/arch/arm/mach-davinci/board-dm355-leopard.c > @@ -29,6 +29,7 @@ > #include > #include > #include > +#include > > /* NOTE: this is geared for the standard config, with a socketed > * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you > @@ -222,10 +223,19 @@ static struct spi_eeprom at25640a = { > .flags = EE_ADDR2, > }; > > +static struct davinci_spi_config at25640a_spi_cfg = { > + .parity_enable = false, > + .intr_level = 0, > + .io_type = SPI_IO_TYPE_DMA, > + .wdelay = 0, > + .timer_disable = true, > +}; > + > static struct spi_board_info dm355_leopard_spi_info[] __initconst = { > { > .modalias = "at25", > .platform_data = &at25640a, > + .controller_data = &at25640a_spi_cfg, > .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ > .bus_num = 0, > .chip_select = 0, > diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c > index 5bb86b2..db85372 100644 > --- a/arch/arm/mach-davinci/board-dm365-evm.c > +++ b/arch/arm/mach-davinci/board-dm365-evm.c > @@ -39,6 +39,7 @@ > #include > #include > #include > +#include > > #include > > @@ -579,10 +580,19 @@ static struct spi_eeprom at25640 = { > .flags = EE_ADDR2, > }; > > +static struct davinci_spi_config at25640_spi_cfg = { > + .parity_enable = false, > + .intr_level = 0, > + .io_type = SPI_IO_TYPE_DMA, > + .wdelay = 0, > + .timer_disable = true, > +}; > + > static struct spi_board_info dm365_evm_spi_info[] __initconst = { > { > .modalias = "at25", > .platform_data = &at25640, > + .controller_data = &at25640_spi_cfg, > .max_speed_hz = 10 * 1000 * 1000, > .bus_num = 0, > .chip_select = 0, > diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c > index 3834781..f747c05 100644 > --- a/arch/arm/mach-davinci/dm355.c > +++ b/arch/arm/mach-davinci/dm355.c > @@ -410,14 +410,8 @@ static struct resource dm355_spi0_resources[] = { > }; > > static struct davinci_spi_platform_data dm355_spi0_pdata = { > - .version = SPI_VERSION_1, > + .version = SPI_VERSION_0, > .num_chipselect = 2, > - .clk_internal = 1, > - .cs_hold = 1, > - .intr_level = 0, > - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ > - .c2tdelay = 0, > - .t2cdelay = 0, > }; > static struct platform_device dm355_spi0_device = { > .name = "spi_davinci", > diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c > index 652f4b6..4aea346 100644 > --- a/arch/arm/mach-davinci/dm365.c > +++ b/arch/arm/mach-davinci/dm365.c > @@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); > static struct davinci_spi_platform_data dm365_spi0_pdata = { > .version = SPI_VERSION_1, > .num_chipselect = 2, > - .clk_internal = 1, > - .cs_hold = 1, > - .intr_level = 0, > - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ > - .c2tdelay = 0, > - .t2cdelay = 0, > }; > > static struct resource dm365_spi0_resources[] = { > diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h > index 910efbf..3f77dab 100644 > --- a/arch/arm/mach-davinci/include/mach/spi.h > +++ b/arch/arm/mach-davinci/include/mach/spi.h > @@ -19,26 +19,35 @@ > #ifndef __ARCH_ARM_DAVINCI_SPI_H > #define __ARCH_ARM_DAVINCI_SPI_H > > +#define SPI_INTERN_CS 0xFF > + > enum { > - SPI_VERSION_1, /* For DM355/DM365/DM6467 */ > + SPI_VERSION_0, /* For DM355 (reduced features, no Tx interrupt) */ > + SPI_VERSION_1, /* For DM365/DM6467 (reduced features) */ > SPI_VERSION_2, /* For DA8xx */ > }; > > struct davinci_spi_platform_data { > u8 version; > - u8 num_chipselect; > - u8 wdelay; > - u8 odd_parity; > - u8 parity_enable; > - u8 wait_enable; > - u8 timer_disable; > - u8 clk_internal; > - u8 cs_hold; > + u16 num_chipselect; > + u8 *chip_sel; > +}; > + > +struct davinci_spi_config { > + bool odd_parity; > + bool parity_enable; > u8 intr_level; > - u8 poll_mode; > - u8 use_dma; > - u8 c2tdelay; > - u8 t2cdelay; > + u8 io_type; > +#define SPI_IO_TYPE_INTR 0 > +#define SPI_IO_TYPE_POLL 1 > +#define SPI_IO_TYPE_DMA 2 > + u8 bytes_per_word; > + u8 wdelay; > + bool timer_disable; > + u8 c2t_delay; > + u8 t2c_delay; > + u8 t2e_delay; > + u8 c2e_delay; > }; > > #endif /* __ARCH_ARM_DAVINCI_SPI_H */ > diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c > index b85090c..931130a 100644 > --- a/drivers/spi/davinci_spi.c > +++ b/drivers/spi/davinci_spi.c > @@ -1,5 +1,6 @@ > /* > * Copyright (C) 2009 Texas Instruments. > + * Copyright (C) 2010 EF Johnson Technologies > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License as published by > @@ -27,21 +28,19 @@ > #include > #include > #include > -#include > > #include > #include > > #define SPI_NO_RESOURCE ((resource_size_t)-1) > > -#define SPI_MAX_CHIPSELECT 2 > - > #define CS_DEFAULT 0xFF > > #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) > -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 > -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 > -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 > + > +#define RX_DMA_INDEX 0 > +#define TX_DMA_INDEX 1 > +#define EVENTQ_DMA_INDEX 2 > > #define SPIFMT_PHASE_MASK BIT(16) > #define SPIFMT_POLARITY_MASK BIT(17) > @@ -53,9 +52,11 @@ > #define SPIFMT_WDELAY_MASK 0x3f000000u > #define SPIFMT_WDELAY_SHIFT 24 > #define SPIFMT_CHARLEN_MASK 0x0000001Fu > +#define SPIFMT_PRESCALE_SHIFT 8 > > /* SPIGCR1 */ > -#define SPIGCR1_SPIENA_MASK 0x01000000u > +#define SPIGCR1_SPIENA_MASK BIT(24) > +#define SPIGCR1_POWERDOWN_MASK BIT(8) > > /* SPIPC0 */ > #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ > @@ -66,20 +67,38 @@ > #define SPIPC0_EN0FUN_MASK BIT(0) > > #define SPIINT_MASKALL 0x0101035F > +#define SPIINT_MASKINT 0x0000035F > #define SPI_INTLVL_1 0x000001FFu > #define SPI_INTLVL_0 0x00000000u > > /* SPIDAT1 */ > +#define SPIDAT1_CSHOLD_MASK BIT(28) > #define SPIDAT1_CSHOLD_SHIFT 28 > +#define SPIDAT1_WDEL_MASK BIT(26) > +#define SPIDAT1_CSNR_MASK 0x00FF0000u > #define SPIDAT1_CSNR_SHIFT 16 > +#define SPIDAT1_DFSEL_MASK (BIT(24 | BIT(25)) > #define SPIGCR1_CLKMOD_MASK BIT(1) > -#define SPIGCR1_MASTER_MASK BIT(0) > +#define SPIGCR1_MASTER_MASK BIT(0) > #define SPIGCR1_LOOPBACK_MASK BIT(16) > > /* SPIBUF */ > #define SPIBUF_TXFULL_MASK BIT(29) > #define SPIBUF_RXEMPTY_MASK BIT(31) > > +/* SPIDELAY */ > +#define SPIDELAY_C2TDELAY_MASK 0xFF000000u > +#define SPIDELAY_C2TDELAY_SHIFT 24 > +#define SPIDELAY_T2CDELAY_MASK 0x00FF0000u > +#define SPIDELAY_T2CDELAY_SHIFT 16 > +#define SPIDELAY_T2EDELAY_MASK 0x0000FF00u > +#define SPIDELAY_T2EDELAY_SHIFT 8 > +#define SPIDELAY_C2EDELAY_MASK 0x000000FFu > +#define SPIDELAY_C2EDELAY_SHIFT 0 > + > +/* SPIDEF */ > +#define SPIDEF_CSDEF_MASK 0x000000FFu > + > /* Error Masks */ > #define SPIFLG_DLEN_ERR_MASK BIT(0) > #define SPIFLG_TIMEOUT_MASK BIT(1) > @@ -90,11 +109,12 @@ > #define SPIFLG_RX_INTR_MASK BIT(8) > #define SPIFLG_TX_INTR_MASK BIT(9) > #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) > -#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \ > +#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ > | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ > | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ > - | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \ > - | SPIFLG_TX_INTR_MASK \ > + | SPIFLG_OVRRUN_MASK) > +#define SPIFLG_MASK (SPIFLG_ERROR_MASK \ > + | SPIFLG_RX_INTR_MASK | SPIFLG_TX_INTR_MASK \ > | SPIFLG_BUF_INIT_ACTIVE_MASK) > > #define SPIINT_DLEN_ERR_INTR BIT(0) > @@ -139,11 +159,10 @@ > #define TGINTVEC0 0x60 > #define TGINTVEC1 0x64 > > -struct davinci_spi_slave { > - u32 cmd_to_write; > - u32 clk_ctrl_to_write; > - u32 bytes_per_word; > - u8 active_cs; > +const char * const io_type_names[] = { > + [SPI_IO_TYPE_INTR] = "Interrupt", > + [SPI_IO_TYPE_POLL] = "Polled", > + [SPI_IO_TYPE_DMA] = "DMA", > }; > > /* We have 2 DMA channels per CS, one for RX and one for TX */ > @@ -152,10 +171,8 @@ struct davinci_spi_dma { > int dma_rx_channel; > int dma_tx_sync_dev; > int dma_rx_sync_dev; > + int dummy_param_slot; > enum dma_event_q eventq; > - > - struct completion dma_tx_completion; > - struct completion dma_rx_completion; > }; > > /* SPI Controller driver's private data. */ > @@ -173,51 +190,53 @@ struct davinci_spi { > const void *tx; > void *rx; > u8 *tmp_buf; > - int count; > - struct davinci_spi_dma *dma_channels; > - struct davinci_spi_platform_data *pdata; > + int rcount; > + int wcount; > + u32 errors; > + struct davinci_spi_dma dma_channels; > + struct davinci_spi_platform_data *pdata; > > void (*get_rx)(u32 rx_data, struct davinci_spi *); > u32 (*get_tx)(struct davinci_spi *); > - > - struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT]; > }; > > -static unsigned use_dma; > - > static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) > { > - u8 *rx = davinci_spi->rx; > - > - *rx++ = (u8)data; > - davinci_spi->rx = rx; > + if (davinci_spi->rx) { > + u8 *rx = davinci_spi->rx; > + *rx++ = (u8)data; > + davinci_spi->rx = rx; > + } > } > > static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) > { > - u16 *rx = davinci_spi->rx; > - > - *rx++ = (u16)data; > - davinci_spi->rx = rx; > + if (davinci_spi->rx) { > + u16 *rx = davinci_spi->rx; > + *rx++ = (u16)data; > + davinci_spi->rx = rx; > + } > } > > static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) > { > - u32 data; > - const u8 *tx = davinci_spi->tx; > - > - data = *tx++; > - davinci_spi->tx = tx; > + u32 data = 0; > + if (davinci_spi->tx) { > + const u8 *tx = davinci_spi->tx; > + data = *tx++; > + davinci_spi->tx = tx; > + } > return data; > } > > static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) > { > - u32 data; > - const u16 *tx = davinci_spi->tx; > - > - data = *tx++; > - davinci_spi->tx = tx; > + u32 data = 0; > + if (davinci_spi->tx) { > + const u16 *tx = davinci_spi->tx; > + data = *tx++; > + davinci_spi->tx = tx; > + } > return data; > } > > @@ -237,26 +256,6 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits) > iowrite32(v, addr); > } > > -static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num) > -{ > - set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); > -} > - > -static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num) > -{ > - clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); > -} > - > -static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) > -{ > - struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); > - > - if (enable) > - set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); > - else > - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); > -} > - > /* > * Interface to control the chip select signal > */ > @@ -264,28 +263,57 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) > { > struct davinci_spi *davinci_spi; > struct davinci_spi_platform_data *pdata; > - u32 data1_reg_val = 0; > + u8 i, chip_sel = spi->chip_select; > + u32 spidat1; > + u16 spidat1_cfg; > > davinci_spi = spi_master_get_devdata(spi->master); > pdata = davinci_spi->pdata; > > - /* > - * Board specific chip select logic decides the polarity and cs > - * line for the controller > - */ > - if (value == BITBANG_CS_INACTIVE) { > - set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT); > - > - data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT; > - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); > + spidat1 = SPIDAT1_CSNR_MASK; > + if (value == BITBANG_CS_ACTIVE) > + spidat1 |= SPIDAT1_CSHOLD_MASK; > + else > + spidat1 |= SPIDAT1_WDEL_MASK; > > - while ((ioread32(davinci_spi->base + SPIBUF) > - & SPIBUF_RXEMPTY_MASK) == 0) > - cpu_relax(); > + if (pdata->chip_sel == NULL) { > + if (value == BITBANG_CS_ACTIVE) > + spidat1 &= ~((0x1 << chip_sel) << SPIDAT1_CSNR_SHIFT); > + } else { > + for (i = 0; i < pdata->num_chipselect; i++) { > + if (pdata->chip_sel[i] == SPI_INTERN_CS) { > + if ((i == chip_sel) && > + (value == BITBANG_CS_ACTIVE)) { > + spidat1 &= ~((0x1 << chip_sel) > + << SPIDAT1_CSNR_SHIFT); > + } > + } else { > + if (value == BITBANG_CS_INACTIVE) > + gpio_set_value(pdata->chip_sel[i], 1); > + else if (i == chip_sel) > + gpio_set_value(pdata->chip_sel[i], 0); > + } > + } > } > + > + spidat1_cfg = spidat1 >> SPIDAT1_CSNR_SHIFT; > + iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); > } > > -/** > +/* > + * davinci_spi_get_prescale - Calculates the correct prescale value > + * @max_speed_hz: the maximum rate the SPI clock can run at > + * > + * This function calculates the prescale value that generates a clock rate > + * less than or equal to the specified maximum > + */ > +static inline u32 davinci_spi_get_prescale(struct davinci_spi *davinci_spi, > + u32 max_speed_hz) > +{ > + return ((clk_get_rate(davinci_spi->clk) - 1) / max_speed_hz) & 0xff; > +} > + > +/* > * davinci_spi_setup_transfer - This functions will determine transfer method > * @spi: spi device on which data transfer to be done > * @t: spi transfer in which transfer info is filled > @@ -297,14 +325,15 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) > static int davinci_spi_setup_transfer(struct spi_device *spi, > struct spi_transfer *t) > { > - > struct davinci_spi *davinci_spi; > struct davinci_spi_platform_data *pdata; > + struct davinci_spi_config *spi_cfg; > u8 bits_per_word = 0; > - u32 hz = 0, prescale = 0, clkspeed; > + u32 hz = 0, spifmt = 0, prescale, delay = 0; > > davinci_spi = spi_master_get_devdata(spi->master); > pdata = davinci_spi->pdata; > + spi_cfg = spi->controller_data; > > if (t) { > bits_per_word = t->bits_per_word; > @@ -322,76 +351,112 @@ static int davinci_spi_setup_transfer(struct spi_device *spi, > if (bits_per_word <= 8 && bits_per_word >= 2) { > davinci_spi->get_rx = davinci_spi_rx_buf_u8; > davinci_spi->get_tx = davinci_spi_tx_buf_u8; > - davinci_spi->slave[spi->chip_select].bytes_per_word = 1; > + spi_cfg->bytes_per_word = 1; > } else if (bits_per_word <= 16 && bits_per_word >= 2) { > davinci_spi->get_rx = davinci_spi_rx_buf_u16; > davinci_spi->get_tx = davinci_spi_tx_buf_u16; > - davinci_spi->slave[spi->chip_select].bytes_per_word = 2; > + spi_cfg->bytes_per_word = 2; > } else > return -EINVAL; > > if (!hz) > hz = spi->max_speed_hz; > > - clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK, > - spi->chip_select); > - set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f, > - spi->chip_select); > + prescale = davinci_spi_get_prescale(davinci_spi, hz); > + spifmt |= (prescale << SPIFMT_PRESCALE_SHIFT); > > - clkspeed = clk_get_rate(davinci_spi->clk); > - if (hz > clkspeed / 2) > - prescale = 1 << 8; > - if (hz < clkspeed / 256) > - prescale = 255 << 8; > - if (!prescale) > - prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00; > + spifmt |= (bits_per_word & 0x1f); > + > + if (spi->mode & SPI_LSB_FIRST) > + spifmt |= SPIFMT_SHIFTDIR_MASK; > + > + if (spi->mode & SPI_CPOL) > + spifmt |= SPIFMT_POLARITY_MASK; > > - clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select); > - set_fmt_bits(davinci_spi->base, prescale, spi->chip_select); > + if (!(spi->mode & SPI_CPHA)) > + spifmt |= SPIFMT_PHASE_MASK; > + > + if (davinci_spi->version == SPI_VERSION_2) { > + spifmt |= ((spi_cfg->wdelay << SPIFMT_WDELAY_SHIFT) > + & SPIFMT_WDELAY_MASK); > + > + if (spi_cfg->odd_parity) > + spifmt |= SPIFMT_ODD_PARITY_MASK; > + > + if (spi_cfg->parity_enable) > + spifmt |= SPIFMT_PARITYENA_MASK; > + > + if (spi->mode & SPI_READY) { > + spifmt |= SPIFMT_WAITENA_MASK; > + delay |= (spi_cfg->t2e_delay > + << SPIDELAY_T2EDELAY_SHIFT) > + & SPIDELAY_T2EDELAY_MASK; > + delay |= (spi_cfg->c2e_delay > + << SPIDELAY_C2EDELAY_SHIFT) > + & SPIDELAY_C2EDELAY_MASK; > + } > + > + if (spi_cfg->timer_disable) { > + spifmt |= SPIFMT_DISTIMER_MASK; > + } else { > + delay |= (spi_cfg->c2t_delay > + << SPIDELAY_C2TDELAY_SHIFT) > + & SPIDELAY_C2TDELAY_MASK; > + delay |= (spi_cfg->t2c_delay > + << SPIDELAY_T2CDELAY_SHIFT) > + & SPIDELAY_T2CDELAY_MASK; > + } > + > + iowrite32(delay, davinci_spi->base + SPIDELAY); > + } > + > + iowrite32(spifmt, davinci_spi->base + SPIFMT0); > + > + if (spi_cfg->intr_level) > + iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); > + else > + iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); > + > + if (spi->mode & SPI_LOOP) > + set_io_bits(davinci_spi->base + SPIGCR1, > + SPIGCR1_LOOPBACK_MASK); > + else > + clear_io_bits(davinci_spi->base + SPIGCR1, > + SPIGCR1_LOOPBACK_MASK); > > return 0; > } > > static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) > { > - struct spi_device *spi = (struct spi_device *)data; > - struct davinci_spi *davinci_spi; > + struct davinci_spi *davinci_spi = (struct davinci_spi *)data; data is a void*, you don't need the cast. > struct davinci_spi_dma *davinci_spi_dma; > struct davinci_spi_platform_data *pdata; > > - davinci_spi = spi_master_get_devdata(spi->master); > - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); > + davinci_spi_dma = &(davinci_spi->dma_channels); > pdata = davinci_spi->pdata; > > + edma_stop(davinci_spi_dma->dma_rx_channel); > + > if (ch_status == DMA_COMPLETE) > - edma_stop(davinci_spi_dma->dma_rx_channel); > - else > - edma_clean_channel(davinci_spi_dma->dma_rx_channel); > + davinci_spi->rcount = 0; > > - complete(&davinci_spi_dma->dma_rx_completion); > - /* We must disable the DMA RX request */ > - davinci_spi_set_dma_req(spi, 0); > + complete(&davinci_spi->done); > } > > static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) > { > - struct spi_device *spi = (struct spi_device *)data; > - struct davinci_spi *davinci_spi; > + struct davinci_spi *davinci_spi = (struct davinci_spi *)data; ditto > struct davinci_spi_dma *davinci_spi_dma; > struct davinci_spi_platform_data *pdata; > > - davinci_spi = spi_master_get_devdata(spi->master); > - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); > + davinci_spi_dma = &(davinci_spi->dma_channels); > pdata = davinci_spi->pdata; > > - if (ch_status == DMA_COMPLETE) > - edma_stop(davinci_spi_dma->dma_tx_channel); > - else > - edma_clean_channel(davinci_spi_dma->dma_tx_channel); > + edma_stop(davinci_spi_dma->dma_tx_channel); > > - complete(&davinci_spi_dma->dma_tx_completion); > - /* We must disable the DMA TX request */ > - davinci_spi_set_dma_req(spi, 0); > + if (ch_status == DMA_COMPLETE) > + davinci_spi->wcount = 0; > } > > static int davinci_spi_request_dma(struct spi_device *spi) > @@ -403,33 +468,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) > int r; > > davinci_spi = spi_master_get_devdata(spi->master); > - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > + davinci_spi_dma = &davinci_spi->dma_channels; > pdata = davinci_spi->pdata; > sdev = davinci_spi->bitbang.master->dev.parent; > > r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, > - davinci_spi_dma_rx_callback, spi, > + davinci_spi_dma_rx_callback, davinci_spi, > davinci_spi_dma->eventq); > if (r < 0) { > - dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); > - return -EAGAIN; > + dev_dbg(sdev, "Unable to request DMA channel for MibSPI RX\n"); > + r = -EAGAIN; > + goto rx_dma_failed; > } > davinci_spi_dma->dma_rx_channel = r; > + > r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, > - davinci_spi_dma_tx_callback, spi, > + davinci_spi_dma_tx_callback, davinci_spi, > davinci_spi_dma->eventq); > if (r < 0) { > - edma_free_channel(davinci_spi_dma->dma_rx_channel); > - davinci_spi_dma->dma_rx_channel = -1; > - dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); > - return -EAGAIN; > + dev_dbg(sdev, "Unable to request DMA channel for MibSPI TX\n"); > + r = -EAGAIN; > + goto tx_dma_failed; > } > davinci_spi_dma->dma_tx_channel = r; > > + r = edma_alloc_slot(EDMA_CTLR(davinci_spi_dma->dma_tx_sync_dev), > + EDMA_SLOT_ANY); > + if (r < 0) { > + dev_dbg(sdev, "Unable to request SPI DMA param slot\n"); > + r = -EAGAIN; > + goto param_failed; > + } > + davinci_spi_dma->dummy_param_slot = r; > + edma_link(davinci_spi_dma->dummy_param_slot, > + davinci_spi_dma->dummy_param_slot); > + > return 0; > + > +param_failed: > + edma_free_channel(davinci_spi_dma->dma_tx_channel); > + davinci_spi_dma->dma_tx_channel = -1; > +tx_dma_failed: > + edma_free_channel(davinci_spi_dma->dma_rx_channel); > + davinci_spi_dma->dma_rx_channel = -1; > +rx_dma_failed: > + return r; > } > > -/** > +/* Don't change this. /** means kernel-doc format. Ditto throughout the file. > * davinci_spi_setup - This functions will set default transfer method > * @spi: spi device on which data transfer to be done > * > @@ -438,129 +524,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) > > static int davinci_spi_setup(struct spi_device *spi) > { > - int retval; > + int retval = 0; > struct davinci_spi *davinci_spi; > - struct davinci_spi_dma *davinci_spi_dma; > - struct device *sdev; > + struct davinci_spi_dma *davinci_dma; > + struct davinci_spi_platform_data *pdata; > + struct davinci_spi_config *spi_cfg; > + u32 prescale; > > davinci_spi = spi_master_get_devdata(spi->master); > - sdev = davinci_spi->bitbang.master->dev.parent; > + pdata = davinci_spi->pdata; > + spi_cfg = (struct davinci_spi_config *)spi->controller_data; > + davinci_dma = &(davinci_spi->dma_channels); > > /* if bits per word length is zero then set it default 8 */ > if (!spi->bits_per_word) > spi->bits_per_word = 8; > > - davinci_spi->slave[spi->chip_select].cmd_to_write = 0; > + if (!(spi->mode & SPI_NO_CS)) { > + if ((pdata->chip_sel == NULL) || > + (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) > + set_io_bits(davinci_spi->base + SPIPC0, > + 1 << spi->chip_select); > > - if (use_dma && davinci_spi->dma_channels) { > - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > - > - if ((davinci_spi_dma->dma_rx_channel == -1) > - || (davinci_spi_dma->dma_tx_channel == -1)) { > - retval = davinci_spi_request_dma(spi); > - if (retval < 0) > - return retval; > - } > - } > - > - /* > - * SPI in DaVinci and DA8xx operate between > - * 600 KHz and 50 MHz > - */ > - if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) { > - dev_dbg(sdev, "Operating frequency is not in acceptable " > - "range\n"); > - return -EINVAL; > } > > - /* > - * Set up SPIFMTn register, unique to this chipselect. > - * > - * NOTE: we could do all of these with one write. Also, some > - * of the "version 2" features are found in chips that don't > - * support all of them... > - */ > - if (spi->mode & SPI_LSB_FIRST) > - set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, > - spi->chip_select); > + if (spi->mode & SPI_READY) > + set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); > > - if (spi->mode & SPI_CPOL) > - set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, > - spi->chip_select); > + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { > + davinci_dma = &(davinci_spi->dma_channels); > > - if (!(spi->mode & SPI_CPHA)) > - set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, > - spi->chip_select); > + if ((davinci_dma->dma_tx_sync_dev == SPI_NO_RESOURCE) || > + (davinci_dma->dma_rx_sync_dev == SPI_NO_RESOURCE) || > + (davinci_dma->eventq == SPI_NO_RESOURCE)) > + spi_cfg->io_type = SPI_IO_TYPE_INTR; > + else if ((davinci_dma->dma_rx_channel == -1) || > + (davinci_dma->dma_tx_channel == -1)) > + retval = davinci_spi_request_dma(spi); > + } > > /* > - * Version 1 hardware supports two basic SPI modes: > - * - Standard SPI mode uses 4 pins, with chipselect > - * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) > - * (distinct from SPI_3WIRE, with just one data wire; > - * or similar variants without MOSI or without MISO) > - * > - * Version 2 hardware supports an optional handshaking signal, > - * so it can support two more modes: > - * - 5 pin SPI variant is standard SPI plus SPI_READY > - * - 4 pin with enable is (SPI_READY | SPI_NO_CS) > + * Validate desired clock rate > */ > + prescale = davinci_spi_get_prescale(davinci_spi, spi->max_speed_hz); > + if ((prescale < 2) || (prescale > 255)) > + return -EINVAL; > > - if (davinci_spi->version == SPI_VERSION_2) { > - clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK, > - spi->chip_select); > - set_fmt_bits(davinci_spi->base, > - (davinci_spi->pdata->wdelay > - << SPIFMT_WDELAY_SHIFT) > - & SPIFMT_WDELAY_MASK, > - spi->chip_select); > - > - if (davinci_spi->pdata->odd_parity) > - set_fmt_bits(davinci_spi->base, > - SPIFMT_ODD_PARITY_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, > - SPIFMT_ODD_PARITY_MASK, > - spi->chip_select); > - > - if (davinci_spi->pdata->parity_enable) > - set_fmt_bits(davinci_spi->base, > - SPIFMT_PARITYENA_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, > - SPIFMT_PARITYENA_MASK, > - spi->chip_select); > - > - if (davinci_spi->pdata->wait_enable) > - set_fmt_bits(davinci_spi->base, > - SPIFMT_WAITENA_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, > - SPIFMT_WAITENA_MASK, > - spi->chip_select); > - > - if (davinci_spi->pdata->timer_disable) > - set_fmt_bits(davinci_spi->base, > - SPIFMT_DISTIMER_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, > - SPIFMT_DISTIMER_MASK, > - spi->chip_select); > - } > - > - retval = davinci_spi_setup_transfer(spi, NULL); > + dev_info(&spi->dev, "DaVinci SPI driver in %s mode\n", > + io_type_names[spi_cfg->io_type]); > > return retval; > } > @@ -569,50 +580,19 @@ static void davinci_spi_cleanup(struct spi_device *spi) > { > struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); > struct davinci_spi_dma *davinci_spi_dma; > + struct davinci_spi_platform_data *pdata; > > - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > - > - if (use_dma && davinci_spi->dma_channels) { > - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > - > - if ((davinci_spi_dma->dma_rx_channel != -1) > - && (davinci_spi_dma->dma_tx_channel != -1)) { > - edma_free_channel(davinci_spi_dma->dma_tx_channel); > - edma_free_channel(davinci_spi_dma->dma_rx_channel); > - } > - } > -} > - > -static int davinci_spi_bufs_prep(struct spi_device *spi, > - struct davinci_spi *davinci_spi) > -{ > - int op_mode = 0; > - > - /* > - * REVISIT unless devices disagree about SPI_LOOP or > - * SPI_READY (SPI_NO_CS only allows one device!), this > - * should not need to be done before each message... > - * optimize for both flags staying cleared. > - */ > - > - op_mode = SPIPC0_DIFUN_MASK > - | SPIPC0_DOFUN_MASK > - | SPIPC0_CLKFUN_MASK; > - if (!(spi->mode & SPI_NO_CS)) > - op_mode |= 1 << spi->chip_select; > - if (spi->mode & SPI_READY) > - op_mode |= SPIPC0_SPIENA_MASK; > + davinci_spi_dma = &davinci_spi->dma_channels; > + pdata = davinci_spi->pdata; > > - iowrite32(op_mode, davinci_spi->base + SPIPC0); > + if (davinci_spi_dma->dma_rx_channel != -1) > + edma_free_channel(davinci_spi_dma->dma_rx_channel); > > - if (spi->mode & SPI_LOOP) > - set_io_bits(davinci_spi->base + SPIGCR1, > - SPIGCR1_LOOPBACK_MASK); > - else > - clear_io_bits(davinci_spi->base + SPIGCR1, > - SPIGCR1_LOOPBACK_MASK); > + if (davinci_spi_dma->dma_tx_channel != -1) > + edma_free_channel(davinci_spi_dma->dma_tx_channel); > > - return 0; > + if (davinci_spi_dma->dummy_param_slot != -1) > + edma_free_slot(davinci_spi_dma->dummy_param_slot); > } > > static int davinci_spi_check_error(struct davinci_spi *davinci_spi, > @@ -659,356 +639,243 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi, > return 0; > } > > -/** > - * davinci_spi_bufs - functions which will handle transfer data > - * @spi: spi device on which data transfer to be done > - * @t: spi transfer in which transfer info is filled > +/* > + * davinci_spi_process_events - check for and handle any SPI controller events > + * @davinci_spi - the controller data > * > - * This function will put data to be transferred into data register > - * of SPI controller and then wait until the completion will be marked > - * by the IRQ Handler. > + * This function will check the SPIFLG register and handle any events that are > + * detected there > */ > -static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) > +static int davinci_spi_process_events(struct davinci_spi *davinci_spi) > { > - struct davinci_spi *davinci_spi; > - int int_status, count, ret; > - u8 conv, tmp; > - u32 tx_data, data1_reg_val; > - u32 buf_val, flg_val; > - struct davinci_spi_platform_data *pdata; > - > - davinci_spi = spi_master_get_devdata(spi->master); > - pdata = davinci_spi->pdata; > - > - davinci_spi->tx = t->tx_buf; > - davinci_spi->rx = t->rx_buf; > - > - /* convert len to words based on bits_per_word */ > - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; > - davinci_spi->count = t->len / conv; > - > - INIT_COMPLETION(davinci_spi->done); > - > - ret = davinci_spi_bufs_prep(spi, davinci_spi); > - if (ret) > - return ret; > - > - /* Enable SPI */ > - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); > - > - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | > - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), > - davinci_spi->base + SPIDELAY); > - > - count = davinci_spi->count; > - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; > - tmp = ~(0x1 << spi->chip_select); > - > - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); > - > - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; > - > - while ((ioread32(davinci_spi->base + SPIBUF) > - & SPIBUF_RXEMPTY_MASK) == 0) > - cpu_relax(); > - > - /* Determine the command to execute READ or WRITE */ > - if (t->tx_buf) { > - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); > - > - while (1) { > - tx_data = davinci_spi->get_tx(davinci_spi); > - > - data1_reg_val &= ~(0xFFFF); > - data1_reg_val |= (0xFFFF & tx_data); > - > - buf_val = ioread32(davinci_spi->base + SPIBUF); > - if ((buf_val & SPIBUF_TXFULL_MASK) == 0) { > - iowrite32(data1_reg_val, > - davinci_spi->base + SPIDAT1); > - > - count--; > - } > - while (ioread32(davinci_spi->base + SPIBUF) > - & SPIBUF_RXEMPTY_MASK) > - cpu_relax(); > - > - /* getting the returned byte */ > - if (t->rx_buf) { > - buf_val = ioread32(davinci_spi->base + SPIBUF); > - davinci_spi->get_rx(buf_val, davinci_spi); > - } > - if (count <= 0) > - break; > - } > - } else { > - if (pdata->poll_mode) { > - while (1) { > - /* keeps the serial clock going */ > - if ((ioread32(davinci_spi->base + SPIBUF) > - & SPIBUF_TXFULL_MASK) == 0) > - iowrite32(data1_reg_val, > - davinci_spi->base + SPIDAT1); > - > - while (ioread32(davinci_spi->base + SPIBUF) & > - SPIBUF_RXEMPTY_MASK) > - cpu_relax(); > - > - flg_val = ioread32(davinci_spi->base + SPIFLG); > - buf_val = ioread32(davinci_spi->base + SPIBUF); > - > - davinci_spi->get_rx(buf_val, davinci_spi); > - > - count--; > - if (count <= 0) > - break; > - } > - } else { /* Receive in Interrupt mode */ > - int i; > - > - for (i = 0; i < davinci_spi->count; i++) { > - set_io_bits(davinci_spi->base + SPIINT, > - SPIINT_BITERR_INTR > - | SPIINT_OVRRUN_INTR > - | SPIINT_RX_INTR); > - > - iowrite32(data1_reg_val, > - davinci_spi->base + SPIDAT1); > - > - while (ioread32(davinci_spi->base + SPIINT) & > - SPIINT_RX_INTR) > - cpu_relax(); > - } > - iowrite32((data1_reg_val & 0x0ffcffff), > - davinci_spi->base + SPIDAT1); > - } > + u32 status, tx_data, rx_data, spidat1; > + u8 tx_word = 0; > + > + status = ioread32(davinci_spi->base + SPIFLG); > + > + if ((davinci_spi->version != SPI_VERSION_0) && > + (likely(status & SPIFLG_TX_INTR_MASK)) && > + (likely(davinci_spi->wcount > 0))) > + tx_word = 1; > + > + if (likely(status & SPIFLG_RX_INTR_MASK)) { > + rx_data = ioread32(davinci_spi->base + SPIBUF) & 0xFFFF; > + davinci_spi->get_rx(rx_data, davinci_spi); > + davinci_spi->rcount--; > + if ((davinci_spi->version == SPI_VERSION_0) && > + (likely(davinci_spi->wcount > 0))) > + tx_word = 1; > } > > - /* > - * Check for bit error, desync error,parity error,timeout error and > - * receive overflow errors > - */ > - int_status = ioread32(davinci_spi->base + SPIFLG); > - > - ret = davinci_spi_check_error(davinci_spi, int_status); > - if (ret != 0) > - return ret; > + if (unlikely(status & SPIFLG_ERROR_MASK)) { > + davinci_spi->errors = (status & SPIFLG_ERROR_MASK); > + return -1; > + } > > - /* SPI Framework maintains the count only in bytes so convert back */ > - davinci_spi->count *= conv; > + if (likely(tx_word)) { > + spidat1 = ioread32(davinci_spi->base + SPIDAT1); > + davinci_spi->wcount--; > + tx_data = davinci_spi->get_tx(davinci_spi); > + spidat1 &= 0xFFFF0000; > + spidat1 |= (tx_data & 0xFFFF); > + iowrite32(spidat1, davinci_spi->base + SPIDAT1); > + } > > - return t->len; > + return 0; > } > > -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 > -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 > -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 > - > -static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) > +/* > + * davinci_spi_txrx_bufs - function which will handle transfer data > + * @spi: spi device on which data transfer to be done > + * @t: spi transfer in which transfer info is filled > + * > + * This function will put data to be transferred into data register > + * of SPI controller and then wait until the completion will be marked > + * by the IRQ Handler. > + */ > +static int davinci_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) > { > struct davinci_spi *davinci_spi; > - int int_status = 0; > - int count, temp_count; > - u8 conv = 1; > - u8 tmp; > - u32 data1_reg_val; > - struct davinci_spi_dma *davinci_spi_dma; > - int word_len, data_type, ret; > - unsigned long tx_reg, rx_reg; > + int data_type, ret = 0; > + u32 tx_data, spidat1; > + u16 tx_buf_count = 0, rx_buf_count = 0; > + struct davinci_spi_config *spi_cfg; > struct davinci_spi_platform_data *pdata; > + struct davinci_spi_dma *davinci_dma; > struct device *sdev; > + dma_addr_t tx_reg, rx_reg; > + void *tx_buf, *rx_buf; > + struct edmacc_param rx_param, tx_param; > > davinci_spi = spi_master_get_devdata(spi->master); > pdata = davinci_spi->pdata; > - sdev = davinci_spi->bitbang.master->dev.parent; > - > - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > - > - tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; > - rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; > + spi_cfg = (struct davinci_spi_config *)spi->controller_data; > + davinci_dma = &(davinci_spi->dma_channels); > > davinci_spi->tx = t->tx_buf; > davinci_spi->rx = t->rx_buf; > + davinci_spi->wcount = t->len / spi_cfg->bytes_per_word; > + davinci_spi->rcount = davinci_spi->wcount; > + davinci_spi->errors = 0; > > - /* convert len to words based on bits_per_word */ > - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; > - davinci_spi->count = t->len / conv; > - > - INIT_COMPLETION(davinci_spi->done); > - > - init_completion(&davinci_spi_dma->dma_rx_completion); > - init_completion(&davinci_spi_dma->dma_tx_completion); > - > - word_len = conv * 8; > - > - if (word_len <= 8) > - data_type = DAVINCI_DMA_DATA_TYPE_S8; > - else if (word_len <= 16) > - data_type = DAVINCI_DMA_DATA_TYPE_S16; > - else if (word_len <= 32) > - data_type = DAVINCI_DMA_DATA_TYPE_S32; > - else > - return -EINVAL; > - > - ret = davinci_spi_bufs_prep(spi, davinci_spi); > - if (ret) > - return ret; > - > - /* Put delay val if required */ > - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | > - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), > - davinci_spi->base + SPIDELAY); > - > - count = davinci_spi->count; /* the number of elements */ > - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; > + spidat1 = ioread32(davinci_spi->base + SPIDAT1); > > - /* CS default = 0xFF */ > - tmp = ~(0x1 << spi->chip_select); > - > - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); > - > - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; > - > - /* disable all interrupts for dma transfers */ > - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); > - /* Disable SPI to write configuration bits in SPIDAT */ > - clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); > - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); > - /* Enable SPI */ > + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); > set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); > > - while ((ioread32(davinci_spi->base + SPIBUF) > - & SPIBUF_RXEMPTY_MASK) == 0) > - cpu_relax(); > - > + INIT_COMPLETION(davinci_spi->done); > > - if (t->tx_buf) { > - t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, > - DMA_TO_DEVICE); > - if (dma_mapping_error(&spi->dev, t->tx_dma)) { > - dev_dbg(sdev, "Unable to DMA map a %d bytes" > - " TX buffer\n", count); > - return -ENOMEM; > + if ((spi_cfg->io_type == SPI_IO_TYPE_INTR) || > + (spi_cfg->io_type == SPI_IO_TYPE_POLL)) { > + > + if (spi_cfg->io_type == SPI_IO_TYPE_INTR) > + set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); > + > + /* start the transfer */ > + davinci_spi->wcount--; > + tx_data = davinci_spi->get_tx(davinci_spi); > + spidat1 &= 0xFFFF0000; > + spidat1 |= (tx_data & 0xFFFF); > + iowrite32(spidat1, davinci_spi->base + SPIDAT1); > + > + } else if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { > + data_type = spi_cfg->bytes_per_word; > + tx_reg = (dma_addr_t)davinci_spi->pbase + SPIDAT1; > + rx_reg = (dma_addr_t)davinci_spi->pbase + SPIBUF; > + > + if (t->tx_buf) { > + tx_buf = ((void *)t->tx_buf); > + tx_buf_count = davinci_spi->wcount; > + } else { > + tx_buf = (void *)davinci_spi->tmp_buf; > + tx_buf_count = SPI_BUFSIZ; > } > - temp_count = count; > - } else { > - /* We need TX clocking for RX transaction */ > - t->tx_dma = dma_map_single(&spi->dev, > - (void *)davinci_spi->tmp_buf, count + 1, > - DMA_TO_DEVICE); > - if (dma_mapping_error(&spi->dev, t->tx_dma)) { > - dev_dbg(sdev, "Unable to DMA map a %d bytes" > - " TX tmp buffer\n", count); > - return -ENOMEM; > + if (t->rx_buf) { > + rx_buf = (void *)t->rx_buf; > + rx_buf_count = davinci_spi->rcount; > + } else { > + rx_buf = (void *)davinci_spi->tmp_buf; > + rx_buf_count = SPI_BUFSIZ; > } > - temp_count = count + 1; > + > + t->tx_dma = dma_map_single(&spi->dev, tx_buf, > + tx_buf_count, DMA_TO_DEVICE); > + t->rx_dma = dma_map_single(&spi->dev, rx_buf, > + rx_buf_count, DMA_FROM_DEVICE); > + > + tx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_tx_channel); > + tx_param.src = t->tx_buf ? t->tx_dma : tx_reg; > + tx_param.a_b_cnt = davinci_spi->wcount << 16 | data_type; > + tx_param.dst = tx_reg; > + tx_param.src_dst_bidx = t->tx_buf ? data_type : 0; > + tx_param.link_bcntrld = 0xffff; > + tx_param.src_dst_cidx = 0; > + tx_param.ccnt = 1; > + edma_write_slot(davinci_dma->dma_tx_channel, &tx_param); > + edma_link(davinci_dma->dma_tx_channel, > + davinci_dma->dummy_param_slot); > + > + rx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_rx_channel); > + rx_param.src = rx_reg; > + rx_param.a_b_cnt = davinci_spi->rcount << 16 | data_type; > + rx_param.dst = t->rx_dma; > + rx_param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; > + rx_param.link_bcntrld = 0xffff; > + rx_param.src_dst_cidx = 0; > + rx_param.ccnt = 1; > + edma_write_slot(davinci_dma->dma_rx_channel, &rx_param); > + > + iowrite16(spidat1 >> SPIDAT1_CSNR_SHIFT, > + davinci_spi->base + SPIDAT1 + 2); > + > + edma_start(davinci_dma->dma_rx_channel); > + edma_start(davinci_dma->dma_tx_channel); > + set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); > } > > - edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, > - data_type, temp_count, 1, 0, ASYNC); > - edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); > - edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT); > - edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0); > - edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); > - > - if (t->rx_buf) { > - /* initiate transaction */ > - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); > - > - t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, > - DMA_FROM_DEVICE); > - if (dma_mapping_error(&spi->dev, t->rx_dma)) { > - dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", > - count); > - if (t->tx_buf != NULL) > - dma_unmap_single(NULL, t->tx_dma, > - count, DMA_TO_DEVICE); > - return -ENOMEM; > + /* Wait for the transfer to complete */ > + if (spi_cfg->io_type != SPI_IO_TYPE_POLL) { > + wait_for_completion_interruptible(&(davinci_spi->done)); > + } else { > + while ((davinci_spi->rcount > 0) && (ret == 0)) { > + ret = davinci_spi_process_events(davinci_spi); > + cpu_relax(); > } > - edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, > - data_type, count, 1, 0, ASYNC); > - edma_set_src(davinci_spi_dma->dma_rx_channel, > - rx_reg, INCR, W8BIT); > - edma_set_dest(davinci_spi_dma->dma_rx_channel, > - t->rx_dma, INCR, W8BIT); > - edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); > - edma_set_dest_index(davinci_spi_dma->dma_rx_channel, > - data_type, 0); > } > > - if ((t->tx_buf) || (t->rx_buf)) > - edma_start(davinci_spi_dma->dma_tx_channel); > - > - if (t->rx_buf) > - edma_start(davinci_spi_dma->dma_rx_channel); > - > - if ((t->rx_buf) || (t->tx_buf)) > - davinci_spi_set_dma_req(spi, 1); > - > - if (t->tx_buf) > - wait_for_completion_interruptible( > - &davinci_spi_dma->dma_tx_completion); > - > - if (t->rx_buf) > - wait_for_completion_interruptible( > - &davinci_spi_dma->dma_rx_completion); > - > - dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE); > - > - if (t->rx_buf) > - dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); > - > - /* > - * Check for bit error, desync error,parity error,timeout error and > - * receive overflow errors > - */ > - int_status = ioread32(davinci_spi->base + SPIFLG); > + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); > + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { > + dma_unmap_single(NULL, t->tx_dma, tx_buf_count, > + DMA_TO_DEVICE); > + dma_unmap_single(NULL, t->rx_dma, rx_buf_count, > + DMA_FROM_DEVICE); > + } > > - ret = davinci_spi_check_error(davinci_spi, int_status); > - if (ret != 0) > - return ret; > + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); > + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); > > - /* SPI Framework maintains the count only in bytes so convert back */ > - davinci_spi->count *= conv; > + if (davinci_spi->errors) { > + ret = davinci_spi_check_error(davinci_spi, davinci_spi->errors); > + if (ret != 0) > + return ret; > + } > + if ((davinci_spi->rcount != 0) || (davinci_spi->wcount != 0)) { > + sdev = davinci_spi->bitbang.master->dev.parent; > + dev_info(sdev, "SPI data transfer error\n"); > + return -EIO; > + } > > return t->len; > } > > -/** > - * davinci_spi_irq - IRQ handler for DaVinci SPI > +/* > + * davinci_spi_irq - probe function for SPI Master Controller > * @irq: IRQ number for this SPI Master > * @context_data: structure for SPI Master controller davinci_spi > + * > + * ISR will determine that interrupt arrives either for READ or WRITE command. > + * According to command it will do the appropriate action. It will check > + * transfer length and if it is not zero then dispatch transfer command again. > + * If transfer length is zero then it will indicate the COMPLETION so that > + * davinci_spi_bufs function can go ahead. > */ > static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) > { > struct davinci_spi *davinci_spi = context_data; > - u32 int_status, rx_data = 0; > - irqreturn_t ret = IRQ_NONE; > + int status; > > - int_status = ioread32(davinci_spi->base + SPIFLG); > + status = davinci_spi_process_events(davinci_spi); > + if (unlikely(status != 0)) > + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); > > - while ((int_status & SPIFLG_RX_INTR_MASK)) { > - if (likely(int_status & SPIFLG_RX_INTR_MASK)) { > - ret = IRQ_HANDLED; > + if ((davinci_spi->rcount == 0) || (status != 0)) > + complete(&(davinci_spi->done)); > > - rx_data = ioread32(davinci_spi->base + SPIBUF); > - davinci_spi->get_rx(rx_data, davinci_spi); > + return IRQ_HANDLED; > +} > > - /* Disable Receive Interrupt */ > - iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR), > - davinci_spi->base + SPIINT); > - } else > - (void)davinci_spi_check_error(davinci_spi, int_status); > +resource_size_t davinci_spi_get_dma_by_index(struct platform_device *dev, > + unsigned long index) > +{ > + struct resource *r; > > - int_status = ioread32(davinci_spi->base + SPIFLG); > - } > + r = platform_get_resource(dev, IORESOURCE_DMA, index); > + if (r != NULL) > + return r->start; > > - return ret; > + return SPI_NO_RESOURCE; > } > > -/** > +/* > * davinci_spi_probe - probe function for SPI Master Controller > * @pdev: platform_device structure which contains plateform specific data > + * > + * According to Linux Device Model this function will be invoked by Linux > + * with platform_device struct which contains the device specific info. > + * This function will map the SPI controller's memory, register IRQ, > + * Reset SPI controller and setting its registers to default value. > + * It will invoke spi_bitbang_start to create work queue so that client driver > + * can register transfer method to work queue. > */ > static int davinci_spi_probe(struct platform_device *pdev) > { > @@ -1020,6 +887,7 @@ static int davinci_spi_probe(struct platform_device *pdev) > resource_size_t dma_tx_chan = SPI_NO_RESOURCE; > resource_size_t dma_eventq = SPI_NO_RESOURCE; > int i = 0, ret = 0; > + u32 spipc0; > > pdata = pdev->dev.platform_data; > if (pdata == NULL) { > @@ -1071,16 +939,18 @@ static int davinci_spi_probe(struct platform_device *pdev) > goto unmap_io; > } > > - ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED, > + ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, > dev_name(&pdev->dev), davinci_spi); > - if (ret) > + if (ret != 0) { > + ret = -EAGAIN; > goto unmap_io; > + } > > /* Allocate tmp_buf for tx_buf */ > davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); > if (davinci_spi->tmp_buf == NULL) { > ret = -ENOMEM; > - goto irq_free; > + goto err1; > } > > davinci_spi->bitbang.master = spi_master_get(master); > @@ -1104,55 +974,23 @@ static int davinci_spi_probe(struct platform_device *pdev) > > davinci_spi->bitbang.chipselect = davinci_spi_chipselect; > davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; > + davinci_spi->bitbang.txrx_bufs = davinci_spi_txrx_bufs; > > davinci_spi->version = pdata->version; > - use_dma = pdata->use_dma; > > davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; > if (davinci_spi->version == SPI_VERSION_2) > davinci_spi->bitbang.flags |= SPI_READY; > > - if (use_dma) { > - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); > - if (r) > - dma_rx_chan = r->start; > - r = platform_get_resource(pdev, IORESOURCE_DMA, 1); > - if (r) > - dma_tx_chan = r->start; > - r = platform_get_resource(pdev, IORESOURCE_DMA, 2); > - if (r) > - dma_eventq = r->start; > - } > - > - if (!use_dma || > - dma_rx_chan == SPI_NO_RESOURCE || > - dma_tx_chan == SPI_NO_RESOURCE || > - dma_eventq == SPI_NO_RESOURCE) { > - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; > - use_dma = 0; > - } else { > - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; > - davinci_spi->dma_channels = kzalloc(master->num_chipselect > - * sizeof(struct davinci_spi_dma), GFP_KERNEL); > - if (davinci_spi->dma_channels == NULL) { > - ret = -ENOMEM; > - goto free_clk; > - } > - > - for (i = 0; i < master->num_chipselect; i++) { > - davinci_spi->dma_channels[i].dma_rx_channel = -1; > - davinci_spi->dma_channels[i].dma_rx_sync_dev = > - dma_rx_chan; > - davinci_spi->dma_channels[i].dma_tx_channel = -1; > - davinci_spi->dma_channels[i].dma_tx_sync_dev = > - dma_tx_chan; > - davinci_spi->dma_channels[i].eventq = dma_eventq; > - } > - dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" > - "Using RX channel = %d , TX channel = %d and " > - "event queue = %d", dma_rx_chan, dma_tx_chan, > - dma_eventq); > - } > + dma_rx_chan = davinci_spi_get_dma_by_index(pdev, RX_DMA_INDEX); > + dma_tx_chan = davinci_spi_get_dma_by_index(pdev, TX_DMA_INDEX); > + dma_eventq = davinci_spi_get_dma_by_index(pdev, EVENTQ_DMA_INDEX); > + davinci_spi->dma_channels.dma_rx_channel = -1; > + davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan; > + davinci_spi->dma_channels.dma_tx_channel = -1; > + davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan; > + davinci_spi->dma_channels.dummy_param_slot = -1; > + davinci_spi->dma_channels.eventq = dma_eventq; > > davinci_spi->get_rx = davinci_spi_rx_buf_u8; > davinci_spi->get_tx = davinci_spi_tx_buf_u8; > @@ -1164,32 +1002,29 @@ static int davinci_spi_probe(struct platform_device *pdev) > udelay(100); > iowrite32(1, davinci_spi->base + SPIGCR0); > > - /* Clock internal */ > - if (davinci_spi->pdata->clk_internal) > - set_io_bits(davinci_spi->base + SPIGCR1, > - SPIGCR1_CLKMOD_MASK); > - else > - clear_io_bits(davinci_spi->base + SPIGCR1, > - SPIGCR1_CLKMOD_MASK); > + /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ > + spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; > + iowrite32(spipc0, davinci_spi->base + SPIPC0); > > - /* master mode default */ > - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); > + /* initialize chip selects */ > + if (pdata->chip_sel != NULL) { > + for (i = 0; i < pdata->num_chipselect; i++) { > + if (pdata->chip_sel[i] != SPI_INTERN_CS) > + gpio_direction_output(pdata->chip_sel[i], 1); > + } > + } > + iowrite32(SPIDEF_CSDEF_MASK, davinci_spi->base + SPIDEF); > > - if (davinci_spi->pdata->intr_level) > - iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); > - else > - iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); > + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); > + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); > + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); > > ret = spi_bitbang_start(&davinci_spi->bitbang); > - if (ret) > + if (ret != 0) > goto free_clk; > > dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base); > > - if (!pdata->poll_mode) > - dev_info(&pdev->dev, "Operating in interrupt mode" > - " using IRQ %d\n", davinci_spi->irq); > - > return ret; > > free_clk: > @@ -1199,7 +1034,7 @@ put_master: > spi_master_put(master); > free_tmp_buf: > kfree(davinci_spi->tmp_buf); > -irq_free: > +err1: why change this? > free_irq(davinci_spi->irq, davinci_spi); > unmap_io: > iounmap(davinci_spi->base); > @@ -1211,7 +1046,7 @@ err: > return ret; > } > > -/** > +/* > * davinci_spi_remove - remove function for SPI Master Controller > * @pdev: platform_device structure which contains plateform specific data > * > @@ -1220,7 +1055,7 @@ err: > * It will also call spi_bitbang_stop to destroy the work queue which was > * created by spi_bitbang_start. > */ > -static int __exit davinci_spi_remove(struct platform_device *pdev) > +static int __devexit davinci_spi_remove(struct platform_device *pdev) > { > struct davinci_spi *davinci_spi; > struct spi_master *master; > @@ -1242,8 +1077,11 @@ static int __exit davinci_spi_remove(struct platform_device *pdev) > } > > static struct platform_driver davinci_spi_driver = { > - .driver.name = "spi_davinci", > - .remove = __exit_p(davinci_spi_remove), > + .driver = { > + .name = "spi_davinci", > + .owner = THIS_MODULE, > + }, > + .remove = __devexit_p(davinci_spi_remove), > }; > > static int __init davinci_spi_init(void) > -- > 1.6.3.3 > From amraldo at hotmail.com Mon Jul 19 01:05:41 2010 From: amraldo at hotmail.com (amr ali) Date: Mon, 19 Jul 2010 09:05:41 +0300 Subject: fb problem In-Reply-To: References: , <201007182019.07466.caglarakyuz@gmail.com>, , Message-ID: Hi, I tried enabling the console fb nothing happened. What do you mean what type of display I am using? Do I need to initialize some layers before running any GUI application? -- Amr Ali Abdel-Naby Embedded Systems Developer www.embedded-tips.blogspot.com -- Amr Ali Abdel-Naby Embedded Systems Developer www.embedded-tips.blogspot.com Date: Sun, 18 Jul 2010 22:35:01 +0300 Subject: Re: fb problem From: caglarakyuz at gmail.com To: amraldo at hotmail.com CC: davinci-linux-open-source at linux.davincidsp.com 2010/7/18 amr ali This is what I found out after sending the email. The fb device is probed twice: one from the device driver itself and the other from the board file under the arch file. What could be wrong with the display. I tried to start the xorg then run any gui program but no output on the screen. Any clues? You can try enabling framebuffer console. What type of display are you using? Caglar _________________________________________________________________ Hotmail: Trusted email with powerful SPAM protection. https://signup.live.com/signup.aspx?id=60969 -------------- next part -------------- An HTML attachment was scrubbed... URL: From nsekhar at ti.com Mon Jul 19 01:35:10 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Mon, 19 Jul 2010 12:05:10 +0530 Subject: [PATCH] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: References: <1279324167.4526.85.camel@Joe-Laptop.home> Message-ID: Hi Mike, On Sun, Jul 18, 2010 at 22:59:32, Mike Williamson wrote: > > > 2010/7/16 Joe Perches > > > On Fri, 2010-07-16 at 10:00 -0400, Michael Williamson wrote: > > +static __init void mityomapl138_setup_lcd(void) > > +{ > > [] > > > + pr_warning("mityomapl138_init: unknown > LCD type : %s\n", > > + > peripheral_config.LCDConfig.PanelName); > > > I think you'd be better off actually using the actual > function name rather than the caller name > > pr_warning("%s: unknown LCD type: %s\n", > __func__, > peripheral_config.LCDConfig.PanelName); > > > > > Absolutely. Didn't catch those when shuffling around during cleanup / > etc. > I will clean these up and resubmit. > > Thank you for the feedback. Can you can you please configure your e-mail client to send plain text and not HTML? I don't think this response of yours reached subscribers of ARM linux kernel mailing list. Thanks, Sekhar From sudhakar.raj at ti.com Mon Jul 19 01:38:26 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Mon, 19 Jul 2010 12:08:26 +0530 Subject: [PATCH v3] mtd-nand: davinci: correct 4-bit error correction Message-ID: <1279521506-4537-1-git-send-email-sudhakar.raj@ti.com> On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the 4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and before waiting for the NAND Flash status register to be equal to 1, 2 or 3, we have to wait till the ECC HW goes to correction state. Without this wait, ECC correction calculations will not be proper. This has been tested on DA830/OMAP-L137, DA850/OMAP-L138, DM355 and DM365 EVMs. Signed-off-by: Sudhakar Rajashekhara Acked-by: Sneha Narnakaje Cc: David Woodhouse Signed-off-by: Andrew Morton --- Since v2, removed spilocks as that would cause jiffies not to increment. drivers/mtd/nand/davinci_nand.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 9c9d893..574c38a 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -311,7 +311,9 @@ static int nand_davinci_correct_4bit(struct mtd_info *mtd, unsigned short ecc10[8]; unsigned short *ecc16; u32 syndrome[4]; + u32 ecc_state; unsigned num_errors, corrected; + unsigned long timeo; /* All bytes 0xff? It's an erased page; ignore its ECC. */ for (i = 0; i < 10; i++) { @@ -361,6 +363,22 @@ compare: */ davinci_nand_writel(info, NANDFCR_OFFSET, davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13)); + + /* + * ECC_STATE field reads 0x3 (Error correction complete) immediately + * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately + * begin trying to poll for the state, you may fall right out of your + * loop without any of the correction calculations having taken place. + * The recommendation from the hardware team is to wait till ECC_STATE + * reads >= 4, which means ECC HW has entered correction state. + */ + timeo = jiffies + usecs_to_jiffies(100); + do { + ecc_state = (davinci_nand_readl(info, + NANDFSR_OFFSET) >> 8) & 0x0f; + cpu_relax(); + } while ((ecc_state < 4) && time_before(jiffies, timeo)); + for (;;) { u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET); -- 1.5.6 From nsekhar at ti.com Mon Jul 19 02:01:16 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Mon, 19 Jul 2010 12:31:16 +0530 Subject: [PATCH v2] asoc: davinci: let platform data define edma queue numbers Message-ID: <1279522876-11834-1-git-send-email-nsekhar@ti.com> Currently the EDMA queue to be used by for servicing ASP through internal RAM is fixed to EDMAQ_0 and that to service internal RAM from external RAM is fixed to EDMAQ_1. This may not be the desirable configuration on all platforms. For example, on DM365, queue 0 has large fifo size and is more suitable for video transfers. Having audio and video transfers on the same queue may lead to starvation on audio side. platform data as defined currently passes a queue number to the driver but that remains unused inside the driver. Fix this by defining one queue each for ASP and RAM transfers in the platform data and using it inside the driver. Since EDMAQ_0 maps to 0, thats the queue that will be used if the asp queue number is not initialized. None of the platforms currently utilize ping-pong transfers through internal RAM so that functionality remains unchanged too. This patch has been tested on DM644x and OMAP-L138 EVMs. Signed-off-by: Sekhar Nori Acked-by: Liam Girdwood --- This patch applies to for-2.6.36 branch of ASoC tree. v2: same as v1 except rebased to branch/tree noted above. arch/arm/mach-davinci/board-da830-evm.c | 2 +- arch/arm/mach-davinci/board-da850-evm.c | 2 +- arch/arm/mach-davinci/board-dm646x-evm.c | 4 ++-- arch/arm/mach-davinci/include/mach/asp.h | 3 ++- sound/soc/davinci/davinci-i2s.c | 10 ++++++++++ sound/soc/davinci/davinci-mcasp.c | 6 ++++-- sound/soc/davinci/davinci-pcm.c | 5 +++-- sound/soc/davinci/davinci-pcm.h | 3 ++- 8 files changed, 25 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 212d970..bc384d3 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -208,7 +208,7 @@ static struct snd_platform_data da830_evm_snd_data = { .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction), .tdm_slots = 2, .serial_dir = da830_iis_serializer_direction, - .eventq_no = EVENTQ_0, + .asp_chan_q = EVENTQ_0, .version = MCASP_VERSION_2, .txnumevt = 1, .rxnumevt = 1, diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 2ec3095..d4ec18d 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -342,7 +342,7 @@ static struct snd_platform_data da850_evm_snd_data = { .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), .tdm_slots = 2, .serial_dir = da850_iis_serializer_direction, - .eventq_no = EVENTQ_1, + .asp_chan_q = EVENTQ_1, .version = MCASP_VERSION_2, .txnumevt = 1, .rxnumevt = 1, diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 6d88893..87521f2 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -323,7 +323,7 @@ static struct snd_platform_data dm646x_evm_snd_data[] = { .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction), .tdm_slots = 2, .serial_dir = dm646x_iis_serializer_direction, - .eventq_no = EVENTQ_0, + .asp_chan_q = EVENTQ_0, }, { .tx_dma_offset = 0x400, @@ -332,7 +332,7 @@ static struct snd_platform_data dm646x_evm_snd_data[] = { .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction), .tdm_slots = 32, .serial_dir = dm646x_dit_serializer_direction, - .eventq_no = EVENTQ_0, + .asp_chan_q = EVENTQ_0, }, }; diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index b12c69e..9aa2409 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -52,7 +52,8 @@ struct snd_platform_data { u32 tx_dma_offset; u32 rx_dma_offset; - enum dma_event_q eventq_no; /* event queue number */ + enum dma_event_q asp_chan_q; /* event queue number for ASP channel */ + enum dma_event_q ram_chan_q; /* event queue number for RAM channel */ unsigned int codec_fmt; /* * Allowing this is more efficient and eliminates left and right swaps diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c index b251bc9..9e8932a 100644 --- a/sound/soc/davinci/davinci-i2s.c +++ b/sound/soc/davinci/davinci-i2s.c @@ -648,6 +648,8 @@ static int davinci_i2s_probe(struct platform_device *pdev) struct snd_platform_data *pdata = pdev->dev.platform_data; struct davinci_mcbsp_dev *dev; struct resource *mem, *ioarea, *res; + enum dma_event_q asp_chan_q = EVENTQ_0; + enum dma_event_q ram_chan_q = EVENTQ_1; int ret; mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -676,7 +678,15 @@ static int davinci_i2s_probe(struct platform_device *pdev) pdata->sram_size_capture; dev->clk_input_pin = pdata->clk_input_pin; dev->i2s_accurate_sck = pdata->i2s_accurate_sck; + asp_chan_q = pdata->asp_chan_q; + ram_chan_q = pdata->ram_chan_q; } + + dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].asp_chan_q = asp_chan_q; + dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].ram_chan_q = ram_chan_q; + dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].asp_chan_q = asp_chan_q; + dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].ram_chan_q = ram_chan_q; + dev->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(dev->clk)) { ret = -ENODEV; diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c index d395509..b247208 100644 --- a/sound/soc/davinci/davinci-mcasp.c +++ b/sound/soc/davinci/davinci-mcasp.c @@ -890,7 +890,8 @@ static int davinci_mcasp_probe(struct platform_device *pdev) dev->rxnumevt = pdata->rxnumevt; dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; - dma_data->eventq_no = pdata->eventq_no; + dma_data->asp_chan_q = pdata->asp_chan_q; + dma_data->ram_chan_q = pdata->ram_chan_q; dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset + io_v2p(dev->base)); @@ -904,7 +905,8 @@ static int davinci_mcasp_probe(struct platform_device *pdev) dma_data->channel = res->start; dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]; - dma_data->eventq_no = pdata->eventq_no; + dma_data->asp_chan_q = pdata->asp_chan_q; + dma_data->ram_chan_q = pdata->ram_chan_q; dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset + io_v2p(dev->base)); diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c index def454e..a712411 100644 --- a/sound/soc/davinci/davinci-pcm.c +++ b/sound/soc/davinci/davinci-pcm.c @@ -381,7 +381,7 @@ static int request_ping_pong(struct snd_pcm_substream *substream, /* Request ram master channel */ link = prtd->ram_channel = edma_alloc_channel(EDMA_CHANNEL_ANY, davinci_pcm_dma_irq, substream, - EVENTQ_1); + prtd->params->ram_chan_q); if (link < 0) goto exit1; @@ -477,7 +477,8 @@ static int davinci_pcm_dma_request(struct snd_pcm_substream *substream) /* Request asp master DMA channel */ link = prtd->asp_channel = edma_alloc_channel(params->channel, - davinci_pcm_dma_irq, substream, EVENTQ_0); + davinci_pcm_dma_irq, substream, + prtd->params->asp_chan_q); if (link < 0) goto exit1; diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h index 0764944..b799a02 100644 --- a/sound/soc/davinci/davinci-pcm.h +++ b/sound/soc/davinci/davinci-pcm.h @@ -21,7 +21,8 @@ struct davinci_pcm_dma_params { unsigned short acnt; dma_addr_t dma_addr; /* device physical address for DMA */ unsigned sram_size; - enum dma_event_q eventq_no; /* event queue number */ + enum dma_event_q asp_chan_q; /* event queue number for ASP channel */ + enum dma_event_q ram_chan_q; /* event queue number for RAM channel */ unsigned char data_type; /* xfer data type */ unsigned char convert_mono_stereo; unsigned int fifo_level; -- 1.6.2.4 From nsekhar at ti.com Mon Jul 19 02:05:54 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Mon, 19 Jul 2010 12:35:54 +0530 Subject: [PATCH] asoc: davinci: let platform data define edma queue numbers In-Reply-To: <20100717185018.GC27456@rakim.wolfsonmicro.main> References: <1279196059-6031-1-git-send-email-nsekhar@ti.com> <20100717185018.GC27456@rakim.wolfsonmicro.main> Message-ID: Hi Mark, On Sun, Jul 18, 2010 at 00:20:19, Mark Brown wrote: > On Thu, Jul 15, 2010 at 05:44:19PM +0530, Sekhar Nori wrote: > > > This patch has been tested on DM644x and OMAP-L138 EVMs. > > > Signed-off-by: Sekhar Nori > > > This patch applies to latest of Linus's tree. > > ...so it doesn't apply against my for-2.6.36 branch (and obviously > there's crossover with Kevin's tree as well which makes things possibly > a bit interesting too). Could you please regenerate against for-2.6.36? > You should generally always send patches against the latest version of > code rather than Linus' tree, using other trees increases the chances > that your patch will not apply. Thanks for the feedback. I rebased against for-2.6.36 and sent a v2. Regards, Sekhar From zhuo_liu at panovasic.com Mon Jul 19 03:32:58 2010 From: zhuo_liu at panovasic.com (zhuo_liu at panovasic.com) Date: 19 Jul 2010 16:32:58 +0800 Subject: TSIF sourcecode Message-ID: <20100719083418.E7757419@smtp5.263xmail.com> An HTML attachment was scrubbed... URL: From michael.williamson at criticallink.com Mon Jul 19 06:43:33 2010 From: michael.williamson at criticallink.com (Michael Williamson) Date: Mon, 19 Jul 2010 07:43:33 -0400 Subject: [PATCH] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: <1279324167.4526.85.camel@Joe-Laptop.home> References: <1279324167.4526.85.camel@Joe-Laptop.home> Message-ID: <4C443A65.4010105@criticallink.com> On 7/16/2010 7:49 PM, Joe Perches wrote: > On Fri, 2010-07-16 at 10:00 -0400, Michael Williamson wrote: > >> +static __init void mityomapl138_setup_lcd(void) >> +{ >> > [] > >> + pr_warning("mityomapl138_init: unknown LCD type : %s\n", >> + peripheral_config.LCDConfig.PanelName); >> > I think you'd be better off actually using the actual > function name rather than the caller name > Absolutely. Didn't catch those when shuffling around during cleanup / etc. I will clean these up and resubmit. Thank you for the feedback. [Message resent due to bad client configuration]. -Mike From michael.williamson at criticallink.com Mon Jul 19 08:21:30 2010 From: michael.williamson at criticallink.com (Michael Williamson) Date: Mon, 19 Jul 2010 09:21:30 -0400 Subject: [PATCH v2] davinci: Add MityDSP-L138/MityARM-1808 SOM support Message-ID: <4C44515A.4030003@criticallink.com> This patch adds support for the MityDSP-L138 and MityARM-1808 system on module (SOM) under the registered machine "mityomapl138". These SOMs are based on the da850 davinci CPU architecture. Information on these SOMs may be found at http://www.mitydsp.com. Signed-off-by: Michael Williamson --- Changes since v1, reworked pr_* calls to use __func__ macro for proper location of error / info messages in source code. Adding ARM PORT list for requested ATAG_PERIPHERAL in /arch/arm/include/asm/setup.h arch/arm/configs/mityomapl138_defconfig | 1764 ++++++++++++++++++++ arch/arm/include/asm/setup.h | 5 + arch/arm/mach-davinci/Kconfig | 7 + arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/board-mityomapl138.c | 799 +++++++++ .../mach-davinci/include/mach/cb-mityomapl138.h | 125 ++ arch/arm/mach-davinci/include/mach/da8xx.h | 1 + arch/arm/mach-davinci/include/mach/uncompress.h | 1 + 8 files changed, 2703 insertions(+), 0 deletions(-) diff --git a/arch/arm/configs/mityomapl138_defconfig b/arch/arm/configs/mityomapl138_defconfig new file mode 100644 index 0000000..513b851 --- /dev/null +++ b/arch/arm/configs/mityomapl138_defconfig @@ -0,0 +1,1764 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.34-rc1 +# Thu Apr 22 09:46:57 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +CONFIG_ARCH_DAVINCI=y +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_CP_INTC=y + +# +# TI DaVinci Implementations +# + +# +# DaVinci Core Type +# +# CONFIG_ARCH_DAVINCI_DM644x is not set +# CONFIG_ARCH_DAVINCI_DM355 is not set +# CONFIG_ARCH_DAVINCI_DM646x is not set +# CONFIG_ARCH_DAVINCI_DA830 is not set +CONFIG_ARCH_DAVINCI_DA850=y +CONFIG_DA8XX_MAX_SPEED_300=y +# CONFIG_DA8XX_MAX_SPEED_372 is not set +# CONFIG_DA8XX_MAX_SPEED_408 is not set +# CONFIG_DA8XX_MAX_SPEED_456 is not set +CONFIG_ARCH_DAVINCI_DA8XX=y +# CONFIG_ARCH_DAVINCI_DM365 is not set + +# +# DaVinci Board Type +# +# CONFIG_MACH_DAVINCI_DA850_EVM is not set +CONFIG_MACH_MITYOMAPL138=y +CONFIG_DAVINCI_MUX=y +CONFIG_DAVINCI_MUX_DEBUG=y +CONFIG_DAVINCI_MUX_WARNINGS=y +CONFIG_DAVINCI_RESET_CLOCKS=y +# CONFIG_DAVINCI_MCBSP is not set + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_CPU_DCACHE_WRITETHROUGH=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=m +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +CONFIG_MTD_DEBUG=y +CONFIG_MTD_DEBUG_VERBOSE=0 +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_FTL=y +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_CFI_AMDSTD is not set +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_DAVINCI_NOR is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_NAND_DAVINCI=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=32768 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_LXT_PHY=y +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +CONFIG_LSI_ET1011C_PHY=y +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +CONFIG_TI_DAVINCI_EMAC=y +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +CONFIG_KEYBOARD_XTKBD=m +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_DAVINCI=y +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_DAVINCI=y +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_PCA953X=y +# CONFIG_GPIO_PCA953X_IRQ is not set +CONFIG_GPIO_PCF857X=y +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_DAVINCI_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507x is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB4500_CORE is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +CONFIG_REGULATOR_TPS65023=y +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_DAVINCI is not set +# CONFIG_FB_VIRTUAL is not set +CONFIG_FB_DA8XX=y +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=m +CONFIG_BACKLIGHT_GENERIC=m + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +CONFIG_NOP_USB_XCEIV=y +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_OMAP=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=m +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=m +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index f392fb4..d6b1a47 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -143,6 +143,11 @@ struct tag_memclk { __u32 fmemclk; }; +/** MityDSP-L138 peripheral configuration info, + * see arch/arm/mach-davinci/include/mach/cb-mityomapl138.h + */ +#define ATAG_PERIPHERALS 0x42000101 + struct tag { struct tag_header hdr; union { diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 71f90f8..064b0e2 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -178,6 +178,13 @@ config DA850_UI_RMII endchoice +config MACH_MITYOMAPL138 + bool "Critical Link MityOMAPL138 SoM" + depends on ARCH_DAVINCI_DA850 + select GPIO_PCA953X + help + Say Y here to select the Critical Link MityOMAP-L138 System on Module. + config MACH_TNETV107X bool "TI TNETV107X Reference Platform" default ARCH_DAVINCI_TNETV107X diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index eab4c0f..dfc0fc4 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o +obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o # Power Management diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c new file mode 100644 index 0000000..ea9328b --- /dev/null +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -0,0 +1,799 @@ +/* + * Critical Link MityOMAP-L138 SoM + * + * Copyright (C) 2010 Critical Link Incorporated - http://www.criticallink.com + * + * Derived from board-da850-evm.c + * Original Copyrights follow: + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from: arch/arm/mach-davinci/board-da830-evm.c + * Original Copyrights follow: + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct tag_peripherals peripheral_config = { + .Version = PERIPHERALS_VERSION, + .Manufacturer = "Critical Link", + .ENETConfig.EnetConfig = ENET_CONFIG_MII, + .ENETConfig.MACAddr = { 0x00, 0x50, 0xC2, 0x49, 0xDF, 0xFF }, + .UARTConfig[0] = { + .Enable = 0, + .IsConsole = 0, + .Baud = 115200, + }, + .UARTConfig[1] = { + .Enable = 1, + .IsConsole = 1, + .Baud = 115200, + }, + .UARTConfig[2] = { + .Enable = 0, + .IsConsole = 0, + .Baud = 115200, + }, + .SPIConfig[0] = { + .Enable = 0, + .CLKOut = 0, + .CSEnable = { 0, 0, 0, 0, 0, 0, 0, 0}, + .ENAEnable = 0, + .CLKRate = 0, + }, + .SPIConfig[1] = { + .Enable = 1, + .CLKOut = 1, + .CSEnable = { 1, 0, 0, 0, 0, 0, 0, 0}, + .ENAEnable = 0, + .CLKRate = 30000000, + }, + .LCDConfig = { + .Enable = 0, + .PanelName = "", + } +}; + + +#define MITYOMAPL138_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ + +#define MSTPRI2_LCD_MASK 0x70000000 +#define MSTPRI2_LCD_SHIFT 28 + +#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) +#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) + +/* MityDSP-L138 includes a 256 MByte large-page NAND flash + * (128K blocks). + */ +struct mtd_partition mityomapl138_nandflash_partition[] = { + { + .name = "rootfs", + .offset = 0, + .size = SZ_128M, + .mask_flags = 0, /* MTD_WRITEABLE, */ + }, + { + .name = "homefs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct davinci_nand_pdata mityomapl138_nandflash_data = { + .parts = mityomapl138_nandflash_partition, + .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16, + .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ +}; + +static struct resource mityomapl138_nandflash_resource[] = { + { + .start = DA8XX_AEMIF_CS3_BASE, + .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mityomapl138_nandflash_device = { + .name = "davinci_nand", + .id = 0, + .dev = { + .platform_data = &mityomapl138_nandflash_data, + }, + .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), + .resource = mityomapl138_nandflash_resource, +}; + +static struct platform_device *mityomapl138_devices[] __initdata = { + &mityomapl138_nandflash_device, +}; + +static __init void mityomapl138_setup_nand(void) +{ + + platform_add_devices(mityomapl138_devices, + ARRAY_SIZE(mityomapl138_devices)); +} + +static int mityomapl138_mmc_get_ro(int index) +{ + return gpio_get_value(DA850_MMCSD_WP_PIN); +} + +static int mityomapl138_mmc_get_cd(int index) +{ + return !gpio_get_value(DA850_MMCSD_CD_PIN); +} + +static struct davinci_mmc_config da850_mmc_config = { + .get_ro = mityomapl138_mmc_get_ro, + .get_cd = mityomapl138_mmc_get_cd, + .wires = 4, + .max_freq = 50000000, + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + .version = MMC_CTLR_VERSION_2, +}; + +static __init void mityomapl138_setup_mmc(void) +{ + int ret; + + ret = davinci_cfg_reg_list(da850_mmcsd0_pins); + if (ret) + pr_warning("%s: mmcsd0 mux setup failed:" " %d\n", __func__,ret); + + ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n"); + if (ret) + pr_warning("%s: can not open GPIO %d\n", __func__, DA850_MMCSD_CD_PIN); + gpio_direction_input(DA850_MMCSD_CD_PIN); + + ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n"); + if (ret) + pr_warning("%s: can not open GPIO %d\n", __func__, DA850_MMCSD_WP_PIN); + gpio_direction_input(DA850_MMCSD_WP_PIN); + + ret = da8xx_register_mmcsd0(&da850_mmc_config); + if (ret) + pr_warning("%s: mmcsd0 registration failed:", __func__, " %d\n", ret); +} + + +static struct davinci_uart_config mityomapl138_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static int __init mityomapl138_config_emac(void) +{ + void __iomem *cfg_chip3_base; + int ret; + u32 val; + struct davinci_soc_info *soc_info = &davinci_soc_info; + u8 rmii_en = 0; + + switch (peripheral_config.ENETConfig.EnetConfig) { + case ENET_CONFIG_RMII: + soc_info->emac_pdata->rmii_en = 1; + rmii_en = 1; + break; + case ENET_CONFIG_MII: + soc_info->emac_pdata->rmii_en = 0; + rmii_en = 0; + break; + case ENET_CONFIG_NONE: + default: + pr_info("EMAC: No Ethernet PHY Selected, EMAC disabled\n"); + return 0; /* no enet... */ + break; + } + memcpy(&soc_info->emac_pdata->mac_addr[0], + &peripheral_config.ENETConfig.MACAddr[0], 6); + + cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); + + val = __raw_readl(cfg_chip3_base); + + if (rmii_en) { + val |= BIT(8); + ret = davinci_cfg_reg_list(da850_rmii_pins); + pr_info("EMAC: RMII PHY configured, MII PHY will not be" + " functional\n"); + } else { + val &= ~BIT(8); + ret = davinci_cfg_reg_list(da850_cpgmac_pins); + pr_info("EMAC: MII PHY configured, RMII PHY will not be" + " functional\n"); + } + + if (ret) + pr_warning("%s: cpgmac/rmii mux setup failed: %d\n", __func__, ret); + + /* configure the CFGCHIP3 register for RMII or MII */ + __raw_writel(val, cfg_chip3_base); + + soc_info->emac_pdata->phy_mask = peripheral_config.ENETConfig.PHYMask ? + peripheral_config.ENETConfig.PHYMask : 1; + pr_info("%s: setting phy_mask to %x\n", __func__, + soc_info->emac_pdata->phy_mask); + soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY; + + ret = da8xx_register_emac(); + if (ret) + pr_warning("%s: emac registration failed: %d\n", __func__, ret); + + return 0; +} +device_initcall(mityomapl138_config_emac); + +static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { + .bus_freq = 100, /* kHz */ + .bus_delay = 0, /* usec */ +}; + +/* TPS65070 voltage regulator support */ + +/* 1.2V Core */ +struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { + { + .supply = "cvdd", + }, +}; + +/* 1.8V */ +struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { + { + .supply = "usb0_vdda18", + }, + { + .supply = "usb1_vdda18", + }, + { + .supply = "ddr_dvdd18", + }, + { + .supply = "sata_vddr", + }, +}; + +/* 1.2V */ +struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { + { + .supply = "sata_vdd", + }, + { + .supply = "usb_cvdd", + }, + { + .supply = "pll0_vdda", + }, + { + .supply = "pll1_vdda", + }, +}; + +/* 1.8V Aux LDO */ +struct regulator_consumer_supply tps65023_ldo1_consumers[] = { + { + .supply = "1.8v_aux", + }, +}; + +/* VCC Aux (1.8 or 3.3) LDO */ +struct regulator_consumer_supply tps65023_ldo2_consumers[] = { + { + .supply = "vccaux", + }, +}; + + +struct regulator_init_data tps65023_regulator_data[] = { + /* dcdc1 */ + { + .constraints = { + .min_uV = 1150000, + .max_uV = 1350000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers), + .consumer_supplies = tps65023_dcdc1_consumers, + }, + + /* dcdc2 */ + { + .constraints = { + .min_uV = 1710000, + .max_uV = 1910000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers), + .consumer_supplies = tps65023_dcdc2_consumers, + }, + + /* dcdc3 */ + { + .constraints = { + .min_uV = 1120000, + .max_uV = 1320000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers), + .consumer_supplies = tps65023_dcdc3_consumers, + }, + + /* ldo1 */ + { + .constraints = { + .min_uV = 1710000, + .max_uV = 1890000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers), + .consumer_supplies = tps65023_ldo1_consumers, + }, + + /* ldo2 */ + { + .constraints = { + .min_uV = 3140000, + .max_uV = 3420000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers), + .consumer_supplies = tps65023_ldo2_consumers, + }, +}; + + +static struct i2c_board_info __initdata mityomap_tps65023_info[] = { + { + I2C_BOARD_INFO("tps65023", 0x48), + .platform_data = &tps65023_regulator_data[0], + }, + { + I2C_BOARD_INFO("24c02", 0x50), + }, +}; + +static int __init pmic_tps65023_init(void) +{ + return i2c_register_board_info(1, mityomap_tps65023_info, + ARRAY_SIZE(mityomap_tps65023_info)); +} + +static struct davinci_spi_platform_data mityomap_spi1_pdata = { + .version = SPI_VERSION_2, + .num_chipselect = 1, + .wdelay = 0, + .odd_parity = 0, + .parity_enable = 0, + .wait_enable = 0, + .timer_disable = 0, + .clk_internal = 1, + .cs_hold = 1, + .intr_level = 0, + .poll_mode = 1, + .use_dma = 0, + .c2tdelay = 8, + .t2cdelay = 8, +}; + +static struct resource mityomap_spi1_resources[] = { + [0] = { + .start = 0x01F0E000, + .end = 0x01F0EFFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DA8XX_SPINT1, + .start = IRQ_DA8XX_SPINT1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = EDMA_CTLR_CHAN(0, 18), + .end = EDMA_CTLR_CHAN(0, 18), + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = EDMA_CTLR_CHAN(0, 19), + .end = EDMA_CTLR_CHAN(0, 19), + .flags = IORESOURCE_DMA, + }, + [4] = { + .start = 1, + .end = 1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device mityomap_spi1_device = { + .name = "spi_davinci", + .id = 1, + .dev = { + .platform_data = &mityomap_spi1_pdata, + }, + .num_resources = ARRAY_SIZE(mityomap_spi1_resources), + .resource = mityomap_spi1_resources, +}; + +/***************************************************************************** + * SPI Devices: + * SPI1_CS0: 8M Flash ST-M25P64-VME6G + ****************************************************************************/ +static struct mtd_partition spi_flash_partitions[] = { + [0] = { + .name = "UBL", + .offset = 0, + .size = SZ_64K, + .mask_flags = MTD_WRITEABLE + }, + [1] = { + .name = "U-Boot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = 0, + }, + [2] = { + .name = "Spare", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct flash_platform_data mityomap_spi_flash_data = { + .name = "m25p80", + .parts = spi_flash_partitions, + .nr_parts = ARRAY_SIZE(spi_flash_partitions), + .type = "m25p64", +}; + +static struct spi_board_info mityomap_spi_flash_info[] = { + { + .modalias = "m25p80", + .platform_data = &mityomap_spi_flash_data, + .mode = SPI_MODE_0, + .max_speed_hz = 30000000, + .bus_num = 1, + .chip_select = 0, + }, +}; + +void __init mityomap_init_spi1(unsigned chipselect_mask, + struct spi_board_info *info, unsigned len) +{ + int ret; + ret = platform_device_register(&mityomap_spi1_device); + if (ret) + pr_warning("%s failed to register spi device : %d\n", __func__, ret); + + ret = spi_register_board_info(info, len); + if (ret) + pr_warning("%s failed to register board info : %d\n", __func__, ret); +} + +/* davinci da850 evm audio machine driver */ +static u8 da850_iis_serializer_direction[] = { + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static struct snd_platform_data mityomapl138_snd_data = { + .tx_dma_offset = 0x2000, + .rx_dma_offset = 0x2000, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), + .tdm_slots = 0, + .serial_dir = da850_iis_serializer_direction, + .eventq_no = EVENTQ_1, + .version = MCASP_VERSION_2, + .txnumevt = 0, + .rxnumevt = 0, +}; + +short mityomapl138_mcasp_pins[24] __initdata = { + DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, + DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, + DA850_AMUTE, + -1, -1, -1, -1, + -1, -1, -1, -1, + -1, -1, -1, -1, + -1, -1, -1, -1, + -1 +}; + +static __init int mityomapl138_setup_mcasp(void) +{ + int ret; + + mityomapl138_mcasp_pins[7+0] = DA850_AXR_13; + da850_iis_serializer_direction[12] = TX_MODE; + + ret = davinci_cfg_reg_list(mityomapl138_mcasp_pins); + if (ret) + pr_warning("%s: mcasp mux setup failed: %d\n", __func__, ret); + + mityomapl138_snd_data.tdm_slots = 2; + mityomapl138_snd_data.txnumevt = 1; + + da8xx_register_mcasp(0, &mityomapl138_snd_data); + + return ret; +} + +static const struct display_panel disp_panel = { + QVGA, + 16, + 16, + COLOR_ACTIVE, +}; + +static struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 255, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 0, + .invert_frm_clock = 0, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + +static struct da8xx_lcdc_platform_data sharp_lq035q7dh06_pdata = { + .manu_name = "sharp", + .controller_data = &lcd_cfg, + .type = "Sharp_LQ035Q7DH06", +}; + +static struct da8xx_lcdc_platform_data chimei_p0430wqlb_pdata = { + .manu_name = "ChiMei", + .controller_data = &lcd_cfg, + .type = "ChiMei_P0430WQLB", +}; + +static struct da8xx_lcdc_platform_data vga_640x480_pdata = { + .manu_name = "VGA", + .controller_data = &lcd_cfg, + .type = "vga_640x480", +}; + +static struct resource da8xx_lcdc_resources[] = { + [0] = { /* registers */ + .start = DA8XX_LCD_CNTRL_BASE, + .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { /* interrupt */ + .start = IRQ_DA8XX_LCDINT, + .end = IRQ_DA8XX_LCDINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_lcdc_device = { + .name = "da8xx_lcdc", + .id = 0, + .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), + .resource = da8xx_lcdc_resources, + .dev = { + .platform_data = &sharp_lq035q7dh06_pdata, + } +}; + +static __init void mityomapl138_setup_lcd(void) +{ + int ret; + + if (peripheral_config.LCDConfig.Enable) { + u32 prio; + + /* set peripheral master priority up to 1 */ + prio = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_MSTPRI2_REG)); + prio &= ~MSTPRI2_LCD_MASK; + prio |= 1<u.cmdline.cmdline[0]; + memcpy(&peripheral_config, ptag, sizeof(peripheral_config)); + pr_info("Peripheral Config Block Found\n"); + pr_info("Enet_Config = %d\n", peripheral_config.ENETConfig.EnetConfig); + pr_info("EMAC = %02X:%02X:%02X:%02X:%02X:%02X\n", + peripheral_config.ENETConfig.MACAddr[0], + peripheral_config.ENETConfig.MACAddr[1], + peripheral_config.ENETConfig.MACAddr[2], + peripheral_config.ENETConfig.MACAddr[3], + peripheral_config.ENETConfig.MACAddr[4], + peripheral_config.ENETConfig.MACAddr[5]); + pr_info("PHYMask = 0x%x\n", peripheral_config.ENETConfig.PHYMask); + if (peripheral_config.LCDConfig.Enable) + pr_info("LCD Configured : %s\n", + peripheral_config.LCDConfig.PanelName); + else + pr_info("No LCD Configured\n"); + + for (i = 0; i < 3; i++) { + pr_info("UART[%d] = %d, %d, %d, %d\n", i, + peripheral_config.UARTConfig[i].Enable, + peripheral_config.UARTConfig[i].IsConsole, + peripheral_config.UARTConfig[i].EnableHWFlowCtrl, + peripheral_config.UARTConfig[i].Baud); + } + for (i = 0; i < 2; i++) { + int mask = 0; + for (j = 0; j < 8; j++) + mask |= ((peripheral_config.SPIConfig[i].CSEnable[j]) ? + (1<> 18) & 0xfffc, + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = mityomapl138_map_io, + .init_irq = cp_intc_init, + .timer = &davinci_timer, + .init_machine = mityomapl138_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h new file mode 100644 index 0000000..7ba085a --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h @@ -0,0 +1,125 @@ +/** + * Factory / Peripheral Configuration Data as provided by ATAG_PERIPHERAL + * for the MityDSP-L138 SOMs. (mityomapl138 machines) + * + * Copyright (C) 2010 Critical Link LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef CONFIG_BLOCK_H_ +#define CONFIG_BLOCK_H_ + +#define CONFIG_MAGIC_WORD 0x00BD0138 +#define CONFIG_VERSION 0x00010000 + +#define ENET_CONFIG_NONE 1 +#define ENET_CONFIG_MII 2 +#define ENET_CONFIG_RMII 3 + +#define CONFIG_I2C_MAGIC_WORD 0x012C0138 +#define CONFIG_I2C_VERSION 0x00010001 + +/** + * Peripherals Version History + * 1.00 Baseline + * 1.01 Added McASP Configuration + * 1.02 Added ethernet phy mask + */ +#define PERIPHERALS_VERSION 0x00010002 + +#ifndef CONFIG_MITYDSP_ENV_SIZE +#define CONFIG_MITYDSP_ENV_SIZE (64 << 10) +#endif + +#define FPGATYPE_NONE 0 +#define FPGATYPE_XC6SLX9 1 +#define FPGATYPE_XC6SLX16 2 +#define FPGATYPE_XC6SLX25 3 +#define FPGATYPE_XC6SLX45 4 +#define FPGATYPE_UNKNOWN 10000 + +struct I2CFactoryConfig { + u32 ConfigMagicWord; /** CONFIG_I2C_MAGIC_WORD */ + u32 ConfigVersion; /** CONFIG_I2C_VERSION */ + u8 MACADDR[6]; /** mac address assigned to part */ + u32 FpgaType; /** fpga installed, see above */ + u32 Spare; /** Not Used */ + u32 SerialNumber; /** serial number of part */ + char PartNumber[32]; /** board part number */ +}; + +struct UARTConfig { + u8 Enable; /** enable Tx/Rx */ + u8 IsConsole; /** cfg as the console */ + u8 EnableHWFlowCtrl; /** cfg CTS/RTS */ + u32 Baud; /** default baud rate */ +}; + +struct SPIConfig { + u8 Enable; /** cfg dev+CLK, SIMO, SOMI pins */ + u8 CLKOut; /** drive the CLK */ + u8 CSEnable[8]; /** cfg the associated CS as output */ + u8 ENAEnable; /** cfg the ENA pin for SPI function */ + u32 CLKRate; /** default clock rate */ + u8 Spare[8]; +}; + +struct LCDConfig { + u8 Enable; + u8 PanelName[32]; +}; + +struct ENETConfig { + u32 EnetConfig; + u8 MACAddr[6]; + u32 PHYMask; + u8 Spare[8]; +}; + +#define MCASP_PINMODE_INACTIVE 0 +#define MCASP_PINMODE_TX 1 +#define MCASP_PINMODE_RX 2 + +struct MCASPConfig { + u8 Enable; + u8 Mode; + u8 PinMode[16]; +}; +/** + * struct tag_peripherals is passed in via kernel ATAG_PERIPHERALS + */ +struct tag_peripherals { + u32 Version; /** == PERIPHERALS_VERSION */ + u8 Manufacturer[64]; /** null terminated string indicating manufacturer */ + struct ENETConfig ENETConfig; /** Enable on-board ethernet */ + struct UARTConfig UARTConfig[3]; /** default UART 0,1,2 Configuration */ + struct SPIConfig SPIConfig[2]; + struct LCDConfig LCDConfig; + struct MCASPConfig MCASPConfig; +}; + +/** + * This structure can only be grown. You cannot make it smaller... + */ +struct MityDSPL138Config { + u32 ConfigMagicWord; /** == CONFIG_MAGIC_WORD */ + u32 ConfigVersion; /** version of the configuration block */ + u32 ConfigSizeBytes; /** configuration size, in bytes */ + struct tag_peripherals Peripherals; +}; + +struct MityDSPL138ConfigBlock { + union { + struct MityDSPL138Config config; + u8 space[CONFIG_MITYDSP_ENV_SIZE-sizeof(int)]; + } Data; + unsigned int CheckSum; /** summed bytes of ConfigSizeBytes */ +}; + +extern struct MityDSPL138Config config_block; +extern struct I2CFactoryConfig factory_config_block; +extern int get_config_block(void); +extern int get_factory_config_block(void); + +#endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 1b31a9a..1989316 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -41,6 +41,7 @@ extern void __iomem *da8xx_syscfg1_base; #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) #define DA8XX_JTAG_ID_REG 0x18 +#define DA8XX_MSTPRI2_REG 0x118 #define DA8XX_CFGCHIP0_REG 0x17c #define DA8XX_CFGCHIP2_REG 0x184 #define DA8XX_CFGCHIP3_REG 0x188 diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 15a6192..db6f1cd 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -88,6 +88,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* DA8xx boards */ DEBUG_LL_DA8XX(davinci_da830_evm, 2); DEBUG_LL_DA8XX(davinci_da850_evm, 2); + DEBUG_LL_DA8XX(mityomapl138, 1); /* TNETV107x boards */ DEBUG_LL_TNETV107X(tnetv107x, 1); -- Mike Williamson www.criticallink.com www.mitydsp.com 315-425-4045x230 From michael.williamson at criticallink.com Mon Jul 19 08:35:43 2010 From: michael.williamson at criticallink.com (Michael Williamson) Date: Mon, 19 Jul 2010 09:35:43 -0400 Subject: [PATCH v2] davinci: Add MityDSP-L138/MityARM-1808 SOM support Message-ID: <4C4454AF.4000801@criticallink.com> This patch adds support for the MityDSP-L138 and MityARM-1808 system on module (SOM) under the registered machine "mityomapl138". These SOMs are based on the da850 davinci CPU architecture. Information on these SOMs may be found at http://www.mitydsp.com. Signed-off-by: Michael Williamson --- Changes since v1, reworked pr_* calls to use __func__ macro for proper location of error / info messages in source code. Adding ARM PORT list for requested ATAG_PERIPHERAL in /arch/arm/include/asm/setup.h Resent -- bounced from arm kernel list for suspicious headers. Would be helpful if the robot gave a hint as to what it didn't like. Sorry for the noise. arch/arm/configs/mityomapl138_defconfig | 1764 ++++++++++++++++++++ arch/arm/include/asm/setup.h | 5 + arch/arm/mach-davinci/Kconfig | 7 + arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/board-mityomapl138.c | 799 +++++++++ .../mach-davinci/include/mach/cb-mityomapl138.h | 125 ++ arch/arm/mach-davinci/include/mach/da8xx.h | 1 + arch/arm/mach-davinci/include/mach/uncompress.h | 1 + 8 files changed, 2703 insertions(+), 0 deletions(-) diff --git a/arch/arm/configs/mityomapl138_defconfig b/arch/arm/configs/mityomapl138_defconfig new file mode 100644 index 0000000..513b851 --- /dev/null +++ b/arch/arm/configs/mityomapl138_defconfig @@ -0,0 +1,1764 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.34-rc1 +# Thu Apr 22 09:46:57 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +CONFIG_ARCH_DAVINCI=y +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_CP_INTC=y + +# +# TI DaVinci Implementations +# + +# +# DaVinci Core Type +# +# CONFIG_ARCH_DAVINCI_DM644x is not set +# CONFIG_ARCH_DAVINCI_DM355 is not set +# CONFIG_ARCH_DAVINCI_DM646x is not set +# CONFIG_ARCH_DAVINCI_DA830 is not set +CONFIG_ARCH_DAVINCI_DA850=y +CONFIG_DA8XX_MAX_SPEED_300=y +# CONFIG_DA8XX_MAX_SPEED_372 is not set +# CONFIG_DA8XX_MAX_SPEED_408 is not set +# CONFIG_DA8XX_MAX_SPEED_456 is not set +CONFIG_ARCH_DAVINCI_DA8XX=y +# CONFIG_ARCH_DAVINCI_DM365 is not set + +# +# DaVinci Board Type +# +# CONFIG_MACH_DAVINCI_DA850_EVM is not set +CONFIG_MACH_MITYOMAPL138=y +CONFIG_DAVINCI_MUX=y +CONFIG_DAVINCI_MUX_DEBUG=y +CONFIG_DAVINCI_MUX_WARNINGS=y +CONFIG_DAVINCI_RESET_CLOCKS=y +# CONFIG_DAVINCI_MCBSP is not set + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_CPU_DCACHE_WRITETHROUGH=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=m +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +CONFIG_MTD_DEBUG=y +CONFIG_MTD_DEBUG_VERBOSE=0 +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_FTL=y +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_CFI_AMDSTD is not set +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_DAVINCI_NOR is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_NAND_DAVINCI=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=32768 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_LXT_PHY=y +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +CONFIG_LSI_ET1011C_PHY=y +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +CONFIG_TI_DAVINCI_EMAC=y +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +CONFIG_KEYBOARD_XTKBD=m +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_DAVINCI=y +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_DAVINCI=y +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_PCA953X=y +# CONFIG_GPIO_PCA953X_IRQ is not set +CONFIG_GPIO_PCF857X=y +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_DAVINCI_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507x is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB4500_CORE is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +CONFIG_REGULATOR_TPS65023=y +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_DAVINCI is not set +# CONFIG_FB_VIRTUAL is not set +CONFIG_FB_DA8XX=y +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=m +CONFIG_BACKLIGHT_GENERIC=m + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +CONFIG_NOP_USB_XCEIV=y +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_OMAP=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=m +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=m +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index f392fb4..d6b1a47 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -143,6 +143,11 @@ struct tag_memclk { __u32 fmemclk; }; +/** MityDSP-L138 peripheral configuration info, + * see arch/arm/mach-davinci/include/mach/cb-mityomapl138.h + */ +#define ATAG_PERIPHERALS 0x42000101 + struct tag { struct tag_header hdr; union { diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 71f90f8..064b0e2 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -178,6 +178,13 @@ config DA850_UI_RMII endchoice +config MACH_MITYOMAPL138 + bool "Critical Link MityOMAPL138 SoM" + depends on ARCH_DAVINCI_DA850 + select GPIO_PCA953X + help + Say Y here to select the Critical Link MityOMAP-L138 System on Module. + config MACH_TNETV107X bool "TI TNETV107X Reference Platform" default ARCH_DAVINCI_TNETV107X diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index eab4c0f..dfc0fc4 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o +obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o # Power Management diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c new file mode 100644 index 0000000..ea9328b --- /dev/null +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -0,0 +1,799 @@ +/* + * Critical Link MityOMAP-L138 SoM + * + * Copyright (C) 2010 Critical Link Incorporated - http://www.criticallink.com + * + * Derived from board-da850-evm.c + * Original Copyrights follow: + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from: arch/arm/mach-davinci/board-da830-evm.c + * Original Copyrights follow: + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct tag_peripherals peripheral_config = { + .Version = PERIPHERALS_VERSION, + .Manufacturer = "Critical Link", + .ENETConfig.EnetConfig = ENET_CONFIG_MII, + .ENETConfig.MACAddr = { 0x00, 0x50, 0xC2, 0x49, 0xDF, 0xFF }, + .UARTConfig[0] = { + .Enable = 0, + .IsConsole = 0, + .Baud = 115200, + }, + .UARTConfig[1] = { + .Enable = 1, + .IsConsole = 1, + .Baud = 115200, + }, + .UARTConfig[2] = { + .Enable = 0, + .IsConsole = 0, + .Baud = 115200, + }, + .SPIConfig[0] = { + .Enable = 0, + .CLKOut = 0, + .CSEnable = { 0, 0, 0, 0, 0, 0, 0, 0}, + .ENAEnable = 0, + .CLKRate = 0, + }, + .SPIConfig[1] = { + .Enable = 1, + .CLKOut = 1, + .CSEnable = { 1, 0, 0, 0, 0, 0, 0, 0}, + .ENAEnable = 0, + .CLKRate = 30000000, + }, + .LCDConfig = { + .Enable = 0, + .PanelName = "", + } +}; + + +#define MITYOMAPL138_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ + +#define MSTPRI2_LCD_MASK 0x70000000 +#define MSTPRI2_LCD_SHIFT 28 + +#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) +#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) + +/* MityDSP-L138 includes a 256 MByte large-page NAND flash + * (128K blocks). + */ +struct mtd_partition mityomapl138_nandflash_partition[] = { + { + .name = "rootfs", + .offset = 0, + .size = SZ_128M, + .mask_flags = 0, /* MTD_WRITEABLE, */ + }, + { + .name = "homefs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct davinci_nand_pdata mityomapl138_nandflash_data = { + .parts = mityomapl138_nandflash_partition, + .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16, + .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ +}; + +static struct resource mityomapl138_nandflash_resource[] = { + { + .start = DA8XX_AEMIF_CS3_BASE, + .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mityomapl138_nandflash_device = { + .name = "davinci_nand", + .id = 0, + .dev = { + .platform_data = &mityomapl138_nandflash_data, + }, + .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), + .resource = mityomapl138_nandflash_resource, +}; + +static struct platform_device *mityomapl138_devices[] __initdata = { + &mityomapl138_nandflash_device, +}; + +static __init void mityomapl138_setup_nand(void) +{ + + platform_add_devices(mityomapl138_devices, + ARRAY_SIZE(mityomapl138_devices)); +} + +static int mityomapl138_mmc_get_ro(int index) +{ + return gpio_get_value(DA850_MMCSD_WP_PIN); +} + +static int mityomapl138_mmc_get_cd(int index) +{ + return !gpio_get_value(DA850_MMCSD_CD_PIN); +} + +static struct davinci_mmc_config da850_mmc_config = { + .get_ro = mityomapl138_mmc_get_ro, + .get_cd = mityomapl138_mmc_get_cd, + .wires = 4, + .max_freq = 50000000, + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + .version = MMC_CTLR_VERSION_2, +}; + +static __init void mityomapl138_setup_mmc(void) +{ + int ret; + + ret = davinci_cfg_reg_list(da850_mmcsd0_pins); + if (ret) + pr_warning("%s: mmcsd0 mux setup failed:" " %d\n", __func__,ret); + + ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n"); + if (ret) + pr_warning("%s: can not open GPIO %d\n", __func__, DA850_MMCSD_CD_PIN); + gpio_direction_input(DA850_MMCSD_CD_PIN); + + ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n"); + if (ret) + pr_warning("%s: can not open GPIO %d\n", __func__, DA850_MMCSD_WP_PIN); + gpio_direction_input(DA850_MMCSD_WP_PIN); + + ret = da8xx_register_mmcsd0(&da850_mmc_config); + if (ret) + pr_warning("%s: mmcsd0 registration failed:", __func__, " %d\n", ret); +} + + +static struct davinci_uart_config mityomapl138_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static int __init mityomapl138_config_emac(void) +{ + void __iomem *cfg_chip3_base; + int ret; + u32 val; + struct davinci_soc_info *soc_info = &davinci_soc_info; + u8 rmii_en = 0; + + switch (peripheral_config.ENETConfig.EnetConfig) { + case ENET_CONFIG_RMII: + soc_info->emac_pdata->rmii_en = 1; + rmii_en = 1; + break; + case ENET_CONFIG_MII: + soc_info->emac_pdata->rmii_en = 0; + rmii_en = 0; + break; + case ENET_CONFIG_NONE: + default: + pr_info("EMAC: No Ethernet PHY Selected, EMAC disabled\n"); + return 0; /* no enet... */ + break; + } + memcpy(&soc_info->emac_pdata->mac_addr[0], + &peripheral_config.ENETConfig.MACAddr[0], 6); + + cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); + + val = __raw_readl(cfg_chip3_base); + + if (rmii_en) { + val |= BIT(8); + ret = davinci_cfg_reg_list(da850_rmii_pins); + pr_info("EMAC: RMII PHY configured, MII PHY will not be" + " functional\n"); + } else { + val &= ~BIT(8); + ret = davinci_cfg_reg_list(da850_cpgmac_pins); + pr_info("EMAC: MII PHY configured, RMII PHY will not be" + " functional\n"); + } + + if (ret) + pr_warning("%s: cpgmac/rmii mux setup failed: %d\n", __func__, ret); + + /* configure the CFGCHIP3 register for RMII or MII */ + __raw_writel(val, cfg_chip3_base); + + soc_info->emac_pdata->phy_mask = peripheral_config.ENETConfig.PHYMask ? + peripheral_config.ENETConfig.PHYMask : 1; + pr_info("%s: setting phy_mask to %x\n", __func__, + soc_info->emac_pdata->phy_mask); + soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY; + + ret = da8xx_register_emac(); + if (ret) + pr_warning("%s: emac registration failed: %d\n", __func__, ret); + + return 0; +} +device_initcall(mityomapl138_config_emac); + +static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { + .bus_freq = 100, /* kHz */ + .bus_delay = 0, /* usec */ +}; + +/* TPS65070 voltage regulator support */ + +/* 1.2V Core */ +struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { + { + .supply = "cvdd", + }, +}; + +/* 1.8V */ +struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { + { + .supply = "usb0_vdda18", + }, + { + .supply = "usb1_vdda18", + }, + { + .supply = "ddr_dvdd18", + }, + { + .supply = "sata_vddr", + }, +}; + +/* 1.2V */ +struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { + { + .supply = "sata_vdd", + }, + { + .supply = "usb_cvdd", + }, + { + .supply = "pll0_vdda", + }, + { + .supply = "pll1_vdda", + }, +}; + +/* 1.8V Aux LDO */ +struct regulator_consumer_supply tps65023_ldo1_consumers[] = { + { + .supply = "1.8v_aux", + }, +}; + +/* VCC Aux (1.8 or 3.3) LDO */ +struct regulator_consumer_supply tps65023_ldo2_consumers[] = { + { + .supply = "vccaux", + }, +}; + + +struct regulator_init_data tps65023_regulator_data[] = { + /* dcdc1 */ + { + .constraints = { + .min_uV = 1150000, + .max_uV = 1350000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers), + .consumer_supplies = tps65023_dcdc1_consumers, + }, + + /* dcdc2 */ + { + .constraints = { + .min_uV = 1710000, + .max_uV = 1910000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers), + .consumer_supplies = tps65023_dcdc2_consumers, + }, + + /* dcdc3 */ + { + .constraints = { + .min_uV = 1120000, + .max_uV = 1320000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers), + .consumer_supplies = tps65023_dcdc3_consumers, + }, + + /* ldo1 */ + { + .constraints = { + .min_uV = 1710000, + .max_uV = 1890000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers), + .consumer_supplies = tps65023_ldo1_consumers, + }, + + /* ldo2 */ + { + .constraints = { + .min_uV = 3140000, + .max_uV = 3420000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers), + .consumer_supplies = tps65023_ldo2_consumers, + }, +}; + + +static struct i2c_board_info __initdata mityomap_tps65023_info[] = { + { + I2C_BOARD_INFO("tps65023", 0x48), + .platform_data = &tps65023_regulator_data[0], + }, + { + I2C_BOARD_INFO("24c02", 0x50), + }, +}; + +static int __init pmic_tps65023_init(void) +{ + return i2c_register_board_info(1, mityomap_tps65023_info, + ARRAY_SIZE(mityomap_tps65023_info)); +} + +static struct davinci_spi_platform_data mityomap_spi1_pdata = { + .version = SPI_VERSION_2, + .num_chipselect = 1, + .wdelay = 0, + .odd_parity = 0, + .parity_enable = 0, + .wait_enable = 0, + .timer_disable = 0, + .clk_internal = 1, + .cs_hold = 1, + .intr_level = 0, + .poll_mode = 1, + .use_dma = 0, + .c2tdelay = 8, + .t2cdelay = 8, +}; + +static struct resource mityomap_spi1_resources[] = { + [0] = { + .start = 0x01F0E000, + .end = 0x01F0EFFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DA8XX_SPINT1, + .start = IRQ_DA8XX_SPINT1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = EDMA_CTLR_CHAN(0, 18), + .end = EDMA_CTLR_CHAN(0, 18), + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = EDMA_CTLR_CHAN(0, 19), + .end = EDMA_CTLR_CHAN(0, 19), + .flags = IORESOURCE_DMA, + }, + [4] = { + .start = 1, + .end = 1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device mityomap_spi1_device = { + .name = "spi_davinci", + .id = 1, + .dev = { + .platform_data = &mityomap_spi1_pdata, + }, + .num_resources = ARRAY_SIZE(mityomap_spi1_resources), + .resource = mityomap_spi1_resources, +}; + +/***************************************************************************** + * SPI Devices: + * SPI1_CS0: 8M Flash ST-M25P64-VME6G + ****************************************************************************/ +static struct mtd_partition spi_flash_partitions[] = { + [0] = { + .name = "UBL", + .offset = 0, + .size = SZ_64K, + .mask_flags = MTD_WRITEABLE + }, + [1] = { + .name = "U-Boot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = 0, + }, + [2] = { + .name = "Spare", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct flash_platform_data mityomap_spi_flash_data = { + .name = "m25p80", + .parts = spi_flash_partitions, + .nr_parts = ARRAY_SIZE(spi_flash_partitions), + .type = "m25p64", +}; + +static struct spi_board_info mityomap_spi_flash_info[] = { + { + .modalias = "m25p80", + .platform_data = &mityomap_spi_flash_data, + .mode = SPI_MODE_0, + .max_speed_hz = 30000000, + .bus_num = 1, + .chip_select = 0, + }, +}; + +void __init mityomap_init_spi1(unsigned chipselect_mask, + struct spi_board_info *info, unsigned len) +{ + int ret; + ret = platform_device_register(&mityomap_spi1_device); + if (ret) + pr_warning("%s failed to register spi device : %d\n", __func__, ret); + + ret = spi_register_board_info(info, len); + if (ret) + pr_warning("%s failed to register board info : %d\n", __func__, ret); +} + +/* davinci da850 evm audio machine driver */ +static u8 da850_iis_serializer_direction[] = { + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static struct snd_platform_data mityomapl138_snd_data = { + .tx_dma_offset = 0x2000, + .rx_dma_offset = 0x2000, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), + .tdm_slots = 0, + .serial_dir = da850_iis_serializer_direction, + .eventq_no = EVENTQ_1, + .version = MCASP_VERSION_2, + .txnumevt = 0, + .rxnumevt = 0, +}; + +short mityomapl138_mcasp_pins[24] __initdata = { + DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, + DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, + DA850_AMUTE, + -1, -1, -1, -1, + -1, -1, -1, -1, + -1, -1, -1, -1, + -1, -1, -1, -1, + -1 +}; + +static __init int mityomapl138_setup_mcasp(void) +{ + int ret; + + mityomapl138_mcasp_pins[7+0] = DA850_AXR_13; + da850_iis_serializer_direction[12] = TX_MODE; + + ret = davinci_cfg_reg_list(mityomapl138_mcasp_pins); + if (ret) + pr_warning("%s: mcasp mux setup failed: %d\n", __func__, ret); + + mityomapl138_snd_data.tdm_slots = 2; + mityomapl138_snd_data.txnumevt = 1; + + da8xx_register_mcasp(0, &mityomapl138_snd_data); + + return ret; +} + +static const struct display_panel disp_panel = { + QVGA, + 16, + 16, + COLOR_ACTIVE, +}; + +static struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 255, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 0, + .invert_frm_clock = 0, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + +static struct da8xx_lcdc_platform_data sharp_lq035q7dh06_pdata = { + .manu_name = "sharp", + .controller_data = &lcd_cfg, + .type = "Sharp_LQ035Q7DH06", +}; + +static struct da8xx_lcdc_platform_data chimei_p0430wqlb_pdata = { + .manu_name = "ChiMei", + .controller_data = &lcd_cfg, + .type = "ChiMei_P0430WQLB", +}; + +static struct da8xx_lcdc_platform_data vga_640x480_pdata = { + .manu_name = "VGA", + .controller_data = &lcd_cfg, + .type = "vga_640x480", +}; + +static struct resource da8xx_lcdc_resources[] = { + [0] = { /* registers */ + .start = DA8XX_LCD_CNTRL_BASE, + .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { /* interrupt */ + .start = IRQ_DA8XX_LCDINT, + .end = IRQ_DA8XX_LCDINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_lcdc_device = { + .name = "da8xx_lcdc", + .id = 0, + .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), + .resource = da8xx_lcdc_resources, + .dev = { + .platform_data = &sharp_lq035q7dh06_pdata, + } +}; + +static __init void mityomapl138_setup_lcd(void) +{ + int ret; + + if (peripheral_config.LCDConfig.Enable) { + u32 prio; + + /* set peripheral master priority up to 1 */ + prio = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_MSTPRI2_REG)); + prio &= ~MSTPRI2_LCD_MASK; + prio |= 1<u.cmdline.cmdline[0]; + memcpy(&peripheral_config, ptag, sizeof(peripheral_config)); + pr_info("Peripheral Config Block Found\n"); + pr_info("Enet_Config = %d\n", peripheral_config.ENETConfig.EnetConfig); + pr_info("EMAC = %02X:%02X:%02X:%02X:%02X:%02X\n", + peripheral_config.ENETConfig.MACAddr[0], + peripheral_config.ENETConfig.MACAddr[1], + peripheral_config.ENETConfig.MACAddr[2], + peripheral_config.ENETConfig.MACAddr[3], + peripheral_config.ENETConfig.MACAddr[4], + peripheral_config.ENETConfig.MACAddr[5]); + pr_info("PHYMask = 0x%x\n", peripheral_config.ENETConfig.PHYMask); + if (peripheral_config.LCDConfig.Enable) + pr_info("LCD Configured : %s\n", + peripheral_config.LCDConfig.PanelName); + else + pr_info("No LCD Configured\n"); + + for (i = 0; i < 3; i++) { + pr_info("UART[%d] = %d, %d, %d, %d\n", i, + peripheral_config.UARTConfig[i].Enable, + peripheral_config.UARTConfig[i].IsConsole, + peripheral_config.UARTConfig[i].EnableHWFlowCtrl, + peripheral_config.UARTConfig[i].Baud); + } + for (i = 0; i < 2; i++) { + int mask = 0; + for (j = 0; j < 8; j++) + mask |= ((peripheral_config.SPIConfig[i].CSEnable[j]) ? + (1<> 18) & 0xfffc, + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = mityomapl138_map_io, + .init_irq = cp_intc_init, + .timer = &davinci_timer, + .init_machine = mityomapl138_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h new file mode 100644 index 0000000..7ba085a --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h @@ -0,0 +1,125 @@ +/** + * Factory / Peripheral Configuration Data as provided by ATAG_PERIPHERAL + * for the MityDSP-L138 SOMs. (mityomapl138 machines) + * + * Copyright (C) 2010 Critical Link LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef CONFIG_BLOCK_H_ +#define CONFIG_BLOCK_H_ + +#define CONFIG_MAGIC_WORD 0x00BD0138 +#define CONFIG_VERSION 0x00010000 + +#define ENET_CONFIG_NONE 1 +#define ENET_CONFIG_MII 2 +#define ENET_CONFIG_RMII 3 + +#define CONFIG_I2C_MAGIC_WORD 0x012C0138 +#define CONFIG_I2C_VERSION 0x00010001 + +/** + * Peripherals Version History + * 1.00 Baseline + * 1.01 Added McASP Configuration + * 1.02 Added ethernet phy mask + */ +#define PERIPHERALS_VERSION 0x00010002 + +#ifndef CONFIG_MITYDSP_ENV_SIZE +#define CONFIG_MITYDSP_ENV_SIZE (64 << 10) +#endif + +#define FPGATYPE_NONE 0 +#define FPGATYPE_XC6SLX9 1 +#define FPGATYPE_XC6SLX16 2 +#define FPGATYPE_XC6SLX25 3 +#define FPGATYPE_XC6SLX45 4 +#define FPGATYPE_UNKNOWN 10000 + +struct I2CFactoryConfig { + u32 ConfigMagicWord; /** CONFIG_I2C_MAGIC_WORD */ + u32 ConfigVersion; /** CONFIG_I2C_VERSION */ + u8 MACADDR[6]; /** mac address assigned to part */ + u32 FpgaType; /** fpga installed, see above */ + u32 Spare; /** Not Used */ + u32 SerialNumber; /** serial number of part */ + char PartNumber[32]; /** board part number */ +}; + +struct UARTConfig { + u8 Enable; /** enable Tx/Rx */ + u8 IsConsole; /** cfg as the console */ + u8 EnableHWFlowCtrl; /** cfg CTS/RTS */ + u32 Baud; /** default baud rate */ +}; + +struct SPIConfig { + u8 Enable; /** cfg dev+CLK, SIMO, SOMI pins */ + u8 CLKOut; /** drive the CLK */ + u8 CSEnable[8]; /** cfg the associated CS as output */ + u8 ENAEnable; /** cfg the ENA pin for SPI function */ + u32 CLKRate; /** default clock rate */ + u8 Spare[8]; +}; + +struct LCDConfig { + u8 Enable; + u8 PanelName[32]; +}; + +struct ENETConfig { + u32 EnetConfig; + u8 MACAddr[6]; + u32 PHYMask; + u8 Spare[8]; +}; + +#define MCASP_PINMODE_INACTIVE 0 +#define MCASP_PINMODE_TX 1 +#define MCASP_PINMODE_RX 2 + +struct MCASPConfig { + u8 Enable; + u8 Mode; + u8 PinMode[16]; +}; +/** + * struct tag_peripherals is passed in via kernel ATAG_PERIPHERALS + */ +struct tag_peripherals { + u32 Version; /** == PERIPHERALS_VERSION */ + u8 Manufacturer[64]; /** null terminated string indicating manufacturer */ + struct ENETConfig ENETConfig; /** Enable on-board ethernet */ + struct UARTConfig UARTConfig[3]; /** default UART 0,1,2 Configuration */ + struct SPIConfig SPIConfig[2]; + struct LCDConfig LCDConfig; + struct MCASPConfig MCASPConfig; +}; + +/** + * This structure can only be grown. You cannot make it smaller... + */ +struct MityDSPL138Config { + u32 ConfigMagicWord; /** == CONFIG_MAGIC_WORD */ + u32 ConfigVersion; /** version of the configuration block */ + u32 ConfigSizeBytes; /** configuration size, in bytes */ + struct tag_peripherals Peripherals; +}; + +struct MityDSPL138ConfigBlock { + union { + struct MityDSPL138Config config; + u8 space[CONFIG_MITYDSP_ENV_SIZE-sizeof(int)]; + } Data; + unsigned int CheckSum; /** summed bytes of ConfigSizeBytes */ +}; + +extern struct MityDSPL138Config config_block; +extern struct I2CFactoryConfig factory_config_block; +extern int get_config_block(void); +extern int get_factory_config_block(void); + +#endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 1b31a9a..1989316 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -41,6 +41,7 @@ extern void __iomem *da8xx_syscfg1_base; #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) #define DA8XX_JTAG_ID_REG 0x18 +#define DA8XX_MSTPRI2_REG 0x118 #define DA8XX_CFGCHIP0_REG 0x17c #define DA8XX_CFGCHIP2_REG 0x184 #define DA8XX_CFGCHIP3_REG 0x188 diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 15a6192..db6f1cd 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -88,6 +88,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* DA8xx boards */ DEBUG_LL_DA8XX(davinci_da830_evm, 2); DEBUG_LL_DA8XX(davinci_da850_evm, 2); + DEBUG_LL_DA8XX(mityomapl138, 1); /* TNETV107x boards */ DEBUG_LL_TNETV107X(tnetv107x, 1); From c.aeschlimann at acn-group.ch Mon Jul 19 09:20:08 2010 From: c.aeschlimann at acn-group.ch (Christophe Aeschlimann) Date: Mon, 19 Jul 2010 16:20:08 +0200 Subject: [PATCH v2] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: <4C44515A.4030003@criticallink.com> References: <4C44515A.4030003@criticallink.com> Message-ID: <4C445F18.60506@acn-group.ch> Hi, Nice to see a new board based on the OMAP-L138. A small comment below. On 19.07.2010 15:21, Michael Williamson wrote: [...] > +static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { > + .bus_freq = 100, /* kHz */ > + .bus_delay = 0, /* usec */ > +}; > + > +/* TPS65070 voltage regulator support */ The comment doesn't match what your supporting. > + > +/* 1.2V Core */ > +struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { > + { > + .supply = "cvdd", > + }, > +}; > + > +/* 1.8V */ > +struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { > + { > + .supply = "usb0_vdda18", > + }, > + { > + .supply = "usb1_vdda18", > + }, > + { > + .supply = "ddr_dvdd18", > + }, > + { > + .supply = "sata_vddr", > + }, > +}; > + [...] Regards, -- Christophe Aeschlimann Embedded Software Engineer Advanced Communications Networks S.A. Rue du Puits-Godet 8a 2000 Neuch?tel, Switzerland T?l. +41 32 724 74 31 c.aeschlimann at acn-group.ch From c.aeschlimann at acn-group.ch Mon Jul 19 09:22:43 2010 From: c.aeschlimann at acn-group.ch (Christophe Aeschlimann) Date: Mon, 19 Jul 2010 16:22:43 +0200 Subject: [PATCH v2] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: <4C44515A.4030003@criticallink.com> References: <4C44515A.4030003@criticallink.com> Message-ID: <4C445FB3.5050901@acn-group.ch> Hi, Nice to see a new board based on the OMAP-L138. A small comment below. On 19.07.2010 15:21, Michael Williamson wrote: [...] > +static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { > + .bus_freq = 100, /* kHz */ > + .bus_delay = 0, /* usec */ > +}; > + > +/* TPS65070 voltage regulator support */ The comment doesn't match what _you are_ supporting. > + > +/* 1.2V Core */ > +struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { > + { > + .supply = "cvdd", > + }, > +}; > + > +/* 1.8V */ > +struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { > + { > + .supply = "usb0_vdda18", > + }, > + { > + .supply = "usb1_vdda18", > + }, > + { > + .supply = "ddr_dvdd18", > + }, > + { > + .supply = "sata_vddr", > + }, > +}; > + [...] Regards, -- Christophe Aeschlimann Embedded Software Engineer Advanced Communications Networks S.A. Rue du Puits-Godet 8a 2000 Neuch?tel, Switzerland T?l. +41 32 724 74 31 c.aeschlimann at acn-group.ch From michael.williamson at criticallink.com Mon Jul 19 11:26:12 2010 From: michael.williamson at criticallink.com (Michael Williamson) Date: Mon, 19 Jul 2010 12:26:12 -0400 Subject: [PATCH v2] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: <1279555114.5434.27.camel@Joe-Laptop.home> References: <4C4454AF.4000801@criticallink.com> <1279555114.5434.27.camel@Joe-Laptop.home> Message-ID: <4C447CA4.2000705@criticallink.com> On 7/19/2010 11:58 AM, Joe Perches wrote: > On Mon, 2010-07-19 at 09:35 -0400, Michael Williamson wrote: >> + pr_warning("%s: mmcsd0 mux setup failed:" " %d\n", __func__,ret); > Isn't this easier to read as a single string? > > pr_warning("%s: mmcsd0 mux setup failed: %d\n", __func__, ret); > > Also, if you want __func__ to prefix every printk you could use: > > #define pr_fmt(fmt) "%s: " fmt, __func__ > > and use: > > pr_warning("mmcsd0 mux setup failed: %d\n", ret); > Didn't know about the pr_fmt macro. Thanks. I'll update / fix the double strings. >> + ret = da8xx_register_mmcsd0(&da850_mmc_config); >> + if (ret) >> + pr_warning("%s: mmcsd0 registration failed:", __func__, " %d\n", ret); > Compile tested? Perhaps you mean: > > pr_warning("%s: mmcsd0 registration failed: %d\n", __func__, ret); > > [] > I did recompile and re-test, but missed the compiler warnings when I built the changes. They were there. I will correct. >> + pr_info("EMAC = %02X:%02X:%02X:%02X:%02X:%02X\n", >> + peripheral_config.ENETConfig.MACAddr[0], >> + peripheral_config.ENETConfig.MACAddr[1], >> + peripheral_config.ENETConfig.MACAddr[2], >> + peripheral_config.ENETConfig.MACAddr[3], >> + peripheral_config.ENETConfig.MACAddr[4], >> + peripheral_config.ENETConfig.MACAddr[5]); > There's are extensions to printk/vsnprintf that is used for > various things like MAC and IP addresses. (see: lib/vsprintf.c) > > This should be: > > pr_info("EMAC = %pM\n", peripheral_config.ENETConfig.MACAddr); > > > OK. Much easier to read. Appreciate the help. I'll go round again and try to be a bit more careful prior to resubmitting. -Mike From linux at arm.linux.org.uk Mon Jul 19 14:36:04 2010 From: linux at arm.linux.org.uk (Russell King - ARM Linux) Date: Mon, 19 Jul 2010 20:36:04 +0100 Subject: [PATCH v2] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: <4C44515A.4030003@criticallink.com> References: <4C44515A.4030003@criticallink.com> Message-ID: <20100719193604.GA22547@n2100.arm.linux.org.uk> On Mon, Jul 19, 2010 at 09:21:30AM -0400, Michael Williamson wrote: > arch/arm/configs/mityomapl138_defconfig | 1764 ++++++++++++++++++++ Please don't include full defconfigs; we've recently reduced the size of those merged because they're getting OTT. Please combine your defconfig with another existing defconfig where possible. If not, Uwe has a script which can be run to reduce the size of the defconfig. However, I'd personally prefer to see a reduction in the number of defconfigs we have now. From michael.williamson at criticallink.com Mon Jul 19 15:24:41 2010 From: michael.williamson at criticallink.com (Michael Williamson) Date: Mon, 19 Jul 2010 16:24:41 -0400 Subject: [PATCH v2] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: <20100719193604.GA22547@n2100.arm.linux.org.uk> References: <4C44515A.4030003@criticallink.com> <20100719193604.GA22547@n2100.arm.linux.org.uk> Message-ID: <4C44B489.8080609@criticallink.com> On 7/19/2010 3:36 PM, Russell King - ARM Linux wrote: > On Mon, Jul 19, 2010 at 09:21:30AM -0400, Michael Williamson wrote: >> arch/arm/configs/mityomapl138_defconfig | 1764 ++++++++++++++++++++ > > Please don't include full defconfigs; we've recently reduced the size of > those merged because they're getting OTT. Please combine your defconfig > with another existing defconfig where possible. > > If not, Uwe has a script which can be run to reduce the size of the > defconfig. However, I'd personally prefer to see a reduction in the > number of defconfigs we have now. OK. I think I can roll this in with the da8xx_omapl_defconfig and scrap the one submitted. Thanks for the feedback. -Mike From broonie at opensource.wolfsonmicro.com Tue Jul 20 03:57:40 2010 From: broonie at opensource.wolfsonmicro.com (Mark Brown) Date: Tue, 20 Jul 2010 09:57:40 +0100 Subject: [PATCH v2] asoc: davinci: let platform data define edma queue numbers In-Reply-To: <1279522876-11834-1-git-send-email-nsekhar@ti.com> References: <1279522876-11834-1-git-send-email-nsekhar@ti.com> Message-ID: <20100720085739.GI10222@rakim.wolfsonmicro.main> On Mon, Jul 19, 2010 at 12:31:16PM +0530, Sekhar Nori wrote: > Currently the EDMA queue to be used by for servicing ASP through > internal RAM is fixed to EDMAQ_0 and that to service internal RAM > from external RAM is fixed to EDMAQ_1. Applied, thanks. It's "ASoC", BTW. From yuvraj.pasi at nextbitcpu.com Tue Jul 20 05:00:41 2010 From: yuvraj.pasi at nextbitcpu.com (Yuvraj Pasi) Date: Tue, 20 Jul 2010 15:30:41 +0530 Subject: kernel crash while running h264 codec on DM6446 based board In-Reply-To: References: <201003240922.29905.caglarakyuz@gmail.com> Message-ID: Hi everyone, I asked about this crash problem some time back & as suggested by you guys that it was due to a segfault by the application. Now my problem is that every time it segfaults of creates any other error it is absorbed by the signal handlers of the dsplink & exits . The signal handlers which i have written on the application side for some specific segfaults for clean up purpose never gets executed. Can anybody suggest a solution or a workaround for this problem!!! 2010/3/24 Kamoolkar, Mugdha > The dump does indicate that the thread is dying (hence the call to > NOTIFY_KnlFinalize). I suspect that this is happening because your > application is somehow generating a seg fault or something that's getting > caught by the DSPLink default signal handler, then resulting in calling the > function that does the cleanup. When cleanup happens, this crash dump is > expected, and you'll see that you can continue and restart your application. > > Can you put prints inside DSPLINK_atExitHandler and DSPLINK_sigHandler > functions (dsplink/gpp/src/api/Linux/drv_api.c), rebuild DSPLink user-side > and see if this print comes up? If yes, then this is probably what's > happening, and you need to find out which signal is getting caught, and > what's the cause of that signal (may be completely DSPLink-unrelated, since > we have stress tests that run for several hours and we have never seen this > issue in a normal run). > > Regards, > Mugdha > > > -----Original Message----- > From: ?a?lar AKY?Z [mailto:caglarakyuz at gmail.com] > Sent: Wednesday, March 24, 2010 12:52 PM > To: davinci-linux-open-source at linux.davincidsp.com > Cc: Yuvraj Pasi; Kamoolkar, Mugdha > Subject: Re: kernel crash while running h264 codec on DM6446 based board > > On Wednesday 24 March 2010 06:36:58 am Yuvraj Pasi wrote: > > Hi, > > Hi, > > > Thanks for the reply. No I'm not calling kill inside the application & > the > > kernel does not hang after the crash. I'm able to restart > > the application again after the crash. & every time it runs smoothly for > > some period before it crashes. > > > > thanks & regards > > yuvraj pasi > > > > [...] > > > > [] (SYNC_WaitSEM+0x0/0x260 [dsplinkk]) from [] > > By looking at oops dump I remembered a smilar problem related to sync in > Dsplink. I don't remember my exact oops dump but maybe your problem is > somehow related to it. Have you checked the thread at [1] ? > > Secondly, this maybe a memory leak issue. Have you checked your free memory > before and after running your application? > > Regards, > Caglar > > [1] > http://www.mail-archive.com/davinci-linux-open-source at linux.davincidsp.com/msg11540.html > > > (UEVENT_AddBufByPid+0x150/0x17c [dsplinkk]) > > > [] (UEVENT_AddBufByPid+0x0/0x17c [dsplinkk]) from > [] > > > (NOTIFY_KnlFinalize+0x14c/0x16c [dsplinkk]) > > > [] (NOTIFY_KnlFinalize+0x0/0x16c [dsplinkk]) from > [] > > > (DRV_CallAPI+0x778/0x8f0 [dsplinkk]) > > > r6:00008000 r5:00008000 r4:c14edf00 > > > [] (DRV_CallAPI+0x0/0x8f0 [dsplinkk]) from [] > > > (DRV_Ioctl+0x90/0x110 [dsplinkk]) > > > r7:00007302 r6:00000000 r5:4391c0b0 r4:00000000 > > > [] (DRV_Ioctl+0x0/0x110 [dsplinkk]) from [] > > > (do_ioctl+0x74/0x84) > > > r7:0000000b r6:4391c0b0 r5:ffffffe7 r4:c6fed160 > > > [] (do_ioctl+0x0/0x84) from [] > > > (vfs_ioctl+0x28c/0x2ac) r6:00000000 r5:4391c0b0 r4:c6fed160 > > > [] (vfs_ioctl+0x0/0x2ac) from [] > > > (sys_ioctl+0x44/0x68) r7:c6fed160 r6:00007302 r5:4391c0b0 r4:fffffff7 > > > [] (sys_ioctl+0x0/0x68) from [] > > > (ret_fast_syscall+0x0/0x2c) > > > > > > According to the FAQ it is a problem with syncronisation between > threads. > > > How can I find out which thread calls are causing this problem because > my > > > application uses different threads > > > for video encode & decoding , audio encoding & decoding. > > > The backtrace given above is of no help!!! > > > > > > > > > On Mon, Mar 22, 2010 at 11:25 PM, Uppal, Deepali > wrote: > > > > > > Hello, > > > > > > > > > > > > Please check here: > > > > > > > > > > > > > > > > http://wiki.davincidsp.com/index.php/DSPLink_FAQs#Why_does_the_MSGQ_get_A > > >PI_call_in_my_application_crash.3F > > > > > > > > > > > > Does this FAQ apply to your scenario? > > > > > > > > > > > > Thanks and Regards, > > > Deepali Uppal > > > DSP/BIOS Link > > > ------------------------------ > > > > > > *From:* davinci-linux-open-source-bounces+deepali=ti.com@ > > > linux.davincidsp.com > > > [mailto:davinci-linux-open-source-bounces+deepali > > >ce-bounces%2Bdeepali> =ti.com at linux.davincidsp.com] *On Behalf Of > *Yuvraj > > > Pasi > > > *Sent:* Friday, March 19, 2010 2:35 PM > > > *To:* davinci-linux-open-source at linux.davincidsp.com > > > *Subject:* kernel crash while running h264 codec on DM6446 based board > > > > > > > > > > > > Hi all, > > > we are using our own custom made board with DM6446. I have written a > > > camera capture application which > > > captures images encodes it in H264, decodes it & then display it on fb. > > > It runs smoothly for some time & then crashes . > > > > > > How do I debug this crash dump so that i can find the source of the > > > problem. > > > > > > ortp-m, *pte=00000000essage-get_pictu, *ppte=00000000re_buffer_size 1 > > > 07 > > > ortp-messageInternal error: Oops: 7 [#1] > > > Modules linked in: dsplinkk cmemk > > > CPU: 0 Not tainted (2.6.23-davinci1 #219) > > > PC is at SYNC_WaitSEM+0x1d0/0x260 [dsplinkk] > > > LR is at __atomic_notifier_call_chain+0x1c/0x24 > > > pc : [] lr : [] psr: 50000013 > > > sp : c1975dd0 ip : 00000000 fp : c1975e44 > > > r10: c0038e14 r9 : 00008000 r8 : c7930008 > > > r7 : c1974000 r6 : c1975de8 r5 : c7930000 r4 : c1975de0 > > > r3 : 00000001 r2 : c04bb900 r1 : 00000002 r0 : c04bb900 > > > Flags: nZcV IRQs on FIQs on Mode SVC_32 ISA ARM Segment user > > > Control: 0005317f Table: 81794000 DAC: 00000015 > > > Process linphonec (pid: 1118, stack limit = 0xc1974260) > > > Stack: (0xc1975dd0 to 0xc1976000) > > > 5dc0: 00000000 c04bb900 c0038e14 > > > 00000000 > > > 5de0: 00000000 00000000 00000001 c04bb900 c0038e14 c7930008 c7930008 > > > c0038edc > > > 5e00: 60000013 ffffffff 00000000 bf02211c 00000000 c7932008 c1975e44 > > > 00008000 > > > 5e20: c15174c0 bf02211c c67526e0 bf02210c 00000000 00000000 c1975e7c > > > c1975e48 > > > 5e40: bf00c4d4 bf00d4c0 bf00b8d8 ffffffff c1975e8c c1975e8c 00000000 > > > 00008000 > > > 5e60: 00007302 c002861c c1974000 00900036 c1975eac c1975e80 bf00c714 > > > bf00c394 > > > 5e80: 00000000 00000000 c1975f0c 00000000 c0027ab4 c1975f00 00008000 > > > 00008000 > > > 5ea0: c1975efc c1975eb0 bf008930 bf00c5d8 40020000 c6687288 00000000 > > > 40020000 > > > 5ec0: 4002b000 40020000 c748d23c c1975f1c c1975f0c c1975ee0 c006e18c > > > 43f60170 > > > 5ee0: 00000000 43f60170 00000000 00007302 c1975f34 c1975f00 bf008138 > > > bf0081c8 > > > 5f00: 00008000 00000000 40020480 00008200 001eff10 00008000 c75758a0 > > > ffffffe7 > > > 5f20: 43f60170 00000011 c1975f54 c1975f38 c008b490 bf0080b8 c1975f84 > > > c75758a0 > > > 5f40: 43f60170 00000000 c1975f7c c1975f58 c008b72c c008b42c 00008680 > > > c6752714 > > > 5f60: fffffff7 43f60170 00007302 c75758a0 c1975fa4 c1975f80 c008b790 > > > c008b4b0 > > > 5f80: c0073d9c 00000001 001f02b0 43f61000 00215d70 00000036 00000000 > > > c1975fa8 > > > 5fa0: c0027e20 c008b75c 001f02b0 43f61000 00000011 00007302 43f60170 > > > 00213e60 > > > 5fc0: 001f02b0 43f61000 00215d70 00000108 00215d34 000005a0 00000000 > > > 43f6016c > > > 5fe0: 001d6024 43f60110 000221e4 401d2294 80000010 00000011 020030fe > > > e2200000 > > > Backtrace: > > > [] (SYNC_WaitSEM+0x0/0x260 [dsplinkk]) from [] > > > (UEVENT_AddBufByPid+0x150/0x17c [dsplinkk]) > > > [] (UEVENT_AddBufByPid+0x0/0x17c [dsplinkk]) from > [] > > > (NOTIFY_KnlFinalize+0x14c/0x16c [dsplinkk]) > > > [] (NOTIFY_KnlFinalize+0x0/0x16c [dsplinkk]) from > [] > > > (DRV_CallAPI+0x778/0x8f0 [dsplinkk]) > > > r6:00008000 r5:00008000 r4:c1975f00 > > > [] (DRV_CallAPI+0x0/0x8f0 [dsplinkk]) from [] > > > (DRV_Ioctl+0x90/0x110 [dsplinkk]) > > > r7:00007302 r6:00000000 r5:43f60170 r4:00000000 > > > [] (DRV_Ioctl+0x0/0x110 [dsplinkk]) from [] > > > (do_ioctl+0x74/0x84) > > > r7:00000011 r6:43f60170 r5:ffffffe7 r4:c75758a0 > > > [] (do_ioctl+0x0/0x84) from [] > > > (vfs_ioctl+0x28c/0x2ac) r6:00000000 r5:43f60170 r4:c75758a0 > > > [] (vfs_ioctl+0x0/0x2ac) from [] > > > (sys_ioctl+0x44/0x68) r7:c75758a0 r6:00007302 r5:43f60170 r4:fffffff7 > > > [] (sys_ioctl+0x0/0x68) from [] > > > (ret_fast_syscall+0x0/0x2c) > > > r7:00000036 r6:00215d70 r5:43f61000 r4:001f02b0 > > > Code: eb410c34 e597200c e3a03001 e5823000 (e5953010) > > > > > > > > > -- > > > Thanks & regards > > > yuvraj pasi > > > > > > > > > > > > > > > -- > > > Thanks & regards > > > yuvraj pasi > > > -- Thanks & regards yuvraj pasi -------------- next part -------------- An HTML attachment was scrubbed... URL: From nsekhar at ti.com Tue Jul 20 06:16:48 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Tue, 20 Jul 2010 16:46:48 +0530 Subject: [PATCH 1/4] davinci: cpufreq: bailout on regulator errors Message-ID: <1279624611-8255-1-git-send-email-nsekhar@ti.com> Current cpufreq code does not consider errors that can occur while changing voltage. Code to increase CPU frequency goes ahead even in the case the regulator has failed to increase the voltage. This leads to hard error since lower voltages cannot support increased frequency. Prevent this by not increasing frequency in case increasing voltage is not successful. Also, do not lower the voltage if changing the cpu frequency has failed for some reason. Note that we do not return error on failure to decrease voltage as that is not a hard error. Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/cpufreq.c | 10 ++++++++-- 1 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c index d3fa6de..bc80142 100644 --- a/arch/arm/mach-davinci/cpufreq.c +++ b/arch/arm/mach-davinci/cpufreq.c @@ -104,15 +104,21 @@ static int davinci_target(struct cpufreq_policy *policy, cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); /* if moving to higher frequency, up the voltage beforehand */ - if (pdata->set_voltage && freqs.new > freqs.old) - pdata->set_voltage(idx); + if (pdata->set_voltage && freqs.new > freqs.old) { + ret = pdata->set_voltage(idx); + if (ret) + goto out; + } ret = clk_set_rate(armclk, idx); + if (ret) + goto out; /* if moving to lower freq, lower the voltage after lowering freq */ if (pdata->set_voltage && freqs.new < freqs.old) pdata->set_voltage(idx); +out: cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); return ret; -- 1.6.2.4 From nsekhar at ti.com Tue Jul 20 06:16:49 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Tue, 20 Jul 2010 16:46:49 +0530 Subject: [PATCH 2/4] davinci: clock: add support for setting sysclk rate In-Reply-To: <1279624611-8255-1-git-send-email-nsekhar@ti.com> References: <1279624611-8255-1-git-send-email-nsekhar@ti.com> Message-ID: <1279624611-8255-2-git-send-email-nsekhar@ti.com> Setting sysclk rate will be useful in cases where the sysclk is not at a fixed ratio to the PLL output but can asynchronously be changed. This support forms the basis of attempt to keep the AEMIF clock constant on OMAP-L138 even as PLL0 output changes as ARM clock is changed to save power. This patch has been tested on OMAP-L138. Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/clock.c | 73 +++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-davinci/clock.h | 5 +++ 2 files changed, 78 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 054c303..d9bd644 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -287,6 +287,79 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) return rate; } +int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) +{ + unsigned v; + struct pll_data *pll; + unsigned long input; + unsigned ratio = 0; + + /* If this is the PLL base clock, wrong function to call */ + if (clk->pll_data) + return -EINVAL; + + /* There must be a parent... */ + if (WARN_ON(!clk->parent)) + return -EINVAL; + + /* ... the parent must be a PLL... */ + if (WARN_ON(!clk->parent->pll_data)) + return -EINVAL; + + /* ... and this clock must have a divider. */ + if (WARN_ON(!clk->div_reg)) + return -EINVAL; + + pll = clk->parent->pll_data; + + input = clk->parent->rate; + + /* If pre-PLL, source clock is before the multiplier and divider(s) */ + if (clk->flags & PRE_PLL) + input = pll->input_rate; + + if (input > rate) { + /* + * Can afford to provide an output little higher than requested + * only if maximum rate supported by hardware on this sysclk + * is known. + */ + if (clk->maxrate) { + ratio = DIV_ROUND_CLOSEST(input, rate); + if (input / ratio > clk->maxrate) + ratio = 0; + } + + if (ratio == 0) + ratio = DIV_ROUND_UP(input, rate); + + ratio = ratio - 1; + } + + if (ratio > PLLDIV_RATIO_MASK) + return -EINVAL; + + do { + v = __raw_readl(pll->base + PLLSTAT); + } while (v & PLLSTAT_GOSTAT); + + v = __raw_readl(pll->base + clk->div_reg); + v &= ~PLLDIV_RATIO_MASK; + v |= ratio | PLLDIV_EN; + __raw_writel(v, pll->base + clk->div_reg); + + v = __raw_readl(pll->base + PLLCMD); + v |= PLLCMD_GOSET; + __raw_writel(v, pll->base + PLLCMD); + + do { + v = __raw_readl(pll->base + PLLSTAT); + } while (v & PLLSTAT_GOSTAT); + + return 0; +} +EXPORT_SYMBOL(davinci_set_sysclk_rate); + static unsigned long clk_leafclk_recalc(struct clk *clk) { if (WARN_ON(!clk->parent)) diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 01e3648..1109998 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -70,6 +70,9 @@ #include #include +#define PLLSTAT_GOSTAT BIT(0) +#define PLLCMD_GOSET BIT(0) + struct pll_data { u32 phys_base; void __iomem *base; @@ -86,6 +89,7 @@ struct clk { struct module *owner; const char *name; unsigned long rate; + unsigned long maxrate; /* H/W supported max rate */ u8 usecount; u8 lpsc; u8 gpsc; @@ -118,6 +122,7 @@ struct clk { int davinci_clk_init(struct clk_lookup *clocks); int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, unsigned int mult, unsigned int postdiv); +int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); extern struct platform_device davinci_wdt_device; extern void davinci_watchdog_reset(struct platform_device *); -- 1.6.2.4 From nsekhar at ti.com Tue Jul 20 06:16:51 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Tue, 20 Jul 2010 16:46:51 +0530 Subject: [PATCH 4/4] davinci: am18x/da850/omap-l138: keep async clock constant with cpufreq In-Reply-To: <1279624611-8255-3-git-send-email-nsekhar@ti.com> References: <1279624611-8255-1-git-send-email-nsekhar@ti.com> <1279624611-8255-2-git-send-email-nsekhar@ti.com> <1279624611-8255-3-git-send-email-nsekhar@ti.com> Message-ID: <1279624611-8255-4-git-send-email-nsekhar@ti.com> Keep PLL0 SYSCLK3 at a constant rate of 100MHz. This enables the AEMIF timing to remain valid even as the PLL0 output is changed by cpufreq driver to save power. Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/board-da850-evm.c | 2 +- arch/arm/mach-davinci/da850.c | 10 +++++++++- arch/arm/mach-davinci/include/mach/da8xx.h | 2 +- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 2ec3095..2806971 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -729,7 +729,7 @@ static __init void da850_evm_init(void) if (ret) pr_warning("da850_evm_init: rtc setup failed: %d\n", ret); - ret = da850_register_cpufreq(); + ret = da850_register_cpufreq("pll0_sysclk3"); if (ret) pr_warning("da850_evm_init: cpufreq registration failed: %d\n", ret); diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 6b8331b..9f63b89 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -86,6 +86,8 @@ static struct clk pll0_sysclk3 = { .parent = &pll0_clk, .flags = CLK_PLL, .div_reg = PLLDIV3, + .set_rate = davinci_set_sysclk_rate, + .maxrate = 100000000, }; static struct clk pll0_sysclk4 = { @@ -954,10 +956,16 @@ static struct platform_device da850_cpufreq_device = { .dev = { .platform_data = &cpufreq_info, }, + .id = -1, }; -int __init da850_register_cpufreq(void) +int __init da850_register_cpufreq(char *async_clk) { + /* cpufreq driver can help keep an "async" clock constant */ + if (async_clk) + clk_add_alias("async", da850_cpufreq_device.name, + async_clk, NULL); + return platform_device_register(&da850_cpufreq_device); } diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 1b31a9a..bf6a044 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -77,7 +77,7 @@ int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); int da8xx_register_mmcsd0(struct davinci_mmc_config *config); void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata); int da8xx_register_rtc(void); -int da850_register_cpufreq(void); +int da850_register_cpufreq(char *async_clk); int da8xx_register_cpuidle(void); void __iomem * __init da8xx_get_mem_ctlr(void); int da850_register_pm(struct platform_device *pdev); -- 1.6.2.4 From nsekhar at ti.com Tue Jul 20 06:16:50 2010 From: nsekhar at ti.com (Sekhar Nori) Date: Tue, 20 Jul 2010 16:46:50 +0530 Subject: [PATCH 3/4] davinci: cpufreq: add support for keeping an additional clock constant In-Reply-To: <1279624611-8255-2-git-send-email-nsekhar@ti.com> References: <1279624611-8255-1-git-send-email-nsekhar@ti.com> <1279624611-8255-2-git-send-email-nsekhar@ti.com> Message-ID: <1279624611-8255-3-git-send-email-nsekhar@ti.com> On OMAP-L138 SoC, some of the sysclks need not be at a fixed ratio to CPU clock and can be kept at a relatively constant rate by adjusting the PLLDIVn ratio even as cpufreq goes ahead and changes the CPU clock. This feature can be used to keep the EMIFA (PLL0 SYSCLK3) clock at a constant rate so that the EMIF timings need not be re-programmed whenever the CPU frequency changes. This patch adds the required suppport to cpufreq driver. Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/cpufreq.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c index bc80142..343de73 100644 --- a/arch/arm/mach-davinci/cpufreq.c +++ b/arch/arm/mach-davinci/cpufreq.c @@ -34,6 +34,8 @@ struct davinci_cpufreq { struct device *dev; struct clk *armclk; + struct clk *asyncclk; + unsigned long asyncrate; }; static struct davinci_cpufreq cpufreq; @@ -114,6 +116,12 @@ static int davinci_target(struct cpufreq_policy *policy, if (ret) goto out; + if (cpufreq.asyncclk) { + ret = clk_set_rate(cpufreq.asyncclk, cpufreq.asyncrate); + if (ret) + goto out; + } + /* if moving to lower freq, lower the voltage after lowering freq */ if (pdata->set_voltage && freqs.new < freqs.old) pdata->set_voltage(idx); @@ -191,6 +199,7 @@ static struct cpufreq_driver davinci_driver = { static int __init davinci_cpufreq_probe(struct platform_device *pdev) { struct davinci_cpufreq_config *pdata = pdev->dev.platform_data; + struct clk *asyncclk; if (!pdata) return -EINVAL; @@ -205,6 +214,12 @@ static int __init davinci_cpufreq_probe(struct platform_device *pdev) return PTR_ERR(cpufreq.armclk); } + asyncclk = clk_get(cpufreq.dev, "async"); + if (!IS_ERR(asyncclk)) { + cpufreq.asyncclk = asyncclk; + cpufreq.asyncrate = clk_get_rate(asyncclk); + } + return cpufreq_register_driver(&davinci_driver); } @@ -212,6 +227,9 @@ static int __exit davinci_cpufreq_remove(struct platform_device *pdev) { clk_put(cpufreq.armclk); + if (cpufreq.asyncclk) + clk_put(cpufreq.asyncclk); + return cpufreq_unregister_driver(&davinci_driver); } -- 1.6.2.4 From sshtylyov at mvista.com Tue Jul 20 07:26:54 2010 From: sshtylyov at mvista.com (Sergei Shtylyov) Date: Tue, 20 Jul 2010 16:26:54 +0400 Subject: [PATCH 2/4] davinci: clock: add support for setting sysclk rate In-Reply-To: <1279624611-8255-2-git-send-email-nsekhar@ti.com> References: <1279624611-8255-1-git-send-email-nsekhar@ti.com> <1279624611-8255-2-git-send-email-nsekhar@ti.com> Message-ID: <4C45960E.9000005@mvista.com> Hello. Sekhar Nori wrote: > Setting sysclk rate will be useful in cases where the > sysclk is not at a fixed ratio to the PLL output but > can asynchronously be changed. > This support forms the basis of attempt to keep the AEMIF > clock constant on OMAP-L138 even as PLL0 output changes > as ARM clock is changed to save power. > This patch has been tested on OMAP-L138. > Signed-off-by: Sekhar Nori [...] > diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c > index 054c303..d9bd644 100644 > --- a/arch/arm/mach-davinci/clock.c > +++ b/arch/arm/mach-davinci/clock.c > @@ -287,6 +287,79 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) > return rate; > } > > +int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) > +{ [...] > + if (input > rate) { > + /* > + * Can afford to provide an output little higher than requested > + * only if maximum rate supported by hardware on this sysclk > + * is known. > + */ > + if (clk->maxrate) { > + ratio = DIV_ROUND_CLOSEST(input, rate); > + if (input / ratio > clk->maxrate) > + ratio = 0; > + } > + > + if (ratio == 0) > + ratio = DIV_ROUND_UP(input, rate); > + > + ratio = ratio - 1; Why not simply ratio--? It's C after all. :-) WBR, Sergei From joe at perches.com Fri Jul 16 18:49:27 2010 From: joe at perches.com (Joe Perches) Date: Fri, 16 Jul 2010 16:49:27 -0700 Subject: [PATCH] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: References: Message-ID: <1279324167.4526.85.camel@Joe-Laptop.home> On Fri, 2010-07-16 at 10:00 -0400, Michael Williamson wrote: > +static __init void mityomapl138_setup_lcd(void) > +{ [] > + pr_warning("mityomapl138_init: unknown LCD type : %s\n", > + peripheral_config.LCDConfig.PanelName); I think you'd be better off actually using the actual function name rather than the caller name pr_warning("%s: unknown LCD type: %s\n", __func__, peripheral_config.LCDConfig.PanelName); [] > + if (ret) { > + pr_warning("mityomapl138_init: lcd pinmux failed : " > + "%d\n", ret); pr_warning("%s: lcd pinmux failed : %d\n", __func__, ret); > + pr_warning("mityomapl138_init: no LCD device enabled\n"); etc. > +static __init void mityomapl138_init(void) > +{ > + int ret; > + > + pr_info("mityomapl138_init...\n"); > + > + ret = pmic_tps65023_init(); > + if (ret) > + pr_warning("mityomapl138_init: TPS65023 PMIC init failed: %d\n", > + ret); pr_warning("%s: TPS65023 PMIC init failed: %d\n", __func__, ret); etc. > + > + ret = da8xx_register_edma(); > + if (ret) > + pr_warning("mityomapl138_init: edma registration failed: %d\n", > + ret); > + > + ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); > + if (ret) > + pr_warning("mityomapl138_init: i2c0 registration failed: %d\n", > + ret); > + > + ret = da8xx_register_watchdog(); > + if (ret) > + pr_warning("mityomapl138_init: watchdog registration failed: " > + "%d\n", ret); > + From segooon at gmail.com Sat Jul 17 10:19:07 2010 From: segooon at gmail.com (Kulikov Vasiliy) Date: Sat, 17 Jul 2010 19:19:07 +0400 Subject: [PATCH 1/5] arm: mach-davinci: check irq2ctlr() result Message-ID: <1279379947-15152-1-git-send-email-segooon@gmail.com> If irq2ctlr() fails return IRQ_NONE. Also as it can fail make 'ctlr' signed. The semantic patch that finds this problem (many false-positive results): (http://coccinelle.lip6.fr/) // @ r1 @ identifier f; @@ int f(...) { ... } @@ identifier r1.f; type T; unsigned T x; @@ *x = f(...) ... *x > 0 Signed-off-by: Kulikov Vasiliy --- arch/arm/mach-davinci/dma.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index d33827a..d1127e1 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -344,10 +344,12 @@ static int irq2ctlr(int irq) static irqreturn_t dma_irq_handler(int irq, void *data) { int i; - unsigned ctlr; + int ctlr; unsigned int cnt = 0; ctlr = irq2ctlr(irq); + if (ctlr < 0) + return IRQ_NONE; dev_dbg(data, "dma_irq_handler\n"); @@ -398,10 +400,12 @@ static irqreturn_t dma_irq_handler(int irq, void *data) static irqreturn_t dma_ccerr_handler(int irq, void *data) { int i; - unsigned ctlr; + int ctlr; unsigned int cnt = 0; ctlr = irq2ctlr(irq); + if (ctlr < 0) + return IRQ_NONE; dev_dbg(data, "dma_ccerr_handler\n"); -- 1.7.0.4 From joe at perches.com Mon Jul 19 10:58:34 2010 From: joe at perches.com (Joe Perches) Date: Mon, 19 Jul 2010 08:58:34 -0700 Subject: [PATCH v2] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: <4C4454AF.4000801@criticallink.com> References: <4C4454AF.4000801@criticallink.com> Message-ID: <1279555114.5434.27.camel@Joe-Laptop.home> On Mon, 2010-07-19 at 09:35 -0400, Michael Williamson wrote: > + pr_warning("%s: mmcsd0 mux setup failed:" " %d\n", __func__,ret); Isn't this easier to read as a single string? pr_warning("%s: mmcsd0 mux setup failed: %d\n", __func__, ret); Also, if you want __func__ to prefix every printk you could use: #define pr_fmt(fmt) "%s: " fmt, __func__ and use: pr_warning("mmcsd0 mux setup failed: %d\n", ret); > + ret = da8xx_register_mmcsd0(&da850_mmc_config); > + if (ret) > + pr_warning("%s: mmcsd0 registration failed:", __func__, " %d\n", ret); Compile tested? Perhaps you mean: pr_warning("%s: mmcsd0 registration failed: %d\n", __func__, ret); [] > + pr_info("EMAC = %02X:%02X:%02X:%02X:%02X:%02X\n", > + peripheral_config.ENETConfig.MACAddr[0], > + peripheral_config.ENETConfig.MACAddr[1], > + peripheral_config.ENETConfig.MACAddr[2], > + peripheral_config.ENETConfig.MACAddr[3], > + peripheral_config.ENETConfig.MACAddr[4], > + peripheral_config.ENETConfig.MACAddr[5]); There's are extensions to printk/vsnprintf that is used for various things like MAC and IP addresses. (see: lib/vsprintf.c) This should be: pr_info("EMAC = %pM\n", peripheral_config.ENETConfig.MACAddr); From michael.williamson at criticallink.com Tue Jul 20 09:10:38 2010 From: michael.williamson at criticallink.com (Michael Williamson) Date: Tue, 20 Jul 2010 10:10:38 -0400 Subject: [PATCH v3] davinci: Add MityDSP-L138/MityARM-1808 SOM support Message-ID: <4C45AE5E.7070905@criticallink.com> This patch adds support for the MityDSP-L138 and MityARM-1808 system on module (SOM) under the registered machine "mityomapl138". These SOMs are based on the da850 davinci CPU architecture. Information on these SOMs may be found at http://www.mitydsp.com. Signed-off-by: Michael Williamson --- Changes since v2 patch was submitted: - Fixed compiler warnings inserted by pr_* statement cleanup attempt in v2. Also simplify pr_* statements per advice provided. - Updated comment block to indicate proper regulator device support. - removed mityomapl138_defconfig file - updated da8xx_omapl_defconfig file to support mityomapl138 machine. * Needed to add JFFS2, MTD, and NAND support as default boot configuration uses NAND mounted root filesystem. * Added TPS65023 regulator support. * process of rerunning make menuconfig altered defconfig a bunch due to migration from 2.32 kernel to 2.35 kernel. I don't believe I altered any other required features, but it might be wise if someone with a da850 or da830 could verify no issues. arch/arm/configs/da8xx_omapl_defconfig | 291 ++++++-- arch/arm/include/asm/setup.h | 5 + arch/arm/mach-davinci/Kconfig | 7 + arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/board-mityomapl138.c | 793 ++++++++++++++++++++ .../mach-davinci/include/mach/cb-mityomapl138.h | 125 +++ arch/arm/mach-davinci/include/mach/da8xx.h | 1 + arch/arm/mach-davinci/include/mach/uncompress.h | 1 + 8 files changed, 1181 insertions(+), 43 deletions(-) diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig index e14c99c..0dd0d00 100644 --- a/arch/arm/configs/da8xx_omapl_defconfig +++ b/arch/arm/configs/da8xx_omapl_defconfig @@ -1,13 +1,15 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc5 -# Thu Oct 22 12:19:19 2009 +# Linux kernel version: 2.6.35-rc3 +# Tue Jul 20 08:30:23 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_HAVE_LATENCYTOP_SUPPORT=y @@ -20,6 +22,7 @@ CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -32,8 +35,16 @@ CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -48,6 +59,7 @@ CONFIG_POSIX_MQUEUE_SYSCTL=y # CONFIG_TREE_RCU=y # CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set # CONFIG_RCU_TRACE is not set CONFIG_RCU_FANOUT=32 # CONFIG_RCU_FANOUT_EXACT is not set @@ -55,11 +67,6 @@ CONFIG_RCU_FANOUT=32 CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set # CONFIG_CGROUPS is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set @@ -69,6 +76,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -90,10 +98,14 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y @@ -131,14 +143,41 @@ CONFIG_LBDAF=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set -CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set # CONFIG_FREEZER is not set # @@ -149,8 +188,11 @@ CONFIG_MMU=y # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set # CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set @@ -159,7 +201,6 @@ CONFIG_MMU=y # CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -167,6 +208,7 @@ CONFIG_MMU=y # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_KIRKWOOD is not set # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set @@ -175,20 +217,27 @@ CONFIG_MMU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set CONFIG_ARCH_DAVINCI=y # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set +# CONFIG_PLAT_SPEAR is not set CONFIG_CP_INTC=y # @@ -205,18 +254,18 @@ CONFIG_ARCH_DAVINCI_DA830=y CONFIG_ARCH_DAVINCI_DA850=y CONFIG_ARCH_DAVINCI_DA8XX=y # CONFIG_ARCH_DAVINCI_DM365 is not set +# CONFIG_ARCH_DAVINCI_TNETV107X is not set # # DaVinci Board Type # CONFIG_MACH_DAVINCI_DA830_EVM=y -CONFIG_DA830_UI=y CONFIG_DA830_UI_LCD=y # CONFIG_DA830_UI_NAND is not set CONFIG_MACH_DAVINCI_DA850_EVM=y -CONFIG_DA850_UI_EXP=y CONFIG_DA850_UI_NONE=y # CONFIG_DA850_UI_RMII is not set +CONFIG_MACH_MITYOMAPL138=y CONFIG_DAVINCI_MUX=y # CONFIG_DAVINCI_MUX_DEBUG is not set # CONFIG_DAVINCI_MUX_WARNINGS is not set @@ -270,6 +319,7 @@ CONFIG_PREEMPT=y CONFIG_HZ=100 CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set # CONFIG_HIGHMEM is not set @@ -280,13 +330,11 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 +CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_LEDS=y @@ -354,7 +402,6 @@ CONFIG_NET=y # Networking options # CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set @@ -404,6 +451,7 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m CONFIG_INET6_XFRM_MODE_BEET=m # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_IPV6_TUNNEL is not set # CONFIG_IPV6_MULTIPLE_TABLES is not set @@ -440,6 +488,7 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set +# CONFIG_L2TP is not set # CONFIG_BRIDGE is not set # CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set @@ -465,10 +514,21 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set +# CONFIG_CAIF is not set # # Device Drivers @@ -486,12 +546,110 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_FTL=y +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_CFI_AMDSTD is not set +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_NAND_DAVINCI=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=m # CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 @@ -501,9 +659,12 @@ CONFIG_BLK_DEV_RAM_SIZE=32768 # CONFIG_ATA_OVER_ETH is not set # CONFIG_MG_DISK is not set CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set # CONFIG_C2PORT is not set # @@ -519,6 +680,7 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=m # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=m CONFIG_SCSI_DMA=y @@ -583,6 +745,7 @@ CONFIG_LXT_PHY=y # CONFIG_NATIONAL_PHY is not set # CONFIG_STE10XP is not set CONFIG_LSI_ET1011C_PHY=y +# CONFIG_MICREL_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y @@ -608,8 +771,7 @@ CONFIG_TI_DAVINCI_EMAC=y # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set +# CONFIG_HOSTAP is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -631,6 +793,7 @@ CONFIG_NET_POLL_CONTROLLER=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -652,6 +815,7 @@ CONFIG_KEYBOARD_ATKBD=m # CONFIG_QT2160 is not set # CONFIG_KEYBOARD_LKKBD is not set CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_TCA6416 is not set # CONFIG_KEYBOARD_MATRIX is not set # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_NEWTON is not set @@ -665,6 +829,8 @@ CONFIG_KEYBOARD_XTKBD=m CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_AD7879_I2C is not set # CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set # CONFIG_TOUCHSCREEN_EETI is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set @@ -680,6 +846,7 @@ CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set # CONFIG_TOUCHSCREEN_TSC2007 is not set # CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set # CONFIG_INPUT_MISC is not set # @@ -689,6 +856,7 @@ CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_GAMEPORT is not set # @@ -701,6 +869,7 @@ CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set # # Serial drivers @@ -716,6 +885,9 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=3 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y @@ -726,6 +898,7 @@ CONFIG_HW_RANDOM=m # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y @@ -743,7 +916,9 @@ CONFIG_I2C_DAVINCI=y # CONFIG_I2C_DESIGNWARE is not set # CONFIG_I2C_GPIO is not set # CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set # # External I2C/SMBus adapter drivers @@ -754,18 +929,10 @@ CONFIG_I2C_DAVINCI=y # # Other I2C/SMBus bus drivers # -# CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set # @@ -780,13 +947,17 @@ CONFIG_GPIOLIB=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: # +# CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set CONFIG_GPIO_PCA953X=y +# CONFIG_GPIO_PCA953X_IRQ is not set CONFIG_GPIO_PCF857X=y +# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: @@ -799,6 +970,10 @@ CONFIG_GPIO_PCF857X=y # # AC97 GPIO expanders: # + +# +# MODULbus GPIO expanders: +# # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set @@ -811,42 +986,50 @@ CONFIG_WATCHDOG=y # # CONFIG_SOFT_WATCHDOG is not set # CONFIG_DAVINCI_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # # CONFIG_SSB is not set - -# -# Multifunction device drivers -# +CONFIG_MFD_SUPPORT=y # CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set # CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set # CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TC35892 is not set # CONFIG_MFD_TMIO is not set # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set # CONFIG_MFD_PCF50633 is not set -# CONFIG_AB3100_CORE is not set +# CONFIG_ABX500_CORE is not set CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set # CONFIG_REGULATOR_FIXED_VOLTAGE is not set # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set # CONFIG_REGULATOR_BQ24022 is not set # CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set # CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set +CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS6507X=y # CONFIG_MEDIA_SUPPORT is not set @@ -950,10 +1133,6 @@ CONFIG_RTC_LIB=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set # @@ -1033,6 +1212,22 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -1062,6 +1257,7 @@ CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m # CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set @@ -1184,6 +1380,7 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set # CONFIG_SYSCTL_SYSCALL_CHECK is not set @@ -1205,6 +1402,7 @@ CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_WORKQUEUE_TRACER is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1213,6 +1411,7 @@ CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set # # Security options @@ -1220,7 +1419,11 @@ CONFIG_DEBUG_ERRORS=y # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # @@ -1323,9 +1526,11 @@ CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y CONFIG_DECOMPRESS_GZIP=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index f392fb4..d6b1a47 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -143,6 +143,11 @@ struct tag_memclk { __u32 fmemclk; }; +/** MityDSP-L138 peripheral configuration info, + * see arch/arm/mach-davinci/include/mach/cb-mityomapl138.h + */ +#define ATAG_PERIPHERALS 0x42000101 + struct tag { struct tag_header hdr; union { diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 71f90f8..064b0e2 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -178,6 +178,13 @@ config DA850_UI_RMII endchoice +config MACH_MITYOMAPL138 + bool "Critical Link MityOMAPL138 SoM" + depends on ARCH_DAVINCI_DA850 + select GPIO_PCA953X + help + Say Y here to select the Critical Link MityOMAP-L138 System on Module. + config MACH_TNETV107X bool "TI TNETV107X Reference Platform" default ARCH_DAVINCI_TNETV107X diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index eab4c0f..dfc0fc4 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o +obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o # Power Management diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c new file mode 100644 index 0000000..c8541f1 --- /dev/null +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -0,0 +1,793 @@ +/* + * Critical Link MityOMAP-L138 SoM + * + * Copyright (C) 2010 Critical Link Incorporated - http://www.criticallink.com + * + * Derived from board-da850-evm.c + * Original Copyrights follow: + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from: arch/arm/mach-davinci/board-da830-evm.c + * Original Copyrights follow: + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct tag_peripherals peripheral_config = { + .Version = PERIPHERALS_VERSION, + .Manufacturer = "Critical Link", + .ENETConfig.EnetConfig = ENET_CONFIG_MII, + .ENETConfig.MACAddr = { 0x00, 0x50, 0xC2, 0x49, 0xDF, 0xFF }, + .UARTConfig[0] = { + .Enable = 0, + .IsConsole = 0, + .Baud = 115200, + }, + .UARTConfig[1] = { + .Enable = 1, + .IsConsole = 1, + .Baud = 115200, + }, + .UARTConfig[2] = { + .Enable = 0, + .IsConsole = 0, + .Baud = 115200, + }, + .SPIConfig[0] = { + .Enable = 0, + .CLKOut = 0, + .CSEnable = { 0, 0, 0, 0, 0, 0, 0, 0}, + .ENAEnable = 0, + .CLKRate = 0, + }, + .SPIConfig[1] = { + .Enable = 1, + .CLKOut = 1, + .CSEnable = { 1, 0, 0, 0, 0, 0, 0, 0}, + .ENAEnable = 0, + .CLKRate = 30000000, + }, + .LCDConfig = { + .Enable = 0, + .PanelName = "", + } +}; + + +#define MITYOMAPL138_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ + +#define MSTPRI2_LCD_MASK 0x70000000 +#define MSTPRI2_LCD_SHIFT 28 + +#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) +#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) + +/* MityDSP-L138 includes a 256 MByte large-page NAND flash + * (128K blocks). + */ +struct mtd_partition mityomapl138_nandflash_partition[] = { + { + .name = "rootfs", + .offset = 0, + .size = SZ_128M, + .mask_flags = 0, /* MTD_WRITEABLE, */ + }, + { + .name = "homefs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct davinci_nand_pdata mityomapl138_nandflash_data = { + .parts = mityomapl138_nandflash_partition, + .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16, + .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ +}; + +static struct resource mityomapl138_nandflash_resource[] = { + { + .start = DA8XX_AEMIF_CS3_BASE, + .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mityomapl138_nandflash_device = { + .name = "davinci_nand", + .id = 0, + .dev = { + .platform_data = &mityomapl138_nandflash_data, + }, + .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), + .resource = mityomapl138_nandflash_resource, +}; + +static struct platform_device *mityomapl138_devices[] __initdata = { + &mityomapl138_nandflash_device, +}; + +static __init void mityomapl138_setup_nand(void) +{ + + platform_add_devices(mityomapl138_devices, + ARRAY_SIZE(mityomapl138_devices)); +} + +static int mityomapl138_mmc_get_ro(int index) +{ + return gpio_get_value(DA850_MMCSD_WP_PIN); +} + +static int mityomapl138_mmc_get_cd(int index) +{ + return !gpio_get_value(DA850_MMCSD_CD_PIN); +} + +static struct davinci_mmc_config da850_mmc_config = { + .get_ro = mityomapl138_mmc_get_ro, + .get_cd = mityomapl138_mmc_get_cd, + .wires = 4, + .max_freq = 50000000, + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + .version = MMC_CTLR_VERSION_2, +}; + +static __init void mityomapl138_setup_mmc(void) +{ + int ret; + + ret = davinci_cfg_reg_list(da850_mmcsd0_pins); + if (ret) + pr_warning("mmcsd0 mux setup failed: %d\n" ,ret); + + ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n"); + if (ret) + pr_warning("can not open GPIO %d\n", DA850_MMCSD_CD_PIN); + gpio_direction_input(DA850_MMCSD_CD_PIN); + + ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n"); + if (ret) + pr_warning("can not open GPIO %d\n", DA850_MMCSD_WP_PIN); + gpio_direction_input(DA850_MMCSD_WP_PIN); + + ret = da8xx_register_mmcsd0(&da850_mmc_config); + if (ret) + pr_warning("mmcsd0 registration failed: %d\n", ret); +} + + +static struct davinci_uart_config mityomapl138_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static int __init mityomapl138_config_emac(void) +{ + void __iomem *cfg_chip3_base; + int ret; + u32 val; + struct davinci_soc_info *soc_info = &davinci_soc_info; + u8 rmii_en = 0; + + switch (peripheral_config.ENETConfig.EnetConfig) { + case ENET_CONFIG_RMII: + soc_info->emac_pdata->rmii_en = 1; + rmii_en = 1; + break; + case ENET_CONFIG_MII: + soc_info->emac_pdata->rmii_en = 0; + rmii_en = 0; + break; + case ENET_CONFIG_NONE: + default: + pr_info("No Ethernet PHY Selected, EMAC disabled\n"); + return 0; /* no enet... */ + break; + } + memcpy(&soc_info->emac_pdata->mac_addr[0], + &peripheral_config.ENETConfig.MACAddr[0], 6); + + cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); + + val = __raw_readl(cfg_chip3_base); + + if (rmii_en) { + val |= BIT(8); + ret = davinci_cfg_reg_list(da850_rmii_pins); + pr_info("RMII PHY configured, MII PHY will not be functional\n"); + } else { + val &= ~BIT(8); + ret = davinci_cfg_reg_list(da850_cpgmac_pins); + pr_info("MII PHY configured, RMII PHY will not be functional\n"); + } + + if (ret) + pr_warning("cpgmac/rmii mux setup failed: %d\n", ret); + + /* configure the CFGCHIP3 register for RMII or MII */ + __raw_writel(val, cfg_chip3_base); + + soc_info->emac_pdata->phy_mask = peripheral_config.ENETConfig.PHYMask ? + peripheral_config.ENETConfig.PHYMask : 1; + pr_info("setting phy_mask to %x\n", soc_info->emac_pdata->phy_mask); + soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY; + + ret = da8xx_register_emac(); + if (ret) + pr_warning("emac registration failed: %d\n", ret); + + return 0; +} +device_initcall(mityomapl138_config_emac); + +static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { + .bus_freq = 100, /* kHz */ + .bus_delay = 0, /* usec */ +}; + +/* TPS65023 voltage regulator support */ + +/* 1.2V Core */ +struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { + { + .supply = "cvdd", + }, +}; + +/* 1.8V */ +struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { + { + .supply = "usb0_vdda18", + }, + { + .supply = "usb1_vdda18", + }, + { + .supply = "ddr_dvdd18", + }, + { + .supply = "sata_vddr", + }, +}; + +/* 1.2V */ +struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { + { + .supply = "sata_vdd", + }, + { + .supply = "usb_cvdd", + }, + { + .supply = "pll0_vdda", + }, + { + .supply = "pll1_vdda", + }, +}; + +/* 1.8V Aux LDO */ +struct regulator_consumer_supply tps65023_ldo1_consumers[] = { + { + .supply = "1.8v_aux", + }, +}; + +/* VCC Aux (1.8 or 3.3) LDO */ +struct regulator_consumer_supply tps65023_ldo2_consumers[] = { + { + .supply = "vccaux", + }, +}; + + +struct regulator_init_data tps65023_regulator_data[] = { + /* dcdc1 */ + { + .constraints = { + .min_uV = 1150000, + .max_uV = 1350000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers), + .consumer_supplies = tps65023_dcdc1_consumers, + }, + + /* dcdc2 */ + { + .constraints = { + .min_uV = 1710000, + .max_uV = 1910000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers), + .consumer_supplies = tps65023_dcdc2_consumers, + }, + + /* dcdc3 */ + { + .constraints = { + .min_uV = 1120000, + .max_uV = 1320000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers), + .consumer_supplies = tps65023_dcdc3_consumers, + }, + + /* ldo1 */ + { + .constraints = { + .min_uV = 1710000, + .max_uV = 1890000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers), + .consumer_supplies = tps65023_ldo1_consumers, + }, + + /* ldo2 */ + { + .constraints = { + .min_uV = 3140000, + .max_uV = 3420000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers), + .consumer_supplies = tps65023_ldo2_consumers, + }, +}; + + +static struct i2c_board_info __initdata mityomap_tps65023_info[] = { + { + I2C_BOARD_INFO("tps65023", 0x48), + .platform_data = &tps65023_regulator_data[0], + }, + { + I2C_BOARD_INFO("24c02", 0x50), + }, +}; + +static int __init pmic_tps65023_init(void) +{ + return i2c_register_board_info(1, mityomap_tps65023_info, + ARRAY_SIZE(mityomap_tps65023_info)); +} + +static struct davinci_spi_platform_data mityomap_spi1_pdata = { + .version = SPI_VERSION_2, + .num_chipselect = 1, + .wdelay = 0, + .odd_parity = 0, + .parity_enable = 0, + .wait_enable = 0, + .timer_disable = 0, + .clk_internal = 1, + .cs_hold = 1, + .intr_level = 0, + .poll_mode = 1, + .use_dma = 0, + .c2tdelay = 8, + .t2cdelay = 8, +}; + +static struct resource mityomap_spi1_resources[] = { + [0] = { + .start = 0x01F0E000, + .end = 0x01F0EFFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DA8XX_SPINT1, + .start = IRQ_DA8XX_SPINT1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = EDMA_CTLR_CHAN(0, 18), + .end = EDMA_CTLR_CHAN(0, 18), + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = EDMA_CTLR_CHAN(0, 19), + .end = EDMA_CTLR_CHAN(0, 19), + .flags = IORESOURCE_DMA, + }, + [4] = { + .start = 1, + .end = 1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device mityomap_spi1_device = { + .name = "spi_davinci", + .id = 1, + .dev = { + .platform_data = &mityomap_spi1_pdata, + }, + .num_resources = ARRAY_SIZE(mityomap_spi1_resources), + .resource = mityomap_spi1_resources, +}; + +/***************************************************************************** + * SPI Devices: + * SPI1_CS0: 8M Flash ST-M25P64-VME6G + ****************************************************************************/ +static struct mtd_partition spi_flash_partitions[] = { + [0] = { + .name = "UBL", + .offset = 0, + .size = SZ_64K, + .mask_flags = MTD_WRITEABLE + }, + [1] = { + .name = "U-Boot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = 0, + }, + [2] = { + .name = "Spare", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct flash_platform_data mityomap_spi_flash_data = { + .name = "m25p80", + .parts = spi_flash_partitions, + .nr_parts = ARRAY_SIZE(spi_flash_partitions), + .type = "m25p64", +}; + +static struct spi_board_info mityomap_spi_flash_info[] = { + { + .modalias = "m25p80", + .platform_data = &mityomap_spi_flash_data, + .mode = SPI_MODE_0, + .max_speed_hz = 30000000, + .bus_num = 1, + .chip_select = 0, + }, +}; + +void __init mityomap_init_spi1(unsigned chipselect_mask, + struct spi_board_info *info, unsigned len) +{ + int ret; + ret = platform_device_register(&mityomap_spi1_device); + if (ret) + pr_warning("failed to register spi device : %d\n", ret); + + ret = spi_register_board_info(info, len); + if (ret) + pr_warning("failed to register board info : %d\n", ret); +} + +/* davinci da850 evm audio machine driver */ +static u8 da850_iis_serializer_direction[] = { + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static struct snd_platform_data mityomapl138_snd_data = { + .tx_dma_offset = 0x2000, + .rx_dma_offset = 0x2000, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), + .tdm_slots = 0, + .serial_dir = da850_iis_serializer_direction, + .eventq_no = EVENTQ_1, + .version = MCASP_VERSION_2, + .txnumevt = 0, + .rxnumevt = 0, +}; + +short mityomapl138_mcasp_pins[24] __initdata = { + DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, + DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, + DA850_AMUTE, + -1, -1, -1, -1, + -1, -1, -1, -1, + -1, -1, -1, -1, + -1, -1, -1, -1, + -1 +}; + +static __init int mityomapl138_setup_mcasp(void) +{ + int ret; + + mityomapl138_mcasp_pins[7+0] = DA850_AXR_13; + da850_iis_serializer_direction[12] = TX_MODE; + + ret = davinci_cfg_reg_list(mityomapl138_mcasp_pins); + if (ret) + pr_warning("mcasp mux setup failed: %d\n", ret); + + mityomapl138_snd_data.tdm_slots = 2; + mityomapl138_snd_data.txnumevt = 1; + + da8xx_register_mcasp(0, &mityomapl138_snd_data); + + return ret; +} + +static const struct display_panel disp_panel = { + QVGA, + 16, + 16, + COLOR_ACTIVE, +}; + +static struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 255, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 0, + .invert_frm_clock = 0, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + +static struct da8xx_lcdc_platform_data sharp_lq035q7dh06_pdata = { + .manu_name = "sharp", + .controller_data = &lcd_cfg, + .type = "Sharp_LQ035Q7DH06", +}; + +static struct da8xx_lcdc_platform_data chimei_p0430wqlb_pdata = { + .manu_name = "ChiMei", + .controller_data = &lcd_cfg, + .type = "ChiMei_P0430WQLB", +}; + +static struct da8xx_lcdc_platform_data vga_640x480_pdata = { + .manu_name = "VGA", + .controller_data = &lcd_cfg, + .type = "vga_640x480", +}; + +static struct resource da8xx_lcdc_resources[] = { + [0] = { /* registers */ + .start = DA8XX_LCD_CNTRL_BASE, + .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { /* interrupt */ + .start = IRQ_DA8XX_LCDINT, + .end = IRQ_DA8XX_LCDINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_lcdc_device = { + .name = "da8xx_lcdc", + .id = 0, + .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), + .resource = da8xx_lcdc_resources, + .dev = { + .platform_data = &sharp_lq035q7dh06_pdata, + } +}; + +static __init void mityomapl138_setup_lcd(void) +{ + int ret; + + if (peripheral_config.LCDConfig.Enable) { + u32 prio; + + /* set peripheral master priority up to 1 */ + prio = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_MSTPRI2_REG)); + prio &= ~MSTPRI2_LCD_MASK; + prio |= 1<u.cmdline.cmdline[0]; + memcpy(&peripheral_config, ptag, sizeof(peripheral_config)); + pr_info("Peripheral Config Block Found\n"); + pr_info("Enet_Config = %d\n", peripheral_config.ENETConfig.EnetConfig); + pr_info("EMAC = %pM\n", peripheral_config.ENETConfig.MACAddr); + pr_info("PHYMask = 0x%x\n", peripheral_config.ENETConfig.PHYMask); + if (peripheral_config.LCDConfig.Enable) + pr_info("LCD Configured : %s\n", + peripheral_config.LCDConfig.PanelName); + else + pr_info("No LCD Configured\n"); + + for (i = 0; i < 3; i++) { + pr_info("UART[%d] = %d, %d, %d, %d\n", i, + peripheral_config.UARTConfig[i].Enable, + peripheral_config.UARTConfig[i].IsConsole, + peripheral_config.UARTConfig[i].EnableHWFlowCtrl, + peripheral_config.UARTConfig[i].Baud); + } + for (i = 0; i < 2; i++) { + int mask = 0; + for (j = 0; j < 8; j++) + mask |= ((peripheral_config.SPIConfig[i].CSEnable[j]) ? + (1<> 18) & 0xfffc, + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = mityomapl138_map_io, + .init_irq = cp_intc_init, + .timer = &davinci_timer, + .init_machine = mityomapl138_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h new file mode 100644 index 0000000..7ba085a --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h @@ -0,0 +1,125 @@ +/** + * Factory / Peripheral Configuration Data as provided by ATAG_PERIPHERAL + * for the MityDSP-L138 SOMs. (mityomapl138 machines) + * + * Copyright (C) 2010 Critical Link LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef CONFIG_BLOCK_H_ +#define CONFIG_BLOCK_H_ + +#define CONFIG_MAGIC_WORD 0x00BD0138 +#define CONFIG_VERSION 0x00010000 + +#define ENET_CONFIG_NONE 1 +#define ENET_CONFIG_MII 2 +#define ENET_CONFIG_RMII 3 + +#define CONFIG_I2C_MAGIC_WORD 0x012C0138 +#define CONFIG_I2C_VERSION 0x00010001 + +/** + * Peripherals Version History + * 1.00 Baseline + * 1.01 Added McASP Configuration + * 1.02 Added ethernet phy mask + */ +#define PERIPHERALS_VERSION 0x00010002 + +#ifndef CONFIG_MITYDSP_ENV_SIZE +#define CONFIG_MITYDSP_ENV_SIZE (64 << 10) +#endif + +#define FPGATYPE_NONE 0 +#define FPGATYPE_XC6SLX9 1 +#define FPGATYPE_XC6SLX16 2 +#define FPGATYPE_XC6SLX25 3 +#define FPGATYPE_XC6SLX45 4 +#define FPGATYPE_UNKNOWN 10000 + +struct I2CFactoryConfig { + u32 ConfigMagicWord; /** CONFIG_I2C_MAGIC_WORD */ + u32 ConfigVersion; /** CONFIG_I2C_VERSION */ + u8 MACADDR[6]; /** mac address assigned to part */ + u32 FpgaType; /** fpga installed, see above */ + u32 Spare; /** Not Used */ + u32 SerialNumber; /** serial number of part */ + char PartNumber[32]; /** board part number */ +}; + +struct UARTConfig { + u8 Enable; /** enable Tx/Rx */ + u8 IsConsole; /** cfg as the console */ + u8 EnableHWFlowCtrl; /** cfg CTS/RTS */ + u32 Baud; /** default baud rate */ +}; + +struct SPIConfig { + u8 Enable; /** cfg dev+CLK, SIMO, SOMI pins */ + u8 CLKOut; /** drive the CLK */ + u8 CSEnable[8]; /** cfg the associated CS as output */ + u8 ENAEnable; /** cfg the ENA pin for SPI function */ + u32 CLKRate; /** default clock rate */ + u8 Spare[8]; +}; + +struct LCDConfig { + u8 Enable; + u8 PanelName[32]; +}; + +struct ENETConfig { + u32 EnetConfig; + u8 MACAddr[6]; + u32 PHYMask; + u8 Spare[8]; +}; + +#define MCASP_PINMODE_INACTIVE 0 +#define MCASP_PINMODE_TX 1 +#define MCASP_PINMODE_RX 2 + +struct MCASPConfig { + u8 Enable; + u8 Mode; + u8 PinMode[16]; +}; +/** + * struct tag_peripherals is passed in via kernel ATAG_PERIPHERALS + */ +struct tag_peripherals { + u32 Version; /** == PERIPHERALS_VERSION */ + u8 Manufacturer[64]; /** null terminated string indicating manufacturer */ + struct ENETConfig ENETConfig; /** Enable on-board ethernet */ + struct UARTConfig UARTConfig[3]; /** default UART 0,1,2 Configuration */ + struct SPIConfig SPIConfig[2]; + struct LCDConfig LCDConfig; + struct MCASPConfig MCASPConfig; +}; + +/** + * This structure can only be grown. You cannot make it smaller... + */ +struct MityDSPL138Config { + u32 ConfigMagicWord; /** == CONFIG_MAGIC_WORD */ + u32 ConfigVersion; /** version of the configuration block */ + u32 ConfigSizeBytes; /** configuration size, in bytes */ + struct tag_peripherals Peripherals; +}; + +struct MityDSPL138ConfigBlock { + union { + struct MityDSPL138Config config; + u8 space[CONFIG_MITYDSP_ENV_SIZE-sizeof(int)]; + } Data; + unsigned int CheckSum; /** summed bytes of ConfigSizeBytes */ +}; + +extern struct MityDSPL138Config config_block; +extern struct I2CFactoryConfig factory_config_block; +extern int get_config_block(void); +extern int get_factory_config_block(void); + +#endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 1b31a9a..1989316 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -41,6 +41,7 @@ extern void __iomem *da8xx_syscfg1_base; #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) #define DA8XX_JTAG_ID_REG 0x18 +#define DA8XX_MSTPRI2_REG 0x118 #define DA8XX_CFGCHIP0_REG 0x17c #define DA8XX_CFGCHIP2_REG 0x184 #define DA8XX_CFGCHIP3_REG 0x188 diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 15a6192..db6f1cd 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -88,6 +88,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* DA8xx boards */ DEBUG_LL_DA8XX(davinci_da830_evm, 2); DEBUG_LL_DA8XX(davinci_da850_evm, 2); + DEBUG_LL_DA8XX(mityomapl138, 1); /* TNETV107x boards */ DEBUG_LL_TNETV107X(tnetv107x, 1); From yuvraj.pasi at nextbitcpu.com Wed Jul 21 02:27:07 2010 From: yuvraj.pasi at nextbitcpu.com (Yuvraj Pasi) Date: Wed, 21 Jul 2010 12:57:07 +0530 Subject: MPEG4 encoder not giving output Message-ID: Hi, We are using our custom made board based on DM6446 platform. we are using dvsdk 2. My problem is that MPEG4 encoder is not giving proper output while for same set of parameter values it is working properly with H264 encoder & giving proper encoded frame which I am able to decode. I am using following settings for the parameter. params.size = sizeof(VIDENC1_Params); params.encodingPreset = XDM_DEFAULT; params.rateControlPreset = IVIDEO_LOW_DELAY; params.maxBitRate = 6000000; params.dataEndianness = XDM_BYTE; params.maxInterFrameInterval = 1; params.inputChromaFormat = XDM_YUV_422ILE; params.inputContentType = IVIDEO_PROGRESSIVE; params.maxHeight = D1_MAX_HEIGHT; params.maxWidth = D1_MAX_WIDTH; params.reconChromaFormat = XDM_CHROMA_NA; params.maxFrameRate = 30000;//videnc->fps*1000; dynamicParams.size = sizeof(VIDENC1_DynamicParams); dynamicParams.inputHeight = videnc->vsize.height; dynamicParams.inputWidth = videnc->vsize.width; dynamicParams.targetBitRate = videnc->maxbr; dynamicParams.intraFrameInterval = 30; dynamicParams.generateHeader = header; dynamicParams.captureWidth = 0; dynamicParams.forceFrame = IVIDEO_NA_FRAME; dynamicParams.interFrameInterval = 1; dynamicParams.mbDataFlag = 0; dynamicParams.targetFrameRate = videnc->fps*1000; dynamicParams.refFrameRate = videnc->fps*1000; Also when I check the outArgs it show the value of outArgs.inputFrameSkip = 1. What am I missing here?? -- Thanks & regards yuvraj pasi -------------- next part -------------- An HTML attachment was scrubbed... URL: From jean-paul.saman at m2x.nl Wed Jul 21 02:38:49 2010 From: jean-paul.saman at m2x.nl (Jean-Paul Saman) Date: Wed, 21 Jul 2010 09:38:49 +0200 Subject: MPEG4 encoder not giving output In-Reply-To: References: Message-ID: <4C46A409.90307@m2x.nl> On 07/21/2010 09:27 AM, Yuvraj Pasi wrote: > Hi, > We are using our custom made board based on DM6446 platform. we are > using dvsdk 2. My problem is that > MPEG4 encoder is not giving proper output while for same set of > parameter values it is working properly > with H264 encoder & giving proper encoded frame which I am able to decode. > I am using following settings for the parameter. > > params.size = sizeof(VIDENC1_Params); > params.encodingPreset = XDM_DEFAULT; > params.rateControlPreset = IVIDEO_LOW_DELAY; > params.maxBitRate = 6000000; > params.dataEndianness = XDM_BYTE; > params.maxInterFrameInterval = 1; Try setting params.maxInterFrameInterval = 0; this is needed for some encoders. > params.inputChromaFormat = XDM_YUV_422ILE; > params.inputContentType = IVIDEO_PROGRESSIVE; > params.maxHeight = D1_MAX_HEIGHT; > params.maxWidth = D1_MAX_WIDTH; > params.reconChromaFormat = XDM_CHROMA_NA; > params.maxFrameRate = 30000;//videnc->fps*1000; > > dynamicParams.size = sizeof(VIDENC1_DynamicParams); > dynamicParams.inputHeight = videnc->vsize.height; > dynamicParams.inputWidth = videnc->vsize.width; > dynamicParams.targetBitRate = videnc->maxbr; > dynamicParams.intraFrameInterval = 30; > dynamicParams.generateHeader = header; > dynamicParams.captureWidth = 0; > dynamicParams.forceFrame = IVIDEO_NA_FRAME; > dynamicParams.interFrameInterval = 1; > dynamicParams.mbDataFlag = 0; > dynamicParams.targetFrameRate = videnc->fps*1000; > dynamicParams.refFrameRate = videnc->fps*1000; > > Also when I check the outArgs it show the value of > outArgs.inputFrameSkip = 1. > > What am I missing here?? > > > -- > Thanks & regards > yuvraj pasi > > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -- Kind Regards, Jean-Paul Saman M2X BV From nsekhar at ti.com Wed Jul 21 03:51:43 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Wed, 21 Jul 2010 14:21:43 +0530 Subject: [PATCH 2/4] davinci: clock: add support for setting sysclk rate In-Reply-To: <4C45960E.9000005@mvista.com> References: <1279624611-8255-1-git-send-email-nsekhar@ti.com> <1279624611-8255-2-git-send-email-nsekhar@ti.com> <4C45960E.9000005@mvista.com> Message-ID: Hi Sergei, On Tue, Jul 20, 2010 at 17:56:54, Sergei Shtylyov wrote: > Hello. > > Sekhar Nori wrote: > [...] > > +int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) > > +{ > [...] > > + if (input > rate) { > > + /* > > + * Can afford to provide an output little higher than requested > > + * only if maximum rate supported by hardware on this sysclk > > + * is known. > > + */ > > + if (clk->maxrate) { > > + ratio = DIV_ROUND_CLOSEST(input, rate); > > + if (input / ratio > clk->maxrate) > > + ratio = 0; > > + } > > + > > + if (ratio == 0) > > + ratio = DIV_ROUND_UP(input, rate); > > + > > + ratio = ratio - 1; > > Why not simply ratio--? It's C after all. :-) > Sure, will change. :) Regards, Sekhar From yuvraj.pasi at nextbitcpu.com Wed Jul 21 04:12:42 2010 From: yuvraj.pasi at nextbitcpu.com (Yuvraj Pasi) Date: Wed, 21 Jul 2010 14:42:42 +0530 Subject: MPEG4 encoder not giving output In-Reply-To: <4C46A409.90307@m2x.nl> References: <4C46A409.90307@m2x.nl> Message-ID: Hi Jean, Thanks for the reply i did what u advised. No difference!!! any more suggestions. On Wed, Jul 21, 2010 at 1:08 PM, Jean-Paul Saman wrote: > On 07/21/2010 09:27 AM, Yuvraj Pasi wrote: > > Hi, > > We are using our custom made board based on DM6446 platform. we are > > using dvsdk 2. My problem is that > > MPEG4 encoder is not giving proper output while for same set of > > parameter values it is working properly > > with H264 encoder & giving proper encoded frame which I am able to > decode. > > I am using following settings for the parameter. > > > > params.size = sizeof(VIDENC1_Params); > > params.encodingPreset = XDM_DEFAULT; > > params.rateControlPreset = IVIDEO_LOW_DELAY; > > params.maxBitRate = 6000000; > > params.dataEndianness = XDM_BYTE; > > params.maxInterFrameInterval = 1; > > Try setting params.maxInterFrameInterval = 0; this is needed for some > encoders. > > > params.inputChromaFormat = XDM_YUV_422ILE; > > params.inputContentType = IVIDEO_PROGRESSIVE; > > params.maxHeight = D1_MAX_HEIGHT; > > params.maxWidth = D1_MAX_WIDTH; > > params.reconChromaFormat = XDM_CHROMA_NA; > > params.maxFrameRate = 30000;//videnc->fps*1000; > > > > dynamicParams.size = sizeof(VIDENC1_DynamicParams); > > dynamicParams.inputHeight = videnc->vsize.height; > > dynamicParams.inputWidth = videnc->vsize.width; > > dynamicParams.targetBitRate = videnc->maxbr; > > dynamicParams.intraFrameInterval = 30; > > dynamicParams.generateHeader = header; > > dynamicParams.captureWidth = 0; > > dynamicParams.forceFrame = IVIDEO_NA_FRAME; > > dynamicParams.interFrameInterval = 1; > > dynamicParams.mbDataFlag = 0; > > dynamicParams.targetFrameRate = videnc->fps*1000; > > dynamicParams.refFrameRate = videnc->fps*1000; > > > > Also when I check the outArgs it show the value of > > outArgs.inputFrameSkip = 1. > > > > What am I missing here?? > > > > > > -- > > Thanks & regards > > yuvraj pasi > > > > > > > > _______________________________________________ > > Davinci-linux-open-source mailing list > > Davinci-linux-open-source at linux.davincidsp.com > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > > -- > Kind Regards, > > Jean-Paul Saman > M2X BV > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > -- Thanks & regards yuvraj pasi -------------- next part -------------- An HTML attachment was scrubbed... URL: From premkumar.j at ti.com Wed Jul 21 04:22:51 2010 From: premkumar.j at ti.com (JayaKumar, PremKumar) Date: Wed, 21 Jul 2010 14:52:51 +0530 Subject: MPEG4 encoder not giving output In-Reply-To: References: <4C46A409.90307@m2x.nl> Message-ID: Hi Yuvraj, When you say "not giving proper output", does that mean that the output is corrupted? Guess there are no failures observed. Can you send the absolute values for all the params that you use instead of variables? Also, can you try explicitly setting the captureWidth value same as that of the inputWidth? Regards, Prem ________________________________ From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Yuvraj Pasi Sent: Wednesday, July 21, 2010 2:43 PM To: Jean-Paul Saman Cc: davinci-linux-open-source at linux.davincidsp.com Subject: Re: MPEG4 encoder not giving output Hi Jean, Thanks for the reply i did what u advised. No difference!!! any more suggestions. On Wed, Jul 21, 2010 at 1:08 PM, Jean-Paul Saman > wrote: On 07/21/2010 09:27 AM, Yuvraj Pasi wrote: > Hi, > We are using our custom made board based on DM6446 platform. we are > using dvsdk 2. My problem is that > MPEG4 encoder is not giving proper output while for same set of > parameter values it is working properly > with H264 encoder & giving proper encoded frame which I am able to decode. > I am using following settings for the parameter. > > params.size = sizeof(VIDENC1_Params); > params.encodingPreset = XDM_DEFAULT; > params.rateControlPreset = IVIDEO_LOW_DELAY; > params.maxBitRate = 6000000; > params.dataEndianness = XDM_BYTE; > params.maxInterFrameInterval = 1; Try setting params.maxInterFrameInterval = 0; this is needed for some encoders. > params.inputChromaFormat = XDM_YUV_422ILE; > params.inputContentType = IVIDEO_PROGRESSIVE; > params.maxHeight = D1_MAX_HEIGHT; > params.maxWidth = D1_MAX_WIDTH; > params.reconChromaFormat = XDM_CHROMA_NA; > params.maxFrameRate = 30000;//videnc->fps*1000; > > dynamicParams.size = sizeof(VIDENC1_DynamicParams); > dynamicParams.inputHeight = videnc->vsize.height; > dynamicParams.inputWidth = videnc->vsize.width; > dynamicParams.targetBitRate = videnc->maxbr; > dynamicParams.intraFrameInterval = 30; > dynamicParams.generateHeader = header; > dynamicParams.captureWidth = 0; > dynamicParams.forceFrame = IVIDEO_NA_FRAME; > dynamicParams.interFrameInterval = 1; > dynamicParams.mbDataFlag = 0; > dynamicParams.targetFrameRate = videnc->fps*1000; > dynamicParams.refFrameRate = videnc->fps*1000; > > Also when I check the outArgs it show the value of > outArgs.inputFrameSkip = 1. > > What am I missing here?? > > > -- > Thanks & regards > yuvraj pasi > > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -- Kind Regards, Jean-Paul Saman M2X BV _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -- Thanks & regards yuvraj pasi -------------- next part -------------- An HTML attachment was scrubbed... URL: From yuvraj.pasi at nextbitcpu.com Wed Jul 21 04:51:53 2010 From: yuvraj.pasi at nextbitcpu.com (Yuvraj Pasi) Date: Wed, 21 Jul 2010 15:21:53 +0530 Subject: MPEG4 encoder not giving output In-Reply-To: References: <4C46A409.90307@m2x.nl> Message-ID: Hi Prem, Thanks for the reply. when I say that improper output it means it is giving some data output after every 30 frames. using following printf i get the output shown below. printf("Encoded framesize %d %d %d\n", outArgs.bytesGenerated, outArgs.encodedFrameType, outArgs.inputFrameSkip); Encoded framesize 1730 0 0 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 1740 0 0 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 1720 0 0 when i feed this 1740 bytes of data to decoder it produce a pink white output screen & gives no error. Below is the absolute value of parameters & these same values works properly for H264 codec. params.size = sizeof(VIDENC1_Params); params.encodingPreset = XDM_DEFAULT; params.rateControlPreset = IVIDEO_LOW_DELAY; params.maxBitRate = 6000000; params.dataEndianness = XDM_BYTE; params.maxInterFrameInterval = 1; params.inputChromaFormat = XDM_YUV_422ILE; params.inputContentType = IVIDEO_PROGRESSIVE; params.maxHeight = 576; params.maxWidth = 720; params.reconChromaFormat = XDM_CHROMA_NA; params.maxFrameRate = 30000; dynamicParams.size = sizeof(VIDENC1_DynamicParams); dynamicParams.inputHeight = 576; dynamicParams.inputWidth = 720; dynamicParams.targetBitRate = 1500000; dynamicParams.intraFrameInterval = 30; dynamicParams.generateHeader = XDM_ENCODE_AU; dynamicParams.captureWidth = 0; dynamicParams.forceFrame = IVIDEO_NA_FRAME; dynamicParams.interFrameInterval = 1; dynamicParams.mbDataFlag = 0; dynamicParams.targetFrameRate = 25000; dynamicParams.refFrameRate = 25000; On Wed, Jul 21, 2010 at 2:52 PM, JayaKumar, PremKumar wrote: > Hi Yuvraj, > > > > When you say ?not giving proper output?, does that mean that the output is > corrupted? Guess there are no failures observed. > > > > Can you send the absolute values for all the params that you use instead of > variables? > > > > Also, can you try explicitly setting the captureWidth value same as that of > the inputWidth? > > > > Regards, > > Prem > > > ------------------------------ > > *From:* davinci-linux-open-source-bounces at linux.davincidsp.com [mailto: > davinci-linux-open-source-bounces at linux.davincidsp.com] *On Behalf Of *Yuvraj > Pasi > *Sent:* Wednesday, July 21, 2010 2:43 PM > *To:* Jean-Paul Saman > *Cc:* davinci-linux-open-source at linux.davincidsp.com > *Subject:* Re: MPEG4 encoder not giving output > > > > Hi Jean, Thanks for the reply i did what u advised. No difference!!! > any more suggestions. > > On Wed, Jul 21, 2010 at 1:08 PM, Jean-Paul Saman > wrote: > > On 07/21/2010 09:27 AM, Yuvraj Pasi wrote: > > Hi, > > We are using our custom made board based on DM6446 platform. we are > > using dvsdk 2. My problem is that > > MPEG4 encoder is not giving proper output while for same set of > > parameter values it is working properly > > with H264 encoder & giving proper encoded frame which I am able to > decode. > > I am using following settings for the parameter. > > > > params.size = sizeof(VIDENC1_Params); > > params.encodingPreset = XDM_DEFAULT; > > params.rateControlPreset = IVIDEO_LOW_DELAY; > > params.maxBitRate = 6000000; > > params.dataEndianness = XDM_BYTE; > > params.maxInterFrameInterval = 1; > > Try setting params.maxInterFrameInterval = 0; this is needed for some > encoders. > > > > params.inputChromaFormat = XDM_YUV_422ILE; > > params.inputContentType = IVIDEO_PROGRESSIVE; > > params.maxHeight = D1_MAX_HEIGHT; > > params.maxWidth = D1_MAX_WIDTH; > > params.reconChromaFormat = XDM_CHROMA_NA; > > params.maxFrameRate = 30000;//videnc->fps*1000; > > > > dynamicParams.size = sizeof(VIDENC1_DynamicParams); > > dynamicParams.inputHeight = videnc->vsize.height; > > dynamicParams.inputWidth = videnc->vsize.width; > > dynamicParams.targetBitRate = videnc->maxbr; > > dynamicParams.intraFrameInterval = 30; > > dynamicParams.generateHeader = header; > > dynamicParams.captureWidth = 0; > > dynamicParams.forceFrame = IVIDEO_NA_FRAME; > > dynamicParams.interFrameInterval = 1; > > dynamicParams.mbDataFlag = 0; > > dynamicParams.targetFrameRate = videnc->fps*1000; > > dynamicParams.refFrameRate = videnc->fps*1000; > > > > Also when I check the outArgs it show the value of > > outArgs.inputFrameSkip = 1. > > > > What am I missing here?? > > > > > > -- > > Thanks & regards > > yuvraj pasi > > > > > > > > > _______________________________________________ > > Davinci-linux-open-source mailing list > > Davinci-linux-open-source at linux.davincidsp.com > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > > -- > Kind Regards, > > Jean-Paul Saman > M2X BV > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > > > > -- > Thanks & regards > yuvraj pasi > -- Thanks & regards yuvraj pasi -------------- next part -------------- An HTML attachment was scrubbed... URL: From yuvraj.pasi at nextbitcpu.com Wed Jul 21 06:15:51 2010 From: yuvraj.pasi at nextbitcpu.com (Yuvraj Pasi) Date: Wed, 21 Jul 2010 16:45:51 +0530 Subject: MPEG4 encoder not giving output In-Reply-To: References: <4C46A409.90307@m2x.nl> Message-ID: Hi Prem, As I said we are using our custom based board & not dvevm. we do not have TVP5146 installed on our board. for this reason DVTB cant run on our board. On Wed, Jul 21, 2010 at 4:09 PM, JayaKumar, PremKumar wrote: > Yuvraj, > > > > I would suggest you to use the DVTB application that is present in your > DVSDK installation to try out the same usecase. > > You would need to build the application (simple steps mentioned in the > Release notes) for DM6446 platform, copy it to your target environment and > run it with the default videnc1.dvs script provided in the DVTB package > under dvtb_x_xx_xx\packages\ti\sdo\dvtb\scripts\dm6446. > > > > Regards, > > Prem > > > ------------------------------ > > *From:* Yuvraj Pasi [mailto:yuvraj.pasi at nextbitcpu.com] > *Sent:* Wednesday, July 21, 2010 4:04 PM > *To:* JayaKumar, PremKumar > > *Subject:* Re: MPEG4 encoder not giving output > > > > Hi Prem, > There is no change if I set captureWidth to 720 or 1440. But when I changed > rateControlPreset to IVIDEO_NONE > the encoder it seems has stopped skipping frames. > Encoded framesize 5569 0 0 829440 > Encoded framesize 3678 1 0 829440 > Encoded framesize 1554 1 0 829440 > Encoded framesize 1322 1 0 829440 > Encoded framesize 1134 1 0 829440 > Encoded framesize 1124 1 0 829440 > Encoded framesize 1034 1 0 829440 > Encoded framesize 1502 1 0 829440 > Encoded framesize 1945 1 0 829440 > Encoded framesize 1867 1 0 829440 > Encoded framesize 1038 1 0 829440 > Encoded framesize 688 1 0 829440 > Encoded framesize 577 1 0 829440 > Encoded framesize 1210 1 0 829440 > Encoded framesize 1563 1 0 829440 > Encoded framesize 1922 1 0 829440 > Encoded framesize 1451 1 0 829440 > Encoded framesize 2271 1 0 829440 > Encoded framesize 2261 1 0 829440 > Encoded framesize 1849 1 0 829440 > Encoded framesize 1104 1 0 829440 > Encoded framesize 1242 1 0 829440 > Encoded framesize 1804 1 0 829440 > Encoded framesize 1902 1 0 829440 > Encoded framesize 1971 1 0 829440 > Encoded framesize 1823 1 0 829440 > Encoded framesize 2282 1 0 829440 > Encoded framesize 1766 1 0 829440 > Encoded framesize 3222 1 0 829440 > Encoded framesize 2721 1 0 829440 > Encoded framesize 5579 0 0 829440 > Encoded framesize 2115 1 0 829440 > > But the output is moving image of white & pink colour blocks. > > On Wed, Jul 21, 2010 at 3:41 PM, JayaKumar, PremKumar > wrote: > > Hi Yuvraj, > > > > Guess we can work one-to-one instead of through davinci-linux-open-source > mailing list. > > What happens when you set the captureWidth explicitly to 720 instead of 0? > > > > Regards, > > Prem > > > ------------------------------ > > *From:* Yuvraj Pasi [mailto:yuvraj.pasi at nextbitcpu.com] > *Sent:* Wednesday, July 21, 2010 3:22 PM > *To:* JayaKumar, PremKumar > > > *Cc:* davinci-linux-open-source at linux.davincidsp.com > *Subject:* Re: MPEG4 encoder not giving output > > > > Hi Prem, > Thanks for the reply. when I say that improper output it means it is giving > some data output after every 30 frames. > using following printf i get the output shown below. > printf("Encoded framesize %d %d %d\n", outArgs.bytesGenerated, > outArgs.encodedFrameType, outArgs.inputFrameSkip); > > Encoded framesize 1730 0 0 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 1740 0 0 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 0 0 1 > Encoded framesize 1720 0 0 > > when i feed this 1740 bytes of data to decoder it produce a pink white > output screen & gives no error. > Below is the absolute value of parameters & these same values works > properly for H264 codec. > > > params.size = sizeof(VIDENC1_Params); > params.encodingPreset = XDM_DEFAULT; > params.rateControlPreset = IVIDEO_LOW_DELAY; > params.maxBitRate = 6000000; > params.dataEndianness = XDM_BYTE; > params.maxInterFrameInterval = 1; > params.inputChromaFormat = XDM_YUV_422ILE; > params.inputContentType = IVIDEO_PROGRESSIVE; > params.maxHeight = 576; > params.maxWidth = 720; > params.reconChromaFormat = XDM_CHROMA_NA; > params.maxFrameRate = 30000; > > dynamicParams.size > > = sizeof(VIDENC1_DynamicParams); > dynamicParams.inputHeight = 576; > dynamicParams.inputWidth = 720; > dynamicParams.targetBitRate = 1500000; > dynamicParams.intraFrameInterval = 30; > dynamicParams.generateHeader = XDM_ENCODE_AU; > dynamicParams.captureWidth = 0; > dynamicParams.forceFrame = IVIDEO_NA_FRAME; > dynamicParams.interFrameInterval = 1; > dynamicParams.mbDataFlag = 0; > dynamicParams.targetFrameRate = 25000; > dynamicParams.refFrameRate = 25000; > > > > On Wed, Jul 21, 2010 at 2:52 PM, JayaKumar, PremKumar > wrote: > > Hi Yuvraj, > > > > When you say ?not giving proper output?, does that mean that the output is > corrupted? Guess there are no failures observed. > > > > Can you send the absolute values for all the params that you use instead of > variables? > > > > Also, can you try explicitly setting the captureWidth value same as that of > the inputWidth? > > > > Regards, > > Prem > > > ------------------------------ > > *From:* davinci-linux-open-source-bounces at linux.davincidsp.com [mailto: > davinci-linux-open-source-bounces at linux.davincidsp.com] *On Behalf Of *Yuvraj > Pasi > *Sent:* Wednesday, July 21, 2010 2:43 PM > *To:* Jean-Paul Saman > *Cc:* davinci-linux-open-source at linux.davincidsp.com > *Subject:* Re: MPEG4 encoder not giving output > > > > Hi Jean, Thanks for the reply i did what u advised. No difference!!! > any more suggestions. > > On Wed, Jul 21, 2010 at 1:08 PM, Jean-Paul Saman > wrote: > > On 07/21/2010 09:27 AM, Yuvraj Pasi wrote: > > Hi, > > We are using our custom made board based on DM6446 platform. we are > > using dvsdk 2. My problem is that > > MPEG4 encoder is not giving proper output while for same set of > > parameter values it is working properly > > with H264 encoder & giving proper encoded frame which I am able to > decode. > > I am using following settings for the parameter. > > > > params.size = sizeof(VIDENC1_Params); > > params.encodingPreset = XDM_DEFAULT; > > params.rateControlPreset = IVIDEO_LOW_DELAY; > > params.maxBitRate = 6000000; > > params.dataEndianness = XDM_BYTE; > > params.maxInterFrameInterval = 1; > > Try setting params.maxInterFrameInterval = 0; this is needed for some > encoders. > > > > params.inputChromaFormat = XDM_YUV_422ILE; > > params.inputContentType = IVIDEO_PROGRESSIVE; > > params.maxHeight = D1_MAX_HEIGHT; > > params.maxWidth = D1_MAX_WIDTH; > > params.reconChromaFormat = XDM_CHROMA_NA; > > params.maxFrameRate = 30000;//videnc->fps*1000; > > > > dynamicParams.size = sizeof(VIDENC1_DynamicParams); > > dynamicParams.inputHeight = videnc->vsize.height; > > dynamicParams.inputWidth = videnc->vsize.width; > > dynamicParams.targetBitRate = videnc->maxbr; > > dynamicParams.intraFrameInterval = 30; > > dynamicParams.generateHeader = header; > > dynamicParams.captureWidth = 0; > > dynamicParams.forceFrame = IVIDEO_NA_FRAME; > > dynamicParams.interFrameInterval = 1; > > dynamicParams.mbDataFlag = 0; > > dynamicParams.targetFrameRate = videnc->fps*1000; > > dynamicParams.refFrameRate = videnc->fps*1000; > > > > Also when I check the outArgs it show the value of > > outArgs.inputFrameSkip = 1. > > > > What am I missing here?? > > > > > > -- > > Thanks & regards > > yuvraj pasi > > > > > > > > > _______________________________________________ > > Davinci-linux-open-source mailing list > > Davinci-linux-open-source at linux.davincidsp.com > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > > -- > Kind Regards, > > Jean-Paul Saman > M2X BV > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > > > > -- > Thanks & regards > yuvraj pasi > > > > > -- > Thanks & regards > yuvraj pasi > > > > > -- > Thanks & regards > yuvraj pasi > -- Thanks & regards yuvraj pasi -------------- next part -------------- An HTML attachment was scrubbed... URL: From Paul_Stuart at seektech.com Wed Jul 21 16:52:37 2010 From: Paul_Stuart at seektech.com (Paul Stuart) Date: Wed, 21 Jul 2010 14:52:37 -0700 Subject: Dm355-270 SD/MMC Module Freq Message-ID: <7F1B6BBBDF05C649BBBA3C853F488A611AA8784361@Hawking.deepsea.com> Hi There, Does anyone know if the DM355-270 can run at full speed and have reliable SD/MMC module behavior? We are using the 270 MHz variety of the DM355, clocked up to 270MHz. Now, the SD/MMC module claims that it only supports a module clock speed up to 100MHz, but running at 270 MHz produces a module's clock of 135 MHz. Since the sysclk2 divider is a fixed, to even get close to spec (108MHz) one would need to clock the ARM down to 216MHz... and start asking why we paid more for the 270 MHz part :) I see mostly good behavior on SDHC cards when we are over clocking the module at 135MHz, but get cards every now and again that throw buffer IO errors on data read timeouts. Anyone vouch for 135 MHz module clock working with a variety of SDHC cards? Thanks, Paul From akpm at linux-foundation.org Wed Jul 21 17:00:58 2010 From: akpm at linux-foundation.org (Andrew Morton) Date: Wed, 21 Jul 2010 15:00:58 -0700 Subject: [PATCH v2] mtd-nand: davinci: correct 4-bit error correction In-Reply-To: <034501cb2415$ad54cc80$07fe6580$@raj@ti.com> References: <1279170641-24494-1-git-send-email-sudhakar.raj@ti.com> <70E876B0EA86DD4BAF101844BC814DFE0903CBD539@Cloud.RL.local> <034101cb2412$ac5bcde0$051369a0$@raj@ti.com> <034501cb2415$ad54cc80$07fe6580$@raj@ti.com> Message-ID: <20100721150058.dfb4ef06.akpm@linux-foundation.org> On Thu, 15 Jul 2010 17:33:03 +0530 "Sudhakar Rajashekhara" wrote: > On Thu, Jul 15, 2010 at 17:11:32, Sudhakar Rajashekhara wrote: > > Hi, > > > > On Thu, Jul 15, 2010 at 16:31:19, Jon Povey wrote: > > > Sudhakar Rajashekhara wrote: > > > > On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the > > > > 4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and > > > > before waiting for the NAND Flash status register to be equal to 1, 2 > > > > or 3, we have to wait till the ECC HW goes to correction state. > > > > Without this wait, ECC correction calculations will not be proper. > > > > > > > > This has been tested on DA830/OMAP-L137, DA850/OMAP-L138, DM355 and > > > > DM365 EVMs. > > > > > > > > Signed-off-by: Sudhakar Rajashekhara > > > > Acked-by: Sneha Narnakaje > > > > Cc: David Woodhouse > > > > Signed-off-by: Andrew Morton > > > > > > Have these people acked and signed off this new version of the patch? > > > > > > > No. Andrew Morton has not signed off this version. I'll remove > > Signed-off-by: Andrew Morton > > > > Andrew Morton had signed off an earlier version of this patch and > it was present in -mm tree for a long time. He has not yet commented > on v2 version of this patch. But I thought I can carry forward the > Sign-offs from previous version to the next version. What's the common > practice? > I've lost the plot on this patch and I think I'll drop my copy. Please update and resend, cc'ing everyone. I've been sitting on this thing since November last year! It fixes a bug! Where the heck are the MTD maintainers and why aren't they running around with hair on fire getting this thing finalised and merged?!?! From anshuman at ti.com Wed Jul 21 20:55:52 2010 From: anshuman at ti.com (Saxena, Anshuman) Date: Thu, 22 Jul 2010 07:25:52 +0530 Subject: Dm355-270 SD/MMC Module Freq Message-ID: <2A3DCF3DA181AD40BDE86A3150B27B6B030CBF1BF2@dbde02.ent.ti.com> Hi, If I remember correctly, there is an internal divider in the MMC/SD module which can control the clock going into the module. I have to double check though. We had used DM355-270 version and had it working with slower SD cards at 25-30 MHz clock also. So I assume your use case should be covered. Regards, Anshuman ----- Original Message ----- From: davinci-linux-open-source-bounces+anshuman=ti.com at linux.davincidsp.com To: davinci-linux-open-source at linux.davincidsp.com Sent: Thu Jul 22 03:22:37 2010 Subject: Dm355-270 SD/MMC Module Freq Hi There, Does anyone know if the DM355-270 can run at full speed and have reliable SD/MMC module behavior? We are using the 270 MHz variety of the DM355, clocked up to 270MHz. Now, the SD/MMC module claims that it only supports a module clock speed up to 100MHz, but running at 270 MHz produces a module's clock of 135 MHz. Since the sysclk2 divider is a fixed, to even get close to spec (108MHz) one would need to clock the ARM down to 216MHz... and start asking why we paid more for the 270 MHz part :) I see mostly good behavior on SDHC cards when we are over clocking the module at 135MHz, but get cards every now and again that throw buffer IO errors on data read timeouts. Anyone vouch for 135 MHz module clock working with a variety of SDHC cards? Thanks, Paul _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source From Paul_Stuart at seektech.com Wed Jul 21 23:45:44 2010 From: Paul_Stuart at seektech.com (Paul Stuart) Date: Wed, 21 Jul 2010 21:45:44 -0700 Subject: Dm355-270 SD/MMC Module Freq In-Reply-To: <2A3DCF3DA181AD40BDE86A3150B27B6B030CBF1BF2@dbde02.ent.ti.com> References: <2A3DCF3DA181AD40BDE86A3150B27B6B030CBF1BF2@dbde02.ent.ti.com> Message-ID: <7F1B6BBBDF05C649BBBA3C853F488A611AA8784365@Hawking.deepsea.com> Unfortunately it is a fixed divide-by-four, so the module frequency is strictly coupled to the system clock. ________________________________________ From: Saxena, Anshuman [anshuman at ti.com] Sent: Wednesday, July 21, 2010 6:55 PM To: Paul Stuart; 'davinci-linux-open-source at linux.davincidsp.com' Subject: Re: Dm355-270 SD/MMC Module Freq Hi, If I remember correctly, there is an internal divider in the MMC/SD module which can control the clock going into the module. I have to double check though. We had used DM355-270 version and had it working with slower SD cards at 25-30 MHz clock also. So I assume your use case should be covered. Regards, Anshuman ----- Original Message ----- From: davinci-linux-open-source-bounces+anshuman=ti.com at linux.davincidsp.com To: davinci-linux-open-source at linux.davincidsp.com Sent: Thu Jul 22 03:22:37 2010 Subject: Dm355-270 SD/MMC Module Freq Hi There, Does anyone know if the DM355-270 can run at full speed and have reliable SD/MMC module behavior? We are using the 270 MHz variety of the DM355, clocked up to 270MHz. Now, the SD/MMC module claims that it only supports a module clock speed up to 100MHz, but running at 270 MHz produces a module's clock of 135 MHz. Since the sysclk2 divider is a fixed, to even get close to spec (108MHz) one would need to clock the ARM down to 216MHz... and start asking why we paid more for the 270 MHz part :) I see mostly good behavior on SDHC cards when we are over clocking the module at 135MHz, but get cards every now and again that throw buffer IO errors on data read timeouts. Anyone vouch for 135 MHz module clock working with a variety of SDHC cards? Thanks, Paul _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source From premkumar.j at ti.com Wed Jul 21 23:56:09 2010 From: premkumar.j at ti.com (JayaKumar, PremKumar) Date: Thu, 22 Jul 2010 10:26:09 +0530 Subject: MPEG4 encoder not giving output In-Reply-To: References: <4C46A409.90307@m2x.nl> Message-ID: Yuvraj, TVP5146 is not mandatory for DVTB to run. DVTB can run in Filebased mode where the input to the Encoder is YUV file. It's only that you need to get DVTB built right first which is fairly straightforward. I just wanted to see if the same usecase works in another application (DVTB with working script) which is in parallel to yours. We tried the same usecase using DVTB in our DVSDK 2.0 development environment with the same parameters and the encoded output is proper. Can you check if you are setting the framePitch of the inBufDesc properly? Regards, Prem ________________________________ From: Yuvraj Pasi [mailto:yuvraj.pasi at nextbitcpu.com] Sent: Wednesday, July 21, 2010 4:46 PM To: JayaKumar, PremKumar Cc: davinci-linux-open-source at linux.davincidsp.com Subject: Re: MPEG4 encoder not giving output Hi Prem, As I said we are using our custom based board & not dvevm. we do not have TVP5146 installed on our board. for this reason DVTB cant run on our board. On Wed, Jul 21, 2010 at 4:09 PM, JayaKumar, PremKumar > wrote: Yuvraj, I would suggest you to use the DVTB application that is present in your DVSDK installation to try out the same usecase. You would need to build the application (simple steps mentioned in the Release notes) for DM6446 platform, copy it to your target environment and run it with the default videnc1.dvs script provided in the DVTB package under dvtb_x_xx_xx\packages\ti\sdo\dvtb\scripts\dm6446. Regards, Prem ________________________________ From: Yuvraj Pasi [mailto:yuvraj.pasi at nextbitcpu.com] Sent: Wednesday, July 21, 2010 4:04 PM To: JayaKumar, PremKumar Subject: Re: MPEG4 encoder not giving output Hi Prem, There is no change if I set captureWidth to 720 or 1440. But when I changed rateControlPreset to IVIDEO_NONE the encoder it seems has stopped skipping frames. Encoded framesize 5569 0 0 829440 Encoded framesize 3678 1 0 829440 Encoded framesize 1554 1 0 829440 Encoded framesize 1322 1 0 829440 Encoded framesize 1134 1 0 829440 Encoded framesize 1124 1 0 829440 Encoded framesize 1034 1 0 829440 Encoded framesize 1502 1 0 829440 Encoded framesize 1945 1 0 829440 Encoded framesize 1867 1 0 829440 Encoded framesize 1038 1 0 829440 Encoded framesize 688 1 0 829440 Encoded framesize 577 1 0 829440 Encoded framesize 1210 1 0 829440 Encoded framesize 1563 1 0 829440 Encoded framesize 1922 1 0 829440 Encoded framesize 1451 1 0 829440 Encoded framesize 2271 1 0 829440 Encoded framesize 2261 1 0 829440 Encoded framesize 1849 1 0 829440 Encoded framesize 1104 1 0 829440 Encoded framesize 1242 1 0 829440 Encoded framesize 1804 1 0 829440 Encoded framesize 1902 1 0 829440 Encoded framesize 1971 1 0 829440 Encoded framesize 1823 1 0 829440 Encoded framesize 2282 1 0 829440 Encoded framesize 1766 1 0 829440 Encoded framesize 3222 1 0 829440 Encoded framesize 2721 1 0 829440 Encoded framesize 5579 0 0 829440 Encoded framesize 2115 1 0 829440 But the output is moving image of white & pink colour blocks. On Wed, Jul 21, 2010 at 3:41 PM, JayaKumar, PremKumar > wrote: Hi Yuvraj, Guess we can work one-to-one instead of through davinci-linux-open-source mailing list. What happens when you set the captureWidth explicitly to 720 instead of 0? Regards, Prem ________________________________ From: Yuvraj Pasi [mailto:yuvraj.pasi at nextbitcpu.com] Sent: Wednesday, July 21, 2010 3:22 PM To: JayaKumar, PremKumar Cc: davinci-linux-open-source at linux.davincidsp.com Subject: Re: MPEG4 encoder not giving output Hi Prem, Thanks for the reply. when I say that improper output it means it is giving some data output after every 30 frames. using following printf i get the output shown below. printf("Encoded framesize %d %d %d\n", outArgs.bytesGenerated, outArgs.encodedFrameType, outArgs.inputFrameSkip); Encoded framesize 1730 0 0 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 1740 0 0 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 0 0 1 Encoded framesize 1720 0 0 when i feed this 1740 bytes of data to decoder it produce a pink white output screen & gives no error. Below is the absolute value of parameters & these same values works properly for H264 codec. params.size = sizeof(VIDENC1_Params); params.encodingPreset = XDM_DEFAULT; params.rateControlPreset = IVIDEO_LOW_DELAY; params.maxBitRate = 6000000; params.dataEndianness = XDM_BYTE; params.maxInterFrameInterval = 1; params.inputChromaFormat = XDM_YUV_422ILE; params.inputContentType = IVIDEO_PROGRESSIVE; params.maxHeight = 576; params.maxWidth = 720; params.reconChromaFormat = XDM_CHROMA_NA; params.maxFrameRate = 30000; dynamicParams.size = sizeof(VIDENC1_DynamicParams); dynamicParams.inputHeight = 576; dynamicParams.inputWidth = 720; dynamicParams.targetBitRate = 1500000; dynamicParams.intraFrameInterval = 30; dynamicParams.generateHeader = XDM_ENCODE_AU; dynamicParams.captureWidth = 0; dynamicParams.forceFrame = IVIDEO_NA_FRAME; dynamicParams.interFrameInterval = 1; dynamicParams.mbDataFlag = 0; dynamicParams.targetFrameRate = 25000; dynamicParams.refFrameRate = 25000; On Wed, Jul 21, 2010 at 2:52 PM, JayaKumar, PremKumar > wrote: Hi Yuvraj, When you say "not giving proper output", does that mean that the output is corrupted? Guess there are no failures observed. Can you send the absolute values for all the params that you use instead of variables? Also, can you try explicitly setting the captureWidth value same as that of the inputWidth? Regards, Prem ________________________________ From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Yuvraj Pasi Sent: Wednesday, July 21, 2010 2:43 PM To: Jean-Paul Saman Cc: davinci-linux-open-source at linux.davincidsp.com Subject: Re: MPEG4 encoder not giving output Hi Jean, Thanks for the reply i did what u advised. No difference!!! any more suggestions. On Wed, Jul 21, 2010 at 1:08 PM, Jean-Paul Saman > wrote: On 07/21/2010 09:27 AM, Yuvraj Pasi wrote: > Hi, > We are using our custom made board based on DM6446 platform. we are > using dvsdk 2. My problem is that > MPEG4 encoder is not giving proper output while for same set of > parameter values it is working properly > with H264 encoder & giving proper encoded frame which I am able to decode. > I am using following settings for the parameter. > > params.size = sizeof(VIDENC1_Params); > params.encodingPreset = XDM_DEFAULT; > params.rateControlPreset = IVIDEO_LOW_DELAY; > params.maxBitRate = 6000000; > params.dataEndianness = XDM_BYTE; > params.maxInterFrameInterval = 1; Try setting params.maxInterFrameInterval = 0; this is needed for some encoders. > params.inputChromaFormat = XDM_YUV_422ILE; > params.inputContentType = IVIDEO_PROGRESSIVE; > params.maxHeight = D1_MAX_HEIGHT; > params.maxWidth = D1_MAX_WIDTH; > params.reconChromaFormat = XDM_CHROMA_NA; > params.maxFrameRate = 30000;//videnc->fps*1000; > > dynamicParams.size = sizeof(VIDENC1_DynamicParams); > dynamicParams.inputHeight = videnc->vsize.height; > dynamicParams.inputWidth = videnc->vsize.width; > dynamicParams.targetBitRate = videnc->maxbr; > dynamicParams.intraFrameInterval = 30; > dynamicParams.generateHeader = header; > dynamicParams.captureWidth = 0; > dynamicParams.forceFrame = IVIDEO_NA_FRAME; > dynamicParams.interFrameInterval = 1; > dynamicParams.mbDataFlag = 0; > dynamicParams.targetFrameRate = videnc->fps*1000; > dynamicParams.refFrameRate = videnc->fps*1000; > > Also when I check the outArgs it show the value of > outArgs.inputFrameSkip = 1. > > What am I missing here?? > > > -- > Thanks & regards > yuvraj pasi > > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -- Kind Regards, Jean-Paul Saman M2X BV _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -- Thanks & regards yuvraj pasi -- Thanks & regards yuvraj pasi -- Thanks & regards yuvraj pasi -- Thanks & regards yuvraj pasi -------------- next part -------------- An HTML attachment was scrubbed... URL: From nsekhar at ti.com Thu Jul 22 00:53:29 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Thu, 22 Jul 2010 11:23:29 +0530 Subject: [PATCH v2] DaVinci: dm365: Added clockout2 management. In-Reply-To: <1279709510-6213-1-git-send-email-lamiaposta71@gmail.com> References: <1279709510-6213-1-git-send-email-lamiaposta71@gmail.com> Message-ID: Hi Raffaele, On Wed, Jul 21, 2010 at 16:21:49, Raffaele Recalcati wrote: > From: Davide Bonfanti > > Clockout2 is added as a child of pll1_sysclk9, because they have > the same pll divisor. > Added dm365_clkout2_set_rate to properly set clockout2 frequency. > Modified the davinci_set_sysclk_rate function in order > to get the right ancestor. This change should be carved into a separate patch since it is not directly related to adding clockout2 support. In the new patch please describe how the existing code isn't getting the right ancestor. Also, that patch should note below the '---' that it depends on this patch submitted to the mailing list: https://patchwork.kernel.org/patch/112994/ This helps maintainer derive the correct order in which patches need to be applied. > > This patch has been developed against the > http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git As, mentioned before, this is implied when submitting to davinci-linux-open-source at linux.davincidsp.com and so can be removed. If you want to note it, please note below the '---' in the patch so it wont make it to the commit log. > git tree and tested on bmx board. > > Signed-off-by: Davide Bonfanti > Signed-off-by: Raffaele Recalcati > --- > arch/arm/mach-davinci/clock.c | 32 ++++++++++++---- > arch/arm/mach-davinci/clock.h | 5 ++ > arch/arm/mach-davinci/dm365.c | 57 ++++++++++++++++++++++++++++ > arch/arm/mach-davinci/include/mach/dm365.h | 1 + > 4 files changed, 87 insertions(+), 8 deletions(-) > > diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c > index f29a526..6e45808 100644 > --- a/arch/arm/mach-davinci/clock.c > +++ b/arch/arm/mach-davinci/clock.c > @@ -254,7 +254,15 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) > u32 v, plldiv; > struct pll_data *pll; > unsigned long rate = clk->rate; > + struct clk *parent = clk; > > + if (clk == NULL || IS_ERR(clk)) > + return -EINVAL; > + while (parent->parent->parent) > + parent = parent->parent; > + > + if (parent == clk) > + return -EPERM; It is not clear to me why this change in needed. It is not described in the patch description as well. Most likely this needs to be carved into a separate patch as well describing what is wrong with the existing clk_sysclk_recalc() routine. [...] > @@ -293,26 +301,33 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) > struct pll_data *pll; > unsigned long input; > unsigned ratio = 0; > + struct clk *parent = clk; > + > + /* searching the right ancestor (pll1_clk or pll2_clk) */ > + while (parent->parent->parent) > + parent = parent->parent; > + if (parent == clk) > + return -EPERM; As noted above, please carve into separate patch. [...] > diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h > index a717d98..df36d73 100644 > --- a/arch/arm/mach-davinci/clock.h > +++ b/arch/arm/mach-davinci/clock.h > @@ -50,6 +50,11 @@ > #define PLLDIV_EN BIT(15) > #define PLLDIV_RATIO_MASK 0x1f > > +#define PERI_CLKCTL 0x48 > +#define CLOCKOUT2EN 2 > +#define CLOCKOUT1EN 1 > +#define CLOCKOUT0EN 0 > + > /* > * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN > * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us > diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c > index 42fd4a4..902e9a0 100644 > --- a/arch/arm/mach-davinci/dm365.c > +++ b/arch/arm/mach-davinci/dm365.c > @@ -40,6 +40,11 @@ > #include "mux.h" > > #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ > +#define PINMUX0 0x00 > +#define PINMUX1 0x04 > +#define PINMUX2 0x08 > +#define PINMUX3 0x0c > +#define PINMUX4 0x10 Why are PINMUX defines added here? You don't seem to use these elsewhere in the patch. > > static struct pll_data pll1_data = { > .num = 1, > @@ -124,6 +129,7 @@ static struct clk pll1_sysclk6 = { > .parent = &pll1_clk, > .flags = CLK_PLL, > .div_reg = PLLDIV6, > + .set_rate = davinci_set_sysclk_rate, > }; > > static struct clk pll1_sysclk7 = { > @@ -145,6 +151,14 @@ static struct clk pll1_sysclk9 = { > .parent = &pll1_clk, > .flags = CLK_PLL, > .div_reg = PLLDIV9, > + .set_rate = davinci_set_sysclk_rate, > +}; > + > +static struct clk clkout2_clk = { > + .name = "clkout2", > + .parent = &pll1_sysclk9, > + .flags = CLK_PLL, > + .set_rate = dm365_clkout2_set_rate, > }; > > static struct clk pll2_clk = { > @@ -421,6 +435,7 @@ static struct clk_lookup dm365_clks[] = { > CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), > CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), > CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), > + CLK(NULL, "clkout2", &clkout2_clk), > CLK(NULL, "pll2", &pll2_clk), > CLK(NULL, "pll2_aux", &pll2_aux_clk), > CLK(NULL, "clkout1", &clkout1_clk), > @@ -657,6 +672,48 @@ static struct resource dm365_spi0_resources[] = { > }, > }; > > +int dm365_clkout2_set_rate(unsigned long rate) Is clockout2 specific to DM365? DM355/DM6446 manuals mention clkout signal as well. If this routine can cater to more SoCs with simple modifications, you can attempt to generalize it. > +{ > + int ret = -EINVAL; > + int i, err, min_err, i_min_err; > + u32 regval; > + struct clk *clk; > + static void __iomem *system_module_base; > + > + clk = &clkout2_clk; > + system_module_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE, SZ_4K); > + regval = __raw_readl(system_module_base + PERI_CLKCTL); This part of the code would make it specific to DM365. May be the div_reg present in clock structure can be used to pass this register address from platform file? It will then be a matter of seeing whether the register bit definitions line up across platforms. You don't have to necessarily test on all platforms as long as the code is written generically enough. > + > + /* check all possibilities to get best fitting for the required freq */ > + i_min_err = min_err = INT_MAX; > + for (i = 0x0F; i > 0; i--) { > + if (clk->parent->set_rate) { > + ret = clk_set_rate(clk->parent, rate * i) ; > + err = clk_get_rate(clk->parent) - rate * i; > + if (min_err > abs(err)) { > + min_err = abs(err); > + i_min_err = i; > + } > + } > + } Why should the child touch the parent's clock output? Users of the clock framework should be able to set these rates independently. Can you please check if there is a need to do this even with the latest patch I posted? In that patch, if the 'maxrate' the sysclk can support is known, the sysclk rate set code using DIV_ROUND_CLOSEST() which should give the least error already. Thanks, Sekhar From anshuman at ti.com Thu Jul 22 02:30:32 2010 From: anshuman at ti.com (Saxena, Anshuman) Date: Thu, 22 Jul 2010 13:00:32 +0530 Subject: Dm355-270 SD/MMC Module Freq In-Reply-To: <7F1B6BBBDF05C649BBBA3C853F488A611AA8784365@Hawking.deepsea.com> References: <2A3DCF3DA181AD40BDE86A3150B27B6B030CBF1BF2@dbde02.ent.ti.com> <7F1B6BBBDF05C649BBBA3C853F488A611AA8784365@Hawking.deepsea.com> Message-ID: <2A3DCF3DA181AD40BDE86A3150B27B6B030E38BF82@dbde02.ent.ti.com> Stuart, I was mentioning about the CLKRT register in MMC/SD controller. That can be programmed to send out a lower clock to SD card, to meet the specification of less than 50MHz for SDHC cards. Regards, Anshuman -----Original Message----- From: Paul Stuart [mailto:Paul_Stuart at seektech.com] Sent: Thursday, July 22, 2010 10:16 AM To: Saxena, Anshuman; 'davinci-linux-open-source at linux.davincidsp.com' Subject: RE: Dm355-270 SD/MMC Module Freq Unfortunately it is a fixed divide-by-four, so the module frequency is strictly coupled to the system clock. ________________________________________ From: Saxena, Anshuman [anshuman at ti.com] Sent: Wednesday, July 21, 2010 6:55 PM To: Paul Stuart; 'davinci-linux-open-source at linux.davincidsp.com' Subject: Re: Dm355-270 SD/MMC Module Freq Hi, If I remember correctly, there is an internal divider in the MMC/SD module which can control the clock going into the module. I have to double check though. We had used DM355-270 version and had it working with slower SD cards at 25-30 MHz clock also. So I assume your use case should be covered. Regards, Anshuman ----- Original Message ----- From: davinci-linux-open-source-bounces+anshuman=ti.com at linux.davincidsp.com To: davinci-linux-open-source at linux.davincidsp.com Sent: Thu Jul 22 03:22:37 2010 Subject: Dm355-270 SD/MMC Module Freq Hi There, Does anyone know if the DM355-270 can run at full speed and have reliable SD/MMC module behavior? We are using the 270 MHz variety of the DM355, clocked up to 270MHz. Now, the SD/MMC module claims that it only supports a module clock speed up to 100MHz, but running at 270 MHz produces a module's clock of 135 MHz. Since the sysclk2 divider is a fixed, to even get close to spec (108MHz) one would need to clock the ARM down to 216MHz... and start asking why we paid more for the 270 MHz part :) I see mostly good behavior on SDHC cards when we are over clocking the module at 135MHz, but get cards every now and again that throw buffer IO errors on data read timeouts. Anyone vouch for 135 MHz module clock working with a variety of SDHC cards? Thanks, Paul _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source From vishwanath.k at ti.com Thu Jul 22 03:55:45 2010 From: vishwanath.k at ti.com (Vishwanath.K) Date: Thu, 22 Jul 2010 14:25:45 +0530 Subject: [PATCH] davinci: I2C: Adding bus frequency as module parameter Message-ID: <1279788945-3643-1-git-send-email-vishwanath.k@ti.com> From: vishwa With current implementation, when I2C is used as a module, for slave devices which operate at different frequencies, the bus frequency needs to be modified in the board configuration file and kernel needs to be re-built. This patch addresses this issue by adding bus frequency as module parameter. Signed-off-by: vishwa --- drivers/i2c/busses/i2c-davinci.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c index 2222c87..ba0817c 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -98,6 +98,13 @@ #define DAVINCI_I2C_IMR_NACK BIT(1) #define DAVINCI_I2C_IMR_AL BIT(0) +/* + * Following are the default values for the module parameters + * If user didn't specify the bus frequency, driver will + * take the bus freq from board configuration. + */ +static int i2c_davinci_busfreq; + struct davinci_i2c_dev { struct device *dev; void __iomem *base; @@ -217,6 +224,9 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) psc++; /* better to run under spec than over */ d = (psc >= 2) ? 5 : 7 - psc; + if (i2c_davinci_busfreq != 0) + pdata->bus_freq = i2c_davinci_busfreq; + clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1); clkh = clk >> 1; clkl = clk - clkh; @@ -818,6 +828,7 @@ static void __exit davinci_i2c_exit_driver(void) platform_driver_unregister(&davinci_i2c_driver); } module_exit(davinci_i2c_exit_driver); +module_param(i2c_davinci_busfreq, int, 0); MODULE_AUTHOR("Texas Instruments India"); MODULE_DESCRIPTION("TI DaVinci I2C bus adapter"); -- 1.5.6 From lrg at slimlogic.co.uk Thu Jul 22 07:05:19 2010 From: lrg at slimlogic.co.uk (Liam Girdwood) Date: Thu, 22 Jul 2010 13:05:19 +0100 Subject: [PATCH v2 2/2] davinci: da850/omap-l138 evm: account for DEFDCDC{2,3} being tied high In-Reply-To: <1278939146.3072.50.camel@odin> References: <1278937581-867-1-git-send-email-nsekhar@ti.com> <20100712122707.GA22701@rakim.wolfsonmicro.main> <1278939146.3072.50.camel@odin> Message-ID: <1279800319.3083.47.camel@odin> On Mon, 2010-07-12 at 13:52 +0100, Liam Girdwood wrote: > On Mon, 2010-07-12 at 13:27 +0100, Mark Brown wrote: > > On Mon, Jul 12, 2010 at 05:56:21PM +0530, Sekhar Nori wrote: > > > Per the da850/omap-l138 Beta EVM SOM schematic, the DEFDCDC2 and > > > DEFDCDC3 lines are tied high. This leads to a 3.3V IO and 1.2V CVDD > > > voltage. > > > > > > Pass the right platform data to the TPS6507x driver so it can operate > > > on the DEFDCDC{2,3}_HIGH register to read and change voltage levels. > > > > > > Signed-off-by: Sekhar Nori > > > > Acked-by: Mark Brown > > Kevin, I can take this through regulator (to reduce dependencies) if you > want ? I think Kevin may be on vacation. Anyone from DaVinci care to comment on taking this patch through regulator ? Thanks Liam -- Freelance Developer, SlimLogic Ltd ASoC and Voltage Regulator Maintainer. http://www.slimlogic.co.uk From pippolini at gmail.com Thu Jul 22 07:21:12 2010 From: pippolini at gmail.com (Emilio C) Date: Thu, 22 Jul 2010 05:21:12 -0700 (PDT) Subject: [PATCH 3/3] davinci: spi: modify platform data for updated SPIdriver In-Reply-To: References: <1275923348-8533-1-git-send-email-bniebuhr@efjohnson.com> <1275923348-8533-2-git-send-email-bniebuhr@efjohnson.com> <1275923348-8533-3-git-send-email-bniebuhr@efjohnson.com> <1275923348-8533-4-git-send-email-bniebuhr@efjohnson.com> <004701cb087a$6cb51470$461f3d50$@raj@ti.com> Message-ID: <1279801272959-5325095.post@n2.nabble.com> Hi, I'm using an Omap L137 based board I've applied Brian's patch (the final version, v4) and I've modified the board configuration file (board_d830_evm.c) according to your post, but I don't see any spi nor mtd device in /dev Do you have any hint about how to modify the udev configuration in order to se the new mtd partitions? Thanks! -- View this message in context: http://davinci-linux-open-source.1494791.n2.nabble.com/PATCH-0-3-davinci-spi-replace-existing-SPI-driver-tp5149493p5325095.html Sent from the davinci-linux-open-source mailing list archive at Nabble.com. From Paul_Stuart at seektech.com Thu Jul 22 09:34:26 2010 From: Paul_Stuart at seektech.com (Paul Stuart) Date: Thu, 22 Jul 2010 07:34:26 -0700 Subject: Dm355-270 SD/MMC Module Freq In-Reply-To: <2A3DCF3DA181AD40BDE86A3150B27B6B030E38BF82@dbde02.ent.ti.com> References: <2A3DCF3DA181AD40BDE86A3150B27B6B030CBF1BF2@dbde02.ent.ti.com> <7F1B6BBBDF05C649BBBA3C853F488A611AA8784365@Hawking.deepsea.com>, <2A3DCF3DA181AD40BDE86A3150B27B6B030E38BF82@dbde02.ent.ti.com> Message-ID: <7F1B6BBBDF05C649BBBA3C853F488A611AA8784366@Hawking.deepsea.com> tis true. The issue I raise though is that the DM355's SD/MMC module itself claims an internal upper frequency range of 100MHz. Check out Page 12 of: " MS320DM35x Digital Media System-on-Chip (DMSoC) Multimedia Card (MMC)/Secure Digital (SD) (SDIO) Card Controller Reference Guide" ( SPRUEE2C) Here's a snip from it "The MMC/SD controller has two clocks, the function clock and the memory clock (Figure 4). The function clock determines the operational frequency of the MMC/SD controller and is the input clock to the MMC/SD controller on the device. The MMC/SD controller is capable of operating with a function clock up to 100 MHz." Problem is, if you are running your part at 270 MHz, the input clock is 135 MHz. ________________________________________ From: Saxena, Anshuman [anshuman at ti.com] Sent: Thursday, July 22, 2010 12:30 AM To: Paul Stuart; 'davinci-linux-open-source at linux.davincidsp.com' Subject: RE: Dm355-270 SD/MMC Module Freq Stuart, I was mentioning about the CLKRT register in MMC/SD controller. That can be programmed to send out a lower clock to SD card, to meet the specification of less than 50MHz for SDHC cards. Regards, Anshuman -----Original Message----- From: Paul Stuart [mailto:Paul_Stuart at seektech.com] Sent: Thursday, July 22, 2010 10:16 AM To: Saxena, Anshuman; 'davinci-linux-open-source at linux.davincidsp.com' Subject: RE: Dm355-270 SD/MMC Module Freq Unfortunately it is a fixed divide-by-four, so the module frequency is strictly coupled to the system clock. ________________________________________ From: Saxena, Anshuman [anshuman at ti.com] Sent: Wednesday, July 21, 2010 6:55 PM To: Paul Stuart; 'davinci-linux-open-source at linux.davincidsp.com' Subject: Re: Dm355-270 SD/MMC Module Freq Hi, If I remember correctly, there is an internal divider in the MMC/SD module which can control the clock going into the module. I have to double check though. We had used DM355-270 version and had it working with slower SD cards at 25-30 MHz clock also. So I assume your use case should be covered. Regards, Anshuman ----- Original Message ----- From: davinci-linux-open-source-bounces+anshuman=ti.com at linux.davincidsp.com To: davinci-linux-open-source at linux.davincidsp.com Sent: Thu Jul 22 03:22:37 2010 Subject: Dm355-270 SD/MMC Module Freq Hi There, Does anyone know if the DM355-270 can run at full speed and have reliable SD/MMC module behavior? We are using the 270 MHz variety of the DM355, clocked up to 270MHz. Now, the SD/MMC module claims that it only supports a module clock speed up to 100MHz, but running at 270 MHz produces a module's clock of 135 MHz. Since the sysclk2 divider is a fixed, to even get close to spec (108MHz) one would need to clock the ARM down to 216MHz... and start asking why we paid more for the 270 MHz part :) I see mostly good behavior on SDHC cards when we are over clocking the module at 135MHz, but get cards every now and again that throw buffer IO errors on data read timeouts. Anyone vouch for 135 MHz module clock working with a variety of SDHC cards? Thanks, Paul _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source From nsekhar at ti.com Thu Jul 22 10:40:10 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Thu, 22 Jul 2010 21:10:10 +0530 Subject: [PATCH v2] rtc: omap: let device wakeup capability be configured from chip init logic In-Reply-To: <389061.41765.qm@web180310.mail.gq1.yahoo.com> References: <389061.41765.qm@web180310.mail.gq1.yahoo.com> Message-ID: Hi Alessandro, On Mon, Jul 19, 2010 at 02:22:13, David Brownell wrote: > > > --- On Wed, 6/16/10, Nori, Sekhar wrote: > > > Date: Wednesday, June 16, 2010, 9:46 PM > > Hi Dave, > > > > Any thoughts on my responses below? If you are > > satisfied, would you please Ack my patch? > > I don't have time to properly review it. If it > works, go for it ... bugs can be fixed later, and > the principle behind the patch is fine. > Since Dave is OK with merging this, would you please queue this for 2.6.36? Thanks, Sekhar From anshuman at ti.com Thu Jul 22 12:44:54 2010 From: anshuman at ti.com (Saxena, Anshuman) Date: Thu, 22 Jul 2010 23:14:54 +0530 Subject: Dm355-270 SD/MMC Module Freq In-Reply-To: <7F1B6BBBDF05C649BBBA3C853F488A611AA8784366@Hawking.deepsea.com> References: <2A3DCF3DA181AD40BDE86A3150B27B6B030CBF1BF2@dbde02.ent.ti.com> <7F1B6BBBDF05C649BBBA3C853F488A611AA8784365@Hawking.deepsea.com>, <2A3DCF3DA181AD40BDE86A3150B27B6B030E38BF82@dbde02.ent.ti.com> <7F1B6BBBDF05C649BBBA3C853F488A611AA8784366@Hawking.deepsea.com> Message-ID: <2A3DCF3DA181AD40BDE86A3150B27B6B030E38C384@dbde02.ent.ti.com> Stuart, Got your point. I understand that your concern is about the function clock itself. But I don't think that should cause the kind of errors you mentioned. Anyways, I would let the device experts to comment on this, but I thought on DM355-270 part, it was ok to use SD controller at 135MHz function clock. The better place to get an answer for this would be the TI E2E forum. I would suggest you post your question there on DM3x processor forum. Regards, Anshuman -----Original Message----- From: Paul Stuart [mailto:Paul_Stuart at seektech.com] Sent: Thursday, July 22, 2010 8:04 PM To: Saxena, Anshuman; 'davinci-linux-open-source at linux.davincidsp.com' Subject: RE: Dm355-270 SD/MMC Module Freq tis true. The issue I raise though is that the DM355's SD/MMC module itself claims an internal upper frequency range of 100MHz. Check out Page 12 of: " MS320DM35x Digital Media System-on-Chip (DMSoC) Multimedia Card (MMC)/Secure Digital (SD) (SDIO) Card Controller Reference Guide" ( SPRUEE2C) Here's a snip from it "The MMC/SD controller has two clocks, the function clock and the memory clock (Figure 4). The function clock determines the operational frequency of the MMC/SD controller and is the input clock to the MMC/SD controller on the device. The MMC/SD controller is capable of operating with a function clock up to 100 MHz." Problem is, if you are running your part at 270 MHz, the input clock is 135 MHz. ________________________________________ From: Saxena, Anshuman [anshuman at ti.com] Sent: Thursday, July 22, 2010 12:30 AM To: Paul Stuart; 'davinci-linux-open-source at linux.davincidsp.com' Subject: RE: Dm355-270 SD/MMC Module Freq Stuart, I was mentioning about the CLKRT register in MMC/SD controller. That can be programmed to send out a lower clock to SD card, to meet the specification of less than 50MHz for SDHC cards. Regards, Anshuman -----Original Message----- From: Paul Stuart [mailto:Paul_Stuart at seektech.com] Sent: Thursday, July 22, 2010 10:16 AM To: Saxena, Anshuman; 'davinci-linux-open-source at linux.davincidsp.com' Subject: RE: Dm355-270 SD/MMC Module Freq Unfortunately it is a fixed divide-by-four, so the module frequency is strictly coupled to the system clock. ________________________________________ From: Saxena, Anshuman [anshuman at ti.com] Sent: Wednesday, July 21, 2010 6:55 PM To: Paul Stuart; 'davinci-linux-open-source at linux.davincidsp.com' Subject: Re: Dm355-270 SD/MMC Module Freq Hi, If I remember correctly, there is an internal divider in the MMC/SD module which can control the clock going into the module. I have to double check though. We had used DM355-270 version and had it working with slower SD cards at 25-30 MHz clock also. So I assume your use case should be covered. Regards, Anshuman ----- Original Message ----- From: davinci-linux-open-source-bounces+anshuman=ti.com at linux.davincidsp.com To: davinci-linux-open-source at linux.davincidsp.com Sent: Thu Jul 22 03:22:37 2010 Subject: Dm355-270 SD/MMC Module Freq Hi There, Does anyone know if the DM355-270 can run at full speed and have reliable SD/MMC module behavior? We are using the 270 MHz variety of the DM355, clocked up to 270MHz. Now, the SD/MMC module claims that it only supports a module clock speed up to 100MHz, but running at 270 MHz produces a module's clock of 135 MHz. Since the sysclk2 divider is a fixed, to even get close to spec (108MHz) one would need to clock the ARM down to 216MHz... and start asking why we paid more for the 270 MHz part :) I see mostly good behavior on SDHC cards when we are over clocking the module at 135MHz, but get cards every now and again that throw buffer IO errors on data read timeouts. Anyone vouch for 135 MHz module clock working with a variety of SDHC cards? Thanks, Paul _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source From Jon.Povey at racelogic.co.uk Fri Jul 23 01:42:58 2010 From: Jon.Povey at racelogic.co.uk (Jon Povey) Date: Fri, 23 Jul 2010 07:42:58 +0100 Subject: Anyone using ftrace on DaVinci git? Message-ID: <70E876B0EA86DD4BAF101844BC814DFE0903CBDFFE@Cloud.RL.local> Is anyone using ftrace on DaVinci git with success? I'm trying to use the irqsoff tracer to look into an irq latency problem on DM355, but it seems not to be recording small time changes, jumping in units of 10ms. Example partial trace: ksoftirq-3 0d..1. 0us : finish_task_switch <-trace_hardirqs_on ksoftirq-3 0d..1. 0us : trace_hardirqs_on <-trace_hardirqs_on ksoftirq-3 0d..1. 0us : do_softirq <-trace_hardirqs_off ksoftirq-3 0d.s1. 0us : __do_softirq <-trace_hardirqs_on ksoftirq-3 0d.s1. 0us : trace_hardirqs_on <-trace_hardirqs_on ksoftirq-3 0d.s1. 0us!: hrtimer_peek_ahead_timers <-trace_hardirqs_off ksoftirq-3 0d.s1. 20000us : hrtimer_peek_ahead_timers <-trace_hardirqs_on ksoftirq-3 0d.s1. 20000us : trace_hardirqs_on <-trace_hardirqs_on ksoftirq-3 0d.s1. 20000us : Related, I have an IRQ handler that seems to be getting interrupted for up to 2+ms by something. This surprises me, I thought IRQs should be disabled? I wonder if CONFIG_PREEMPT is related? Any hints welcome. For now I suppose I'll go back to poking around with LED wiggling and logic analyser. -- Jon Povey jon.povey at racelogic.co.uk Racelogic is a limited company registered in England. Registered number 2743719 . Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB . The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network From mcuos.com at gmail.com Fri Jul 23 04:46:19 2010 From: mcuos.com at gmail.com (Wan ZongShun) Date: Fri, 23 Jul 2010 17:46:19 +0800 Subject: [rtc-linux] RE: [PATCH v2] rtc: omap: let device wakeup capability be configured from chip init logic In-Reply-To: References: <389061.41765.qm@web180310.mail.gq1.yahoo.com> Message-ID: 2010/7/22 Nori, Sekhar : > Hi Alessandro, > > On Mon, Jul 19, 2010 at 02:22:13, David Brownell wrote: >> >> >> --- On Wed, 6/16/10, Nori, Sekhar wrote: >> >> > Date: Wednesday, June 16, 2010, 9:46 PM >> > Hi Dave, >> > >> > Any thoughts on my responses below? If you are >> > satisfied, would you please Ack my patch? >> >> I don't have time to properly review it. ?If it >> works, go for it ... bugs can be fixed later, and >> the principle behind the patch is fine. >> > > Since Dave is OK with merging this, would you please > queue this for 2.6.36? Alessandro is so busy too, you can get merging help from Andrew. > > Thanks, > Sekhar > > -- > You received this message because you are subscribed to "rtc-linux". > Membership options at http://groups.google.com/group/rtc-linux . > Please read http://groups.google.com/group/rtc-linux/web/checklist > before submitting a driver. -- *linux-arm-kernel mailing list mail addr:linux-arm-kernel at lists.infradead.org you can subscribe by: http://lists.infradead.org/mailman/listinfo/linux-arm-kernel * linux-arm-NUC900 mailing list mail addr:NUC900 at googlegroups.com main web: https://groups.google.com/group/NUC900 you can subscribe it by sending me mail: mcuos.com at gmail.com From nsekhar at ti.com Fri Jul 23 04:51:19 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Fri, 23 Jul 2010 15:21:19 +0530 Subject: [PATCH v2 2/2] davinci: da850/omap-l138 evm: account for DEFDCDC{2,3} being tied high In-Reply-To: <1279800319.3083.47.camel@odin> References: <1278937581-867-1-git-send-email-nsekhar@ti.com> <20100712122707.GA22701@rakim.wolfsonmicro.main> <1278939146.3072.50.camel@odin> <1279800319.3083.47.camel@odin> Message-ID: Hi Liam, On Thu, Jul 22, 2010 at 17:35:19, Liam Girdwood wrote: > On Mon, 2010-07-12 at 13:52 +0100, Liam Girdwood wrote: > > On Mon, 2010-07-12 at 13:27 +0100, Mark Brown wrote: > > > On Mon, Jul 12, 2010 at 05:56:21PM +0530, Sekhar Nori wrote: > > > > Per the da850/omap-l138 Beta EVM SOM schematic, the DEFDCDC2 and > > > > DEFDCDC3 lines are tied high. This leads to a 3.3V IO and 1.2V CVDD > > > > voltage. > > > > > > > > Pass the right platform data to the TPS6507x driver so it can operate > > > > on the DEFDCDC{2,3}_HIGH register to read and change voltage levels. > > > > > > > > Signed-off-by: Sekhar Nori > > > > > > Acked-by: Mark Brown > > > > Kevin, I can take this through regulator (to reduce dependencies) if you > > want ? > > I think Kevin may be on vacation. Yes, I believe he is. > Anyone from DaVinci care to comment on taking this patch through > regulator ? If you intended to push this for 2.6.35, I think you should go ahead. I am not aware of any fixes Kevin had lined up for 2.6.35. If you intended this for the 2.6.36 merge, I think we can wait for Kevin to return. The patch actually fixes an issue, so ideally it should be in 2.6.35. Thanks, Sekhar From sudhakar.raj at ti.com Fri Jul 23 04:49:49 2010 From: sudhakar.raj at ti.com (Sudhakar Rajashekhara) Date: Fri, 23 Jul 2010 15:19:49 +0530 Subject: [PATCH v2] mtd-nand: davinci: correct 4-bit error correction In-Reply-To: <20100721150058.dfb4ef06.akpm@linux-foundation.org> References: <1279170641-24494-1-git-send-email-sudhakar.raj@ti.com> <70E876B0EA86DD4BAF101844BC814DFE0903CBD539@Cloud.RL.local> <034101cb2412$ac5bcde0$051369a0$@raj@ti.com> <034501cb2415$ad54cc80$07fe6580$@raj@ti.com> <20100721150058.dfb4ef06.akpm@linux-foundation.org> Message-ID: <051701cb2a4c$6456ead0$2d04c070$@raj@ti.com> Hi, On Thu, Jul 22, 2010 at 03:30:58, Andrew Morton wrote: > On Thu, 15 Jul 2010 17:33:03 +0530 > "Sudhakar Rajashekhara" wrote: > > > On Thu, Jul 15, 2010 at 17:11:32, Sudhakar Rajashekhara wrote: > > > Hi, > > > > > > On Thu, Jul 15, 2010 at 16:31:19, Jon Povey wrote: > > > > Sudhakar Rajashekhara wrote: > > > > > On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the > > > > > 4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and > > > > > before waiting for the NAND Flash status register to be equal to 1, 2 > > > > > or 3, we have to wait till the ECC HW goes to correction state. > > > > > Without this wait, ECC correction calculations will not be proper. > > > > > > > > > > This has been tested on DA830/OMAP-L137, DA850/OMAP-L138, DM355 and > > > > > DM365 EVMs. > > > > > > > > > > Signed-off-by: Sudhakar Rajashekhara > > > > > Acked-by: Sneha Narnakaje > > > > > Cc: David Woodhouse > > > > > Signed-off-by: Andrew Morton > > > > > > > > Have these people acked and signed off this new version of the patch? > > > > > > > > > > No. Andrew Morton has not signed off this version. I'll remove > > > Signed-off-by: Andrew Morton > > > > > > > Andrew Morton had signed off an earlier version of this patch and > > it was present in -mm tree for a long time. He has not yet commented > > on v2 version of this patch. But I thought I can carry forward the > > Sign-offs from previous version to the next version. What's the common > > practice? > > > > > I've lost the plot on this patch and I think I'll drop my copy. Please > update and resend, cc'ing everyone. > > I've been sitting on this thing since November last year! It fixes a > bug! Where the heck are the MTD maintainers and why aren't they > running around with hair on fire getting this thing finalised and > merged?!?! > I got an e-mail from Artem Bityutskiy(dedekind1 at gmail.com) saying that he has pushed this patch to his l2-mtd-2.6/master tree. May be it will get to upstream from there. Thanks, Sudhakar From vit.macarrow at gmail.com Fri Jul 23 10:57:13 2010 From: vit.macarrow at gmail.com (Vitaly Makarov) Date: Fri, 23 Jul 2010 11:57:13 -0400 Subject: GIT Kernel and CMEM 2.25.04.10 Message-ID: Dear All, I am trying to compile the latest CMEM (2.25.04.10) for the latest git kernel and getting the following error: WARNING: "arm926_dma_map_area" [BSP/cmem/src/module/cmemk.ko] and this module can not be used with the kernel due unresolved symbol. Did anyone faced the issue and successfully resolved it? Thank you -- With best regards, Vitaly Makarov -------------- next part -------------- An HTML attachment was scrubbed... URL: From nsekhar at ti.com Mon Jul 26 04:29:18 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Mon, 26 Jul 2010 14:59:18 +0530 Subject: [PATCH v3] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: <4C45AE5E.7070905@criticallink.com> References: <4C45AE5E.7070905@criticallink.com> Message-ID: Hi Michael, On Tue, Jul 20, 2010 at 19:40:38, Michael Williamson wrote: > This patch adds support for the MityDSP-L138 and MityARM-1808 system on > module (SOM) under the registered machine "mityomapl138". These SOMs > are based on the da850 davinci CPU architecture. Information on these > SOMs may be found at http://www.mitydsp.com. > > Signed-off-by: Michael Williamson > --- [...] > > arch/arm/configs/da8xx_omapl_defconfig | 291 ++++++-- > arch/arm/include/asm/setup.h | 5 + > arch/arm/mach-davinci/Kconfig | 7 + > arch/arm/mach-davinci/Makefile | 1 + > arch/arm/mach-davinci/board-mityomapl138.c | 793 ++++++++++++++++++++ > .../mach-davinci/include/mach/cb-mityomapl138.h | 125 +++ > arch/arm/mach-davinci/include/mach/da8xx.h | 1 + > arch/arm/mach-davinci/include/mach/uncompress.h | 1 + > 8 files changed, 1181 insertions(+), 43 deletions(-) > [...] > diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h > index f392fb4..d6b1a47 100644 > --- a/arch/arm/include/asm/setup.h > +++ b/arch/arm/include/asm/setup.h > @@ -143,6 +143,11 @@ struct tag_memclk { > __u32 fmemclk; > }; > > +/** MityDSP-L138 peripheral configuration info, > + * see arch/arm/mach-davinci/include/mach/cb-mityomapl138.h > + */ > +#define ATAG_PERIPHERALS 0x42000101 Instead of naming this so generic, can you call this ATAG_MITYDSPL138 or something like that? Since passing peripheral configuration from bootloader is a first for DaVinci, can you please explain why this is the best suited method for this board and why methods used on other boards wont work? > + > struct tag { > struct tag_header hdr; > union { > diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig > index 71f90f8..064b0e2 100644 > --- a/arch/arm/mach-davinci/Kconfig > +++ b/arch/arm/mach-davinci/Kconfig > @@ -178,6 +178,13 @@ config DA850_UI_RMII > > endchoice > > +config MACH_MITYOMAPL138 > + bool "Critical Link MityOMAPL138 SoM" > + depends on ARCH_DAVINCI_DA850 > + select GPIO_PCA953X > + help > + Say Y here to select the Critical Link MityOMAP-L138 System on Module. Here you can include some pointers on where more information about the board can be found. > + > config MACH_TNETV107X > bool "TI TNETV107X Reference Platform" > default ARCH_DAVINCI_TNETV107X > diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile > index eab4c0f..dfc0fc4 100644 > --- a/arch/arm/mach-davinci/Makefile > +++ b/arch/arm/mach-davinci/Makefile > @@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o > obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o > obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o > obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o > +obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o > obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o > > # Power Management > diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c > new file mode 100644 > index 0000000..c8541f1 > --- /dev/null > +++ b/arch/arm/mach-davinci/board-mityomapl138.c > @@ -0,0 +1,793 @@ > +/* > + * Critical Link MityOMAP-L138 SoM > + * > + * Copyright (C) 2010 Critical Link Incorporated - http://www.criticallink.com > + * > + * Derived from board-da850-evm.c > + * Original Copyrights follow: > + * > + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ > + * > + * Derived from: arch/arm/mach-davinci/board-da830-evm.c > + * Original Copyrights follow: > + * > + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under > + * the terms of the GNU General Public License version 2. This program > + * is licensed "as is" without any warranty of any kind, whether express > + * or implied. > + */ > + > +#define pr_fmt(fmt) "%s: " fmt, __func__ > + > +#include > +#include > +#include > +#include > +#include > +#include You do not seem to have defined platform data for pca953. I guess the include here and the config select above are copy-paste errors? > +#include > +#include > +#include > +#include > +#include > +#include I didn't see any NOR devices registered? > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +static struct tag_peripherals peripheral_config = { > + .Version = PERIPHERALS_VERSION, > + .Manufacturer = "Critical Link", > + .ENETConfig.EnetConfig = ENET_CONFIG_MII, > + .ENETConfig.MACAddr = { 0x00, 0x50, 0xC2, 0x49, 0xDF, 0xFF }, > + .UARTConfig[0] = { > + .Enable = 0, > + .IsConsole = 0, > + .Baud = 115200, > + }, > + .UARTConfig[1] = { > + .Enable = 1, > + .IsConsole = 1, > + .Baud = 115200, > + }, > + .UARTConfig[2] = { > + .Enable = 0, > + .IsConsole = 0, > + .Baud = 115200, > + }, > + .SPIConfig[0] = { > + .Enable = 0, > + .CLKOut = 0, > + .CSEnable = { 0, 0, 0, 0, 0, 0, 0, 0}, > + .ENAEnable = 0, > + .CLKRate = 0, > + }, > + .SPIConfig[1] = { > + .Enable = 1, > + .CLKOut = 1, > + .CSEnable = { 1, 0, 0, 0, 0, 0, 0, 0}, > + .ENAEnable = 0, > + .CLKRate = 30000000, > + }, > + .LCDConfig = { > + .Enable = 0, > + .PanelName = "", > + } > +}; Do we really need the camel case naming? [...] > + > +static __init void mityomapl138_setup_nand(void) > +{ > + Extra line here.. > + platform_add_devices(mityomapl138_devices, > + ARRAY_SIZE(mityomapl138_devices)); > +} > + > +static int mityomapl138_mmc_get_ro(int index) > +{ > + return gpio_get_value(DA850_MMCSD_WP_PIN); > +} > + > +static int mityomapl138_mmc_get_cd(int index) > +{ > + return !gpio_get_value(DA850_MMCSD_CD_PIN); > +} > + > +static struct davinci_mmc_config da850_mmc_config = { > + .get_ro = mityomapl138_mmc_get_ro, > + .get_cd = mityomapl138_mmc_get_cd, > + .wires = 4, > + .max_freq = 50000000, > + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, > + .version = MMC_CTLR_VERSION_2, > +}; > + > +static __init void mityomapl138_setup_mmc(void) > +{ > + int ret; > + > + ret = davinci_cfg_reg_list(da850_mmcsd0_pins); > + if (ret) > + pr_warning("mmcsd0 mux setup failed: %d\n" ,ret); > + > + ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n"); > + if (ret) > + pr_warning("can not open GPIO %d\n", DA850_MMCSD_CD_PIN); > + gpio_direction_input(DA850_MMCSD_CD_PIN); > + > + ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n"); > + if (ret) > + pr_warning("can not open GPIO %d\n", DA850_MMCSD_WP_PIN); > + gpio_direction_input(DA850_MMCSD_WP_PIN); Its not nice to go ahead and operate on the GPIO even though the request call fails. I can see the EVM code does it this way, but that code needs fixing too. > + > + ret = da8xx_register_mmcsd0(&da850_mmc_config); > + if (ret) > + pr_warning("mmcsd0 registration failed: %d\n", ret); > +} > + > + Extra line here.. > +static struct davinci_uart_config mityomapl138_uart_config __initdata = { > + .enabled_uarts = 0x7, > +}; > + > +static int __init mityomapl138_config_emac(void) > +{ > + void __iomem *cfg_chip3_base; > + int ret; > + u32 val; > + struct davinci_soc_info *soc_info = &davinci_soc_info; > + u8 rmii_en = 0; > + > + switch (peripheral_config.ENETConfig.EnetConfig) { > + case ENET_CONFIG_RMII: > + soc_info->emac_pdata->rmii_en = 1; > + rmii_en = 1; > + break; > + case ENET_CONFIG_MII: > + soc_info->emac_pdata->rmii_en = 0; > + rmii_en = 0; > + break; > + case ENET_CONFIG_NONE: > + default: > + pr_info("No Ethernet PHY Selected, EMAC disabled\n"); > + return 0; /* no enet... */ > + break; > + } > + memcpy(&soc_info->emac_pdata->mac_addr[0], > + &peripheral_config.ENETConfig.MACAddr[0], 6); > + > + cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); > + > + val = __raw_readl(cfg_chip3_base); > + > + if (rmii_en) { > + val |= BIT(8); > + ret = davinci_cfg_reg_list(da850_rmii_pins); > + pr_info("RMII PHY configured, MII PHY will not be functional\n"); > + } else { > + val &= ~BIT(8); > + ret = davinci_cfg_reg_list(da850_cpgmac_pins); > + pr_info("MII PHY configured, RMII PHY will not be functional\n"); > + } > + > + if (ret) > + pr_warning("cpgmac/rmii mux setup failed: %d\n", ret); > + > + /* configure the CFGCHIP3 register for RMII or MII */ > + __raw_writel(val, cfg_chip3_base); > + > + soc_info->emac_pdata->phy_mask = peripheral_config.ENETConfig.PHYMask ? > + peripheral_config.ENETConfig.PHYMask : 1; > + pr_info("setting phy_mask to %x\n", soc_info->emac_pdata->phy_mask); > + soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY; > + > + ret = da8xx_register_emac(); > + if (ret) > + pr_warning("emac registration failed: %d\n", ret); > + > + return 0; > +} > +device_initcall(mityomapl138_config_emac); Using device_initcall here is not good. It will get called on other boards as well just because support for this board is built into the kernel. So, at a minimum, there should be check to bail out if machine != mityomapl138. Better still, please re-evaluate whether you really need a device_initcall() here. On the EVM this method was chosen since the Ethernet init was tied to UI card detection. You should aim to eliminate it on this board. > + > +static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { > + .bus_freq = 100, /* kHz */ > + .bus_delay = 0, /* usec */ > +}; This is exactly the pdata that davinci I2C driver uses by default, so you can save a few bytes and a few lines of code by passing NULL pdata. [...] > + > +static struct davinci_spi_platform_data mityomap_spi1_pdata = { > + .version = SPI_VERSION_2, > + .num_chipselect = 1, > + .wdelay = 0, > + .odd_parity = 0, > + .parity_enable = 0, > + .wait_enable = 0, > + .timer_disable = 0, > + .clk_internal = 1, > + .cs_hold = 1, > + .intr_level = 0, > + .poll_mode = 1, > + .use_dma = 0, > + .c2tdelay = 8, > + .t2cdelay = 8, > +}; > + > +static struct resource mityomap_spi1_resources[] = { > + [0] = { > + .start = 0x01F0E000, > + .end = 0x01F0EFFF, > + .flags = IORESOURCE_MEM, > + }, > + [1] = { > + .start = IRQ_DA8XX_SPINT1, > + .start = IRQ_DA8XX_SPINT1, > + .flags = IORESOURCE_IRQ, > + }, > + [2] = { > + .start = EDMA_CTLR_CHAN(0, 18), > + .end = EDMA_CTLR_CHAN(0, 18), > + .flags = IORESOURCE_DMA, > + }, > + [3] = { > + .start = EDMA_CTLR_CHAN(0, 19), > + .end = EDMA_CTLR_CHAN(0, 19), > + .flags = IORESOURCE_DMA, > + }, > + [4] = { > + .start = 1, > + .end = 1, > + .flags = IORESOURCE_DMA, > + }, > +}; > + > +static struct platform_device mityomap_spi1_device = { > + .name = "spi_davinci", > + .id = 1, > + .dev = { > + .platform_data = &mityomap_spi1_pdata, > + }, > + .num_resources = ARRAY_SIZE(mityomap_spi1_resources), > + .resource = mityomap_spi1_resources, > +}; > + > +/***************************************************************************** > + * SPI Devices: > + * SPI1_CS0: 8M Flash ST-M25P64-VME6G > + ****************************************************************************/ > +static struct mtd_partition spi_flash_partitions[] = { > + [0] = { > + .name = "UBL", > + .offset = 0, > + .size = SZ_64K, > + .mask_flags = MTD_WRITEABLE > + }, > + [1] = { > + .name = "U-Boot", > + .offset = MTDPART_OFS_APPEND, > + .size = SZ_512K, > + .mask_flags = 0, > + }, > + [2] = { > + .name = "Spare", > + .offset = MTDPART_OFS_APPEND, > + .size = MTDPART_SIZ_FULL, > + .mask_flags = 0, > + }, > +}; > + > +static struct flash_platform_data mityomap_spi_flash_data = { > + .name = "m25p80", > + .parts = spi_flash_partitions, > + .nr_parts = ARRAY_SIZE(spi_flash_partitions), > + .type = "m25p64", > +}; > + > +static struct spi_board_info mityomap_spi_flash_info[] = { > + { > + .modalias = "m25p80", > + .platform_data = &mityomap_spi_flash_data, > + .mode = SPI_MODE_0, > + .max_speed_hz = 30000000, > + .bus_num = 1, > + .chip_select = 0, > + }, > +}; > + > +void __init mityomap_init_spi1(unsigned chipselect_mask, > + struct spi_board_info *info, unsigned len) > +{ > + int ret; > + ret = platform_device_register(&mityomap_spi1_device); > + if (ret) > + pr_warning("failed to register spi device : %d\n", ret); > + > + ret = spi_register_board_info(info, len); > + if (ret) > + pr_warning("failed to register board info : %d\n", ret); > +} > + > +/* davinci da850 evm audio machine driver */ > +static u8 da850_iis_serializer_direction[] = { > + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, > + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, > + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, > + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, > +}; > + > +static struct snd_platform_data mityomapl138_snd_data = { > + .tx_dma_offset = 0x2000, > + .rx_dma_offset = 0x2000, > + .op_mode = DAVINCI_MCASP_IIS_MODE, > + .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), > + .tdm_slots = 0, > + .serial_dir = da850_iis_serializer_direction, > + .eventq_no = EVENTQ_1, This field was recently changed in a patch[1] which is already queued for ASoC merge for 2.6.36. You will need to base this on that change. When you do that please note the dependency below the '---' in the patch so maintainer knows the order in which to commit patches. [1] http://git.kernel.org/?p=linux/kernel/git/broonie/sound-2.6.git;a=commit;h=48519f0ae03bc7e86b3dc93e56f1334d53803770 > + .version = MCASP_VERSION_2, > + .txnumevt = 0, > + .rxnumevt = 0, > +}; > + > +short mityomapl138_mcasp_pins[24] __initdata = { > + DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, > + DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, > + DA850_AMUTE, > + -1, -1, -1, -1, > + -1, -1, -1, -1, > + -1, -1, -1, -1, > + -1, -1, -1, -1, > + -1 Do we really need all these -1s? > +}; > + > +static __init int mityomapl138_setup_mcasp(void) > +{ > + int ret; > + > + mityomapl138_mcasp_pins[7+0] = DA850_AXR_13; > + da850_iis_serializer_direction[12] = TX_MODE; Why not stick these into the static initialization? > + > + ret = davinci_cfg_reg_list(mityomapl138_mcasp_pins); > + if (ret) > + pr_warning("mcasp mux setup failed: %d\n", ret); > + > + mityomapl138_snd_data.tdm_slots = 2; > + mityomapl138_snd_data.txnumevt = 1; And the same for these? > + > + da8xx_register_mcasp(0, &mityomapl138_snd_data); > + > + return ret; > +} > + > +static const struct display_panel disp_panel = { > + QVGA, > + 16, > + 16, > + COLOR_ACTIVE, > +}; > + > +static struct lcd_ctrl_config lcd_cfg = { > + &disp_panel, > + .ac_bias = 255, > + .ac_bias_intrpt = 0, > + .dma_burst_sz = 16, > + .bpp = 16, > + .fdd = 255, > + .tft_alt_mode = 0, > + .stn_565_mode = 0, > + .mono_8bit_mode = 0, > + .invert_line_clock = 0, > + .invert_frm_clock = 0, > + .sync_edge = 0, > + .sync_ctrl = 1, > + .raster_order = 0, > +}; > + > +static struct da8xx_lcdc_platform_data sharp_lq035q7dh06_pdata = { > + .manu_name = "sharp", > + .controller_data = &lcd_cfg, > + .type = "Sharp_LQ035Q7DH06", > +}; > + > +static struct da8xx_lcdc_platform_data chimei_p0430wqlb_pdata = { > + .manu_name = "ChiMei", > + .controller_data = &lcd_cfg, > + .type = "ChiMei_P0430WQLB", > +}; > + > +static struct da8xx_lcdc_platform_data vga_640x480_pdata = { > + .manu_name = "VGA", > + .controller_data = &lcd_cfg, > + .type = "vga_640x480", > +}; > + > +static struct resource da8xx_lcdc_resources[] = { > + [0] = { /* registers */ > + .start = DA8XX_LCD_CNTRL_BASE, > + .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, > + .flags = IORESOURCE_MEM, > + }, > + [1] = { /* interrupt */ > + .start = IRQ_DA8XX_LCDINT, > + .end = IRQ_DA8XX_LCDINT, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +static struct platform_device da8xx_lcdc_device = { > + .name = "da8xx_lcdc", > + .id = 0, > + .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), > + .resource = da8xx_lcdc_resources, > + .dev = { > + .platform_data = &sharp_lq035q7dh06_pdata, > + } Should have ',' on the last member as well. > +}; > + > +static __init void mityomapl138_setup_lcd(void) > +{ > + int ret; > + > + if (peripheral_config.LCDConfig.Enable) { > + u32 prio; > + > + /* set peripheral master priority up to 1 */ > + prio = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_MSTPRI2_REG)); > + prio &= ~MSTPRI2_LCD_MASK; > + prio |= 1< + __raw_writel(prio, DA8XX_SYSCFG0_VIRT(DA8XX_MSTPRI2_REG)); > + > + if (0 == strncmp("Sharp_LQ035Q7DH06", > + peripheral_config.LCDConfig.PanelName, > + sizeof(peripheral_config. > + LCDConfig.PanelName))) { Why strncmp instead of just strcmp? > + da8xx_lcdc_device.dev.platform_data = > + &sharp_lq035q7dh06_pdata; > + } else if (0 == strncmp("ChiMei_P0430WQLB", > + peripheral_config.LCDConfig.PanelName, > + sizeof(peripheral_config.LCDConfig.PanelName))) { > + da8xx_lcdc_device.dev.platform_data = > + &chimei_p0430wqlb_pdata; > + } else if (0 == strncmp("vga_640x480", > + peripheral_config.LCDConfig.PanelName, > + sizeof(peripheral_config. > + LCDConfig.PanelName))) { > + da8xx_lcdc_device.dev.platform_data = > + &vga_640x480_pdata; > + } else { > + pr_warning("unknown LCD type : %s\n", > + peripheral_config.LCDConfig.PanelName); > + return; > + } > + > + ret = davinci_cfg_reg_list(da850_lcdcntl_pins); > + if (ret) { > + pr_warning("lcd pinmux failed : %d\n", ret); > + return; > + } > + > + ret = platform_device_register(&da8xx_lcdc_device); > + } else { > + pr_warning("no LCD device enabled\n"); > + } > +} > + > +static __init void mityomapl138_init(void) > +{ > + int ret; > + > + ret = pmic_tps65023_init(); > + if (ret) > + pr_warning("TPS65023 PMIC init failed: %d\n", ret); > + > + ret = da8xx_register_edma(); > + if (ret) > + pr_warning("edma registration failed: %d\n", ret); > + > + ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); > + if (ret) > + pr_warning("i2c0 registration failed: %d\n", ret); > + > + ret = da8xx_register_watchdog(); > + if (ret) > + pr_warning("watchdog registration failed: %d\n", ret); > + > + davinci_serial_init(&mityomapl138_uart_config); > + > + ret = da8xx_register_rtc(); > + if (ret) > + pr_warning("rtc setup failed: %d\n", ret); > + > + ret = da850_register_cpufreq(); > + if (ret) > + pr_warning("cpufreq registration failed: %d\n", ret); > + > + ret = da8xx_register_cpuidle(); > + if (ret) > + pr_warning("cpuidle registration failed: %d\n", ret); > + > + mityomapl138_setup_nand(); > + > + mityomap_init_spi1(1, mityomap_spi_flash_info, > + ARRAY_SIZE(mityomap_spi_flash_info)); > + > + mityomapl138_setup_lcd(); > + > + mityomapl138_setup_mmc(); > + > + mityomapl138_setup_mcasp(); > +} > + > +#ifdef CONFIG_SERIAL_8250_CONSOLE > +static int __init mityomapl138_console_init(void) > +{ > + return add_preferred_console("ttyS", 1, "115200"); > +} > +console_initcall(mityomapl138_console_init); > +#endif > + > +static void __init mityomapl138_map_io(void) > +{ > + da850_init(); > +} > + > +static int __init parse_tag_peripherals(const struct tag *tag) > +{ > + struct tag_peripherals *ptag; > + int i, j; > + > + ptag = (struct tag_peripherals *)&tag->u.cmdline.cmdline[0]; > + memcpy(&peripheral_config, ptag, sizeof(peripheral_config)); > + pr_info("Peripheral Config Block Found\n"); > + pr_info("Enet_Config = %d\n", peripheral_config.ENETConfig.EnetConfig); > + pr_info("EMAC = %pM\n", peripheral_config.ENETConfig.MACAddr); > + pr_info("PHYMask = 0x%x\n", peripheral_config.ENETConfig.PHYMask); > + if (peripheral_config.LCDConfig.Enable) > + pr_info("LCD Configured : %s\n", > + peripheral_config.LCDConfig.PanelName); > + else > + pr_info("No LCD Configured\n"); > + > + for (i = 0; i < 3; i++) { > + pr_info("UART[%d] = %d, %d, %d, %d\n", i, > + peripheral_config.UARTConfig[i].Enable, > + peripheral_config.UARTConfig[i].IsConsole, > + peripheral_config.UARTConfig[i].EnableHWFlowCtrl, > + peripheral_config.UARTConfig[i].Baud); Without explaining what you are printing, this wont be of much info. You intended this to be debug instead? Even then it is better to include some information on what is being dumped. > + } > + for (i = 0; i < 2; i++) { > + int mask = 0; > + for (j = 0; j < 8; j++) > + mask |= ((peripheral_config.SPIConfig[i].CSEnable[j]) ? > + (1< + > + pr_info("SPI[%d] = %d, %d, %02X, %d, %d\n", i, > + peripheral_config.SPIConfig[i].Enable, > + peripheral_config.SPIConfig[i].CLKOut, > + mask, > + peripheral_config.SPIConfig[i].ENAEnable, > + peripheral_config.SPIConfig[i].CLKRate); Same here.. > + } > + return 0; > +} > +__tagtable(ATAG_PERIPHERALS, parse_tag_peripherals); > + > + > +MACHINE_START(MITYOMAPL138, "MityDSP-L138") > + .phys_io = IO_PHYS, > + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, > + .boot_params = (DA8XX_DDR_BASE + 0x100), > + .map_io = mityomapl138_map_io, > + .init_irq = cp_intc_init, > + .timer = &davinci_timer, > + .init_machine = mityomapl138_init, > +MACHINE_END > diff --git a/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h > new file mode 100644 > index 0000000..7ba085a > --- /dev/null > +++ b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h > @@ -0,0 +1,125 @@ > +/** > + * Factory / Peripheral Configuration Data as provided by ATAG_PERIPHERAL > + * for the MityDSP-L138 SOMs. (mityomapl138 machines) > + * > + * Copyright (C) 2010 Critical Link LLC. This file is licensed under > + * the terms of the GNU General Public License version 2. This program > + * is licensed "as is" without any warranty of any kind, whether express > + * or implied. > + */ > +#ifndef CONFIG_BLOCK_H_ > +#define CONFIG_BLOCK_H_ Copy paste error? > + > +#define CONFIG_MAGIC_WORD 0x00BD0138 > +#define CONFIG_VERSION 0x00010000 > + > +#define ENET_CONFIG_NONE 1 > +#define ENET_CONFIG_MII 2 > +#define ENET_CONFIG_RMII 3 > + > +#define CONFIG_I2C_MAGIC_WORD 0x012C0138 > +#define CONFIG_I2C_VERSION 0x00010001 > + > +/** > + * Peripherals Version History > + * 1.00 Baseline > + * 1.01 Added McASP Configuration > + * 1.02 Added ethernet phy mask > + */ > +#define PERIPHERALS_VERSION 0x00010002 > + > +#ifndef CONFIG_MITYDSP_ENV_SIZE > +#define CONFIG_MITYDSP_ENV_SIZE (64 << 10) > +#endif > + > +#define FPGATYPE_NONE 0 > +#define FPGATYPE_XC6SLX9 1 > +#define FPGATYPE_XC6SLX16 2 > +#define FPGATYPE_XC6SLX25 3 > +#define FPGATYPE_XC6SLX45 4 > +#define FPGATYPE_UNKNOWN 10000 > + > +struct I2CFactoryConfig { > + u32 ConfigMagicWord; /** CONFIG_I2C_MAGIC_WORD */ > + u32 ConfigVersion; /** CONFIG_I2C_VERSION */ > + u8 MACADDR[6]; /** mac address assigned to part */ > + u32 FpgaType; /** fpga installed, see above */ > + u32 Spare; /** Not Used */ > + u32 SerialNumber; /** serial number of part */ > + char PartNumber[32]; /** board part number */ > +}; > + > +struct UARTConfig { > + u8 Enable; /** enable Tx/Rx */ > + u8 IsConsole; /** cfg as the console */ > + u8 EnableHWFlowCtrl; /** cfg CTS/RTS */ > + u32 Baud; /** default baud rate */ > +}; > + > +struct SPIConfig { > + u8 Enable; /** cfg dev+CLK, SIMO, SOMI pins */ > + u8 CLKOut; /** drive the CLK */ > + u8 CSEnable[8]; /** cfg the associated CS as output */ > + u8 ENAEnable; /** cfg the ENA pin for SPI function */ > + u32 CLKRate; /** default clock rate */ > + u8 Spare[8]; > +}; > + > +struct LCDConfig { > + u8 Enable; > + u8 PanelName[32]; > +}; > + > +struct ENETConfig { > + u32 EnetConfig; > + u8 MACAddr[6]; > + u32 PHYMask; > + u8 Spare[8]; > +}; > + > +#define MCASP_PINMODE_INACTIVE 0 > +#define MCASP_PINMODE_TX 1 > +#define MCASP_PINMODE_RX 2 > + > +struct MCASPConfig { > + u8 Enable; > + u8 Mode; > + u8 PinMode[16]; > +}; > +/** > + * struct tag_peripherals is passed in via kernel ATAG_PERIPHERALS > + */ > +struct tag_peripherals { > + u32 Version; /** == PERIPHERALS_VERSION */ > + u8 Manufacturer[64]; /** null terminated string indicating manufacturer */ > + struct ENETConfig ENETConfig; /** Enable on-board ethernet */ > + struct UARTConfig UARTConfig[3]; /** default UART 0,1,2 Configuration */ > + struct SPIConfig SPIConfig[2]; > + struct LCDConfig LCDConfig; > + struct MCASPConfig MCASPConfig; > +}; > + > +/** > + * This structure can only be grown. You cannot make it smaller... > + */ > +struct MityDSPL138Config { > + u32 ConfigMagicWord; /** == CONFIG_MAGIC_WORD */ > + u32 ConfigVersion; /** version of the configuration block */ > + u32 ConfigSizeBytes; /** configuration size, in bytes */ > + struct tag_peripherals Peripherals; > +}; > + > +struct MityDSPL138ConfigBlock { > + union { > + struct MityDSPL138Config config; > + u8 space[CONFIG_MITYDSP_ENV_SIZE-sizeof(int)]; > + } Data; > + unsigned int CheckSum; /** summed bytes of ConfigSizeBytes */ > +}; > + > +extern struct MityDSPL138Config config_block; > +extern struct I2CFactoryConfig factory_config_block; > +extern int get_config_block(void); > +extern int get_factory_config_block(void); These are not defined in this patch. > + > +#endif > diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h > index 1b31a9a..1989316 100644 > --- a/arch/arm/mach-davinci/include/mach/da8xx.h > +++ b/arch/arm/mach-davinci/include/mach/da8xx.h > @@ -41,6 +41,7 @@ extern void __iomem *da8xx_syscfg1_base; > #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) > #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) > #define DA8XX_JTAG_ID_REG 0x18 > +#define DA8XX_MSTPRI2_REG 0x118 > #define DA8XX_CFGCHIP0_REG 0x17c > #define DA8XX_CFGCHIP2_REG 0x184 > #define DA8XX_CFGCHIP3_REG 0x188 > diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h > index 15a6192..db6f1cd 100644 > --- a/arch/arm/mach-davinci/include/mach/uncompress.h > +++ b/arch/arm/mach-davinci/include/mach/uncompress.h > @@ -88,6 +88,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) > /* DA8xx boards */ > DEBUG_LL_DA8XX(davinci_da830_evm, 2); > DEBUG_LL_DA8XX(davinci_da850_evm, 2); > + DEBUG_LL_DA8XX(mityomapl138, 1); Need to thank Cyril here for making this so simple. Thanks, Sekhar From michael.williamson at criticallink.com Mon Jul 26 07:49:13 2010 From: michael.williamson at criticallink.com (Michael Williamson) Date: Mon, 26 Jul 2010 08:49:13 -0400 Subject: [PATCH v3] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: References: <4C45AE5E.7070905@criticallink.com> Message-ID: <4C4D8449.9040706@criticallink.com> On 7/26/2010 5:29 AM, Nori, Sekhar wrote: > > Hi Michael, > > On Tue, Jul 20, 2010 at 19:40:38, Michael Williamson wrote: >> This patch adds support for the MityDSP-L138 and MityARM-1808 system on >> module (SOM) under the registered machine "mityomapl138". These SOMs >> are based on the da850 davinci CPU architecture. Information on these >> SOMs may be found at http://www.mitydsp.com. >> >> Signed-off-by: Michael Williamson >> --- > > [...] > >> >> arch/arm/configs/da8xx_omapl_defconfig | 291 ++++++-- >> arch/arm/include/asm/setup.h | 5 + >> arch/arm/mach-davinci/Kconfig | 7 + >> arch/arm/mach-davinci/Makefile | 1 + >> arch/arm/mach-davinci/board-mityomapl138.c | 793 ++++++++++++++++++++ >> .../mach-davinci/include/mach/cb-mityomapl138.h | 125 +++ >> arch/arm/mach-davinci/include/mach/da8xx.h | 1 + >> arch/arm/mach-davinci/include/mach/uncompress.h | 1 + >> 8 files changed, 1181 insertions(+), 43 deletions(-) >> > > [...] > >> diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h >> index f392fb4..d6b1a47 100644 >> --- a/arch/arm/include/asm/setup.h >> +++ b/arch/arm/include/asm/setup.h >> @@ -143,6 +143,11 @@ struct tag_memclk { >> __u32 fmemclk; >> }; >> >> +/** MityDSP-L138 peripheral configuration info, >> + * see arch/arm/mach-davinci/include/mach/cb-mityomapl138.h >> + */ >> +#define ATAG_PERIPHERALS 0x42000101 > > Instead of naming this so generic, can you call this ATAG_MITYDSPL138 or > something like that? Yes. I would be glad to rename it, assuming some other approach is not used instead. > > Since passing peripheral configuration from bootloader is a first for > DaVinci, can you please explain why this is the best suited method for this > board and why methods used on other boards wont work? > Well, the problem we are struggling with is that we'd like to avoid generating a pile of separate machine types for the different boards that are needed to support for this common SOM part with regards to the peripheral selection. There are already have 4 different boards with slightly different peripherals already being used with this SOM, and it's a challenge enough just to try to get one configuration through this cycle (which I am new to). We are expecting many more (10's per year). In general, the only real difference on any of these boards will be in regards to peripheral selection/configuration. E.G., using RMII vs. MII, or using different McASP pins or different numbers of channels, or adding a couple of SPI devices on different chip selects, LCD settings, etc. Seems like we shouldn't need to make a whole new machine up to support these kinds of things. This came up in a thread on this mailing list, see http://www.mail-archive.com/davinci-linux-open-source at linux.davincidsp.com/msg17042.html The approach here was pretty much what Kevin suggested as an alternate to trying to port a flat device tree implementation like the powerpc folks use. The only difference was that I didn't think I could jam everything I wanted onto the kernel command line without it getting out of hand, so I am proposing a separate ATAG to provide the peripheral configuration. It's not perfect, but I wanted to get something out there as if it's rejected then we only have a few boards to rewrite code for. Other than device trees, the only other approaches I've seen so far to sort out altering peripheral configuration is: a) Make a new board (a new board file, etc., KConfig option, etc.) b) Start in with a pile of #ifdefs, etc., and add a lot of peripheral on/off options to the KConfig/Make system. That means supporting many variants of kernels for the different host boards, not just an EVM. I'd like to avoid that if I could, as the regression testing for new options might get out of hand. And it didn't seem consistent with making a flexible kernel. c) Allow peripheral drivers to probe and initialize pins, etc. in the modules, then load the right drivers up for your board. There are a lot of threads about why letting drivers mess with the pins is bad. So this is a non-starter. The approach I'm proposing does have the downside of some additional platform code that parses the peripheral configuration at runtime, but from a supportability perspective that's a trade I think users of this module are willing to make. And, it only happens during init. So, if I do it right, I can at least release the memory for the code once it's been run. Are there other approaches than an ATAG? It seems like that's what it was there for. I'll be glad to rework if there is a way to pass up configuration options to allow a single kernel image to at least instantiate the right devices and configure the pins correctly at runtime. I can move the pin configuration to the bootloader, but not the device instantiation. Right? I'd really like to avoid proliferating initialization code (multiple board files) and specific kernel images for this SoM. To be honest, I wanted to just add patches to the 850 EVM code, but as I started into that I immediately ran into piles of #ifdefs that made the code unreadable. Seems like some other architectures have found ways to deal with this. Maybe I am missing something? >> + >> struct tag { >> struct tag_header hdr; >> union { >> diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig >> index 71f90f8..064b0e2 100644 >> --- a/arch/arm/mach-davinci/Kconfig >> +++ b/arch/arm/mach-davinci/Kconfig >> @@ -178,6 +178,13 @@ config DA850_UI_RMII >> >> endchoice >> >> +config MACH_MITYOMAPL138 >> + bool "Critical Link MityOMAPL138 SoM" >> + depends on ARCH_DAVINCI_DA850 >> + select GPIO_PCA953X >> + help >> + Say Y here to select the Critical Link MityOMAP-L138 System on Module. > > Here you can include some pointers on where more information about the > board can be found. OK. Thanks. > >> + >> config MACH_TNETV107X >> bool "TI TNETV107X Reference Platform" >> default ARCH_DAVINCI_TNETV107X >> diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile >> index eab4c0f..dfc0fc4 100644 >> --- a/arch/arm/mach-davinci/Makefile >> +++ b/arch/arm/mach-davinci/Makefile >> @@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o >> obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o >> obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o >> obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o >> +obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o >> obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o >> >> # Power Management >> diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c >> new file mode 100644 >> index 0000000..c8541f1 >> --- /dev/null >> +++ b/arch/arm/mach-davinci/board-mityomapl138.c >> @@ -0,0 +1,793 @@ >> +/* >> + * Critical Link MityOMAP-L138 SoM >> + * >> + * Copyright (C) 2010 Critical Link Incorporated - http://www.criticallink.com >> + * >> + * Derived from board-da850-evm.c >> + * Original Copyrights follow: >> + * >> + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ >> + * >> + * Derived from: arch/arm/mach-davinci/board-da830-evm.c >> + * Original Copyrights follow: >> + * >> + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under >> + * the terms of the GNU General Public License version 2. This program >> + * is licensed "as is" without any warranty of any kind, whether express >> + * or implied. >> + */ >> + >> +#define pr_fmt(fmt) "%s: " fmt, __func__ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include > > You do not seem to have defined platform data for pca953. > > I guess the include here and the config select above are > copy-paste errors? Yes. I will go through the includes and strip out anything not required. Thank you. > >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include > > I didn't see any NOR devices registered? No Parallel NOR, just NAND should be initialized below. If there are extra includes I'll clean them up. Thanks. > >> +#include >> +#include >> +#include >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +static struct tag_peripherals peripheral_config = { >> + .Version = PERIPHERALS_VERSION, >> + .Manufacturer = "Critical Link", >> + .ENETConfig.EnetConfig = ENET_CONFIG_MII, >> + .ENETConfig.MACAddr = { 0x00, 0x50, 0xC2, 0x49, 0xDF, 0xFF }, >> + .UARTConfig[0] = { >> + .Enable = 0, >> + .IsConsole = 0, >> + .Baud = 115200, >> + }, >> + .UARTConfig[1] = { >> + .Enable = 1, >> + .IsConsole = 1, >> + .Baud = 115200, >> + }, >> + .UARTConfig[2] = { >> + .Enable = 0, >> + .IsConsole = 0, >> + .Baud = 115200, >> + }, >> + .SPIConfig[0] = { >> + .Enable = 0, >> + .CLKOut = 0, >> + .CSEnable = { 0, 0, 0, 0, 0, 0, 0, 0}, >> + .ENAEnable = 0, >> + .CLKRate = 0, >> + }, >> + .SPIConfig[1] = { >> + .Enable = 1, >> + .CLKOut = 1, >> + .CSEnable = { 1, 0, 0, 0, 0, 0, 0, 0}, >> + .ENAEnable = 0, >> + .CLKRate = 30000000, >> + }, >> + .LCDConfig = { >> + .Enable = 0, >> + .PanelName = "", >> + } >> +}; > > Do we really need the camel case naming? > Sorry that was company code policy that crept in. I can replace with all lowercase and underscores, correct? > [...] > >> + >> +static __init void mityomapl138_setup_nand(void) >> +{ >> + > > Extra line here.. OK. > >> + platform_add_devices(mityomapl138_devices, >> + ARRAY_SIZE(mityomapl138_devices)); >> +} >> + >> +static int mityomapl138_mmc_get_ro(int index) >> +{ >> + return gpio_get_value(DA850_MMCSD_WP_PIN); >> +} >> + >> +static int mityomapl138_mmc_get_cd(int index) >> +{ >> + return !gpio_get_value(DA850_MMCSD_CD_PIN); >> +} >> + >> +static struct davinci_mmc_config da850_mmc_config = { >> + .get_ro = mityomapl138_mmc_get_ro, >> + .get_cd = mityomapl138_mmc_get_cd, >> + .wires = 4, >> + .max_freq = 50000000, >> + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, >> + .version = MMC_CTLR_VERSION_2, >> +}; >> + >> +static __init void mityomapl138_setup_mmc(void) >> +{ >> + int ret; >> + >> + ret = davinci_cfg_reg_list(da850_mmcsd0_pins); >> + if (ret) >> + pr_warning("mmcsd0 mux setup failed: %d\n" ,ret); >> + >> + ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n"); >> + if (ret) >> + pr_warning("can not open GPIO %d\n", DA850_MMCSD_CD_PIN); >> + gpio_direction_input(DA850_MMCSD_CD_PIN); >> + >> + ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n"); >> + if (ret) >> + pr_warning("can not open GPIO %d\n", DA850_MMCSD_WP_PIN); >> + gpio_direction_input(DA850_MMCSD_WP_PIN); > > Its not nice to go ahead and operate on the GPIO even > though the request call fails. I can see the EVM code does > it this way, but that code needs fixing too. > OK. I will rework not to mess with the IO if I don't get the resource. >> + >> + ret = da8xx_register_mmcsd0(&da850_mmc_config); >> + if (ret) >> + pr_warning("mmcsd0 registration failed: %d\n", ret); >> +} >> + >> + > > Extra line here.. OK > >> +static struct davinci_uart_config mityomapl138_uart_config __initdata = { >> + .enabled_uarts = 0x7, >> +}; >> + >> +static int __init mityomapl138_config_emac(void) >> +{ >> + void __iomem *cfg_chip3_base; >> + int ret; >> + u32 val; >> + struct davinci_soc_info *soc_info = &davinci_soc_info; >> + u8 rmii_en = 0; >> + >> + switch (peripheral_config.ENETConfig.EnetConfig) { >> + case ENET_CONFIG_RMII: >> + soc_info->emac_pdata->rmii_en = 1; >> + rmii_en = 1; >> + break; >> + case ENET_CONFIG_MII: >> + soc_info->emac_pdata->rmii_en = 0; >> + rmii_en = 0; >> + break; >> + case ENET_CONFIG_NONE: >> + default: >> + pr_info("No Ethernet PHY Selected, EMAC disabled\n"); >> + return 0; /* no enet... */ >> + break; >> + } >> + memcpy(&soc_info->emac_pdata->mac_addr[0], >> + &peripheral_config.ENETConfig.MACAddr[0], 6); >> + >> + cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); >> + >> + val = __raw_readl(cfg_chip3_base); >> + >> + if (rmii_en) { >> + val |= BIT(8); >> + ret = davinci_cfg_reg_list(da850_rmii_pins); >> + pr_info("RMII PHY configured, MII PHY will not be functional\n"); >> + } else { >> + val &= ~BIT(8); >> + ret = davinci_cfg_reg_list(da850_cpgmac_pins); >> + pr_info("MII PHY configured, RMII PHY will not be functional\n"); >> + } >> + >> + if (ret) >> + pr_warning("cpgmac/rmii mux setup failed: %d\n", ret); >> + >> + /* configure the CFGCHIP3 register for RMII or MII */ >> + __raw_writel(val, cfg_chip3_base); >> + >> + soc_info->emac_pdata->phy_mask = peripheral_config.ENETConfig.PHYMask ? >> + peripheral_config.ENETConfig.PHYMask : 1; >> + pr_info("setting phy_mask to %x\n", soc_info->emac_pdata->phy_mask); >> + soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY; >> + >> + ret = da8xx_register_emac(); >> + if (ret) >> + pr_warning("emac registration failed: %d\n", ret); >> + >> + return 0; >> +} >> +device_initcall(mityomapl138_config_emac); > > Using device_initcall here is not good. It will get called on other > boards as well just because support for this board is built into > the kernel. So, at a minimum, there should be check to bail out > if machine != mityomapl138. > > Better still, please re-evaluate whether you really need a > device_initcall() here. On the EVM this method was chosen > since the Ethernet init was tied to UI card detection. You > should aim to eliminate it on this board. OK. I will sort this out on the next submission. Thanks. > >> + >> +static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { >> + .bus_freq = 100, /* kHz */ >> + .bus_delay = 0, /* usec */ >> +}; > > This is exactly the pdata that davinci I2C driver uses by default, > so you can save a few bytes and a few lines of code by passing NULL > pdata. > > [...] OK. Thanks. > >> + >> +static struct davinci_spi_platform_data mityomap_spi1_pdata = { >> + .version = SPI_VERSION_2, >> + .num_chipselect = 1, >> + .wdelay = 0, >> + .odd_parity = 0, >> + .parity_enable = 0, >> + .wait_enable = 0, >> + .timer_disable = 0, >> + .clk_internal = 1, >> + .cs_hold = 1, >> + .intr_level = 0, >> + .poll_mode = 1, >> + .use_dma = 0, >> + .c2tdelay = 8, >> + .t2cdelay = 8, >> +}; >> + >> +static struct resource mityomap_spi1_resources[] = { >> + [0] = { >> + .start = 0x01F0E000, >> + .end = 0x01F0EFFF, >> + .flags = IORESOURCE_MEM, >> + }, >> + [1] = { >> + .start = IRQ_DA8XX_SPINT1, >> + .start = IRQ_DA8XX_SPINT1, >> + .flags = IORESOURCE_IRQ, >> + }, >> + [2] = { >> + .start = EDMA_CTLR_CHAN(0, 18), >> + .end = EDMA_CTLR_CHAN(0, 18), >> + .flags = IORESOURCE_DMA, >> + }, >> + [3] = { >> + .start = EDMA_CTLR_CHAN(0, 19), >> + .end = EDMA_CTLR_CHAN(0, 19), >> + .flags = IORESOURCE_DMA, >> + }, >> + [4] = { >> + .start = 1, >> + .end = 1, >> + .flags = IORESOURCE_DMA, >> + }, >> +}; >> + >> +static struct platform_device mityomap_spi1_device = { >> + .name = "spi_davinci", >> + .id = 1, >> + .dev = { >> + .platform_data = &mityomap_spi1_pdata, >> + }, >> + .num_resources = ARRAY_SIZE(mityomap_spi1_resources), >> + .resource = mityomap_spi1_resources, >> +}; >> + >> +/***************************************************************************** >> + * SPI Devices: >> + * SPI1_CS0: 8M Flash ST-M25P64-VME6G >> + ****************************************************************************/ >> +static struct mtd_partition spi_flash_partitions[] = { >> + [0] = { >> + .name = "UBL", >> + .offset = 0, >> + .size = SZ_64K, >> + .mask_flags = MTD_WRITEABLE >> + }, >> + [1] = { >> + .name = "U-Boot", >> + .offset = MTDPART_OFS_APPEND, >> + .size = SZ_512K, >> + .mask_flags = 0, >> + }, >> + [2] = { >> + .name = "Spare", >> + .offset = MTDPART_OFS_APPEND, >> + .size = MTDPART_SIZ_FULL, >> + .mask_flags = 0, >> + }, >> +}; >> + >> +static struct flash_platform_data mityomap_spi_flash_data = { >> + .name = "m25p80", >> + .parts = spi_flash_partitions, >> + .nr_parts = ARRAY_SIZE(spi_flash_partitions), >> + .type = "m25p64", >> +}; >> + >> +static struct spi_board_info mityomap_spi_flash_info[] = { >> + { >> + .modalias = "m25p80", >> + .platform_data = &mityomap_spi_flash_data, >> + .mode = SPI_MODE_0, >> + .max_speed_hz = 30000000, >> + .bus_num = 1, >> + .chip_select = 0, >> + }, >> +}; >> + >> +void __init mityomap_init_spi1(unsigned chipselect_mask, >> + struct spi_board_info *info, unsigned len) >> +{ >> + int ret; >> + ret = platform_device_register(&mityomap_spi1_device); >> + if (ret) >> + pr_warning("failed to register spi device : %d\n", ret); >> + >> + ret = spi_register_board_info(info, len); >> + if (ret) >> + pr_warning("failed to register board info : %d\n", ret); >> +} >> + >> +/* davinci da850 evm audio machine driver */ >> +static u8 da850_iis_serializer_direction[] = { >> + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, >> + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, >> + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, >> + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, >> +}; >> + >> +static struct snd_platform_data mityomapl138_snd_data = { >> + .tx_dma_offset = 0x2000, >> + .rx_dma_offset = 0x2000, >> + .op_mode = DAVINCI_MCASP_IIS_MODE, >> + .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), >> + .tdm_slots = 0, >> + .serial_dir = da850_iis_serializer_direction, >> + .eventq_no = EVENTQ_1, > > This field was recently changed in a patch[1] which is already > queued for ASoC merge for 2.6.36. You will need to base this on that > change. When you do that please note the dependency below the '---' > in the patch so maintainer knows the order in which to commit patches. > > [1] http://git.kernel.org/?p=linux/kernel/git/broonie/sound-2.6.git;a=commit;h=48519f0ae03bc7e86b3dc93e56f1334d53803770 OK. Thanks. > >> + .version = MCASP_VERSION_2, >> + .txnumevt = 0, >> + .rxnumevt = 0, >> +}; >> + >> +short mityomapl138_mcasp_pins[24] __initdata = { >> + DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, >> + DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, >> + DA850_AMUTE, >> + -1, -1, -1, -1, >> + -1, -1, -1, -1, >> + -1, -1, -1, -1, >> + -1, -1, -1, -1, >> + -1 > > Do we really need all these -1s? I think so, because 0 is valid, see next response... > >> +}; >> + >> +static __init int mityomapl138_setup_mcasp(void) >> +{ >> + int ret; >> + >> + mityomapl138_mcasp_pins[7+0] = DA850_AXR_13; >> + da850_iis_serializer_direction[12] = TX_MODE; > > Why not stick these into the static initialization? The intent is to use the peripheral configuration block to set these up. I know it's not in there yet, but I felt that I'd better get that concept approved before I went much further with the code. If the peripheral config design is not acceptable, then all of this code needs to be reworked. We'd like to be able to specify which pins the McASP can use during boot time. I can tear out this init code if it will hold up the patch, but at the moment it is OK with the configurations that use this SoM. > >> + >> + ret = davinci_cfg_reg_list(mityomapl138_mcasp_pins); >> + if (ret) >> + pr_warning("mcasp mux setup failed: %d\n", ret); >> + >> + mityomapl138_snd_data.tdm_slots = 2; >> + mityomapl138_snd_data.txnumevt = 1; > > And the same for these? Same as above. These should be set up based on peripheral config, but I wanted to get concept approved before pushing that in. > >> + >> + da8xx_register_mcasp(0, &mityomapl138_snd_data); >> + >> + return ret; >> +} >> + >> +static const struct display_panel disp_panel = { >> + QVGA, >> + 16, >> + 16, >> + COLOR_ACTIVE, >> +}; >> + >> +static struct lcd_ctrl_config lcd_cfg = { >> + &disp_panel, >> + .ac_bias = 255, >> + .ac_bias_intrpt = 0, >> + .dma_burst_sz = 16, >> + .bpp = 16, >> + .fdd = 255, >> + .tft_alt_mode = 0, >> + .stn_565_mode = 0, >> + .mono_8bit_mode = 0, >> + .invert_line_clock = 0, >> + .invert_frm_clock = 0, >> + .sync_edge = 0, >> + .sync_ctrl = 1, >> + .raster_order = 0, >> +}; >> + >> +static struct da8xx_lcdc_platform_data sharp_lq035q7dh06_pdata = { >> + .manu_name = "sharp", >> + .controller_data = &lcd_cfg, >> + .type = "Sharp_LQ035Q7DH06", >> +}; >> + >> +static struct da8xx_lcdc_platform_data chimei_p0430wqlb_pdata = { >> + .manu_name = "ChiMei", >> + .controller_data = &lcd_cfg, >> + .type = "ChiMei_P0430WQLB", >> +}; >> + >> +static struct da8xx_lcdc_platform_data vga_640x480_pdata = { >> + .manu_name = "VGA", >> + .controller_data = &lcd_cfg, >> + .type = "vga_640x480", >> +}; >> + >> +static struct resource da8xx_lcdc_resources[] = { >> + [0] = { /* registers */ >> + .start = DA8XX_LCD_CNTRL_BASE, >> + .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, >> + .flags = IORESOURCE_MEM, >> + }, >> + [1] = { /* interrupt */ >> + .start = IRQ_DA8XX_LCDINT, >> + .end = IRQ_DA8XX_LCDINT, >> + .flags = IORESOURCE_IRQ, >> + }, >> +}; >> + >> +static struct platform_device da8xx_lcdc_device = { >> + .name = "da8xx_lcdc", >> + .id = 0, >> + .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), >> + .resource = da8xx_lcdc_resources, >> + .dev = { >> + .platform_data = &sharp_lq035q7dh06_pdata, >> + } > > Should have ',' on the last member as well. OK. Thanks. > >> +}; >> + >> +static __init void mityomapl138_setup_lcd(void) >> +{ >> + int ret; >> + >> + if (peripheral_config.LCDConfig.Enable) { >> + u32 prio; >> + >> + /* set peripheral master priority up to 1 */ >> + prio = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_MSTPRI2_REG)); >> + prio &= ~MSTPRI2_LCD_MASK; >> + prio |= 1< > Spaces around binary '<<' OK. Thanks. > >> + __raw_writel(prio, DA8XX_SYSCFG0_VIRT(DA8XX_MSTPRI2_REG)); >> + >> + if (0 == strncmp("Sharp_LQ035Q7DH06", >> + peripheral_config.LCDConfig.PanelName, >> + sizeof(peripheral_config. >> + LCDConfig.PanelName))) { > > Why strncmp instead of just strcmp? Good catch. Was trying to avoid matches to "Sharp" or some other substring. strncmp doesn't really help there. I'll correct. > >> + da8xx_lcdc_device.dev.platform_data = >> + &sharp_lq035q7dh06_pdata; >> + } else if (0 == strncmp("ChiMei_P0430WQLB", >> + peripheral_config.LCDConfig.PanelName, >> + sizeof(peripheral_config.LCDConfig.PanelName))) { >> + da8xx_lcdc_device.dev.platform_data = >> + &chimei_p0430wqlb_pdata; >> + } else if (0 == strncmp("vga_640x480", >> + peripheral_config.LCDConfig.PanelName, >> + sizeof(peripheral_config. >> + LCDConfig.PanelName))) { >> + da8xx_lcdc_device.dev.platform_data = >> + &vga_640x480_pdata; >> + } else { >> + pr_warning("unknown LCD type : %s\n", >> + peripheral_config.LCDConfig.PanelName); >> + return; >> + } >> + >> + ret = davinci_cfg_reg_list(da850_lcdcntl_pins); >> + if (ret) { >> + pr_warning("lcd pinmux failed : %d\n", ret); >> + return; >> + } >> + >> + ret = platform_device_register(&da8xx_lcdc_device); >> + } else { >> + pr_warning("no LCD device enabled\n"); >> + } >> +} >> + >> +static __init void mityomapl138_init(void) >> +{ >> + int ret; >> + >> + ret = pmic_tps65023_init(); >> + if (ret) >> + pr_warning("TPS65023 PMIC init failed: %d\n", ret); >> + >> + ret = da8xx_register_edma(); >> + if (ret) >> + pr_warning("edma registration failed: %d\n", ret); >> + >> + ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); >> + if (ret) >> + pr_warning("i2c0 registration failed: %d\n", ret); >> + >> + ret = da8xx_register_watchdog(); >> + if (ret) >> + pr_warning("watchdog registration failed: %d\n", ret); >> + >> + davinci_serial_init(&mityomapl138_uart_config); >> + >> + ret = da8xx_register_rtc(); >> + if (ret) >> + pr_warning("rtc setup failed: %d\n", ret); >> + >> + ret = da850_register_cpufreq(); >> + if (ret) >> + pr_warning("cpufreq registration failed: %d\n", ret); >> + >> + ret = da8xx_register_cpuidle(); >> + if (ret) >> + pr_warning("cpuidle registration failed: %d\n", ret); >> + >> + mityomapl138_setup_nand(); >> + >> + mityomap_init_spi1(1, mityomap_spi_flash_info, >> + ARRAY_SIZE(mityomap_spi_flash_info)); >> + >> + mityomapl138_setup_lcd(); >> + >> + mityomapl138_setup_mmc(); >> + >> + mityomapl138_setup_mcasp(); >> +} >> + >> +#ifdef CONFIG_SERIAL_8250_CONSOLE >> +static int __init mityomapl138_console_init(void) >> +{ >> + return add_preferred_console("ttyS", 1, "115200"); >> +} >> +console_initcall(mityomapl138_console_init); >> +#endif >> + >> +static void __init mityomapl138_map_io(void) >> +{ >> + da850_init(); >> +} >> + >> +static int __init parse_tag_peripherals(const struct tag *tag) >> +{ >> + struct tag_peripherals *ptag; >> + int i, j; >> + >> + ptag = (struct tag_peripherals *)&tag->u.cmdline.cmdline[0]; >> + memcpy(&peripheral_config, ptag, sizeof(peripheral_config)); >> + pr_info("Peripheral Config Block Found\n"); >> + pr_info("Enet_Config = %d\n", peripheral_config.ENETConfig.EnetConfig); >> + pr_info("EMAC = %pM\n", peripheral_config.ENETConfig.MACAddr); >> + pr_info("PHYMask = 0x%x\n", peripheral_config.ENETConfig.PHYMask); >> + if (peripheral_config.LCDConfig.Enable) >> + pr_info("LCD Configured : %s\n", >> + peripheral_config.LCDConfig.PanelName); >> + else >> + pr_info("No LCD Configured\n"); >> + >> + for (i = 0; i < 3; i++) { >> + pr_info("UART[%d] = %d, %d, %d, %d\n", i, >> + peripheral_config.UARTConfig[i].Enable, >> + peripheral_config.UARTConfig[i].IsConsole, >> + peripheral_config.UARTConfig[i].EnableHWFlowCtrl, >> + peripheral_config.UARTConfig[i].Baud); > > Without explaining what you are printing, this wont be of > much info. You intended this to be debug instead? Even then > it is better to include some information on what is being > dumped. OK. These statements could be assigned to debug level, and I can add more text when they are printed out. Thanks. > >> + } >> + for (i = 0; i < 2; i++) { >> + int mask = 0; >> + for (j = 0; j < 8; j++) >> + mask |= ((peripheral_config.SPIConfig[i].CSEnable[j]) ? >> + (1<> + >> + pr_info("SPI[%d] = %d, %d, %02X, %d, %d\n", i, >> + peripheral_config.SPIConfig[i].Enable, >> + peripheral_config.SPIConfig[i].CLKOut, >> + mask, >> + peripheral_config.SPIConfig[i].ENAEnable, >> + peripheral_config.SPIConfig[i].CLKRate); > > Same here.. Right. > >> + } >> + return 0; >> +} >> +__tagtable(ATAG_PERIPHERALS, parse_tag_peripherals); >> + >> + >> +MACHINE_START(MITYOMAPL138, "MityDSP-L138") >> + .phys_io = IO_PHYS, >> + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, >> + .boot_params = (DA8XX_DDR_BASE + 0x100), >> + .map_io = mityomapl138_map_io, >> + .init_irq = cp_intc_init, >> + .timer = &davinci_timer, >> + .init_machine = mityomapl138_init, >> +MACHINE_END >> diff --git a/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h >> new file mode 100644 >> index 0000000..7ba085a >> --- /dev/null >> +++ b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h >> @@ -0,0 +1,125 @@ >> +/** >> + * Factory / Peripheral Configuration Data as provided by ATAG_PERIPHERAL >> + * for the MityDSP-L138 SOMs. (mityomapl138 machines) >> + * >> + * Copyright (C) 2010 Critical Link LLC. This file is licensed under >> + * the terms of the GNU General Public License version 2. This program >> + * is licensed "as is" without any warranty of any kind, whether express >> + * or implied. >> + */ >> +#ifndef CONFIG_BLOCK_H_ >> +#define CONFIG_BLOCK_H_ > > Copy paste error? This file was originally named "config_block.h" but I renamed it prior to submission to make it specific to the SoM. Missed these. I will correct. Thank you. > >> + >> +#define CONFIG_MAGIC_WORD 0x00BD0138 >> +#define CONFIG_VERSION 0x00010000 >> + >> +#define ENET_CONFIG_NONE 1 >> +#define ENET_CONFIG_MII 2 >> +#define ENET_CONFIG_RMII 3 >> + >> +#define CONFIG_I2C_MAGIC_WORD 0x012C0138 >> +#define CONFIG_I2C_VERSION 0x00010001 >> + >> +/** >> + * Peripherals Version History >> + * 1.00 Baseline >> + * 1.01 Added McASP Configuration >> + * 1.02 Added ethernet phy mask >> + */ >> +#define PERIPHERALS_VERSION 0x00010002 >> + >> +#ifndef CONFIG_MITYDSP_ENV_SIZE >> +#define CONFIG_MITYDSP_ENV_SIZE (64 << 10) >> +#endif >> + >> +#define FPGATYPE_NONE 0 >> +#define FPGATYPE_XC6SLX9 1 >> +#define FPGATYPE_XC6SLX16 2 >> +#define FPGATYPE_XC6SLX25 3 >> +#define FPGATYPE_XC6SLX45 4 >> +#define FPGATYPE_UNKNOWN 10000 >> + >> +struct I2CFactoryConfig { >> + u32 ConfigMagicWord; /** CONFIG_I2C_MAGIC_WORD */ >> + u32 ConfigVersion; /** CONFIG_I2C_VERSION */ >> + u8 MACADDR[6]; /** mac address assigned to part */ >> + u32 FpgaType; /** fpga installed, see above */ >> + u32 Spare; /** Not Used */ >> + u32 SerialNumber; /** serial number of part */ >> + char PartNumber[32]; /** board part number */ >> +}; >> + >> +struct UARTConfig { >> + u8 Enable; /** enable Tx/Rx */ >> + u8 IsConsole; /** cfg as the console */ >> + u8 EnableHWFlowCtrl; /** cfg CTS/RTS */ >> + u32 Baud; /** default baud rate */ >> +}; >> + >> +struct SPIConfig { >> + u8 Enable; /** cfg dev+CLK, SIMO, SOMI pins */ >> + u8 CLKOut; /** drive the CLK */ >> + u8 CSEnable[8]; /** cfg the associated CS as output */ >> + u8 ENAEnable; /** cfg the ENA pin for SPI function */ >> + u32 CLKRate; /** default clock rate */ >> + u8 Spare[8]; >> +}; >> + >> +struct LCDConfig { >> + u8 Enable; >> + u8 PanelName[32]; >> +}; >> + >> +struct ENETConfig { >> + u32 EnetConfig; >> + u8 MACAddr[6]; >> + u32 PHYMask; >> + u8 Spare[8]; >> +}; >> + >> +#define MCASP_PINMODE_INACTIVE 0 >> +#define MCASP_PINMODE_TX 1 >> +#define MCASP_PINMODE_RX 2 >> + >> +struct MCASPConfig { >> + u8 Enable; >> + u8 Mode; >> + u8 PinMode[16]; >> +}; >> +/** >> + * struct tag_peripherals is passed in via kernel ATAG_PERIPHERALS >> + */ >> +struct tag_peripherals { >> + u32 Version; /** == PERIPHERALS_VERSION */ >> + u8 Manufacturer[64]; /** null terminated string indicating manufacturer */ >> + struct ENETConfig ENETConfig; /** Enable on-board ethernet */ >> + struct UARTConfig UARTConfig[3]; /** default UART 0,1,2 Configuration */ >> + struct SPIConfig SPIConfig[2]; >> + struct LCDConfig LCDConfig; >> + struct MCASPConfig MCASPConfig; >> +}; >> + >> +/** >> + * This structure can only be grown. You cannot make it smaller... >> + */ >> +struct MityDSPL138Config { >> + u32 ConfigMagicWord; /** == CONFIG_MAGIC_WORD */ >> + u32 ConfigVersion; /** version of the configuration block */ >> + u32 ConfigSizeBytes; /** configuration size, in bytes */ >> + struct tag_peripherals Peripherals; >> +}; >> + >> +struct MityDSPL138ConfigBlock { >> + union { >> + struct MityDSPL138Config config; >> + u8 space[CONFIG_MITYDSP_ENV_SIZE-sizeof(int)]; >> + } Data; >> + unsigned int CheckSum; /** summed bytes of ConfigSizeBytes */ >> +}; >> + >> +extern struct MityDSPL138Config config_block; >> +extern struct I2CFactoryConfig factory_config_block; >> +extern int get_config_block(void); >> +extern int get_factory_config_block(void); > > These are not defined in this patch. Right. This file is common with our bootloader port, which needs these functions. They should be removed. Good catch. I don't get any warnings on them as no functions in the kernel are looking for them... > >> + >> +#endif >> diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h >> index 1b31a9a..1989316 100644 >> --- a/arch/arm/mach-davinci/include/mach/da8xx.h >> +++ b/arch/arm/mach-davinci/include/mach/da8xx.h >> @@ -41,6 +41,7 @@ extern void __iomem *da8xx_syscfg1_base; >> #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) >> #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) >> #define DA8XX_JTAG_ID_REG 0x18 >> +#define DA8XX_MSTPRI2_REG 0x118 >> #define DA8XX_CFGCHIP0_REG 0x17c >> #define DA8XX_CFGCHIP2_REG 0x184 >> #define DA8XX_CFGCHIP3_REG 0x188 >> diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h >> index 15a6192..db6f1cd 100644 >> --- a/arch/arm/mach-davinci/include/mach/uncompress.h >> +++ b/arch/arm/mach-davinci/include/mach/uncompress.h >> @@ -88,6 +88,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) >> /* DA8xx boards */ >> DEBUG_LL_DA8XX(davinci_da830_evm, 2); >> DEBUG_LL_DA8XX(davinci_da850_evm, 2); >> + DEBUG_LL_DA8XX(mityomapl138, 1); > > Need to thank Cyril here for making this so simple. > > Thanks, > Sekhar > Thanks for the comments. -Mike From lamiaposta71 at gmail.com Mon Jul 26 11:39:20 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Mon, 26 Jul 2010 18:39:20 +0200 Subject: [PATCH v2] DaVinci: dm365: Added clockout2 management. In-Reply-To: References: <1279709510-6213-1-git-send-email-lamiaposta71@gmail.com> Message-ID: 2010/7/22 Nori, Sekhar > Hi Raffaele, > > On Wed, Jul 21, 2010 at 16:21:49, Raffaele Recalcati wrote: > > From: Davide Bonfanti > > > > Clockout2 is added as a child of pll1_sysclk9, because they have > > the same pll divisor. > > Added dm365_clkout2_set_rate to properly set clockout2 frequency. > > > Modified the davinci_set_sysclk_rate function in order > > to get the right ancestor. > > This change should be carved into a separate patch since > it is not directly related to adding clockout2 support. > ok, it will be done > > In the new patch please describe how the existing code isn't > getting the right ancestor. > now it is not more needed. there was a mistake in the call. > > Also, that patch should note below the '---' that it depends > on this patch submitted to the mailing list: > > https://patchwork.kernel.org/patch/112994/ > > This helps maintainer derive the correct order in which patches > need to be applied. > > > > > This patch has been developed against the > > > http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git > > As, mentioned before, this is implied when submitting to > davinci-linux-open-source at linux.davincidsp.com and so can > be removed. If you want to note it, please note below the > '---' in the patch so it wont make it to the commit log. > ok,thx > > git tree and tested on bmx board. > > > > Signed-off-by: Davide Bonfanti > > Signed-off-by: Raffaele Recalcati > > --- > > arch/arm/mach-davinci/clock.c | 32 ++++++++++++---- > > arch/arm/mach-davinci/clock.h | 5 ++ > > arch/arm/mach-davinci/dm365.c | 57 > ++++++++++++++++++++++++++++ > > arch/arm/mach-davinci/include/mach/dm365.h | 1 + > > 4 files changed, 87 insertions(+), 8 deletions(-) > > > > diff --git a/arch/arm/mach-davinci/clock.c > b/arch/arm/mach-davinci/clock.c > > index f29a526..6e45808 100644 > > --- a/arch/arm/mach-davinci/clock.c > > +++ b/arch/arm/mach-davinci/clock.c > > @@ -254,7 +254,15 @@ static unsigned long clk_sysclk_recalc(struct clk > *clk) > > u32 v, plldiv; > > struct pll_data *pll; > > unsigned long rate = clk->rate; > > + struct clk *parent = clk; > > > > + if (clk == NULL || IS_ERR(clk)) > > + return -EINVAL; > > + while (parent->parent->parent) > > + parent = parent->parent; > > + > > + if (parent == clk) > > + return -EPERM; > > It is not clear to me why this change in needed. It is not > described in the patch description as well. Most likely this > needs to be carved into a separate patch as well describing > what is wrong with the existing clk_sysclk_recalc() routine. > now, whith the last check, we don't need that modifications, but only /* Otherwise, the parent must be a PLL */ - if (WARN_ON(!parent->pll_data)) + if (!clk->parent->pll_data) clkout2 is a sub-divider and so its parent is not a pll. > > [...] > > > @@ -293,26 +301,33 @@ int davinci_set_sysclk_rate(struct clk *clk, > unsigned long rate) > > struct pll_data *pll; > > unsigned long input; > > unsigned ratio = 0; > > + struct clk *parent = clk; > > + > > + /* searching the right ancestor (pll1_clk or pll2_clk) */ > > + while (parent->parent->parent) > > + parent = parent->parent; > > + if (parent == clk) > > + return -EPERM; > > As noted above, please carve into separate patch. > ok > > [...] > > > diff --git a/arch/arm/mach-davinci/clock.h > b/arch/arm/mach-davinci/clock.h > > index a717d98..df36d73 100644 > > --- a/arch/arm/mach-davinci/clock.h > > +++ b/arch/arm/mach-davinci/clock.h > > @@ -50,6 +50,11 @@ > > #define PLLDIV_EN BIT(15) > > #define PLLDIV_RATIO_MASK 0x1f > > > > +#define PERI_CLKCTL 0x48 > > +#define CLOCKOUT2EN 2 > > +#define CLOCKOUT1EN 1 > > +#define CLOCKOUT0EN 0 > > + > > /* > > * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN > > * cycles to ensure that the PLLC has switched to bypass mode. Delay of > 1us > > diff --git a/arch/arm/mach-davinci/dm365.c > b/arch/arm/mach-davinci/dm365.c > > index 42fd4a4..902e9a0 100644 > > --- a/arch/arm/mach-davinci/dm365.c > > +++ b/arch/arm/mach-davinci/dm365.c > > @@ -40,6 +40,11 @@ > > #include "mux.h" > > > > #define DM365_REF_FREQ 24000000 /* 24 MHz on the > DM365 EVM */ > > +#define PINMUX0 0x00 > > +#define PINMUX1 0x04 > > +#define PINMUX2 0x08 > > +#define PINMUX3 0x0c > > +#define PINMUX4 0x10 > > Why are PINMUX defines added here? You don't seem to use > these elsewhere in the patch. > deleting ... > > > > > static struct pll_data pll1_data = { > > .num = 1, > > @@ -124,6 +129,7 @@ static struct clk pll1_sysclk6 = { > > .parent = &pll1_clk, > > .flags = CLK_PLL, > > .div_reg = PLLDIV6, > > + .set_rate = davinci_set_sysclk_rate, > > }; > > > > static struct clk pll1_sysclk7 = { > > @@ -145,6 +151,14 @@ static struct clk pll1_sysclk9 = { > > .parent = &pll1_clk, > > .flags = CLK_PLL, > > .div_reg = PLLDIV9, > > + .set_rate = davinci_set_sysclk_rate, > > +}; > > + > > +static struct clk clkout2_clk = { > > + .name = "clkout2", > > + .parent = &pll1_sysclk9, > > + .flags = CLK_PLL, > > + .set_rate = dm365_clkout2_set_rate, > > }; > > > > static struct clk pll2_clk = { > > @@ -421,6 +435,7 @@ static struct clk_lookup dm365_clks[] = { > > CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), > > CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), > > CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), > > + CLK(NULL, "clkout2", &clkout2_clk), > > CLK(NULL, "pll2", &pll2_clk), > > CLK(NULL, "pll2_aux", &pll2_aux_clk), > > CLK(NULL, "clkout1", &clkout1_clk), > > @@ -657,6 +672,48 @@ static struct resource dm365_spi0_resources[] = { > > }, > > }; > > > > +int dm365_clkout2_set_rate(unsigned long rate) > > Is clockout2 specific to DM365? DM355/DM6446 manuals mention > clkout signal as well. If this routine can cater to more SoCs > with simple modifications, you can attempt to generalize it. > we check in dm355 and clkout2 is really a different clock. it seems difficult to integrate. we'd prefer not to do it. > > > +{ > > + int ret = -EINVAL; > > + int i, err, min_err, i_min_err; > > + u32 regval; > > + struct clk *clk; > > + static void __iomem *system_module_base; > > + > > + clk = &clkout2_clk; > > + system_module_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE, SZ_4K); > > + regval = __raw_readl(system_module_base + PERI_CLKCTL); > > This part of the code would make it specific to DM365. May be > the div_reg present in clock structure can be used to pass this > register address from platform file? It will then be a matter of > seeing whether the register bit definitions line up across > platforms. > > You don't have to necessarily test on all platforms as long as > the code is written generically enough. > yes, but again we have not so a deep davinci knowledge to write code without testing it. > > > + > > + /* check all possibilities to get best fitting for the required > freq */ > > + i_min_err = min_err = INT_MAX; > > + for (i = 0x0F; i > 0; i--) { > > + if (clk->parent->set_rate) { > > + ret = clk_set_rate(clk->parent, rate * i) ; > > + err = clk_get_rate(clk->parent) - rate * i; > > + if (min_err > abs(err)) { > > + min_err = abs(err); > > + i_min_err = i; > > + } > > + } > > + } > > Why should the child touch the parent's clock output? Users of the > clock framework should be able to set these rates independently. > right. we tried. the problem is that the clkout2 is used for uda1345 system clock. without chenig the parent we can't get close. the sound is really too fast. > > Can you please check if there is a need to do this even with the > latest patch I posted? In that patch, if the 'maxrate' the sysclk > can support is known, the sysclk rate set code using DIV_ROUND_CLOSEST() > which should give the least error already. > yes. in our application we need to change pll1_sysclk9. we can't find another possibility. an idea should be to "occupy", if possible, the pll1_sysclk9 only for our goal, so other drivers can't discover a wrong clock after our call. > > Thanks, > Sekhar > > Tomorrow, if you agree, I'll send you 2 patches: -patch1: clkout2 -patch2: removing warn from sysclk recalc Please let me know how to proceed. Raffaele -------------- next part -------------- An HTML attachment was scrubbed... URL: From hankm at mtinet.com Mon Jul 26 14:15:25 2010 From: hankm at mtinet.com (Hank Magnuski) Date: Mon, 26 Jul 2010 12:15:25 -0700 (PDT) Subject: Davinci RTC In-Reply-To: References: Message-ID: In rtv-davinci.c there is this piece of code: static inline void davinci_rtcif_wait(struct davinci_rtc *davinci_rtc) { while (davinci_rtcif_read(davinci_rtc, DAVINCI_PRTCIF_CTLR) & DAVINCI_PRTCIF_CTLR_BUSY) cpu_relax(); } If there is any problem with the hardware configuration so that the rtc is not receiving clocking, this wait loop will completely hang the kernel. Is it normal in the kernel to have wait loops with no exits? I would have expected some type of countdown loop with an unconditional exit. Hank From Jon.Povey at racelogic.co.uk Mon Jul 26 22:02:18 2010 From: Jon.Povey at racelogic.co.uk (Jon Povey) Date: Tue, 27 Jul 2010 04:02:18 +0100 Subject: [PATCH v3] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: <4C4D8449.9040706@criticallink.com> Message-ID: <70E876B0EA86DD4BAF101844BC814DFE0903CBE398@Cloud.RL.local> Hi Michael, I am coming up against some similar sounding issues here for supporting multiple hardware configurations. Michael Williamson wrote: > c) Allow peripheral drivers to probe and initialize pins, etc. in the > modules, then load the right drivers up for your board. There are a > lot > of threads about why letting drivers mess with the pins is bad. So > this > is a non-starter. I have one type switch at the moment which I'm intending to do in this way; sensing a gpio pull in a driver. Why is this bad? It doesn't feel too great, but.. not seen any threads about it. If you could point me at these discussions, I'd appreciate it. Thanks, and good luck with your projects, -- Jon Povey jon.povey at racelogic.co.uk Racelogic is a limited company registered in England. Registered number 2743719 . Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB . The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network From lamiaposta71 at gmail.com Tue Jul 27 01:39:04 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Tue, 27 Jul 2010 08:39:04 +0200 Subject: Davinci RTC In-Reply-To: References: Message-ID: 2010/7/26 Hank Magnuski > > In rtv-davinci.c there is this piece of code: > > static inline void davinci_rtcif_wait(struct davinci_rtc *davinci_rtc) > { > while (davinci_rtcif_read(davinci_rtc, DAVINCI_PRTCIF_CTLR) & > DAVINCI_PRTCIF_CTLR_BUSY) > cpu_relax(); > } > > > If there is any problem with the hardware configuration so that the rtc is > not receiving clocking, this wait loop will completely hang the kernel. > > Is it normal in the kernel to have wait loops with no exits? > > I would have expected some type of countdown loop with an unconditional > exit. > > Hank > Hi Hank, in http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git I don't see this call. Where do you find it, please? Raffaele -------------- next part -------------- An HTML attachment was scrubbed... URL: From nsekhar at ti.com Tue Jul 27 03:37:22 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Tue, 27 Jul 2010 14:07:22 +0530 Subject: [PATCH v3] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE0903CBE398@Cloud.RL.local> References: <4C4D8449.9040706@criticallink.com> <70E876B0EA86DD4BAF101844BC814DFE0903CBE398@Cloud.RL.local> Message-ID: Hi Jon, On Tue, Jul 27, 2010 at 08:32:18, Jon Povey wrote: > Hi Michael, > > I am coming up against some similar sounding issues here for supporting multiple hardware configurations. > > Michael Williamson wrote: > > c) Allow peripheral drivers to probe and initialize pins, etc. in the > > modules, then load the right drivers up for your board. There are a > > lot > > of threads about why letting drivers mess with the pins is bad. So > > this > > is a non-starter. > > I have one type switch at the moment which I'm intending to do in this way; sensing a gpio pull in a driver. > > Why is this bad? It doesn't feel too great, but.. not seen any threads about it. If you could point me at these discussions, I'd appreciate it. > In my mind this thread remains the most comprehensive discussion on this topic: http://www.mail-archive.com/davinci-linux-open-source at linux.davincidsp.com/msg11285.html Quoting David Brownell from somewhere in that long thread: " I thought there was pretty much a consensus that drivers should never be directly involved in pinmux. Among other things, it's rare that those details stay the same between different revisions of a given SoC. " Thanks, Sekhar From Jon.Povey at racelogic.co.uk Tue Jul 27 03:45:49 2010 From: Jon.Povey at racelogic.co.uk (Jon Povey) Date: Tue, 27 Jul 2010 09:45:49 +0100 Subject: [PATCH v3] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: Message-ID: <70E876B0EA86DD4BAF101844BC814DFE0903CBE3F2@Cloud.RL.local> Nori, Sekhar wrote: > On Tue, Jul 27, 2010 at 08:32:18, Jon Povey wrote: >> I have one type switch at the moment which I'm intending to do in >> this way; sensing a gpio pull in a driver. >> >> Why is this bad? It doesn't feel too great, but.. not seen any >> threads about it. If you could point me at these discussions, I'd >> appreciate it. >> > > In my mind this thread remains the most comprehensive discussion on > this topic: > > http://www.mail-archive.com/davinci-linux-open-source at linux.davincidsp.com/msg11285.html > > Quoting David Brownell from somewhere in that long thread: > > " > I thought there was pretty much a consensus that drivers > should never be directly involved in pinmux. Among other > things, it's rare that those details stay the same between > different revisions of a given SoC. > " Oh, OK, pinmux. I think my situation is sufficiently different, bespoke, and obscure.. and doesn't mess with pinmuxing. Thanks for the info. -- Jon Povey jon.povey at racelogic.co.uk Racelogic is a limited company registered in England. Registered number 2743719 . Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB . The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network From Jon.Povey at racelogic.co.uk Tue Jul 27 04:38:34 2010 From: Jon.Povey at racelogic.co.uk (Jon Povey) Date: Tue, 27 Jul 2010 10:38:34 +0100 Subject: UBI and subpage writes on DaVinci Message-ID: <70E876B0EA86DD4BAF101844BC814DFE0903CBE41D@Cloud.RL.local> I am getting started with UBI/UBIFS on DM355, things go quite wrong if I use the default options to ubiattach; I have to use the -O 2048 option to force the location of some metadata to a page offset (on 2K page SLC NAND). I can live with this, but - aiui I lose 4KB to UBI metadata per 128K eraseblock, instead of 2K - something is clearly wrong somewhere and should be fixed, either the default 512-byte offset it is trying to use should work, or it should be detecting that it must use the 2048-byte offset. I found this which looks similar, from Caglar Akyuz: http://patchwork.ozlabs.org/patch/50601/ Anyone run into this and know the issues? Any clues welcome. -- Jon Povey jon.povey at racelogic.co.uk Racelogic is a limited company registered in England. Registered number 2743719 . Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB . The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network From jaya.krishnan at samsung.com Tue Jul 27 06:08:17 2010 From: jaya.krishnan at samsung.com (Jaya krishnan) Date: Tue, 27 Jul 2010 11:08:17 +0000 (GMT) Subject: DM6467 McASP Frame Sync Message-ID: <0L67009GHQXTE970@ms1.samsung.com> Hi We have some design issues with interfacing DM6467 McASP to a third party DAC.(CS4353- A paasive DAC with stereo output) We actually tried to replace AIC33 with CS4353. In the board which uses AIC33 , McASP is receiving Serial clk and FS from AIC33. But in our board, we can't provide Serial clk and FS from DAC and hence McASP gives FS to DAC . Serial clock is provided by a CDCE949 clk synthesizer. (I have attached the connection diagram). The problem is , the FS generated by McASP is governed by the follwoing relationship FS= Serial clk/(slot size * No of Slots) I have given serial clk=256KHz, slot size=32, I2S and FS=4KHz. And I get the output quite normally. I am confused in this. 1) How can a data (speech )sampled at 8KHz, 16 bit sample width plays normally at FS= 4KHz? If I change the slot size to 16 bit , FS becomes 8 KHz, and the audio plays at double speed. 2) Why is it like that? Pls help Jayakrishnan M M Research Engineer R&D Team-2 , Group-5 Security Solutions Division SAMSUNG TECHWIN CO.,LTD TEL +82-70-7147-8482 FAX +82-31-8018-3712 Mobile +82-10-6409-3619 E-mail:jaya.krishnan at samsung.com -------------- next part -------------- A non-text attachment was scrubbed... Name: Audio Interface.doc Type: application/octet-stream Size: 30208 bytes Desc: not available URL: From schen at mvista.com Tue Jul 27 07:36:55 2010 From: schen at mvista.com (Steve Chen) Date: Tue, 27 Jul 2010 07:36:55 -0500 Subject: DM6467 McASP Frame Sync In-Reply-To: <0L67009GHQXTE970@ms1.samsung.com> References: <0L67009GHQXTE970@ms1.samsung.com> Message-ID: On Tue, Jul 27, 2010 at 6:08 AM, Jaya krishnan wrote: > > Hi > We have ?some design issues ?with interfacing DM6467 McASP to a ?third party DAC.(CS4353- A paasive DAC with stereo output) > We ?actually ?tried ?to replace AIC33 with CS4353. In the board which uses AIC33 , McASP is receiving Serial clk and FS ?from AIC33. > But in our ?board, we can't provide Serial clk and FS ?from DAC and hence McASP gives ?FS ?to DAC ?. Serial ?clock is provided ?by > a CDCE949 clk synthesizer. (I have attached the ?connection diagram). > The problem is , the FS ?generated by McASP is governed ?by the ?follwoing relationship > FS= Serial clk/(slot size * No of Slots) > I have ?given serial clk=256KHz, slot size=32, I2S ?and FS=4KHz. And I get the output quite ?normally. > I am confused in this. > 1) How can a data ?(speech )sampled ?at 8KHz, 16 bit sample ?width ?plays ?normally at FS= 4KHz? As you point out, at FS=4kHz, serial clock is 256KHz which provide enough cycles to shift out 8Kb/s of data. > If ?I ?change the ?slot size to 16 bit , FS becomes ?8 KHz, and ?the audio plays ?at ?double ?speed. > 2) Why is ?it like that? May want to check out the DMA settings. I suspect DMA engine is still grabbing 32 bits at a time but at double speed. Regards, Steve From hankm at ncast.com Tue Jul 27 08:53:37 2010 From: hankm at ncast.com (Hank Magnuski) Date: Tue, 27 Jul 2010 06:53:37 -0700 (PDT) Subject: Davinci RTC In-Reply-To: References: Message-ID: We are using 2.6.32-rc2 and the file is drivers/rtc/rtc-davinci.c line 137 Hank On Tue, 27 Jul 2010, Raffaele Recalcati wrote: > 2010/7/26 Hank Magnuski > >> >> In rtv-davinci.c there is this piece of code: >> >> static inline void davinci_rtcif_wait(struct davinci_rtc *davinci_rtc) >> { >> while (davinci_rtcif_read(davinci_rtc, DAVINCI_PRTCIF_CTLR) & >> DAVINCI_PRTCIF_CTLR_BUSY) >> cpu_relax(); >> } >> >> >> If there is any problem with the hardware configuration so that the rtc is >> not receiving clocking, this wait loop will completely hang the kernel. >> >> Is it normal in the kernel to have wait loops with no exits? >> >> I would have expected some type of countdown loop with an unconditional >> exit. >> >> Hank >> > > > Hi Hank, > in http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git > I don't see this call. > > Where do you find it, please? > > Raffaele From philipp.schrader at gmail.com Tue Jul 27 13:48:39 2010 From: philipp.schrader at gmail.com (Philipp Schrader) Date: Tue, 27 Jul 2010 14:48:39 -0400 Subject: UBI and subpage writes on DaVinci In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE0903CBE41D@Cloud.RL.local> References: <70E876B0EA86DD4BAF101844BC814DFE0903CBE41D@Cloud.RL.local> Message-ID: On Tue, Jul 27, 2010 at 05:38, Jon Povey wrote: > I am getting started with UBI/UBIFS on DM355, things go quite wrong if I > use the default options to ubiattach; I have to use the -O 2048 option to > force the location of some metadata to a page offset (on 2K page SLC NAND). > > I can live with this, but > > - aiui I lose 4KB to UBI metadata per 128K eraseblock, instead of 2K > > - something is clearly wrong somewhere and should be fixed, either the > default 512-byte offset it is trying to use should work, or it should be > detecting that it must use the 2048-byte offset. > > I found this which looks similar, from Caglar Akyuz: > http://patchwork.ozlabs.org/patch/50601/ > > Anyone run into this and know the issues? > > Any clues welcome. > > I ran into the same issues, and it took me a while to figure out that disabling sub-pages fixes my problems. I can't tell you what exactly is wrong or what needs to be changed, but the UBI section in the MTD FAQ ( http://www.linux-mtd.infradead.org/faq/ubi.html#L_ecc_error) says: "Another possibility is that your flash reports that it supports sub-pages, but does not actually support them properly." Not very helpful, but it is a possibility. -------------- next part -------------- An HTML attachment was scrubbed... URL: From jaya.krishnan at samsung.com Tue Jul 27 21:05:49 2010 From: jaya.krishnan at samsung.com (Jaya krishnan) Date: Wed, 28 Jul 2010 02:05:49 +0000 (GMT) Subject: DM6467 McASP Frame Sync Message-ID: <986359.142091280282748573.JavaMail.weblogic@epv6ml07> Hi Steve, As you said, DMA was tranferring two samples to transmit buffer register when the slot size was configured to 16. When I changed it to one sample (i.e.,16 bit) it worked, and now the FS= 8KHz. Thanks a lot ! Regards JK ------- Original Message ------- Sender : Steve Chen Date : Jul 27, 2010 21:36 (GMT+09:00) Title : Re: DM6467 McASP Frame Sync On Tue, Jul 27, 2010 at 6:08 AM, Jaya krishnan wrote: > > Hi > We have some design issues with interfacing DM6467 McASP to a third party DAC.(CS4353- A paasive DAC with stereo output) > We actually tried to replace AIC33 with CS4353. In the board which uses AIC33 , McASP is receiving Serial clk and FS from AIC33. > But in our board, we can't provide Serial clk and FS from DAC and hence McASP gives FS to DAC . Serial clock is provided by > a CDCE949 clk synthesizer. (I have attached the connection diagram). > The problem is , the FS generated by McASP is governed by the follwoing relationship > FS= Serial clk/(slot size * No of Slots) > I have given serial clk=256KHz, slot size=32, I2S and FS=4KHz. And I get the output quite normally. > I am confused in this. > 1) How can a data (speech )sampled at 8KHz, 16 bit sample width plays normally at FS= 4KHz? As you point out, at FS=4kHz, serial clock is 256KHz which provide enough cycles to shift out 8Kb/s of data. > If I change the slot size to 16 bit , FS becomes 8 KHz, and the audio plays at double speed. > 2) Why is it like that? May want to check out the DMA settings. I suspect DMA engine is still grabbing 32 bits at a time but at double speed. Regards, Steve Jayakrishnan M M Research Engineer R&D Team-2 , Group-5 Security Solutions Division SAMSUNG TECHWIN CO.,LTD TEL +82-70-7147-8482 FAX +82-31-8018-3712 Mobile +82-10-6409-3619 E-mail:jaya.krishnan at samsung.com From michael.williamson at criticallink.com Wed Jul 28 11:02:26 2010 From: michael.williamson at criticallink.com (Michael Williamson) Date: Wed, 28 Jul 2010 12:02:26 -0400 Subject: [PATCH v3] davinci: Add MityDSP-L138/MityARM-1808 SOM support In-Reply-To: References: <4C45AE5E.7070905@criticallink.com> Message-ID: <4C505492.3060404@criticallink.com> On 7/26/2010 5:29 AM, Nori, Sekhar wrote: > > >> + >> +static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { >> + .bus_freq = 100, /* kHz */ >> + .bus_delay = 0, /* usec */ >> +}; > This is exactly the pdata that davinci I2C driver uses by default, > so you can save a few bytes and a few lines of code by passing NULL > pdata. > > [...] > So I tried your suggestion and passed NULL as the pdata argument, e.g., ... ret = da8xx_register_i2c(0, NULL); ... and the kernel locks up during initialization. Did I not understand what you were suggesting? I will back this suggestion out until I get a chance to hunt down the problem. I see no other boards initialize the i2c this way (they explicitly provide a structure). Thanks. -Mike From luna.id at gmail.com Wed Jul 28 14:59:53 2010 From: luna.id at gmail.com (Nicolas Luna) Date: Wed, 28 Jul 2010 15:59:53 -0400 Subject: Boot time Message-ID: Hi guys, I'm trying to make by board boot as quick as possible. I did some optimisation with the "All This For 1 Second Boot" wiki and other website. I would like to reduce a little bit more the boot time and I wonder if you guys could give me some clues. I copied my boot log below. For sure I'll remove the uboot autoboot delay and probably build a new kernel with modules. I putted in bold part that I think it is possible to do more optimisation. 1- See bullet #3. 2- The verifying Checksum is about 400 msec is it possible to skip it? 3- It takes ~1 sec to start booting the kernel and there is a other ~1 sec delay between the starting kernel and the beginning of the uncompressing. Why it's so long? Ok maybe there is the copy from NOR to RAM but it should not take more than few msec. 4- It takes ~1 sec to the kernel to free 120K memory... I got enought RAM is it possible to remove it? I got custom hardware based on OMAP-L138 with FS (jffs2) and compressed kernel in NOR Flash. Thanks a lot Nicolas ------------------------------------------------------------------------------------- 0.000 0.000: OMAP-L138 initialization passed! 0.000 0.000: Booting TI User Boot Loader 0.004 0.004: UBL Version: 1.65 0.004 0.000: UBL Flashtype: NOR 0.008 0.004: Starting NOR Copy... 0.008 0.000: CFI Query...passed. 0.012 0.004: NOR Initialization: 0.012 0.000: Command Set: Intel 0.012 0.000: Manufacturer: INTEL 0.016 0.004: Size: 0x00000020 MB 0.020 0.004: Valid magicnum, 0x55424CBB, found.. 0.184 0.164: DONE 0.188 0.004: Jumping to entry point at 0xC1080000. 0.504 0.316: 1.548 1.044: Hit any key to stop autoboot: 0 *2.372 0.824: ## Booting kernel from Legacy Image at c0007fc0 ...* 2.372 0.000: Image Name: Linux-2.6.34 2.380 0.008: Image Type: ARM Linux Kernel Image (uncompressed) 2.380 0.000: Data Size: 1505956 Bytes = 1.4 MB 2.384 0.004: Load Address: c0008000 2.388 0.004: Entry Point: c0008000 *2.808 0.420: Verifying Checksum ... OK* 2.808 0.000: Loading Kernel Image ... OK 2.808 0.000: OK 2.808 0.000: *2.812 0.004: Starting kernel ...* *2.812 0.000:* *3.860 1.048: Uncompressing Linux... done, booting the kernel.* 4.264 0.404: Linux version 2.6.34 (id at idt-ubuntu-linux) (gcc version 4.3.3 (Sourcery G++ Lite 2009q1-203) ) #89 PREEMPT Thu Jul 22 15:24:03 EDT 2010 4.268 0.004: CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177 4.272 0.004: CPU: VIVT data cache, VIVT instruction cache 4.276 0.004: Machine: DaVinci DA850/OMAP-L138 EVM 4.280 0.004: Memory policy: ECC disabled, Data cache writeback 4.284 0.004: DaVinci da850/omap-l138 variant 0x0 4.288 0.004: Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 4.300 0.012: Kernel command line: lpj=747520 mem=128M console=ttyS2,115200n8 root=/dev/mtdblock2 rootfstype=jffs2 rw ip=off 4.304 0.004: PID hash table entries: 512 (order: -1, 2048 bytes) 4.308 0.004: Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) 4.316 0.008: Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) 4.316 0.000: Memory: 128MB = 128MB total 4.324 0.008: Memory: 126752k/126752k available, 4320k reserved, 0K highmem 4.324 0.000: Virtual kernel memory layout: 4.332 0.008: vector : 0xffff0000 - 0xffff1000 ( 4 kB) 4.336 0.004: fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) 4.340 0.004: DMA : 0xff000000 - 0xffe00000 ( 14 MB) 4.344 0.004: vmalloc : 0xc8800000 - 0xfea00000 ( 866 MB) 4.348 0.004: lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) 4.352 0.004: modules : 0xbf000000 - 0xc0000000 ( 16 MB) 4.356 0.004: .init : 0xc0008000 - 0xc0026000 ( 120 kB) 4.360 0.004: .text : 0xc0026000 - 0xc02e8000 (2824 kB) 4.364 0.004: .data : 0xc02e8000 - 0xc0307a60 ( 127 kB) 4.372 0.008: SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 4.376 0.004: Hierarchical RCU implementation. 4.376 0.000: NR_IRQS:245 4.380 0.004: Console: colour dummy device 80x30 4.384 0.004: Calibrating delay loop (skipped) preset value.. 149.50 BogoMIPS (lpj=747520) 4.388 0.004: Mount-cache hash table entries: 512 4.392 0.004: CPU: Testing write buffer coherency: ok 4.396 0.004: DaVinci: 144 gpio irqs 4.396 0.000: NET: Registered protocol family 16 4.400 0.004: bio: create slab at 0 4.404 0.004: SCSI subsystem initialized 4.408 0.004: usbcore: registered new interface driver usbfs 4.412 0.004: usbcore: registered new interface driver hub 4.416 0.004: usbcore: registered new device driver usb 4.416 0.000: Switching to clocksource timer0_1 4.420 0.004: musb_hdrc: version 6.0, pio, host, debug=0 4.424 0.004: Waiting for USB PHY clock good... 4.428 0.004: musb_hdrc musb_hdrc: MUSB HDRC host driver 4.432 0.004: musb_hdrc musb_hdrc: new USB bus registered, assigned bus number 1 4.436 0.004: hub 1-0:1.0: USB hub found 4.440 0.004: hub 1-0:1.0: 1 port detected 4.444 0.004: musb_hdrc musb_hdrc: USB Host mode controller at fee00000 using PIO, IRQ 58 4.448 0.004: NET: Registered protocol family 2 4.456 0.008: IP route cache hash table entries: 1024 (order: 0, 4096 bytes) 4.460 0.004: TCP established hash table entries: 4096 (order: 3, 32768 bytes) 4.464 0.004: TCP bind hash table entries: 4096 (order: 2, 16384 bytes) 4.468 0.004: TCP: Hash tables configured (established 4096 bind 4096) 4.472 0.004: TCP reno registered 4.476 0.004: UDP hash table entries: 256 (order: 0, 4096 bytes) 4.480 0.004: UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) 4.484 0.004: NET: Registered protocol family 1 4.488 0.004: RPC: Registered udp transport module. 4.492 0.004: RPC: Registered tcp transport module. 4.496 0.004: RPC: Registered tcp NFSv4.1 backchannel transport module. 4.500 0.004: JFFS2 version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc. 4.504 0.004: msgmni has been set to 247 4.508 0.004: io scheduler noop registered (default) 4.512 0.004: da8xx_lcdc da8xx_lcdc.0: GLCD: Found Sharp_LK043T1DG01 panel 4.516 0.004: Console: switching to colour frame buffer device 60x34 4.520 0.004: Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled 4.528 0.008: serial8250.0: ttyS0 at MMIO 0x1c42000 (irq = 25) is a 16550A 4.532 0.004: serial8250.0: ttyS1 at MMIO 0x1d0c000 (irq = 53) is a 16550A 4.540 0.008: serial8250.0: ttyS2 at MMIO 0x1d0d000 (irq = 61) is a 16550A 4.540 0.000: console [ttyS2] enabled 4.548 0.008: brd: module loaded 4.556 0.008: physmap platform flash device: 02000000 at 60000000 4.564 0.008: physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank 4.568 0.004: Intel/Sharp Extended Query Table at 0x010A 4.572 0.004: Intel/Sharp Extended Query Table at 0x010A 4.576 0.004: Intel/Sharp Extended Query Table at 0x010A 4.580 0.004: Intel/Sharp Extended Query Table at 0x010A 4.584 0.004: Intel/Sharp Extended Query Table at 0x010A 4.588 0.004: Using buffer write method 4.588 0.000: Using auto-unlock on power-up/resume 4.592 0.004: cfi_cmdset_0001: Erase suspend on write enabled 4.596 0.004: RedBoot partition parsing not available 4.600 0.004: Using physmap partition information 4.604 0.004: Creating 3 MTD partitions on "physmap-flash.0": 4.608 0.004: 0x000000000000-0x000000080000 : "bootloaders + env" 4.620 0.012: 0x000000080000-0x000000280000 : "kernel" 4.628 0.008: 0x000000280000-0x000002000000 : "filesystem" 4.636 0.008: physmap-flash.0: failed to claim resource 0 4.644 0.008: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron NAND 512MiB 3,3V 8-bit) 4.652 0.008: Creating 2 MTD partitions on "davinci_nand.1": 4.656 0.004: 0x000000000000-0x000001900000 : "data" 4.664 0.008: 0x000001900000-0x000020000000 : "else" 4.672 0.008: davinci_nand davinci_nand.1: controller rev. 2.5 4.680 0.008: spi_davinci spi_davinci.1: Controller at 0xfef0e000 4.692 0.012: tun: Universal TUN/TAP device driver, 1.6 4.696 0.004: tun: (C) 1999-2004 Max Krasnyansky 4.704 0.008: ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver 4.708 0.004: ohci ohci.0: DA8xx OHCI 4.712 0.004: ohci ohci.0: new USB bus registered, assigned bus number 2 4.716 0.004: Waiting for USB PHY clock good... 4.720 0.004: ohci ohci.0: irq 59, io mem 0x01e25000 4.788 0.068: hub 2-0:1.0: USB hub found 4.788 0.000: hub 2-0:1.0: 1 port detected 4.796 0.008: Initializing USB Mass Storage driver... 4.804 0.008: usbcore: registered new interface driver usb-storage 4.804 0.000: USB Mass Storage support registered. 5.804 1.000: i2c_davinci i2c_davinci.1: controller timed out 5.808 0.004: i2c_davinci i2c_davinci.1: initiating i2c bus recovery 5.812 0.004: tps6507x-ts: probe of tps6507x-ts failed with error -110 5.820 0.008: omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc0 5.824 0.004: omap_rtc: RTC power up reset detected 5.824 0.000: omap_rtc: already running 5.828 0.004: i2c /dev entries driver 5.832 0.004: TCP cubic registered 5.836 0.004: Clocks: disable unused i2c1 5.840 0.004: Clocks: disable unused emac 5.848 0.008: davinci_emac_probe: using random MAC addr: 72:93:72:ad:15:13 5.852 0.004: emac-mii: probed 5.860 0.008: omap_rtc omap_rtc: setting system clock to 2000-01-01 01:34:03 UTC (946690443) 6.136 0.276: VFS: Mounted root (jffs2 filesystem) on device 31:2. *6.140 0.004: Freeing init memory: 120K* *7.356 1.216: Mounting proc* -------------- next part -------------- An HTML attachment was scrubbed... URL: From luna.id at gmail.com Wed Jul 28 15:46:16 2010 From: luna.id at gmail.com (Nicolas Luna) Date: Wed, 28 Jul 2010 16:46:16 -0400 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: <1276114677.21486.872.camel@sax-lx> References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> Message-ID: Todd, What do I need to change if I want to use the bitbang i2c driver and stop to get those error messages. I added support for "GPIO-based bitbaging I2C" into the kernel, anything else to change in the TPS driver source code? Thanks Regards, Nicolas On Wed, Jun 9, 2010 at 4:17 PM, Todd Fischer wrote: > HI Bastian and Nicolas, > > I recall getting this error when I wasn't using the bitbang i2c driver on > the OMAP-L138. > > Todd > > > On Wed, 2010-06-09 at 10:59 +0200, Bastian Ruppert wrote: > > Hello Nicolas, > > thanks for the .conf file. > > > this will help you to check if your hardware is ok. > > It helped. > > I applied your file on the khilman commit you are using but i had to patch > the kernel in order to > compile drivers/mfd/tps6507x.c . I think if you don`t have the same > problems, that is anomalous. > > After that the touchscreen driver is running on that kernel. It`s a little > bit unstable, there are sometimes errors like > > tps6507x 1-0048: TSC mode read failed > i2c_davinci i2c_davinci.1: controller timed out > i2c_davinci i2c_davinci.1: initiating i2c bus recovery > i2c_davinci i2c_davinci.1: controller timed out > i2c_davinci i2c_davinci.1: initiating i2c bus recovery > > but the hardware can in principle do it. > > Regards, > > Bastian. > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.comhttp://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From todd.fischer at ridgerun.com Wed Jul 28 15:51:20 2010 From: todd.fischer at ridgerun.com (Todd Fischer) Date: Wed, 28 Jul 2010 14:51:20 -0600 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> Message-ID: <1280350280.20670.15378.camel@sax-lx> On Wed, 2010-07-28 at 16:46 -0400, Nicolas Luna wrote: > Todd, > > > > What do I need to change if I want to use the bitbang i2c driver and > stop to get those error messages. > > > I added support for "GPIO-based bitbaging I2C" into the kernel, > anything else to change in the TPS driver source code? You need to modify the arm/arch/mach-davinci board file to configure the pinmux as GPIOs, not I2C signaling. Which hardware board are you using? > > > Thanks > > > Regards, > > > Nicolas > > > > > On Wed, Jun 9, 2010 at 4:17 PM, Todd Fischer > wrote: > > HI Bastian and Nicolas, > > I recall getting this error when I wasn't using the bitbang > i2c driver on the OMAP-L138. > > Todd > > > > > On Wed, 2010-06-09 at 10:59 +0200, Bastian Ruppert wrote: > > > > > Hello Nicolas, > > > > thanks for the .conf file. > > > > > this will help you to check if your hardware is ok. > > > > It helped. > > > > I applied your file on the khilman commit you are using but > > i had to patch the kernel in order to > > compile drivers/mfd/tps6507x.c . I think if you don`t have > > the same problems, that is anomalous. > > > > After that the touchscreen driver is running on that kernel. > > It`s a little bit unstable, there are sometimes errors like > > > > tps6507x 1-0048: TSC mode read failed > > i2c_davinci i2c_davinci.1: controller timed out > > i2c_davinci i2c_davinci.1: initiating i2c bus recovery > > i2c_davinci i2c_davinci.1: controller timed out > > i2c_davinci i2c_davinci.1: initiating i2c bus recovery > > > > but the hardware can in principle do it. > > > > Regards, > > > > Bastian. > > > > _______________________________________________ > > Davinci-linux-open-source mailing list > > > > Davinci-linux-open-source at linux.davincidsp.com > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From luna.id at gmail.com Wed Jul 28 16:08:51 2010 From: luna.id at gmail.com (Nicolas Luna) Date: Wed, 28 Jul 2010 17:08:51 -0400 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: <1280350280.20670.15378.camel@sax-lx> References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> <1280350280.20670.15378.camel@sax-lx> Message-ID: board-da850-evm.c Nicolas On Wed, Jul 28, 2010 at 4:51 PM, Todd Fischer wrote: > On Wed, 2010-07-28 at 16:46 -0400, Nicolas Luna wrote: > > Todd, > > > > What do I need to change if I want to use the bitbang i2c driver and stop > to get those error messages. > > > > I added support for "GPIO-based bitbaging I2C" into the kernel, anything > else to change in the TPS driver source code? > > > You need to modify the arm/arch/mach-davinci board file to configure the > pinmux as GPIOs, not I2C signaling. > > Which hardware board are you using? > > > > > Thanks > > > > Regards, > > > > Nicolas > > > > On Wed, Jun 9, 2010 at 4:17 PM, Todd Fischer > wrote: > > HI Bastian and Nicolas, > > I recall getting this error when I wasn't using the bitbang i2c driver on > the OMAP-L138. > > Todd > > > > > On Wed, 2010-06-09 at 10:59 +0200, Bastian Ruppert wrote: > > > Hello Nicolas, > > thanks for the .conf file. > > > this will help you to check if your hardware is ok. > > It helped. > > I applied your file on the khilman commit you are using but i had to patch > the kernel in order to > compile drivers/mfd/tps6507x.c . I think if you don`t have the same > problems, that is anomalous. > > After that the touchscreen driver is running on that kernel. It`s a little > bit unstable, there are sometimes errors like > > tps6507x 1-0048: TSC mode read failed > i2c_davinci i2c_davinci.1: controller timed out > i2c_davinci i2c_davinci.1: initiating i2c bus recovery > i2c_davinci i2c_davinci.1: controller timed out > i2c_davinci i2c_davinci.1: initiating i2c bus recovery > > but the hardware can in principle do it. > > Regards, > > Bastian. > > _______________________________________________ > Davinci-linux-open-source mailing list > > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From luna.id at gmail.com Wed Jul 28 16:18:23 2010 From: luna.id at gmail.com (Nicolas Luna) Date: Wed, 28 Jul 2010 17:18:23 -0400 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> <1280350280.20670.15378.camel@sax-lx> Message-ID: I changed MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) to MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 8, false) MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 8, false) seems to have the same behaviour.. Nicolas On Wed, Jul 28, 2010 at 5:08 PM, Nicolas Luna wrote: > board-da850-evm.c > > Nicolas > > > > > On Wed, Jul 28, 2010 at 4:51 PM, Todd Fischer wrote: > >> On Wed, 2010-07-28 at 16:46 -0400, Nicolas Luna wrote: >> >> Todd, >> >> >> >> What do I need to change if I want to use the bitbang i2c driver and >> stop to get those error messages. >> >> >> >> I added support for "GPIO-based bitbaging I2C" into the kernel, anything >> else to change in the TPS driver source code? >> >> >> You need to modify the arm/arch/mach-davinci board file to configure the >> pinmux as GPIOs, not I2C signaling. >> >> Which hardware board are you using? >> >> >> >> >> Thanks >> >> >> >> Regards, >> >> >> >> Nicolas >> >> >> >> On Wed, Jun 9, 2010 at 4:17 PM, Todd Fischer >> wrote: >> >> HI Bastian and Nicolas, >> >> I recall getting this error when I wasn't using the bitbang i2c driver on >> the OMAP-L138. >> >> Todd >> >> >> >> >> On Wed, 2010-06-09 at 10:59 +0200, Bastian Ruppert wrote: >> >> >> Hello Nicolas, >> >> thanks for the .conf file. >> >> > this will help you to check if your hardware is ok. >> >> It helped. >> >> I applied your file on the khilman commit you are using but i had to patch >> the kernel in order to >> compile drivers/mfd/tps6507x.c . I think if you don`t have the same >> problems, that is anomalous. >> >> After that the touchscreen driver is running on that kernel. It`s a little >> bit unstable, there are sometimes errors like >> >> tps6507x 1-0048: TSC mode read failed >> i2c_davinci i2c_davinci.1: controller timed out >> i2c_davinci i2c_davinci.1: initiating i2c bus recovery >> i2c_davinci i2c_davinci.1: controller timed out >> i2c_davinci i2c_davinci.1: initiating i2c bus recovery >> >> but the hardware can in principle do it. >> >> Regards, >> >> Bastian. >> >> _______________________________________________ >> Davinci-linux-open-source mailing list >> >> Davinci-linux-open-source at linux.davincidsp.com >> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source >> >> >> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From luna.id at gmail.com Wed Jul 28 16:44:52 2010 From: luna.id at gmail.com (Nicolas Luna) Date: Wed, 28 Jul 2010 17:44:52 -0400 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> <1280350280.20670.15378.camel@sax-lx> Message-ID: Oh I did'nt loaded the right kernel, my fault... Well now it's not working at all, I got this error " *QWSTslibMouseHandlerPrivate: ts_open() failed with error: 'No such file or directory' " *and no more /dev/input/touchscreen0 detected by udev. Any clues? Regards, Nicolas On Wed, Jul 28, 2010 at 5:18 PM, Nicolas Luna wrote: > I changed > > MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) > MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) > > to > > MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 8, false) > MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 8, false) > > seems to have the same behaviour.. > > Nicolas > > > > > On Wed, Jul 28, 2010 at 5:08 PM, Nicolas Luna wrote: > >> board-da850-evm.c >> >> Nicolas >> >> >> >> >> On Wed, Jul 28, 2010 at 4:51 PM, Todd Fischer wrote: >> >>> On Wed, 2010-07-28 at 16:46 -0400, Nicolas Luna wrote: >>> >>> Todd, >>> >>> >>> >>> What do I need to change if I want to use the bitbang i2c driver and >>> stop to get those error messages. >>> >>> >>> >>> I added support for "GPIO-based bitbaging I2C" into the kernel, >>> anything else to change in the TPS driver source code? >>> >>> >>> You need to modify the arm/arch/mach-davinci board file to configure the >>> pinmux as GPIOs, not I2C signaling. >>> >>> Which hardware board are you using? >>> >>> >>> >>> >>> Thanks >>> >>> >>> >>> Regards, >>> >>> >>> >>> Nicolas >>> >>> >>> >>> On Wed, Jun 9, 2010 at 4:17 PM, Todd Fischer >>> wrote: >>> >>> HI Bastian and Nicolas, >>> >>> I recall getting this error when I wasn't using the bitbang i2c driver on >>> the OMAP-L138. >>> >>> Todd >>> >>> >>> >>> >>> On Wed, 2010-06-09 at 10:59 +0200, Bastian Ruppert wrote: >>> >>> >>> Hello Nicolas, >>> >>> thanks for the .conf file. >>> >>> > this will help you to check if your hardware is ok. >>> >>> It helped. >>> >>> I applied your file on the khilman commit you are using but i had to >>> patch the kernel in order to >>> compile drivers/mfd/tps6507x.c . I think if you don`t have the same >>> problems, that is anomalous. >>> >>> After that the touchscreen driver is running on that kernel. It`s a >>> little bit unstable, there are sometimes errors like >>> >>> tps6507x 1-0048: TSC mode read failed >>> i2c_davinci i2c_davinci.1: controller timed out >>> i2c_davinci i2c_davinci.1: initiating i2c bus recovery >>> i2c_davinci i2c_davinci.1: controller timed out >>> i2c_davinci i2c_davinci.1: initiating i2c bus recovery >>> >>> but the hardware can in principle do it. >>> >>> Regards, >>> >>> Bastian. >>> >>> _______________________________________________ >>> Davinci-linux-open-source mailing list >>> >>> Davinci-linux-open-source at linux.davincidsp.com >>> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source >>> >>> >>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From bniebuhr3 at gmail.com Wed Jul 28 17:18:09 2010 From: bniebuhr3 at gmail.com (Brian Niebuhr) Date: Wed, 28 Jul 2010 17:18:09 -0500 Subject: [PATCH v5 0/1] davinci: spi: replace existing driver Message-ID: <1280355490-11878-1-git-send-email-bniebuhr@efjohnson.com> Fixed in this version: - Addressed all comments from the previous version ** NOTE ** This patch requires the EDMA patch at: http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-March/018022.html which is queued waiting on another driver fix, for DMA mode to work correctly. Brian Niebuhr (1): davinci: spi: replace existing driver arch/arm/mach-davinci/board-dm355-evm.c | 10 + arch/arm/mach-davinci/board-dm355-leopard.c | 10 + arch/arm/mach-davinci/board-dm365-evm.c | 10 + arch/arm/mach-davinci/dm355.c | 8 +- arch/arm/mach-davinci/dm365.c | 6 - arch/arm/mach-davinci/include/mach/spi.h | 35 +- drivers/spi/davinci_spi.c | 1098 ++++++++++++--------------- 7 files changed, 521 insertions(+), 656 deletions(-) From bniebuhr3 at gmail.com Wed Jul 28 17:18:10 2010 From: bniebuhr3 at gmail.com (Brian Niebuhr) Date: Wed, 28 Jul 2010 17:18:10 -0500 Subject: [PATCH v5 1/1] davinci: spi: replace existing driver In-Reply-To: <1280355490-11878-1-git-send-email-bniebuhr@efjohnson.com> References: <1280355490-11878-1-git-send-email-bniebuhr@efjohnson.com> Message-ID: <1280355490-11878-2-git-send-email-bniebuhr@efjohnson.com> INTRODUCTION I have been working on a custom OMAP-L138 board that has multiple spi devices (seven) on one controller. These devices have a wide range of transfer parameters (speed, phase, polarity, internal and gpio chip selects). During my testing I found multiple errors in the davinci spi driver as a result of this complex setup. The primary issues were: 1. There is a race condition due to the SPIBUF read busy-waits for slow devices 2. I found some DMA transfer length errors under some conditions 3. The chip select code caused extra byte transfers (with no chip select active) due to writes to SPIDAT1 4. Several issues prevented using multiple SPI devices, especially the DMA code, as disucussed previously on the davinci list. The fixes to these problems were not simple. I ended up making fairly large changes to the driver, and those changes are contained in these patches. The full list of changes follows. CHANGE LIST 1. davinci_spi_chipelect() now performs both activation and deactivation of chip selects. This lets spi_bitbang fully control chip select activation, as intended by the SPI API. 2. Chip select activation does not cause extra writes to the SPI bus 3. Chip select activation does not use SPIDEF for control. This change will also allow for implementation of inverted (active high) chip selects in the future. 4. Added back gpio chip select capability from the old driver 5. Fixed prescale calculation for non-integer fractions of spi clock 6. Allow specification of SPI transfer parameters on a per-device (instead of per-controller) basis 7. Allow specification of polled, interrupt-based, or DMA operation on a per-device basis 8. Allow DMA with when more than one device is connected 9. Combined pio and dma txrx_bufs functions into one since they share large parts of their functionality, and to simplify item (8). 10. Use only SPIFMT0 to allow more than 4 devices TESTING I have tested the driver using a custom SPI stress test on my OMAP-L138-based board with three devices connected. I have tested configurations with all three devices polled, all three interrupt-based, all three DMA, and a mixture. I have compiled with the davinci_all_defconfig, but I don't have EVMs for the other davinci platforms to test with. Signed-off-by: Brian Niebuhr --- arch/arm/mach-davinci/board-dm355-evm.c | 10 + arch/arm/mach-davinci/board-dm355-leopard.c | 10 + arch/arm/mach-davinci/board-dm365-evm.c | 10 + arch/arm/mach-davinci/dm355.c | 8 +- arch/arm/mach-davinci/dm365.c | 6 - arch/arm/mach-davinci/include/mach/spi.h | 35 +- drivers/spi/davinci_spi.c | 1098 ++++++++++++--------------- 7 files changed, 521 insertions(+), 656 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index a319101..ad8779b 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -32,6 +32,7 @@ #include #include #include +#include /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you @@ -300,10 +301,19 @@ static struct spi_eeprom at25640a = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640a_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm355_evm_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640a, + .controller_data = &at25640a_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index f1d8132..b2d8d48 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -29,6 +29,7 @@ #include #include #include +#include /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you @@ -222,10 +223,19 @@ static struct spi_eeprom at25640a = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640a_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm355_leopard_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640a, + .controller_data = &at25640a_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 5bb86b2..db85372 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -39,6 +39,7 @@ #include #include #include +#include #include @@ -579,10 +580,19 @@ static struct spi_eeprom at25640 = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm365_evm_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640, + .controller_data = &at25640_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 3834781..b79b798 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -410,14 +410,8 @@ static struct resource dm355_spi0_resources[] = { }; static struct davinci_spi_platform_data dm355_spi0_pdata = { - .version = SPI_VERSION_1, + .version = SPI_VERSION_0, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, }; static struct platform_device dm355_spi0_device = { .name = "spi_davinci", diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 652f4b6..4aea346 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); static struct davinci_spi_platform_data dm365_spi0_pdata = { .version = SPI_VERSION_1, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, }; static struct resource dm365_spi0_resources[] = { diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h index 910efbf..3f77dab 100644 --- a/arch/arm/mach-davinci/include/mach/spi.h +++ b/arch/arm/mach-davinci/include/mach/spi.h @@ -19,26 +19,35 @@ #ifndef __ARCH_ARM_DAVINCI_SPI_H #define __ARCH_ARM_DAVINCI_SPI_H +#define SPI_INTERN_CS 0xFF + enum { - SPI_VERSION_1, /* For DM355/DM365/DM6467 */ + SPI_VERSION_0, /* For DM355 (reduced features, no Tx interrupt) */ + SPI_VERSION_1, /* For DM365/DM6467 (reduced features) */ SPI_VERSION_2, /* For DA8xx */ }; struct davinci_spi_platform_data { u8 version; - u8 num_chipselect; - u8 wdelay; - u8 odd_parity; - u8 parity_enable; - u8 wait_enable; - u8 timer_disable; - u8 clk_internal; - u8 cs_hold; + u16 num_chipselect; + u8 *chip_sel; +}; + +struct davinci_spi_config { + bool odd_parity; + bool parity_enable; u8 intr_level; - u8 poll_mode; - u8 use_dma; - u8 c2tdelay; - u8 t2cdelay; + u8 io_type; +#define SPI_IO_TYPE_INTR 0 +#define SPI_IO_TYPE_POLL 1 +#define SPI_IO_TYPE_DMA 2 + u8 bytes_per_word; + u8 wdelay; + bool timer_disable; + u8 c2t_delay; + u8 t2c_delay; + u8 t2e_delay; + u8 c2e_delay; }; #endif /* __ARCH_ARM_DAVINCI_SPI_H */ diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index b85090c..5c9e9ce 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2009 Texas Instruments. + * Copyright (C) 2010 EF Johnson Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,21 +28,19 @@ #include #include #include -#include #include #include #define SPI_NO_RESOURCE ((resource_size_t)-1) -#define SPI_MAX_CHIPSELECT 2 - #define CS_DEFAULT 0xFF #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 + +#define RX_DMA_INDEX 0 +#define TX_DMA_INDEX 1 +#define EVENTQ_DMA_INDEX 2 #define SPIFMT_PHASE_MASK BIT(16) #define SPIFMT_POLARITY_MASK BIT(17) @@ -53,9 +52,11 @@ #define SPIFMT_WDELAY_MASK 0x3f000000u #define SPIFMT_WDELAY_SHIFT 24 #define SPIFMT_CHARLEN_MASK 0x0000001Fu +#define SPIFMT_PRESCALE_SHIFT 8 /* SPIGCR1 */ -#define SPIGCR1_SPIENA_MASK 0x01000000u +#define SPIGCR1_SPIENA_MASK BIT(24) +#define SPIGCR1_POWERDOWN_MASK BIT(8) /* SPIPC0 */ #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ @@ -66,20 +67,38 @@ #define SPIPC0_EN0FUN_MASK BIT(0) #define SPIINT_MASKALL 0x0101035F +#define SPIINT_MASKINT 0x0000035F #define SPI_INTLVL_1 0x000001FFu #define SPI_INTLVL_0 0x00000000u /* SPIDAT1 */ +#define SPIDAT1_CSHOLD_MASK BIT(28) #define SPIDAT1_CSHOLD_SHIFT 28 +#define SPIDAT1_WDEL_MASK BIT(26) +#define SPIDAT1_CSNR_MASK 0x00FF0000u #define SPIDAT1_CSNR_SHIFT 16 +#define SPIDAT1_DFSEL_MASK (BIT(24 | BIT(25)) #define SPIGCR1_CLKMOD_MASK BIT(1) -#define SPIGCR1_MASTER_MASK BIT(0) +#define SPIGCR1_MASTER_MASK BIT(0) #define SPIGCR1_LOOPBACK_MASK BIT(16) /* SPIBUF */ #define SPIBUF_TXFULL_MASK BIT(29) #define SPIBUF_RXEMPTY_MASK BIT(31) +/* SPIDELAY */ +#define SPIDELAY_C2TDELAY_MASK 0xFF000000u +#define SPIDELAY_C2TDELAY_SHIFT 24 +#define SPIDELAY_T2CDELAY_MASK 0x00FF0000u +#define SPIDELAY_T2CDELAY_SHIFT 16 +#define SPIDELAY_T2EDELAY_MASK 0x0000FF00u +#define SPIDELAY_T2EDELAY_SHIFT 8 +#define SPIDELAY_C2EDELAY_MASK 0x000000FFu +#define SPIDELAY_C2EDELAY_SHIFT 0 + +/* SPIDEF */ +#define SPIDEF_CSDEF_MASK 0x000000FFu + /* Error Masks */ #define SPIFLG_DLEN_ERR_MASK BIT(0) #define SPIFLG_TIMEOUT_MASK BIT(1) @@ -90,11 +109,12 @@ #define SPIFLG_RX_INTR_MASK BIT(8) #define SPIFLG_TX_INTR_MASK BIT(9) #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) -#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \ +#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ - | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \ - | SPIFLG_TX_INTR_MASK \ + | SPIFLG_OVRRUN_MASK) +#define SPIFLG_MASK (SPIFLG_ERROR_MASK \ + | SPIFLG_RX_INTR_MASK | SPIFLG_TX_INTR_MASK \ | SPIFLG_BUF_INIT_ACTIVE_MASK) #define SPIINT_DLEN_ERR_INTR BIT(0) @@ -139,11 +159,10 @@ #define TGINTVEC0 0x60 #define TGINTVEC1 0x64 -struct davinci_spi_slave { - u32 cmd_to_write; - u32 clk_ctrl_to_write; - u32 bytes_per_word; - u8 active_cs; +const char * const io_type_names[] = { + [SPI_IO_TYPE_INTR] = "Interrupt", + [SPI_IO_TYPE_POLL] = "Polled", + [SPI_IO_TYPE_DMA] = "DMA", }; /* We have 2 DMA channels per CS, one for RX and one for TX */ @@ -152,10 +171,8 @@ struct davinci_spi_dma { int dma_rx_channel; int dma_tx_sync_dev; int dma_rx_sync_dev; + int dummy_param_slot; enum dma_event_q eventq; - - struct completion dma_tx_completion; - struct completion dma_rx_completion; }; /* SPI Controller driver's private data. */ @@ -173,51 +190,53 @@ struct davinci_spi { const void *tx; void *rx; u8 *tmp_buf; - int count; - struct davinci_spi_dma *dma_channels; - struct davinci_spi_platform_data *pdata; + int rcount; + int wcount; + u32 errors; + struct davinci_spi_dma dma_channels; + struct davinci_spi_platform_data *pdata; void (*get_rx)(u32 rx_data, struct davinci_spi *); u32 (*get_tx)(struct davinci_spi *); - - struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT]; }; -static unsigned use_dma; - static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) { - u8 *rx = davinci_spi->rx; - - *rx++ = (u8)data; - davinci_spi->rx = rx; + if (davinci_spi->rx) { + u8 *rx = davinci_spi->rx; + *rx++ = (u8)data; + davinci_spi->rx = rx; + } } static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) { - u16 *rx = davinci_spi->rx; - - *rx++ = (u16)data; - davinci_spi->rx = rx; + if (davinci_spi->rx) { + u16 *rx = davinci_spi->rx; + *rx++ = (u16)data; + davinci_spi->rx = rx; + } } static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) { - u32 data; - const u8 *tx = davinci_spi->tx; - - data = *tx++; - davinci_spi->tx = tx; + u32 data = 0; + if (davinci_spi->tx) { + const u8 *tx = davinci_spi->tx; + data = *tx++; + davinci_spi->tx = tx; + } return data; } static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) { - u32 data; - const u16 *tx = davinci_spi->tx; - - data = *tx++; - davinci_spi->tx = tx; + u32 data = 0; + if (davinci_spi->tx) { + const u16 *tx = davinci_spi->tx; + data = *tx++; + davinci_spi->tx = tx; + } return data; } @@ -237,26 +256,6 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits) iowrite32(v, addr); } -static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num) -{ - set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); -} - -static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num) -{ - clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); -} - -static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) -{ - struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); - - if (enable) - set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); - else - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); -} - /* * Interface to control the chip select signal */ @@ -264,25 +263,54 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) { struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; - u32 data1_reg_val = 0; + u8 i, chip_sel = spi->chip_select; + u32 spidat1; + u16 spidat1_cfg; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; - /* - * Board specific chip select logic decides the polarity and cs - * line for the controller - */ - if (value == BITBANG_CS_INACTIVE) { - set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT); - - data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT; - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); + spidat1 = SPIDAT1_CSNR_MASK; + if (value == BITBANG_CS_ACTIVE) + spidat1 |= SPIDAT1_CSHOLD_MASK; + else + spidat1 |= SPIDAT1_WDEL_MASK; - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); + if (pdata->chip_sel == NULL) { + if (value == BITBANG_CS_ACTIVE) + spidat1 &= ~((0x1 << chip_sel) << SPIDAT1_CSNR_SHIFT); + } else { + for (i = 0; i < pdata->num_chipselect; i++) { + if (pdata->chip_sel[i] == SPI_INTERN_CS) { + if ((i == chip_sel) && + (value == BITBANG_CS_ACTIVE)) { + spidat1 &= ~((0x1 << chip_sel) + << SPIDAT1_CSNR_SHIFT); + } + } else { + if (value == BITBANG_CS_INACTIVE) + gpio_set_value(pdata->chip_sel[i], 1); + else if (i == chip_sel) + gpio_set_value(pdata->chip_sel[i], 0); + } + } } + + spidat1_cfg = spidat1 >> SPIDAT1_CSNR_SHIFT; + iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); +} + +/** + * davinci_spi_get_prescale - Calculates the correct prescale value + * @max_speed_hz: the maximum rate the SPI clock can run at + * + * This function calculates the prescale value that generates a clock rate + * less than or equal to the specified maximum + */ +static inline u32 davinci_spi_get_prescale(struct davinci_spi *davinci_spi, + u32 max_speed_hz) +{ + return ((clk_get_rate(davinci_spi->clk) - 1) / max_speed_hz) & 0xff; } /** @@ -297,14 +325,15 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) static int davinci_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { - struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; + struct davinci_spi_config *spi_cfg; u8 bits_per_word = 0; - u32 hz = 0, prescale = 0, clkspeed; + u32 hz = 0, spifmt = 0, prescale, delay = 0; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; + spi_cfg = spi->controller_data; if (t) { bits_per_word = t->bits_per_word; @@ -322,76 +351,112 @@ static int davinci_spi_setup_transfer(struct spi_device *spi, if (bits_per_word <= 8 && bits_per_word >= 2) { davinci_spi->get_rx = davinci_spi_rx_buf_u8; davinci_spi->get_tx = davinci_spi_tx_buf_u8; - davinci_spi->slave[spi->chip_select].bytes_per_word = 1; + spi_cfg->bytes_per_word = 1; } else if (bits_per_word <= 16 && bits_per_word >= 2) { davinci_spi->get_rx = davinci_spi_rx_buf_u16; davinci_spi->get_tx = davinci_spi_tx_buf_u16; - davinci_spi->slave[spi->chip_select].bytes_per_word = 2; + spi_cfg->bytes_per_word = 2; } else return -EINVAL; if (!hz) hz = spi->max_speed_hz; - clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK, - spi->chip_select); - set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f, - spi->chip_select); + prescale = davinci_spi_get_prescale(davinci_spi, hz); + spifmt |= (prescale << SPIFMT_PRESCALE_SHIFT); + + spifmt |= (bits_per_word & 0x1f); + + if (spi->mode & SPI_LSB_FIRST) + spifmt |= SPIFMT_SHIFTDIR_MASK; + + if (spi->mode & SPI_CPOL) + spifmt |= SPIFMT_POLARITY_MASK; + + if (!(spi->mode & SPI_CPHA)) + spifmt |= SPIFMT_PHASE_MASK; + + if (davinci_spi->version == SPI_VERSION_2) { + spifmt |= ((spi_cfg->wdelay << SPIFMT_WDELAY_SHIFT) + & SPIFMT_WDELAY_MASK); + + if (spi_cfg->odd_parity) + spifmt |= SPIFMT_ODD_PARITY_MASK; + + if (spi_cfg->parity_enable) + spifmt |= SPIFMT_PARITYENA_MASK; + + if (spi->mode & SPI_READY) { + spifmt |= SPIFMT_WAITENA_MASK; + delay |= (spi_cfg->t2e_delay + << SPIDELAY_T2EDELAY_SHIFT) + & SPIDELAY_T2EDELAY_MASK; + delay |= (spi_cfg->c2e_delay + << SPIDELAY_C2EDELAY_SHIFT) + & SPIDELAY_C2EDELAY_MASK; + } + + if (spi_cfg->timer_disable) { + spifmt |= SPIFMT_DISTIMER_MASK; + } else { + delay |= (spi_cfg->c2t_delay + << SPIDELAY_C2TDELAY_SHIFT) + & SPIDELAY_C2TDELAY_MASK; + delay |= (spi_cfg->t2c_delay + << SPIDELAY_T2CDELAY_SHIFT) + & SPIDELAY_T2CDELAY_MASK; + } - clkspeed = clk_get_rate(davinci_spi->clk); - if (hz > clkspeed / 2) - prescale = 1 << 8; - if (hz < clkspeed / 256) - prescale = 255 << 8; - if (!prescale) - prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00; + iowrite32(delay, davinci_spi->base + SPIDELAY); + } + + iowrite32(spifmt, davinci_spi->base + SPIFMT0); - clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select); - set_fmt_bits(davinci_spi->base, prescale, spi->chip_select); + if (spi_cfg->intr_level) + iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); + else + iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); + + if (spi->mode & SPI_LOOP) + set_io_bits(davinci_spi->base + SPIGCR1, + SPIGCR1_LOOPBACK_MASK); + else + clear_io_bits(davinci_spi->base + SPIGCR1, + SPIGCR1_LOOPBACK_MASK); return 0; } static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) { - struct spi_device *spi = (struct spi_device *)data; - struct davinci_spi *davinci_spi; + struct davinci_spi *davinci_spi = data; struct davinci_spi_dma *davinci_spi_dma; struct davinci_spi_platform_data *pdata; - davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); + davinci_spi_dma = &(davinci_spi->dma_channels); pdata = davinci_spi->pdata; + edma_stop(davinci_spi_dma->dma_rx_channel); + if (ch_status == DMA_COMPLETE) - edma_stop(davinci_spi_dma->dma_rx_channel); - else - edma_clean_channel(davinci_spi_dma->dma_rx_channel); + davinci_spi->rcount = 0; - complete(&davinci_spi_dma->dma_rx_completion); - /* We must disable the DMA RX request */ - davinci_spi_set_dma_req(spi, 0); + complete(&davinci_spi->done); } static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) { - struct spi_device *spi = (struct spi_device *)data; - struct davinci_spi *davinci_spi; + struct davinci_spi *davinci_spi = data; struct davinci_spi_dma *davinci_spi_dma; struct davinci_spi_platform_data *pdata; - davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); + davinci_spi_dma = &(davinci_spi->dma_channels); pdata = davinci_spi->pdata; - if (ch_status == DMA_COMPLETE) - edma_stop(davinci_spi_dma->dma_tx_channel); - else - edma_clean_channel(davinci_spi_dma->dma_tx_channel); + edma_stop(davinci_spi_dma->dma_tx_channel); - complete(&davinci_spi_dma->dma_tx_completion); - /* We must disable the DMA TX request */ - davinci_spi_set_dma_req(spi, 0); + if (ch_status == DMA_COMPLETE) + davinci_spi->wcount = 0; } static int davinci_spi_request_dma(struct spi_device *spi) @@ -403,30 +468,51 @@ static int davinci_spi_request_dma(struct spi_device *spi) int r; davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; + davinci_spi_dma = &davinci_spi->dma_channels; pdata = davinci_spi->pdata; sdev = davinci_spi->bitbang.master->dev.parent; r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, - davinci_spi_dma_rx_callback, spi, + davinci_spi_dma_rx_callback, davinci_spi, davinci_spi_dma->eventq); if (r < 0) { - dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); - return -EAGAIN; + dev_dbg(sdev, "Unable to request DMA channel for MibSPI RX\n"); + r = -EAGAIN; + goto rx_dma_failed; } davinci_spi_dma->dma_rx_channel = r; + r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, - davinci_spi_dma_tx_callback, spi, + davinci_spi_dma_tx_callback, davinci_spi, davinci_spi_dma->eventq); if (r < 0) { - edma_free_channel(davinci_spi_dma->dma_rx_channel); - davinci_spi_dma->dma_rx_channel = -1; - dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); - return -EAGAIN; + dev_dbg(sdev, "Unable to request DMA channel for MibSPI TX\n"); + r = -EAGAIN; + goto tx_dma_failed; } davinci_spi_dma->dma_tx_channel = r; + r = edma_alloc_slot(EDMA_CTLR(davinci_spi_dma->dma_tx_sync_dev), + EDMA_SLOT_ANY); + if (r < 0) { + dev_dbg(sdev, "Unable to request SPI DMA param slot\n"); + r = -EAGAIN; + goto param_failed; + } + davinci_spi_dma->dummy_param_slot = r; + edma_link(davinci_spi_dma->dummy_param_slot, + davinci_spi_dma->dummy_param_slot); + return 0; + +param_failed: + edma_free_channel(davinci_spi_dma->dma_tx_channel); + davinci_spi_dma->dma_tx_channel = -1; +tx_dma_failed: + edma_free_channel(davinci_spi_dma->dma_rx_channel); + davinci_spi_dma->dma_rx_channel = -1; +rx_dma_failed: + return r; } /** @@ -438,129 +524,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) static int davinci_spi_setup(struct spi_device *spi) { - int retval; + int retval = 0; struct davinci_spi *davinci_spi; - struct davinci_spi_dma *davinci_spi_dma; - struct device *sdev; + struct davinci_spi_dma *davinci_dma; + struct davinci_spi_platform_data *pdata; + struct davinci_spi_config *spi_cfg; + u32 prescale; davinci_spi = spi_master_get_devdata(spi->master); - sdev = davinci_spi->bitbang.master->dev.parent; + pdata = davinci_spi->pdata; + spi_cfg = (struct davinci_spi_config *)spi->controller_data; + davinci_dma = &(davinci_spi->dma_channels); /* if bits per word length is zero then set it default 8 */ if (!spi->bits_per_word) spi->bits_per_word = 8; - davinci_spi->slave[spi->chip_select].cmd_to_write = 0; + if (!(spi->mode & SPI_NO_CS)) { + if ((pdata->chip_sel == NULL) || + (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) + set_io_bits(davinci_spi->base + SPIPC0, + 1 << spi->chip_select); - if (use_dma && davinci_spi->dma_channels) { - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if ((davinci_spi_dma->dma_rx_channel == -1) - || (davinci_spi_dma->dma_tx_channel == -1)) { - retval = davinci_spi_request_dma(spi); - if (retval < 0) - return retval; - } - } - - /* - * SPI in DaVinci and DA8xx operate between - * 600 KHz and 50 MHz - */ - if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) { - dev_dbg(sdev, "Operating frequency is not in acceptable " - "range\n"); - return -EINVAL; } - /* - * Set up SPIFMTn register, unique to this chipselect. - * - * NOTE: we could do all of these with one write. Also, some - * of the "version 2" features are found in chips that don't - * support all of them... - */ - if (spi->mode & SPI_LSB_FIRST) - set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, - spi->chip_select); + if (spi->mode & SPI_READY) + set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); - if (spi->mode & SPI_CPOL) - set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, - spi->chip_select); + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + davinci_dma = &(davinci_spi->dma_channels); - if (!(spi->mode & SPI_CPHA)) - set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, - spi->chip_select); + if ((davinci_dma->dma_tx_sync_dev == SPI_NO_RESOURCE) || + (davinci_dma->dma_rx_sync_dev == SPI_NO_RESOURCE) || + (davinci_dma->eventq == SPI_NO_RESOURCE)) + spi_cfg->io_type = SPI_IO_TYPE_INTR; + else if ((davinci_dma->dma_rx_channel == -1) || + (davinci_dma->dma_tx_channel == -1)) + retval = davinci_spi_request_dma(spi); + } /* - * Version 1 hardware supports two basic SPI modes: - * - Standard SPI mode uses 4 pins, with chipselect - * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) - * (distinct from SPI_3WIRE, with just one data wire; - * or similar variants without MOSI or without MISO) - * - * Version 2 hardware supports an optional handshaking signal, - * so it can support two more modes: - * - 5 pin SPI variant is standard SPI plus SPI_READY - * - 4 pin with enable is (SPI_READY | SPI_NO_CS) + * Validate desired clock rate */ + prescale = davinci_spi_get_prescale(davinci_spi, spi->max_speed_hz); + if ((prescale < 2) || (prescale > 255)) + return -EINVAL; - if (davinci_spi->version == SPI_VERSION_2) { - clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK, - spi->chip_select); - set_fmt_bits(davinci_spi->base, - (davinci_spi->pdata->wdelay - << SPIFMT_WDELAY_SHIFT) - & SPIFMT_WDELAY_MASK, - spi->chip_select); - - if (davinci_spi->pdata->odd_parity) - set_fmt_bits(davinci_spi->base, - SPIFMT_ODD_PARITY_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_ODD_PARITY_MASK, - spi->chip_select); - - if (davinci_spi->pdata->parity_enable) - set_fmt_bits(davinci_spi->base, - SPIFMT_PARITYENA_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_PARITYENA_MASK, - spi->chip_select); - - if (davinci_spi->pdata->wait_enable) - set_fmt_bits(davinci_spi->base, - SPIFMT_WAITENA_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_WAITENA_MASK, - spi->chip_select); - - if (davinci_spi->pdata->timer_disable) - set_fmt_bits(davinci_spi->base, - SPIFMT_DISTIMER_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_DISTIMER_MASK, - spi->chip_select); - } - - retval = davinci_spi_setup_transfer(spi, NULL); + dev_info(&spi->dev, "DaVinci SPI driver in %s mode\n", + io_type_names[spi_cfg->io_type]); return retval; } @@ -569,50 +580,19 @@ static void davinci_spi_cleanup(struct spi_device *spi) { struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); struct davinci_spi_dma *davinci_spi_dma; + struct davinci_spi_platform_data *pdata; - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if (use_dma && davinci_spi->dma_channels) { - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if ((davinci_spi_dma->dma_rx_channel != -1) - && (davinci_spi_dma->dma_tx_channel != -1)) { - edma_free_channel(davinci_spi_dma->dma_tx_channel); - edma_free_channel(davinci_spi_dma->dma_rx_channel); - } - } -} - -static int davinci_spi_bufs_prep(struct spi_device *spi, - struct davinci_spi *davinci_spi) -{ - int op_mode = 0; - - /* - * REVISIT unless devices disagree about SPI_LOOP or - * SPI_READY (SPI_NO_CS only allows one device!), this - * should not need to be done before each message... - * optimize for both flags staying cleared. - */ - - op_mode = SPIPC0_DIFUN_MASK - | SPIPC0_DOFUN_MASK - | SPIPC0_CLKFUN_MASK; - if (!(spi->mode & SPI_NO_CS)) - op_mode |= 1 << spi->chip_select; - if (spi->mode & SPI_READY) - op_mode |= SPIPC0_SPIENA_MASK; + davinci_spi_dma = &davinci_spi->dma_channels; + pdata = davinci_spi->pdata; - iowrite32(op_mode, davinci_spi->base + SPIPC0); + if (davinci_spi_dma->dma_rx_channel != -1) + edma_free_channel(davinci_spi_dma->dma_rx_channel); - if (spi->mode & SPI_LOOP) - set_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_LOOPBACK_MASK); - else - clear_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_LOOPBACK_MASK); + if (davinci_spi_dma->dma_tx_channel != -1) + edma_free_channel(davinci_spi_dma->dma_tx_channel); - return 0; + if (davinci_spi_dma->dummy_param_slot != -1) + edma_free_slot(davinci_spi_dma->dummy_param_slot); } static int davinci_spi_check_error(struct davinci_spi *davinci_spi, @@ -660,355 +640,242 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi, } /** - * davinci_spi_bufs - functions which will handle transfer data - * @spi: spi device on which data transfer to be done - * @t: spi transfer in which transfer info is filled + * davinci_spi_process_events - check for and handle any SPI controller events + * @davinci_spi: the controller data * - * This function will put data to be transferred into data register - * of SPI controller and then wait until the completion will be marked - * by the IRQ Handler. + * This function will check the SPIFLG register and handle any events that are + * detected there */ -static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) +static int davinci_spi_process_events(struct davinci_spi *davinci_spi) { - struct davinci_spi *davinci_spi; - int int_status, count, ret; - u8 conv, tmp; - u32 tx_data, data1_reg_val; - u32 buf_val, flg_val; - struct davinci_spi_platform_data *pdata; - - davinci_spi = spi_master_get_devdata(spi->master); - pdata = davinci_spi->pdata; - - davinci_spi->tx = t->tx_buf; - davinci_spi->rx = t->rx_buf; - - /* convert len to words based on bits_per_word */ - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; - davinci_spi->count = t->len / conv; - - INIT_COMPLETION(davinci_spi->done); - - ret = davinci_spi_bufs_prep(spi, davinci_spi); - if (ret) - return ret; - - /* Enable SPI */ - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), - davinci_spi->base + SPIDELAY); - - count = davinci_spi->count; - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; - tmp = ~(0x1 << spi->chip_select); - - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); - - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; - - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); - - /* Determine the command to execute READ or WRITE */ - if (t->tx_buf) { - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); - - while (1) { - tx_data = davinci_spi->get_tx(davinci_spi); - - data1_reg_val &= ~(0xFFFF); - data1_reg_val |= (0xFFFF & tx_data); - - buf_val = ioread32(davinci_spi->base + SPIBUF); - if ((buf_val & SPIBUF_TXFULL_MASK) == 0) { - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - count--; - } - while (ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) - cpu_relax(); - - /* getting the returned byte */ - if (t->rx_buf) { - buf_val = ioread32(davinci_spi->base + SPIBUF); - davinci_spi->get_rx(buf_val, davinci_spi); - } - if (count <= 0) - break; - } - } else { - if (pdata->poll_mode) { - while (1) { - /* keeps the serial clock going */ - if ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_TXFULL_MASK) == 0) - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - while (ioread32(davinci_spi->base + SPIBUF) & - SPIBUF_RXEMPTY_MASK) - cpu_relax(); - - flg_val = ioread32(davinci_spi->base + SPIFLG); - buf_val = ioread32(davinci_spi->base + SPIBUF); - - davinci_spi->get_rx(buf_val, davinci_spi); - - count--; - if (count <= 0) - break; - } - } else { /* Receive in Interrupt mode */ - int i; - - for (i = 0; i < davinci_spi->count; i++) { - set_io_bits(davinci_spi->base + SPIINT, - SPIINT_BITERR_INTR - | SPIINT_OVRRUN_INTR - | SPIINT_RX_INTR); - - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - while (ioread32(davinci_spi->base + SPIINT) & - SPIINT_RX_INTR) - cpu_relax(); - } - iowrite32((data1_reg_val & 0x0ffcffff), - davinci_spi->base + SPIDAT1); - } + u32 status, tx_data, rx_data, spidat1; + u8 tx_word = 0; + + status = ioread32(davinci_spi->base + SPIFLG); + + if ((davinci_spi->version != SPI_VERSION_0) && + (likely(status & SPIFLG_TX_INTR_MASK)) && + (likely(davinci_spi->wcount > 0))) + tx_word = 1; + + if (likely(status & SPIFLG_RX_INTR_MASK)) { + rx_data = ioread32(davinci_spi->base + SPIBUF) & 0xFFFF; + davinci_spi->get_rx(rx_data, davinci_spi); + davinci_spi->rcount--; + if ((davinci_spi->version == SPI_VERSION_0) && + (likely(davinci_spi->wcount > 0))) + tx_word = 1; } - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - int_status = ioread32(davinci_spi->base + SPIFLG); - - ret = davinci_spi_check_error(davinci_spi, int_status); - if (ret != 0) - return ret; + if (unlikely(status & SPIFLG_ERROR_MASK)) { + davinci_spi->errors = (status & SPIFLG_ERROR_MASK); + return -1; + } - /* SPI Framework maintains the count only in bytes so convert back */ - davinci_spi->count *= conv; + if (likely(tx_word)) { + spidat1 = ioread32(davinci_spi->base + SPIDAT1); + davinci_spi->wcount--; + tx_data = davinci_spi->get_tx(davinci_spi); + spidat1 &= 0xFFFF0000; + spidat1 |= (tx_data & 0xFFFF); + iowrite32(spidat1, davinci_spi->base + SPIDAT1); + } - return t->len; + return 0; } -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 - -static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) +/** + * davinci_spi_txrx_bufs - function which will handle transfer data + * @spi: spi device on which data transfer to be done + * @t: spi transfer in which transfer info is filled + * + * This function will put data to be transferred into data register + * of SPI controller and then wait until the completion will be marked + * by the IRQ Handler. + */ +static int davinci_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) { struct davinci_spi *davinci_spi; - int int_status = 0; - int count, temp_count; - u8 conv = 1; - u8 tmp; - u32 data1_reg_val; - struct davinci_spi_dma *davinci_spi_dma; - int word_len, data_type, ret; - unsigned long tx_reg, rx_reg; + int data_type, ret = 0; + u32 tx_data, spidat1; + u16 tx_buf_count = 0, rx_buf_count = 0; + struct davinci_spi_config *spi_cfg; struct davinci_spi_platform_data *pdata; + struct davinci_spi_dma *davinci_dma; struct device *sdev; + dma_addr_t tx_reg, rx_reg; + void *tx_buf, *rx_buf; + struct edmacc_param rx_param, tx_param; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; - sdev = davinci_spi->bitbang.master->dev.parent; - - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; - rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; + spi_cfg = (struct davinci_spi_config *)spi->controller_data; + davinci_dma = &(davinci_spi->dma_channels); davinci_spi->tx = t->tx_buf; davinci_spi->rx = t->rx_buf; + davinci_spi->wcount = t->len / spi_cfg->bytes_per_word; + davinci_spi->rcount = davinci_spi->wcount; + davinci_spi->errors = 0; - /* convert len to words based on bits_per_word */ - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; - davinci_spi->count = t->len / conv; + spidat1 = ioread32(davinci_spi->base + SPIDAT1); - INIT_COMPLETION(davinci_spi->done); - - init_completion(&davinci_spi_dma->dma_rx_completion); - init_completion(&davinci_spi_dma->dma_tx_completion); - - word_len = conv * 8; - - if (word_len <= 8) - data_type = DAVINCI_DMA_DATA_TYPE_S8; - else if (word_len <= 16) - data_type = DAVINCI_DMA_DATA_TYPE_S16; - else if (word_len <= 32) - data_type = DAVINCI_DMA_DATA_TYPE_S32; - else - return -EINVAL; - - ret = davinci_spi_bufs_prep(spi, davinci_spi); - if (ret) - return ret; - - /* Put delay val if required */ - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), - davinci_spi->base + SPIDELAY); - - count = davinci_spi->count; /* the number of elements */ - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; - - /* CS default = 0xFF */ - tmp = ~(0x1 << spi->chip_select); - - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); - - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; - - /* disable all interrupts for dma transfers */ - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); - /* Disable SPI to write configuration bits in SPIDAT */ - clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); - /* Enable SPI */ + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); - + INIT_COMPLETION(davinci_spi->done); - if (t->tx_buf) { - t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, - DMA_TO_DEVICE); - if (dma_mapping_error(&spi->dev, t->tx_dma)) { - dev_dbg(sdev, "Unable to DMA map a %d bytes" - " TX buffer\n", count); - return -ENOMEM; + if ((spi_cfg->io_type == SPI_IO_TYPE_INTR) || + (spi_cfg->io_type == SPI_IO_TYPE_POLL)) { + + if (spi_cfg->io_type == SPI_IO_TYPE_INTR) + set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); + + /* start the transfer */ + davinci_spi->wcount--; + tx_data = davinci_spi->get_tx(davinci_spi); + spidat1 &= 0xFFFF0000; + spidat1 |= (tx_data & 0xFFFF); + iowrite32(spidat1, davinci_spi->base + SPIDAT1); + + } else if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + data_type = spi_cfg->bytes_per_word; + tx_reg = (dma_addr_t)davinci_spi->pbase + SPIDAT1; + rx_reg = (dma_addr_t)davinci_spi->pbase + SPIBUF; + + if (t->tx_buf) { + tx_buf = ((void *)t->tx_buf); + tx_buf_count = davinci_spi->wcount; + } else { + tx_buf = (void *)davinci_spi->tmp_buf; + tx_buf_count = SPI_BUFSIZ; } - temp_count = count; - } else { - /* We need TX clocking for RX transaction */ - t->tx_dma = dma_map_single(&spi->dev, - (void *)davinci_spi->tmp_buf, count + 1, - DMA_TO_DEVICE); - if (dma_mapping_error(&spi->dev, t->tx_dma)) { - dev_dbg(sdev, "Unable to DMA map a %d bytes" - " TX tmp buffer\n", count); - return -ENOMEM; + if (t->rx_buf) { + rx_buf = (void *)t->rx_buf; + rx_buf_count = davinci_spi->rcount; + } else { + rx_buf = (void *)davinci_spi->tmp_buf; + rx_buf_count = SPI_BUFSIZ; } - temp_count = count + 1; + + t->tx_dma = dma_map_single(&spi->dev, tx_buf, + tx_buf_count, DMA_TO_DEVICE); + t->rx_dma = dma_map_single(&spi->dev, rx_buf, + rx_buf_count, DMA_FROM_DEVICE); + + tx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_tx_channel); + tx_param.src = t->tx_buf ? t->tx_dma : tx_reg; + tx_param.a_b_cnt = davinci_spi->wcount << 16 | data_type; + tx_param.dst = tx_reg; + tx_param.src_dst_bidx = t->tx_buf ? data_type : 0; + tx_param.link_bcntrld = 0xffff; + tx_param.src_dst_cidx = 0; + tx_param.ccnt = 1; + edma_write_slot(davinci_dma->dma_tx_channel, &tx_param); + edma_link(davinci_dma->dma_tx_channel, + davinci_dma->dummy_param_slot); + + rx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_rx_channel); + rx_param.src = rx_reg; + rx_param.a_b_cnt = davinci_spi->rcount << 16 | data_type; + rx_param.dst = t->rx_dma; + rx_param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; + rx_param.link_bcntrld = 0xffff; + rx_param.src_dst_cidx = 0; + rx_param.ccnt = 1; + edma_write_slot(davinci_dma->dma_rx_channel, &rx_param); + + iowrite16(spidat1 >> SPIDAT1_CSNR_SHIFT, + davinci_spi->base + SPIDAT1 + 2); + + edma_start(davinci_dma->dma_rx_channel); + edma_start(davinci_dma->dma_tx_channel); + set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); } - edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, - data_type, temp_count, 1, 0, ASYNC); - edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); - edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT); - edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0); - edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); - - if (t->rx_buf) { - /* initiate transaction */ - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); - - t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, - DMA_FROM_DEVICE); - if (dma_mapping_error(&spi->dev, t->rx_dma)) { - dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", - count); - if (t->tx_buf != NULL) - dma_unmap_single(NULL, t->tx_dma, - count, DMA_TO_DEVICE); - return -ENOMEM; + /* Wait for the transfer to complete */ + if (spi_cfg->io_type != SPI_IO_TYPE_POLL) { + wait_for_completion_interruptible(&(davinci_spi->done)); + } else { + while ((davinci_spi->rcount > 0) && (ret == 0)) { + ret = davinci_spi_process_events(davinci_spi); + cpu_relax(); } - edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, - data_type, count, 1, 0, ASYNC); - edma_set_src(davinci_spi_dma->dma_rx_channel, - rx_reg, INCR, W8BIT); - edma_set_dest(davinci_spi_dma->dma_rx_channel, - t->rx_dma, INCR, W8BIT); - edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); - edma_set_dest_index(davinci_spi_dma->dma_rx_channel, - data_type, 0); } - if ((t->tx_buf) || (t->rx_buf)) - edma_start(davinci_spi_dma->dma_tx_channel); - - if (t->rx_buf) - edma_start(davinci_spi_dma->dma_rx_channel); - - if ((t->rx_buf) || (t->tx_buf)) - davinci_spi_set_dma_req(spi, 1); - - if (t->tx_buf) - wait_for_completion_interruptible( - &davinci_spi_dma->dma_tx_completion); - - if (t->rx_buf) - wait_for_completion_interruptible( - &davinci_spi_dma->dma_rx_completion); - - dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE); - - if (t->rx_buf) - dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); - - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - int_status = ioread32(davinci_spi->base + SPIFLG); + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + dma_unmap_single(NULL, t->tx_dma, tx_buf_count, + DMA_TO_DEVICE); + dma_unmap_single(NULL, t->rx_dma, rx_buf_count, + DMA_FROM_DEVICE); + } - ret = davinci_spi_check_error(davinci_spi, int_status); - if (ret != 0) - return ret; + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - /* SPI Framework maintains the count only in bytes so convert back */ - davinci_spi->count *= conv; + if (davinci_spi->errors) { + ret = davinci_spi_check_error(davinci_spi, davinci_spi->errors); + if (ret != 0) + return ret; + } + if ((davinci_spi->rcount != 0) || (davinci_spi->wcount != 0)) { + sdev = davinci_spi->bitbang.master->dev.parent; + dev_info(sdev, "SPI data transfer error\n"); + return -EIO; + } return t->len; } /** - * davinci_spi_irq - IRQ handler for DaVinci SPI + * davinci_spi_irq - probe function for SPI Master Controller * @irq: IRQ number for this SPI Master * @context_data: structure for SPI Master controller davinci_spi + * + * ISR will determine that interrupt arrives either for READ or WRITE command. + * According to command it will do the appropriate action. It will check + * transfer length and if it is not zero then dispatch transfer command again. + * If transfer length is zero then it will indicate the COMPLETION so that + * davinci_spi_bufs function can go ahead. */ static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) { struct davinci_spi *davinci_spi = context_data; - u32 int_status, rx_data = 0; - irqreturn_t ret = IRQ_NONE; + int status; - int_status = ioread32(davinci_spi->base + SPIFLG); + status = davinci_spi_process_events(davinci_spi); + if (unlikely(status != 0)) + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); - while ((int_status & SPIFLG_RX_INTR_MASK)) { - if (likely(int_status & SPIFLG_RX_INTR_MASK)) { - ret = IRQ_HANDLED; + if ((davinci_spi->rcount == 0) || (status != 0)) + complete(&(davinci_spi->done)); - rx_data = ioread32(davinci_spi->base + SPIBUF); - davinci_spi->get_rx(rx_data, davinci_spi); + return IRQ_HANDLED; +} - /* Disable Receive Interrupt */ - iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR), - davinci_spi->base + SPIINT); - } else - (void)davinci_spi_check_error(davinci_spi, int_status); +resource_size_t davinci_spi_get_dma_by_index(struct platform_device *dev, + unsigned long index) +{ + struct resource *r; - int_status = ioread32(davinci_spi->base + SPIFLG); - } + r = platform_get_resource(dev, IORESOURCE_DMA, index); + if (r != NULL) + return r->start; - return ret; + return SPI_NO_RESOURCE; } /** * davinci_spi_probe - probe function for SPI Master Controller * @pdev: platform_device structure which contains plateform specific data + * + * According to Linux Device Model this function will be invoked by Linux + * with platform_device struct which contains the device specific info. + * This function will map the SPI controller's memory, register IRQ, + * Reset SPI controller and setting its registers to default value. + * It will invoke spi_bitbang_start to create work queue so that client driver + * can register transfer method to work queue. */ static int davinci_spi_probe(struct platform_device *pdev) { @@ -1020,6 +887,7 @@ static int davinci_spi_probe(struct platform_device *pdev) resource_size_t dma_tx_chan = SPI_NO_RESOURCE; resource_size_t dma_eventq = SPI_NO_RESOURCE; int i = 0, ret = 0; + u32 spipc0; pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -1071,10 +939,12 @@ static int davinci_spi_probe(struct platform_device *pdev) goto unmap_io; } - ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED, + ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev), davinci_spi); - if (ret) + if (ret != 0) { + ret = -EAGAIN; goto unmap_io; + } /* Allocate tmp_buf for tx_buf */ davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); @@ -1104,55 +974,23 @@ static int davinci_spi_probe(struct platform_device *pdev) davinci_spi->bitbang.chipselect = davinci_spi_chipselect; davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; + davinci_spi->bitbang.txrx_bufs = davinci_spi_txrx_bufs; davinci_spi->version = pdata->version; - use_dma = pdata->use_dma; davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; if (davinci_spi->version == SPI_VERSION_2) davinci_spi->bitbang.flags |= SPI_READY; - if (use_dma) { - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (r) - dma_rx_chan = r->start; - r = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (r) - dma_tx_chan = r->start; - r = platform_get_resource(pdev, IORESOURCE_DMA, 2); - if (r) - dma_eventq = r->start; - } - - if (!use_dma || - dma_rx_chan == SPI_NO_RESOURCE || - dma_tx_chan == SPI_NO_RESOURCE || - dma_eventq == SPI_NO_RESOURCE) { - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; - use_dma = 0; - } else { - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; - davinci_spi->dma_channels = kzalloc(master->num_chipselect - * sizeof(struct davinci_spi_dma), GFP_KERNEL); - if (davinci_spi->dma_channels == NULL) { - ret = -ENOMEM; - goto free_clk; - } - - for (i = 0; i < master->num_chipselect; i++) { - davinci_spi->dma_channels[i].dma_rx_channel = -1; - davinci_spi->dma_channels[i].dma_rx_sync_dev = - dma_rx_chan; - davinci_spi->dma_channels[i].dma_tx_channel = -1; - davinci_spi->dma_channels[i].dma_tx_sync_dev = - dma_tx_chan; - davinci_spi->dma_channels[i].eventq = dma_eventq; - } - dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" - "Using RX channel = %d , TX channel = %d and " - "event queue = %d", dma_rx_chan, dma_tx_chan, - dma_eventq); - } + dma_rx_chan = davinci_spi_get_dma_by_index(pdev, RX_DMA_INDEX); + dma_tx_chan = davinci_spi_get_dma_by_index(pdev, TX_DMA_INDEX); + dma_eventq = davinci_spi_get_dma_by_index(pdev, EVENTQ_DMA_INDEX); + davinci_spi->dma_channels.dma_rx_channel = -1; + davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan; + davinci_spi->dma_channels.dma_tx_channel = -1; + davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan; + davinci_spi->dma_channels.dummy_param_slot = -1; + davinci_spi->dma_channels.eventq = dma_eventq; davinci_spi->get_rx = davinci_spi_rx_buf_u8; davinci_spi->get_tx = davinci_spi_tx_buf_u8; @@ -1164,31 +1002,28 @@ static int davinci_spi_probe(struct platform_device *pdev) udelay(100); iowrite32(1, davinci_spi->base + SPIGCR0); - /* Clock internal */ - if (davinci_spi->pdata->clk_internal) - set_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_CLKMOD_MASK); - else - clear_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_CLKMOD_MASK); + /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ + spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; + iowrite32(spipc0, davinci_spi->base + SPIPC0); - /* master mode default */ - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + /* initialize chip selects */ + if (pdata->chip_sel != NULL) { + for (i = 0; i < pdata->num_chipselect; i++) { + if (pdata->chip_sel[i] != SPI_INTERN_CS) + gpio_direction_output(pdata->chip_sel[i], 1); + } + } + iowrite32(SPIDEF_CSDEF_MASK, davinci_spi->base + SPIDEF); - if (davinci_spi->pdata->intr_level) - iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); - else - iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); ret = spi_bitbang_start(&davinci_spi->bitbang); - if (ret) + if (ret != 0) goto free_clk; - dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base); - - if (!pdata->poll_mode) - dev_info(&pdev->dev, "Operating in interrupt mode" - " using IRQ %d\n", davinci_spi->irq); + dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base); return ret; @@ -1220,7 +1055,7 @@ err: * It will also call spi_bitbang_stop to destroy the work queue which was * created by spi_bitbang_start. */ -static int __exit davinci_spi_remove(struct platform_device *pdev) +static int __devexit davinci_spi_remove(struct platform_device *pdev) { struct davinci_spi *davinci_spi; struct spi_master *master; @@ -1242,8 +1077,11 @@ static int __exit davinci_spi_remove(struct platform_device *pdev) } static struct platform_driver davinci_spi_driver = { - .driver.name = "spi_davinci", - .remove = __exit_p(davinci_spi_remove), + .driver = { + .name = "spi_davinci", + .owner = THIS_MODULE, + }, + .remove = __devexit_p(davinci_spi_remove), }; static int __init davinci_spi_init(void) -- 1.6.3.3 From todd.fischer at ridgerun.com Wed Jul 28 18:49:43 2010 From: todd.fischer at ridgerun.com (Todd Fischer) Date: Wed, 28 Jul 2010 17:49:43 -0600 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> <1280350280.20670.15378.camel@sax-lx> Message-ID: <1280360983.20670.15674.camel@sax-lx> Try i2c-tools i2cdetect and see if any chips are showing up on the bus. On Wed, 2010-07-28 at 17:44 -0400, Nicolas Luna wrote: > Oh I did'nt loaded the right kernel, my fault... > > > > Well now it's not working at all, I got this error > " QWSTslibMouseHandlerPrivate: ts_open() failed with error: 'No such > file or directory' " and no more /dev/input/touchscreen0 detected by > udev. > > > Any clues? > > Regards, > > > Nicolas > > > > On Wed, Jul 28, 2010 at 5:18 PM, Nicolas Luna > wrote: > > I changed > > > > MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) > MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) > > > to > > > MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 8, false) > MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 8, false) > > > seems to have the same behaviour.. > > > > Nicolas > > > > > > > > On Wed, Jul 28, 2010 at 5:08 PM, Nicolas Luna > wrote: > > board-da850-evm.c > > > Nicolas > > > > > > > > On Wed, Jul 28, 2010 at 4:51 PM, Todd Fischer > wrote: > > On Wed, 2010-07-28 at 16:46 -0400, Nicolas > Luna wrote: > > > Todd, > > > > > > What do I need to change if I want to use > > the bitbang i2c driver and stop to get those > > error messages. > > > > > > I added support for "GPIO-based bitbaging > > I2C" into the kernel, anything else to > > change in the TPS driver source code? > > > > > You need to modify the arm/arch/mach-davinci > board file to configure the pinmux as GPIOs, > not I2C signaling. > > Which hardware board are you using? > > > > > > > > > > > Thanks > > > > > > Regards, > > > > > > Nicolas > > > > > > > > On Wed, Jun 9, 2010 at 4:17 PM, Todd Fischer > > wrote: > > > > HI Bastian and Nicolas, > > > > I recall getting this error when I > > wasn't using the bitbang i2c driver > > on the OMAP-L138. > > > > Todd > > > > > > > > On Wed, 2010-06-09 at 10:59 +0200, > > Bastian Ruppert wrote: > > > > > > > > > > Hello Nicolas, > > > > > > thanks for the .conf file. > > > > > > > this will help you to check if > > > your hardware is ok. > > > > > > It helped. > > > > > > I applied your file on the khilman > > > commit you are using but i had to > > > patch the kernel in order to > > > compile drivers/mfd/tps6507x.c . I > > > think if you don`t have the same > > > problems, that is anomalous. > > > > > > After that the touchscreen driver > > > is running on that kernel. It`s a > > > little bit unstable, there are > > > sometimes errors like > > > > > > tps6507x 1-0048: TSC mode read > > > failed > > > i2c_davinci i2c_davinci.1: > > > controller timed out > > > i2c_davinci i2c_davinci.1: > > > initiating i2c bus recovery > > > i2c_davinci i2c_davinci.1: > > > controller timed out > > > i2c_davinci i2c_davinci.1: > > > initiating i2c bus recovery > > > > > > but the hardware can in principle > > > do it. > > > > > > Regards, > > > > > > Bastian. > > > > > > _______________________________________________ > > > Davinci-linux-open-source mailing list > > > > > > Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > > > > > > > > > > > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From nsekhar at ti.com Thu Jul 29 00:12:59 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Thu, 29 Jul 2010 10:42:59 +0530 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> Message-ID: Hi Nicolas, On Thu, Jul 29, 2010 at 02:16:16, Nicolas Luna wrote: > Todd, > > What do I need to change if I want to use the bitbang i2c driver and > stop to get those error messages. You can try the patch here: http://arago-project.org/git/projects/?p=linux-omapl1.git;a=commit;h=7d8accda275fdbe6e727e7ac02ae5a92f5695326 This issue should be fixed in future revisions of Logic EVMs so this patch wont be needed afterward. Thanks, Sekhar From lamiaposta71 at gmail.com Thu Jul 29 01:37:47 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Thu, 29 Jul 2010 08:37:47 +0200 Subject: Boot time In-Reply-To: References: Message-ID: Hi Nicolas, 2010/7/28 Nicolas Luna > Hi guys, > > I'm trying to make by board boot as quick as possible. I did some > optimisation with the "All This For 1 Second Boot" wiki and other website. I > would like to reduce a little bit more the boot time and I wonder if you > guys could give me some clues. > Did you also look at: http://processors.wiki.ti.com/index.php/Boot_Time_Optimization http://processors.wiki.ti.com/index.php/Measuring_Boot_Time > > I copied my boot log below. For sure I'll remove the uboot autoboot delay > and probably build a new kernel with modules. I putted in bold part that I > think it is possible to do more optimisation. > > 1- See bullet #3. > 2- The verifying Checksum is about 400 msec is it possible to skip it? > use: set verify n 3- It takes ~1 sec to start booting the kernel and there is a other ~1 sec > delay between the starting kernel and the beginning of the uncompressing. > Why it's so long? Ok maybe there is the copy from NOR to RAM but it should > not take more than few msec. > In the links above there was the possibility to use EDMA to copy from NOR to RAM. It is also possible to use uncompresses kernel and there is a trade of about uncompressing kernel and managing a bigger uncompressed kernel image. > 4- It takes ~1 sec to the kernel to free 120K memory... I got enought RAM > is it possible to remove it? > I don't know.. but interesting. > > I got custom hardware based on OMAP-L138 with FS (jffs2) and compressed > kernel in NOR Flash. > Have you used JFFS2_SUMMARY ? UBIFS? Have you checked cpu frequency? Have you checked NOR bus timings? > Thanks a lot > > Nicolas > > > ------------------------------------------------------------------------------------- > > 0.000 0.000: OMAP-L138 initialization passed! > 0.000 0.000: Booting TI User Boot Loader > 0.004 0.004: UBL Version: 1.65 > 0.004 0.000: UBL Flashtype: NOR > 0.008 0.004: Starting NOR Copy... > 0.008 0.000: CFI Query...passed. > 0.012 0.004: NOR Initialization: > 0.012 0.000: Command Set: Intel > 0.012 0.000: Manufacturer: INTEL > 0.016 0.004: Size: 0x00000020 MB > 0.020 0.004: Valid magicnum, 0x55424CBB, found.. > 0.184 0.164: DONE > 0.188 0.004: Jumping to entry point at 0xC1080000. > Delete every messages not absolutely critical. Did you skip from .config every DEBUG,KALLSYMS and similar configs? > 0.504 0.316: > 1.548 1.044: Hit any key to stop autoboot: 0 > *2.372 0.824: ## Booting kernel from Legacy Image at c0007fc0 ...* > 2.372 0.000: Image Name: Linux-2.6.34 > 2.380 0.008: Image Type: ARM Linux Kernel Image (uncompressed) > 2.380 0.000: Data Size: 1505956 Bytes = 1.4 MB > 2.384 0.004: Load Address: c0008000 > 2.388 0.004: Entry Point: c0008000 > *2.808 0.420: Verifying Checksum ... OK* > 2.808 0.000: Loading Kernel Image ... OK > 2.808 0.000: OK > 2.808 0.000: > *2.812 0.004: Starting kernel ...* > *2.812 0.000:* > *3.860 1.048: Uncompressing Linux... done, booting the kernel.* > 4.264 0.404: Linux version 2.6.34 (id at idt-ubuntu-linux) (gcc version 4.3.3 > (Sourcery G++ Lite 2009q1-203) ) #89 PREEMPT Thu Jul 22 15:24:03 EDT 2010 > 4.268 0.004: CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177 > 4.272 0.004: CPU: VIVT data cache, VIVT instruction cache > 4.276 0.004: Machine: DaVinci DA850/OMAP-L138 EVM > 4.280 0.004: Memory policy: ECC disabled, Data cache writeback > 4.284 0.004: DaVinci da850/omap-l138 variant 0x0 > 4.288 0.004: Built 1 zonelists in Zone order, mobility grouping on. Total > pages: 32512 > 4.300 0.012: Kernel command line: lpj=747520 mem=128M > console=ttyS2,115200n8 root=/dev/mtdblock2 rootfstype=jffs2 rw ip=off > 4.304 0.004: PID hash table entries: 512 (order: -1, 2048 bytes) > 4.308 0.004: Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) > 4.316 0.008: Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) > 4.316 0.000: Memory: 128MB = 128MB total > 4.324 0.008: Memory: 126752k/126752k available, 4320k reserved, 0K highmem > 4.324 0.000: Virtual kernel memory layout: > 4.332 0.008: vector : 0xffff0000 - 0xffff1000 ( 4 kB) > Put 'quiet' at the end of bootargs > 4.336 0.004: fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) > 4.340 0.004: DMA : 0xff000000 - 0xffe00000 ( 14 MB) > 4.344 0.004: vmalloc : 0xc8800000 - 0xfea00000 ( 866 MB) > 4.348 0.004: lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) > 4.352 0.004: modules : 0xbf000000 - 0xc0000000 ( 16 MB) > 4.356 0.004: .init : 0xc0008000 - 0xc0026000 ( 120 kB) > 4.360 0.004: .text : 0xc0026000 - 0xc02e8000 (2824 kB) > 4.364 0.004: .data : 0xc02e8000 - 0xc0307a60 ( 127 kB) > 4.372 0.008: SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, > CPUs=1, Nodes=1 > 4.376 0.004: Hierarchical RCU implementation. > 4.376 0.000: NR_IRQS:245 > 4.380 0.004: Console: colour dummy device 80x30 > 4.384 0.004: Calibrating delay loop (skipped) preset value.. 149.50 > BogoMIPS (lpj=747520) > 4.388 0.004: Mount-cache hash table entries: 512 > 4.392 0.004: CPU: Testing write buffer coherency: ok > 4.396 0.004: DaVinci: 144 gpio irqs > 4.396 0.000: NET: Registered protocol family 16 > 4.400 0.004: bio: create slab at 0 > 4.404 0.004: SCSI subsystem initialized > 4.408 0.004: usbcore: registered new interface driver usbfs > 4.412 0.004: usbcore: registered new interface driver hub > 4.416 0.004: usbcore: registered new device driver usb > 4.416 0.000: Switching to clocksource timer0_1 > 4.420 0.004: musb_hdrc: version 6.0, pio, host, debug=0 > 4.424 0.004: Waiting for USB PHY clock good... > 4.428 0.004: musb_hdrc musb_hdrc: MUSB HDRC host driver > 4.432 0.004: musb_hdrc musb_hdrc: new USB bus registered, assigned bus > number 1 > 4.436 0.004: hub 1-0:1.0: USB hub found > 4.440 0.004: hub 1-0:1.0: 1 port detected > 4.444 0.004: musb_hdrc musb_hdrc: USB Host mode controller at fee00000 > using PIO, IRQ 58 > 4.448 0.004: NET: Registered protocol family 2 > 4.456 0.008: IP route cache hash table entries: 1024 (order: 0, 4096 bytes) > 4.460 0.004: TCP established hash table entries: 4096 (order: 3, 32768 > bytes) > 4.464 0.004: TCP bind hash table entries: 4096 (order: 2, 16384 bytes) > 4.468 0.004: TCP: Hash tables configured (established 4096 bind 4096) > 4.472 0.004: TCP reno registered > 4.476 0.004: UDP hash table entries: 256 (order: 0, 4096 bytes) > 4.480 0.004: UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) > 4.484 0.004: NET: Registered protocol family 1 > 4.488 0.004: RPC: Registered udp transport module. > 4.492 0.004: RPC: Registered tcp transport module. > 4.496 0.004: RPC: Registered tcp NFSv4.1 backchannel transport module. > 4.500 0.004: JFFS2 version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc. > 4.504 0.004: msgmni has been set to 247 > 4.508 0.004: io scheduler noop registered (default) > 4.512 0.004: da8xx_lcdc da8xx_lcdc.0: GLCD: Found Sharp_LK043T1DG01 panel > 4.516 0.004: Console: switching to colour frame buffer device 60x34 > 4.520 0.004: Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled > 4.528 0.008: serial8250.0: ttyS0 at MMIO 0x1c42000 (irq = 25) is a 16550A > 4.532 0.004: serial8250.0: ttyS1 at MMIO 0x1d0c000 (irq = 53) is a 16550A > 4.540 0.008: serial8250.0: ttyS2 at MMIO 0x1d0d000 (irq = 61) is a 16550A > 4.540 0.000: console [ttyS2] enabled > 4.548 0.008: brd: module loaded > 4.556 0.008: physmap platform flash device: 02000000 at 60000000 > 4.564 0.008: physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank > 4.568 0.004: Intel/Sharp Extended Query Table at 0x010A > 4.572 0.004: Intel/Sharp Extended Query Table at 0x010A > 4.576 0.004: Intel/Sharp Extended Query Table at 0x010A > 4.580 0.004: Intel/Sharp Extended Query Table at 0x010A > 4.584 0.004: Intel/Sharp Extended Query Table at 0x010A > 4.588 0.004: Using buffer write method > 4.588 0.000: Using auto-unlock on power-up/resume > 4.592 0.004: cfi_cmdset_0001: Erase suspend on write enabled > 4.596 0.004: RedBoot partition parsing not available > 4.600 0.004: Using physmap partition information > 4.604 0.004: Creating 3 MTD partitions on "physmap-flash.0": > 4.608 0.004: 0x000000000000-0x000000080000 : "bootloaders + env" > 4.620 0.012: 0x000000080000-0x000000280000 : "kernel" > 4.628 0.008: 0x000000280000-0x000002000000 : "filesystem" > 4.636 0.008: physmap-flash.0: failed to claim resource 0 > 4.644 0.008: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron NAND > 512MiB 3,3V 8-bit) > 4.652 0.008: Creating 2 MTD partitions on "davinci_nand.1": > 4.656 0.004: 0x000000000000-0x000001900000 : "data" > 4.664 0.008: 0x000001900000-0x000020000000 : "else" > 4.672 0.008: davinci_nand davinci_nand.1: controller rev. 2.5 > 4.680 0.008: spi_davinci spi_davinci.1: Controller at 0xfef0e000 > 4.692 0.012: tun: Universal TUN/TAP device driver, 1.6 > 4.696 0.004: tun: (C) 1999-2004 Max Krasnyansky > 4.704 0.008: ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver > 4.708 0.004: ohci ohci.0: DA8xx OHCI > 4.712 0.004: ohci ohci.0: new USB bus registered, assigned bus number 2 > 4.716 0.004: Waiting for USB PHY clock good... > 4.720 0.004: ohci ohci.0: irq 59, io mem 0x01e25000 > 4.788 0.068: hub 2-0:1.0: USB hub found > 4.788 0.000: hub 2-0:1.0: 1 port detected > 4.796 0.008: Initializing USB Mass Storage driver... > 4.804 0.008: usbcore: registered new interface driver usb-storage > 4.804 0.000: USB Mass Storage support registered. > 5.804 1.000: i2c_davinci i2c_davinci.1: controller timed out > 5.808 0.004: i2c_davinci i2c_davinci.1: initiating i2c bus recovery > 5.812 0.004: tps6507x-ts: probe of tps6507x-ts failed with error -110 > what's happening? if you don't have tps650 delete its initialization. if you don't have any other chip on the board skip its config. > 5.820 0.008: omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc0 > 5.824 0.004: omap_rtc: RTC power up reset detected > 5.824 0.000: omap_rtc: already running > 5.828 0.004: i2c /dev entries driver > 5.832 0.004: TCP cubic registered > 5.836 0.004: Clocks: disable unused i2c1 > 5.840 0.004: Clocks: disable unused emac > 5.848 0.008: davinci_emac_probe: using random MAC addr: 72:93:72:ad:15:13 > 5.852 0.004: emac-mii: probed > 5.860 0.008: omap_rtc omap_rtc: setting system clock to 2000-01-01 01:34:03 > UTC (946690443) > 6.136 0.276: VFS: Mounted root (jffs2 filesystem) on device 31:2. > *6.140 0.004: Freeing init memory: 120K* > *7.356 1.216: Mounting proc* > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > bootchart: t0=0 t1=Starting Kernel=*2.812* set verify n If it is possible to know... t2=init ... how much? t3=yourapplicationworking ... how much? I hope these info can help you. Let me know, if possible, the new t1,t2,t3,t4 you may suggestions. Regards, Raffaele -------------- next part -------------- An HTML attachment was scrubbed... URL: From caglarakyuz at gmail.com Thu Jul 29 02:16:36 2010 From: caglarakyuz at gmail.com (Caglar Akyuz) Date: Thu, 29 Jul 2010 10:16:36 +0300 Subject: Boot time In-Reply-To: References: Message-ID: <201007291016.36189.caglarakyuz@gmail.com> On Wednesday 28 July 2010 10:59:53 pm Nicolas Luna wrote: > Hi guys, > Hi, > I'm trying to make by board boot as quick as possible. I did some > optimisation with the "All This For 1 Second Boot" wiki and other website. > I would like to reduce a little bit more the boot time and I wonder if you > guys could give me some clues. > > I copied my boot log below. For sure I'll remove the uboot autoboot delay > and probably build a new kernel with modules. I putted in bold part that I > think it is possible to do more optimisation. > > 1- See bullet #3. > 2- The verifying Checksum is about 400 msec is it possible to skip it? Yes.(mentioned in an other reply) > 3- It takes ~1 sec to start booting the kernel and there is a other ~1 sec > delay between the starting kernel and the beginning of the uncompressing. > Why it's so long? Ok maybe there is the copy from NOR to RAM but it should > not take more than few msec. There can be some other optimizations in u-boot. For instance, there is one extra copy of kernel image which can be removed. You can use EDMA to increase flash to ram copy speed. When I did this for my nand, I was able to get maximum performance from my NAND flash, which was not possible without DMA. In that case, use of uncompressed image was more optimal. Otherwise decompressing kernel image was faster than transferring uncompressed kernel image from flash. Disadvantage of DMA was ECC wasn't working. But my favourite optimization was removing u-boot completely and booting Linux kernel from ubl directly. Though this is not an option for everyone. > 4- It takes ~1 sec to the kernel to free 120K memory... I got enought RAM > is it possible to remove it? > There is deferred init calls concept. Patches are present in [1]. Regards, Caglar [1] http://elinux.org/Deferred_Initcalls From theo.debrouwere at barco.com Thu Jul 29 02:40:49 2010 From: theo.debrouwere at barco.com (Theo Debrouwere) Date: Thu, 29 Jul 2010 09:40:49 +0200 Subject: Boot time In-Reply-To: <201007291016.36189.caglarakyuz@gmail.com> References: <201007291016.36189.caglarakyuz@gmail.com> Message-ID: <4C513081.2090000@barco.com> > But my favourite optimization was removing u-boot completely and booting Linux > kernel from ubl directly. Though this is not an option for everyone. What did you do for this? Any UBL patch available to take a look at? Theo DISCLAIMER: Unless indicated otherwise, the information contained in this message is privileged and confidential, and is intended only for the use of the addressee(s) named above and others who have been specifically authorized to receive it. If you are not the intended recipient, you are hereby notified that any dissemination, distribution or copying of this message and/or attachments is strictly prohibited. The company accepts no liability for any damage caused by any virus transmitted by this email. Furthermore, the company does not warrant a proper and complete transmission of this information, nor does it accept liability for any delays. If you have received this message in error, please contact the sender and delete the message. Thank you. From caglarakyuz at gmail.com Thu Jul 29 04:10:11 2010 From: caglarakyuz at gmail.com (Caglar Akyuz) Date: Thu, 29 Jul 2010 12:10:11 +0300 Subject: Boot time In-Reply-To: <4C513081.2090000@barco.com> References: <201007291016.36189.caglarakyuz@gmail.com> <4C513081.2090000@barco.com> Message-ID: <201007291210.11268.caglarakyuz@gmail.com> On Thursday 29 July 2010 10:40:49 am Theo Debrouwere wrote: > > But my favourite optimization was removing u-boot completely and booting > > Linux kernel from ubl directly. Though this is not an option for > > everyone. > > What did you do for this? Any UBL patch available to take a look at? > There was an C example at [1] which I stole most of the bits but I can not find that example at the moment. I attached my code to the end of this e-mail. Then all I need to do is call following from ubl.c: extern int start_linux(void); start_linux(); If you want to look at my complete UBL, I can send it to you privately.(not to waste list bw) I have a local git tree for that. In my tree I have LCD and EDMA support for UBL as well. But my tree is for a custom DM6446 board, no EVM support in it. Regards, Caglar [1] http://www.arm.linux.org.uk/developer/booting.php > Theo > > > DISCLAIMER: > Unless indicated otherwise, the information contained in this message is > privileged and confidential, and is intended only for the use of the > addressee(s) named above and others who have been specifically authorized > to receive it. If you are not the intended recipient, you are hereby > notified that any dissemination, distribution or copying of this message > and/or attachments is strictly prohibited. The company accepts no > liability for any damage caused by any virus transmitted by this email. > Furthermore, the company does not warrant a proper and complete > transmission of this information, nor does it accept liability for any > delays. If you have received this message in error, please contact the > sender and delete the message. Thank you. > -------------- next part -------------- A non-text attachment was scrubbed... Name: linux_nand.c Type: text/x-csrc Size: 5798 bytes Desc: not available URL: From nsekhar at ti.com Thu Jul 29 04:20:32 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Thu, 29 Jul 2010 14:50:32 +0530 Subject: [PATCH v2] DaVinci: dm365: Added clockout2 management. In-Reply-To: References: <1279709510-6213-1-git-send-email-lamiaposta71@gmail.com> Message-ID: Hi Raffaele, On Mon, Jul 26, 2010 at 22:09:20, Raffaele Recalcati wrote: > 2010/7/22 Nori, Sekhar > [...] > > diff --git a/arch/arm/mach-davinci/clock.c > b/arch/arm/mach-davinci/clock.c > > index f29a526..6e45808 100644 > > --- a/arch/arm/mach-davinci/clock.c > > +++ b/arch/arm/mach-davinci/clock.c > > @@ -254,7 +254,15 @@ static unsigned long > clk_sysclk_recalc(struct clk *clk) > > u32 v, plldiv; > > struct pll_data *pll; > > unsigned long rate = clk->rate; > > + struct clk *parent = clk; > > > > + if (clk == NULL || IS_ERR(clk)) > > + return -EINVAL; > > + while (parent->parent->parent) > > + parent = parent->parent; > > + > > + if (parent == clk) > > + return -EPERM; > > > It is not clear to me why this change in needed. It is not > described in the patch description as well. Most likely this > needs to be carved into a separate patch as well describing > what is wrong with the existing clk_sysclk_recalc() routine. > > > > > now, whith the last check, we don't need that modifications, but only > > /* Otherwise, the parent must be a PLL */ > - if (WARN_ON(!parent->pll_data)) > + if (!clk->parent->pll_data) > > clkout2 is a sub-divider and so its parent is not a pll. This function is meant to recalculate the rate for a sysclk. For clkout2, a new recalculate function should be written. [...] > > +int dm365_clkout2_set_rate(unsigned long rate) > > > Is clockout2 specific to DM365? DM355/DM6446 manuals mention > clkout signal as well. If this routine can cater to more SoCs > with simple modifications, you can attempt to generalize it. > > > > we check in dm355 and clkout2 is really a different clock. > it seems difficult to integrate. > we'd prefer not to do it. Okay. [...] > > > + > > + /* check all possibilities to get best fitting for the > required freq */ > > > + i_min_err = min_err = INT_MAX; > > + for (i = 0x0F; i > 0; i--) { > > + if (clk->parent->set_rate) { > > + ret = clk_set_rate(clk->parent, rate * > i) ; > > + err = clk_get_rate(clk->parent) - rate * > i; > > + if (min_err > abs(err)) { > > + min_err = abs(err); > > + i_min_err = i; > > + } > > + } > > + } > > > Why should the child touch the parent's clock output? Users of > the > clock framework should be able to set these rates independently. > > > > right. > we tried. > the problem is that the clkout2 is used for uda1345 system clock. > without chenig the parent we can't get close. > the sound is really too fast. > You should be able to change both clocks independently. Example, in your board code: xxx uda135_set_clk_rate(xxx) { clk_set_rate(sysclkN, desired_rate); clk_set_rate(clkout2, desired_rate); } That should work? > > > > Tomorrow, if you agree, I'll send you 2 patches: > -patch1: clkout2 This is fine.. > -patch2: removing warn from sysclk recalc ... but as I wrote above, still don't see a need for this. Thanks, Sekhar From luna.id at gmail.com Thu Jul 29 06:28:55 2010 From: luna.id at gmail.com (Nicolas Luna) Date: Thu, 29 Jul 2010 07:28:55 -0400 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> Message-ID: Sekhar, Thank you for the advice. I would like to know if you are aware of the modification that will be made by Logic. I suppose that if Logic is in the loop it means that the problem is hardware? I have custom hardware based on OMAPL138 EVM. We are releasing the REV2 very soon, so maybe I could change it. Thanks. Regards, Nicolas On Thu, Jul 29, 2010 at 1:12 AM, Nori, Sekhar wrote: > Hi Nicolas, > > On Thu, Jul 29, 2010 at 02:16:16, Nicolas Luna wrote: > > Todd, > > > > What do I need to change if I want to use the bitbang i2c driver and > > stop to get those error messages. > > You can try the patch here: > http://arago-project.org/git/projects/?p=linux-omapl1.git;a=commit;h=7d8accda275fdbe6e727e7ac02ae5a92f5695326 > > This issue should be fixed in future revisions of Logic EVMs so this patch > wont be needed afterward. > > Thanks, > Sekhar > -------------- next part -------------- An HTML attachment was scrubbed... URL: From michael.williamson at criticallink.com Thu Jul 29 06:29:56 2010 From: michael.williamson at criticallink.com (Michael Williamson) Date: Thu, 29 Jul 2010 07:29:56 -0400 Subject: [PATCH v4] davinci: Add MityDSP-L138/MityARM-1808 SOM support Message-ID: <4C516634.5040804@criticallink.com> This patch adds support for the MityDSP-L138 and MityARM-1808 system on module (SOM) under the registered machine "mityomapl138". These SOMs are based on the da850 davinci CPU architecture. Information on these SOMs may be found at http://www.mitydsp.com. Signed-off-by: Michael Williamson --- This patch is against Kevin's tree, but is dependent on the following patch, which is queued for 2.6.36: [1] http://git.kernel.org/?p=linux/kernel/git/broonie/sound-2.6.git;a=commit;h=48519f0ae03bc7e86b3dc93e56f1334d53803770 Changes since v3 patch was submitted: * renamed ATAG_PERIPHERALS to ATAG_MITYDSPL138 * removed unused header files * renamed config structure items to remove camel case naming * don't use GPIO if resources aren't acquired * don't use device_initcall on emac config * handle upcoming patch to platform sound config * clean up mcasp configuration * misc cleanup per comments arch/arm/configs/da8xx_omapl_defconfig | 291 ++++++- arch/arm/include/asm/setup.h | 5 + arch/arm/mach-davinci/Kconfig | 8 + arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/board-mityomapl138.c | 806 ++++++++++++++++++++ .../mach-davinci/include/mach/cb-mityomapl138.h | 120 +++ arch/arm/mach-davinci/include/mach/da8xx.h | 1 + arch/arm/mach-davinci/include/mach/uncompress.h | 1 + 8 files changed, 1190 insertions(+), 43 deletions(-) diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig index e14c99c..0dd0d00 100644 --- a/arch/arm/configs/da8xx_omapl_defconfig +++ b/arch/arm/configs/da8xx_omapl_defconfig @@ -1,13 +1,15 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc5 -# Thu Oct 22 12:19:19 2009 +# Linux kernel version: 2.6.35-rc3 +# Tue Jul 20 08:30:23 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_HAVE_LATENCYTOP_SUPPORT=y @@ -20,6 +22,7 @@ CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -32,8 +35,16 @@ CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -48,6 +59,7 @@ CONFIG_POSIX_MQUEUE_SYSCTL=y # CONFIG_TREE_RCU=y # CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set # CONFIG_RCU_TRACE is not set CONFIG_RCU_FANOUT=32 # CONFIG_RCU_FANOUT_EXACT is not set @@ -55,11 +67,6 @@ CONFIG_RCU_FANOUT=32 CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set # CONFIG_CGROUPS is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set @@ -69,6 +76,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -90,10 +98,14 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y @@ -131,14 +143,41 @@ CONFIG_LBDAF=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set -CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set # CONFIG_FREEZER is not set # @@ -149,8 +188,11 @@ CONFIG_MMU=y # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set # CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set @@ -159,7 +201,6 @@ CONFIG_MMU=y # CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -167,6 +208,7 @@ CONFIG_MMU=y # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_KIRKWOOD is not set # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set @@ -175,20 +217,27 @@ CONFIG_MMU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set CONFIG_ARCH_DAVINCI=y # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set +# CONFIG_PLAT_SPEAR is not set CONFIG_CP_INTC=y # @@ -205,18 +254,18 @@ CONFIG_ARCH_DAVINCI_DA830=y CONFIG_ARCH_DAVINCI_DA850=y CONFIG_ARCH_DAVINCI_DA8XX=y # CONFIG_ARCH_DAVINCI_DM365 is not set +# CONFIG_ARCH_DAVINCI_TNETV107X is not set # # DaVinci Board Type # CONFIG_MACH_DAVINCI_DA830_EVM=y -CONFIG_DA830_UI=y CONFIG_DA830_UI_LCD=y # CONFIG_DA830_UI_NAND is not set CONFIG_MACH_DAVINCI_DA850_EVM=y -CONFIG_DA850_UI_EXP=y CONFIG_DA850_UI_NONE=y # CONFIG_DA850_UI_RMII is not set +CONFIG_MACH_MITYOMAPL138=y CONFIG_DAVINCI_MUX=y # CONFIG_DAVINCI_MUX_DEBUG is not set # CONFIG_DAVINCI_MUX_WARNINGS is not set @@ -270,6 +319,7 @@ CONFIG_PREEMPT=y CONFIG_HZ=100 CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set # CONFIG_HIGHMEM is not set @@ -280,13 +330,11 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 +CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_LEDS=y @@ -354,7 +402,6 @@ CONFIG_NET=y # Networking options # CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set @@ -404,6 +451,7 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m CONFIG_INET6_XFRM_MODE_BEET=m # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_IPV6_TUNNEL is not set # CONFIG_IPV6_MULTIPLE_TABLES is not set @@ -440,6 +488,7 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set +# CONFIG_L2TP is not set # CONFIG_BRIDGE is not set # CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set @@ -465,10 +514,21 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set +# CONFIG_CAIF is not set # # Device Drivers @@ -486,12 +546,110 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_FTL=y +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_CFI_AMDSTD is not set +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_NAND_DAVINCI=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=m # CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 @@ -501,9 +659,12 @@ CONFIG_BLK_DEV_RAM_SIZE=32768 # CONFIG_ATA_OVER_ETH is not set # CONFIG_MG_DISK is not set CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set # CONFIG_C2PORT is not set # @@ -519,6 +680,7 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=m # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=m CONFIG_SCSI_DMA=y @@ -583,6 +745,7 @@ CONFIG_LXT_PHY=y # CONFIG_NATIONAL_PHY is not set # CONFIG_STE10XP is not set CONFIG_LSI_ET1011C_PHY=y +# CONFIG_MICREL_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y @@ -608,8 +771,7 @@ CONFIG_TI_DAVINCI_EMAC=y # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set +# CONFIG_HOSTAP is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -631,6 +793,7 @@ CONFIG_NET_POLL_CONTROLLER=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -652,6 +815,7 @@ CONFIG_KEYBOARD_ATKBD=m # CONFIG_QT2160 is not set # CONFIG_KEYBOARD_LKKBD is not set CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_TCA6416 is not set # CONFIG_KEYBOARD_MATRIX is not set # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_NEWTON is not set @@ -665,6 +829,8 @@ CONFIG_KEYBOARD_XTKBD=m CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_AD7879_I2C is not set # CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set # CONFIG_TOUCHSCREEN_EETI is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set @@ -680,6 +846,7 @@ CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set # CONFIG_TOUCHSCREEN_TSC2007 is not set # CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set # CONFIG_INPUT_MISC is not set # @@ -689,6 +856,7 @@ CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_GAMEPORT is not set # @@ -701,6 +869,7 @@ CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set # # Serial drivers @@ -716,6 +885,9 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=3 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y @@ -726,6 +898,7 @@ CONFIG_HW_RANDOM=m # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y @@ -743,7 +916,9 @@ CONFIG_I2C_DAVINCI=y # CONFIG_I2C_DESIGNWARE is not set # CONFIG_I2C_GPIO is not set # CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set # # External I2C/SMBus adapter drivers @@ -754,18 +929,10 @@ CONFIG_I2C_DAVINCI=y # # Other I2C/SMBus bus drivers # -# CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set # @@ -780,13 +947,17 @@ CONFIG_GPIOLIB=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: # +# CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set CONFIG_GPIO_PCA953X=y +# CONFIG_GPIO_PCA953X_IRQ is not set CONFIG_GPIO_PCF857X=y +# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: @@ -799,6 +970,10 @@ CONFIG_GPIO_PCF857X=y # # AC97 GPIO expanders: # + +# +# MODULbus GPIO expanders: +# # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set @@ -811,42 +986,50 @@ CONFIG_WATCHDOG=y # # CONFIG_SOFT_WATCHDOG is not set # CONFIG_DAVINCI_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # # CONFIG_SSB is not set - -# -# Multifunction device drivers -# +CONFIG_MFD_SUPPORT=y # CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set # CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set # CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TC35892 is not set # CONFIG_MFD_TMIO is not set # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set # CONFIG_MFD_PCF50633 is not set -# CONFIG_AB3100_CORE is not set +# CONFIG_ABX500_CORE is not set CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set # CONFIG_REGULATOR_FIXED_VOLTAGE is not set # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set # CONFIG_REGULATOR_BQ24022 is not set # CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set # CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set +CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS6507X=y # CONFIG_MEDIA_SUPPORT is not set @@ -950,10 +1133,6 @@ CONFIG_RTC_LIB=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set # @@ -1033,6 +1212,22 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -1062,6 +1257,7 @@ CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m # CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set @@ -1184,6 +1380,7 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set # CONFIG_SYSCTL_SYSCALL_CHECK is not set @@ -1205,6 +1402,7 @@ CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_WORKQUEUE_TRACER is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1213,6 +1411,7 @@ CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set # # Security options @@ -1220,7 +1419,11 @@ CONFIG_DEBUG_ERRORS=y # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # @@ -1323,9 +1526,11 @@ CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y CONFIG_DECOMPRESS_GZIP=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index f392fb4..1d3a8cf 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -143,6 +143,11 @@ struct tag_memclk { __u32 fmemclk; }; +/** MityDSP-L138 peripheral configuration info, + * see arch/arm/mach-davinci/include/mach/cb-mityomapl138.h + */ +#define ATAG_MITYDSPL138 0x42000101 + struct tag { struct tag_header hdr; union { diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 71f90f8..8fcf47d 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -178,6 +178,14 @@ config DA850_UI_RMII endchoice +config MACH_MITYOMAPL138 + bool "Critical Link MityDSP-L138/MityARM-1808 SoM" + depends on ARCH_DAVINCI_DA850 + help + Say Y here to select the Critical Link MityDSP-L138/MityARM-1808 + System on Module. Information on this SoM may be found at + http://www.mitydsp.com. + config MACH_TNETV107X bool "TI TNETV107X Reference Platform" default ARCH_DAVINCI_TNETV107X diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index eab4c0f..dfc0fc4 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o +obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o # Power Management diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c new file mode 100644 index 0000000..57a4ab4 --- /dev/null +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -0,0 +1,806 @@ +/* + * Critical Link MityOMAP-L138 SoM + * + * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com + * + * Derived from board-da850-evm.c + * Original Copyrights follow: + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from: arch/arm/mach-davinci/board-da830-evm.c + * Original Copyrights follow: + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct tag_peripherals peripheral_config = { + .version = PERIPHERALS_VERSION, + .manufacturer = "Critical Link", + .enet.enet_config = ENET_CONFIG_MII, + .enet.mac = { 0x00, 0x50, 0xC2, 0x49, 0xDF, 0xFF }, + .uart[0] = { + .enable = 0, + .is_console = 0, + .baud = 115200, + }, + .uart[1] = { + .enable = 1, + .is_console = 1, + .baud = 115200, + }, + .uart[2] = { + .enable = 0, + .is_console = 0, + .baud = 115200, + }, + .spi[0] = { + .enable = 0, + .clkout = 0, + .cs_enable = { 0, 0, 0, 0, 0, 0, 0, 0}, + .ena_enable = 0, + .clkrate = 0, + }, + .spi[1] = { + .enable = 1, + .clkout = 1, + .cs_enable = { 1, 0, 0, 0, 0, 0, 0, 0}, + .ena_enable = 0, + .clkrate = 30000000, + }, + .lcd = { + .enable = 0, + .panel_name = "", + } +}; + + +#define MITYOMAPL138_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ + +#define MSTPRI2_LCD_MASK 0x70000000 +#define MSTPRI2_LCD_SHIFT 28 + +#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) +#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) + +/* MityDSP-L138 includes a 256 MByte large-page NAND flash + * (128K blocks). + */ +struct mtd_partition mityomapl138_nandflash_partition[] = { + { + .name = "rootfs", + .offset = 0, + .size = SZ_128M, + .mask_flags = 0, /* MTD_WRITEABLE, */ + }, + { + .name = "homefs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct davinci_nand_pdata mityomapl138_nandflash_data = { + .parts = mityomapl138_nandflash_partition, + .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16, + .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ +}; + +static struct resource mityomapl138_nandflash_resource[] = { + { + .start = DA8XX_AEMIF_CS3_BASE, + .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mityomapl138_nandflash_device = { + .name = "davinci_nand", + .id = 0, + .dev = { + .platform_data = &mityomapl138_nandflash_data, + }, + .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), + .resource = mityomapl138_nandflash_resource, +}; + +static struct platform_device *mityomapl138_devices[] __initdata = { + &mityomapl138_nandflash_device, +}; + +static void __init mityomapl138_setup_nand(void) +{ + platform_add_devices(mityomapl138_devices, + ARRAY_SIZE(mityomapl138_devices)); +} + +static int mityomapl138_mmc_get_ro(int index) +{ + return gpio_get_value(DA850_MMCSD_WP_PIN); +} + +static int mityomapl138_mmc_get_cd(int index) +{ + return !gpio_get_value(DA850_MMCSD_CD_PIN); +} + +static struct davinci_mmc_config da850_mmc_config = { + .get_ro = mityomapl138_mmc_get_ro, + .get_cd = mityomapl138_mmc_get_cd, + .wires = 4, + .max_freq = 50000000, + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + .version = MMC_CTLR_VERSION_2, +}; + +static void __init mityomapl138_setup_mmc(void) +{ + int ret; + + ret = davinci_cfg_reg_list(da850_mmcsd0_pins); + if (ret) { + pr_warning("mmcsd0 mux setup failed: %d\n" ,ret); + return; + } + ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n"); + if (ret) { + pr_warning("can not open GPIO %d\n", DA850_MMCSD_CD_PIN); + return; + } + gpio_direction_input(DA850_MMCSD_CD_PIN); + + ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n"); + if (ret) { + pr_warning("can not open GPIO %d\n", DA850_MMCSD_WP_PIN); + return; + } + gpio_direction_input(DA850_MMCSD_WP_PIN); + + ret = da8xx_register_mmcsd0(&da850_mmc_config); + if (ret) { + pr_warning("mmcsd0 registration failed: %d\n", ret); + return; + } +} + +static struct davinci_uart_config mityomapl138_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static void __init mityomapl138_config_emac(void) +{ + void __iomem *cfg_chip3_base; + int ret; + u32 val; + struct davinci_soc_info *soc_info = &davinci_soc_info; + u8 rmii_en = 0; + + switch (peripheral_config.enet.enet_config) { + case ENET_CONFIG_RMII: + soc_info->emac_pdata->rmii_en = 1; + rmii_en = 1; + break; + case ENET_CONFIG_MII: + soc_info->emac_pdata->rmii_en = 0; + rmii_en = 0; + break; + case ENET_CONFIG_NONE: + default: + pr_info("No Ethernet PHY Selected, EMAC disabled\n"); + return; /* no enet... */ + break; + } + memcpy(&soc_info->emac_pdata->mac_addr[0], + &peripheral_config.enet.mac[0], 6); + + cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); + + val = __raw_readl(cfg_chip3_base); + + if (rmii_en) { + val |= BIT(8); + ret = davinci_cfg_reg_list(da850_rmii_pins); + pr_info("RMII PHY configured, MII PHY will not be functional\n"); + } else { + val &= ~BIT(8); + ret = davinci_cfg_reg_list(da850_cpgmac_pins); + pr_info("MII PHY configured, RMII PHY will not be functional\n"); + } + + if (ret) { + pr_warning("cpgmac/rmii mux setup failed: %d\n", ret); + return; + } + + /* configure the CFGCHIP3 register for RMII or MII */ + __raw_writel(val, cfg_chip3_base); + + soc_info->emac_pdata->phy_mask = peripheral_config.enet.phy_mask ? + peripheral_config.enet.phy_mask : 1; + pr_info("setting phy_mask to %x\n", soc_info->emac_pdata->phy_mask); + soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY; + + ret = da8xx_register_emac(); + if (ret) + pr_warning("emac registration failed: %d\n", ret); +} + +static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { + .bus_freq = 100, /* kHz */ + .bus_delay = 0, /* usec */ +}; + +/* TPS65023 voltage regulator support */ + +/* 1.2V Core */ +struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { + { + .supply = "cvdd", + }, +}; + +/* 1.8V */ +struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { + { + .supply = "usb0_vdda18", + }, + { + .supply = "usb1_vdda18", + }, + { + .supply = "ddr_dvdd18", + }, + { + .supply = "sata_vddr", + }, +}; + +/* 1.2V */ +struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { + { + .supply = "sata_vdd", + }, + { + .supply = "usb_cvdd", + }, + { + .supply = "pll0_vdda", + }, + { + .supply = "pll1_vdda", + }, +}; + +/* 1.8V Aux LDO */ +struct regulator_consumer_supply tps65023_ldo1_consumers[] = { + { + .supply = "1.8v_aux", + }, +}; + +/* VCC Aux (1.8 or 3.3) LDO */ +struct regulator_consumer_supply tps65023_ldo2_consumers[] = { + { + .supply = "vccaux", + }, +}; + + +struct regulator_init_data tps65023_regulator_data[] = { + /* dcdc1 */ + { + .constraints = { + .min_uV = 1150000, + .max_uV = 1350000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers), + .consumer_supplies = tps65023_dcdc1_consumers, + }, + + /* dcdc2 */ + { + .constraints = { + .min_uV = 1710000, + .max_uV = 1910000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers), + .consumer_supplies = tps65023_dcdc2_consumers, + }, + + /* dcdc3 */ + { + .constraints = { + .min_uV = 1120000, + .max_uV = 1320000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers), + .consumer_supplies = tps65023_dcdc3_consumers, + }, + + /* ldo1 */ + { + .constraints = { + .min_uV = 1710000, + .max_uV = 1890000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers), + .consumer_supplies = tps65023_ldo1_consumers, + }, + + /* ldo2 */ + { + .constraints = { + .min_uV = 3140000, + .max_uV = 3420000, + .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS), + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers), + .consumer_supplies = tps65023_ldo2_consumers, + }, +}; + + +static struct i2c_board_info __initdata mityomap_tps65023_info[] = { + { + I2C_BOARD_INFO("tps65023", 0x48), + .platform_data = &tps65023_regulator_data[0], + }, + { + I2C_BOARD_INFO("24c02", 0x50), + }, +}; + +static int __init pmic_tps65023_init(void) +{ + return i2c_register_board_info(1, mityomap_tps65023_info, + ARRAY_SIZE(mityomap_tps65023_info)); +} + +static struct davinci_spi_platform_data mityomap_spi1_pdata = { + .version = SPI_VERSION_2, + .num_chipselect = 1, + .wdelay = 0, + .odd_parity = 0, + .parity_enable = 0, + .wait_enable = 0, + .timer_disable = 0, + .clk_internal = 1, + .cs_hold = 1, + .intr_level = 0, + .poll_mode = 1, + .use_dma = 0, + .c2tdelay = 8, + .t2cdelay = 8, +}; + +static struct resource mityomap_spi1_resources[] = { + [0] = { + .start = 0x01F0E000, + .end = 0x01F0EFFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DA8XX_SPINT1, + .start = IRQ_DA8XX_SPINT1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = EDMA_CTLR_CHAN(0, 18), + .end = EDMA_CTLR_CHAN(0, 18), + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = EDMA_CTLR_CHAN(0, 19), + .end = EDMA_CTLR_CHAN(0, 19), + .flags = IORESOURCE_DMA, + }, + [4] = { + .start = 1, + .end = 1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device mityomap_spi1_device = { + .name = "spi_davinci", + .id = 1, + .dev = { + .platform_data = &mityomap_spi1_pdata, + }, + .num_resources = ARRAY_SIZE(mityomap_spi1_resources), + .resource = mityomap_spi1_resources, +}; + +/***************************************************************************** + * SPI Devices: + * SPI1_CS0: 8M Flash ST-M25P64-VME6G + ****************************************************************************/ +static struct mtd_partition spi_flash_partitions[] = { + [0] = { + .name = "UBL", + .offset = 0, + .size = SZ_64K, + .mask_flags = MTD_WRITEABLE + }, + [1] = { + .name = "U-Boot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = 0, + }, + [2] = { + .name = "Spare", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct flash_platform_data mityomap_spi_flash_data = { + .name = "m25p80", + .parts = spi_flash_partitions, + .nr_parts = ARRAY_SIZE(spi_flash_partitions), + .type = "m25p64", +}; + +static struct spi_board_info mityomap_spi_flash_info[] = { + { + .modalias = "m25p80", + .platform_data = &mityomap_spi_flash_data, + .mode = SPI_MODE_0, + .max_speed_hz = 30000000, + .bus_num = 1, + .chip_select = 0, + }, +}; + +void __init mityomap_init_spi1(unsigned chipselect_mask, + struct spi_board_info *info, unsigned len) +{ + int ret; + ret = platform_device_register(&mityomap_spi1_device); + if (ret) + pr_warning("failed to register spi device : %d\n", ret); + + ret = spi_register_board_info(info, len); + if (ret) + pr_warning("failed to register board info : %d\n", ret); +} + +/* davinci da850 evm audio machine driver */ +static u8 da850_iis_serializer_direction[16]; + +static struct snd_platform_data mityomapl138_snd_data = { + .tx_dma_offset = 0x2000, + .rx_dma_offset = 0x2000, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), + .tdm_slots = 2, + .serial_dir = da850_iis_serializer_direction, + .asp_chan_q = EVENTQ_1, + .version = MCASP_VERSION_2, + .txnumevt = 0, + .rxnumevt = 0, +}; + +short mityomapl138_mcasp_pins[24] __initdata = { + DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, + DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, + DA850_AMUTE, +}; + +static __init void mityomapl138_setup_mcasp(void) +{ + int ret, i, j; + + if (!peripheral_config.mcasp.enable) + return; + + j = 7; /* start after AMUTE pin */ + for (i = 0; iu.cmdline.cmdline[0]; + memcpy(&peripheral_config, ptag, sizeof(peripheral_config)); + pr_info("Peripheral Config Block Found\n"); + pr_info("Enet_Config = %d\n", peripheral_config.enet.enet_config); + pr_info("EMAC = %pM\n", peripheral_config.enet.mac); + pr_info("PHYMask = 0x%x\n", peripheral_config.enet.phy_mask); + if (peripheral_config.lcd.enable) + pr_info("LCD Configured : %s\n", + peripheral_config.lcd.panel_name); + else + pr_info("No LCD Configured\n"); + + for (i = 0; i < 3; i++) { + pr_info("UART[%d] : Enable=%d, Cons=%d, FlwCtl=%d, Baud=%d\n", + i, + peripheral_config.uart[i].enable, + peripheral_config.uart[i].is_console, + peripheral_config.uart[i].enable_flowctl, + peripheral_config.uart[i].baud); + } + for (i = 0; i < 2; i++) { + int mask = 0; + for (j = 0; j < 8; j++) + mask |= ((peripheral_config.spi[i].cs_enable[j]) ? + (1<> 18) & 0xfffc, + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = mityomapl138_map_io, + .init_irq = cp_intc_init, + .timer = &davinci_timer, + .init_machine = mityomapl138_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h new file mode 100644 index 0000000..547c876 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/cb-mityomapl138.h @@ -0,0 +1,120 @@ +/** + * Factory / Peripheral Configuration Data as provided by ATAG_PERIPHERAL + * for the MityDSP-L138 SOMs. (mityomapl138 machines) + * + * Copyright (C) 2010 Critical Link LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef CB_MITYOMAPL138_H_ +#define CB_MITYOMAPL138_H_ + +#define CONFIG_MAGIC_WORD 0x00BD0138 +#define CONFIG_VERSION 0x00010000 + +#define ENET_CONFIG_NONE 1 +#define ENET_CONFIG_MII 2 +#define ENET_CONFIG_RMII 3 + +#define CONFIG_I2C_MAGIC_WORD 0x012C0138 +#define CONFIG_I2C_VERSION 0x00010001 + +/** + * Peripherals Version History + * 1.00 Baseline + * 1.01 Added McASP Configuration + * 1.02 Added ethernet phy mask + */ +#define PERIPHERALS_VERSION 0x00010002 + +#ifndef CONFIG_MITYDSP_ENV_SIZE +#define CONFIG_MITYDSP_ENV_SIZE (64 << 10) +#endif + +#define FPGATYPE_NONE 0 +#define FPGATYPE_XC6SLX9 1 +#define FPGATYPE_XC6SLX16 2 +#define FPGATYPE_XC6SLX25 3 +#define FPGATYPE_XC6SLX45 4 +#define FPGATYPE_UNKNOWN 10000 + +struct i2c_factory_config { + u32 magic_word; /** CONFIG_I2C_MAGIC_WORD */ + u32 version; /** CONFIG_I2C_VERSION */ + u8 mac[6]; /** mac address assigned to part */ + u32 fpga; /** fpga installed, see above */ + u32 spare; /** Not Used */ + u32 serial_no; /** serial number of part */ + char partnum[32]; /** board part number */ +}; + +struct uart_config { + u8 enable; /** enable Tx/Rx */ + u8 is_console; /** cfg as the console */ + u8 enable_flowctl; /** cfg CTS/RTS */ + u32 baud; /** default baud rate */ +}; + +struct spi_config { + u8 enable; /** cfg dev+CLK, SIMO, SOMI pins */ + u8 clkout; /** drive the CLK */ + u8 cs_enable[8]; /** cfg the associated CS as output */ + u8 ena_enable; /** cfg the ENA pin for SPI function */ + u32 clkrate; /** default clock rate */ + u8 spare[8]; +}; + +struct lcd_config { + u8 enable; + u8 panel_name[32]; +}; + +struct enet_config { + u32 enet_config; + u8 mac[6]; + u32 phy_mask; + u8 spare[8]; +}; + +#define MCASP_PINMODE_INACTIVE 0 +#define MCASP_PINMODE_TX 1 +#define MCASP_PINMODE_RX 2 + +struct mcasp_config { + u8 enable; + u8 mode; + u8 pin_mode[16]; +}; +/** + * struct tag_peripherals is passed in via kernel ATAG_PERIPHERALS + */ +struct tag_peripherals { + u32 version; /** == PERIPHERALS_VERSION */ + u8 manufacturer[64]; /** null terminated string indicating manufacturer */ + struct enet_config enet; /** Enable on-board ethernet */ + struct uart_config uart[3]; /** default UART 0,1,2 Configuration */ + struct spi_config spi[2]; + struct lcd_config lcd; + struct mcasp_config mcasp; +}; + +/** + * This structure can only be grown. You cannot make it smaller... + */ +struct mitydspl138_config { + u32 magic_word; /** == CONFIG_MAGIC_WORD */ + u32 version; /** version of the configuration block */ + u32 config_size; /** configuration size, in bytes */ + struct tag_peripherals peripherals; +}; + +struct mitydspl138_config_block { + union { + struct mitydspl138_config config; + u8 space[CONFIG_MITYDSP_ENV_SIZE-sizeof(int)]; + } data; + unsigned int checksum; /** summed bytes of ConfigSizeBytes */ +}; + +#endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 1b31a9a..1989316 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -41,6 +41,7 @@ extern void __iomem *da8xx_syscfg1_base; #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) #define DA8XX_JTAG_ID_REG 0x18 +#define DA8XX_MSTPRI2_REG 0x118 #define DA8XX_CFGCHIP0_REG 0x17c #define DA8XX_CFGCHIP2_REG 0x184 #define DA8XX_CFGCHIP3_REG 0x188 diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 15a6192..db6f1cd 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -88,6 +88,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* DA8xx boards */ DEBUG_LL_DA8XX(davinci_da830_evm, 2); DEBUG_LL_DA8XX(davinci_da850_evm, 2); + DEBUG_LL_DA8XX(mityomapl138, 1); /* TNETV107x boards */ DEBUG_LL_TNETV107X(tnetv107x, 1); From todd.fischer at ridgerun.com Thu Jul 29 06:43:10 2010 From: todd.fischer at ridgerun.com (Todd Fischer) Date: Thu, 29 Jul 2010 05:43:10 -0600 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> Message-ID: <1280403790.22713.8.camel@sax-lx> Nicolas, Also, due to another hardware limitation, the touch screen driver using polling instead of interrupts. I heard a hardware change that will allow for interrupts to be used is planned as well. The polling overhead costs around 2% ARM CPU. Todd On Thu, 2010-07-29 at 10:42 +0530, Nori, Sekhar wrote: > Hi Nicolas, > > On Thu, Jul 29, 2010 at 02:16:16, Nicolas Luna wrote: > > Todd, > > > > What do I need to change if I want to use the bitbang i2c driver and > > stop to get those error messages. > > You can try the patch here: http://arago-project.org/git/projects/?p=linux-omapl1.git;a=commit;h=7d8accda275fdbe6e727e7ac02ae5a92f5695326 > > This issue should be fixed in future revisions of Logic EVMs so this patch > wont be needed afterward. > > Thanks, > Sekhar -------------- next part -------------- An HTML attachment was scrubbed... URL: From luna.id at gmail.com Thu Jul 29 07:24:50 2010 From: luna.id at gmail.com (Nicolas Luna) Date: Thu, 29 Jul 2010 08:24:50 -0400 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: <1280403790.22713.8.camel@sax-lx> References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> <1280403790.22713.8.camel@sax-lx> Message-ID: Todd, Yes the polling is not such a problem because 2% is not that much. Probably that the bitbang will be more than that it's why I would like to avoid it. If there is a hardware mod to correct NACK problem I'll be glad to apply it. Thanks, Nicolas On Thu, Jul 29, 2010 at 7:43 AM, Todd Fischer wrote: > Nicolas, > > Also, due to another hardware limitation, the touch screen driver using > polling instead of interrupts. I heard a hardware change that will allow > for interrupts to be used is planned as well. The polling overhead costs > around 2% ARM CPU. > > Todd > > > On Thu, 2010-07-29 at 10:42 +0530, Nori, Sekhar wrote: > > Hi Nicolas, > > On Thu, Jul 29, 2010 at 02:16:16, Nicolas Luna wrote: > > Todd, > > > > What do I need to change if I want to use the bitbang i2c driver and > > stop to get those error messages. > > You can try the patch here: http://arago-project.org/git/projects/?p=linux-omapl1.git;a=commit;h=7d8accda275fdbe6e727e7ac02ae5a92f5695326 > > This issue should be fixed in future revisions of Logic EVMs so this patch > wont be needed afterward. > > Thanks, > Sekhar > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From srk at ti.com Thu Jul 29 07:33:58 2010 From: srk at ti.com (Sriramakrishnan) Date: Thu, 29 Jul 2010 18:03:58 +0530 Subject: [PATCH 1/3] TI DaVinci EMAC : Implement interrupt pacing functionality. Message-ID: <1280406840-27393-1-git-send-email-srk@ti.com> DaVinci EMAC module includes an interrupt pacing block that can be programmed to throttle the rate at which interrupts are generated. This patch implements interrupt pacing logic that can be controlled through the ethtool interface(only rx_coalesce_usecs param is honored) Signed-off-by: Sriramakrishnan --- drivers/net/davinci_emac.c | 133 +++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 131 insertions(+), 2 deletions(-) diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 08e82b1..bc1b270 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -298,6 +298,11 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; #define EMAC_CTRL_EWCTL (0x4) #define EMAC_CTRL_EWINTTCNT (0x8) +/* EMAC DM644x control module masks */ +#define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF +#define EMAC_DM644X_INTMIN_INTVL 0x1 +#define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK) + /* EMAC MDIO related */ /* Mask & Control defines */ #define MDIO_CONTROL_CLKDIV (0xFF) @@ -318,8 +323,20 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; #define MDIO_CONTROL (0x04) /* EMAC DM646X control module registers */ -#define EMAC_DM646X_CMRXINTEN (0x14) -#define EMAC_DM646X_CMTXINTEN (0x18) +#define EMAC_DM646X_CMINTCTRL 0x0C +#define EMAC_DM646X_CMRXINTEN 0x14 +#define EMAC_DM646X_CMTXINTEN 0x18 +#define EMAC_DM646X_CMRXINTMAX 0x70 +#define EMAC_DM646X_CMTXINTMAX 0x74 + +/* EMAC DM646X control module masks */ +#define EMAC_DM646X_INTPACEEN (0x3 << 16) +#define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0) +#define EMAC_DM646X_CMINTMAX_CNT 63 +#define EMAC_DM646X_CMINTMIN_CNT 2 +#define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT) +#define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1) + /* EMAC EOI codes for C0 */ #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) @@ -468,6 +485,8 @@ struct emac_priv { u32 duplex; /* Link duplex: 0=Half, 1=Full */ u32 rx_buf_size; u32 isr_count; + u32 coal_intvl; + u32 bus_freq_mhz; u8 rmii_en; u8 version; struct net_device_stats net_dev_stats; @@ -692,6 +711,103 @@ static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) } /** + * emac_get_coalesce : Get interrupt coalesce settings for this device + * @ndev : The DaVinci EMAC network adapter + * @coal : ethtool coalesce settings structure + * + * Fetch the current interrupt coalesce settings + * + */ +static int emac_get_coalesce(struct net_device *ndev, + struct ethtool_coalesce *coal) +{ + struct emac_priv *priv = netdev_priv(ndev); + + coal->rx_coalesce_usecs = priv->coal_intvl; + return 0; + +} + +/** + * emac_set_coalesce : Set interrupt coalesce settings for this device + * @ndev : The DaVinci EMAC network adapter + * @coal : ethtool coalesce settings structure + * + * Set interrupt coalesce parameters + * + */ +static int emac_set_coalesce(struct net_device *ndev, + struct ethtool_coalesce *coal) +{ + struct emac_priv *priv = netdev_priv(ndev); + u32 int_ctrl, num_interrupts = 0; + u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0; + + if (!coal->rx_coalesce_usecs) + return -EINVAL; + + coal_intvl = coal->rx_coalesce_usecs; + + switch (priv->version) { + case EMAC_VERSION_2: + int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL); + prescale = priv->bus_freq_mhz * 4; + + if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL) + coal_intvl = EMAC_DM646X_CMINTMIN_INTVL; + + if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) { + /* + * Interrupt pacer works with 4us Pulse, we can + * throttle further by dilating the 4us pulse. + */ + addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale; + + if (addnl_dvdr > 1) { + prescale *= addnl_dvdr; + if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL + * addnl_dvdr)) + coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL + * addnl_dvdr); + } else { + addnl_dvdr = 1; + coal_intvl = EMAC_DM646X_CMINTMAX_INTVL; + } + } + + num_interrupts = (1000 * addnl_dvdr) / coal_intvl; + + int_ctrl |= EMAC_DM646X_INTPACEEN; + int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK); + int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK); + emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl); + + emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts); + emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts); + + break; + default: + int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT); + int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK); + prescale = coal_intvl * priv->bus_freq_mhz; + if (prescale > EMAC_DM644X_EWINTCNT_MASK) { + prescale = EMAC_DM644X_EWINTCNT_MASK; + coal_intvl = prescale / priv->bus_freq_mhz; + } + emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale)); + + break; + } + + printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl); + priv->coal_intvl = coal_intvl; + + return 0; + +} + + +/** * ethtool_ops: DaVinci EMAC Ethtool structure * * Ethtool support for EMAC adapter @@ -702,6 +818,8 @@ static const struct ethtool_ops ethtool_ops = { .get_settings = emac_get_settings, .set_settings = emac_set_settings, .get_link = ethtool_op_get_link, + .get_coalesce = emac_get_coalesce, + .set_coalesce = emac_set_coalesce, }; /** @@ -2437,6 +2555,14 @@ static int emac_dev_open(struct net_device *ndev) /* Start/Enable EMAC hardware */ emac_hw_enable(priv); + /* Enable Interrupt pacing if configured */ + if (priv->coal_intvl != 0) { + struct ethtool_coalesce coal; + + coal.rx_coalesce_usecs = (priv->coal_intvl << 4); + emac_set_coalesce(ndev, &coal); + } + /* find the first phy */ priv->phydev = NULL; if (priv->phy_mask) { @@ -2677,6 +2803,9 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev) priv->int_enable = pdata->interrupt_enable; priv->int_disable = pdata->interrupt_disable; + priv->coal_intvl = 0; + priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000); + emac_dev = &ndev->dev; /* Get EMAC platform data */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- 1.6.2.4 From srk at ti.com Thu Jul 29 07:34:00 2010 From: srk at ti.com (Sriramakrishnan) Date: Thu, 29 Jul 2010 18:04:00 +0530 Subject: [PATCH 3/3] TI DaVinci EMAC: Fix incorrect reference to EMAC_CTRL registers. In-Reply-To: <1280406840-27393-2-git-send-email-srk@ti.com> References: <1280406840-27393-1-git-send-email-srk@ti.com> <1280406840-27393-2-git-send-email-srk@ti.com> Message-ID: <1280406840-27393-3-git-send-email-srk@ti.com> The EMAC modules control registers vary as per the version of the EMAC module. EMAC_CTRL_EWCTL,EMAC_CTRL_EWINTTCNT are available only on EMAC_VERSION_1. The emac_dump_regs() function accesses these indiscriminately. This patch fixes the issue. Signed-off-by: Sriramakrishnan --- drivers/net/davinci_emac.c | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 4ee9af6..12196ad 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -565,9 +565,11 @@ static void emac_dump_regs(struct emac_priv *priv) /* Print important registers in EMAC */ dev_info(emac_dev, "EMAC Basic registers\n"); - dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n", - emac_ctrl_read(EMAC_CTRL_EWCTL), - emac_ctrl_read(EMAC_CTRL_EWINTTCNT)); + if (priv->version == EMAC_VERSION_1) { + dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n", + emac_ctrl_read(EMAC_CTRL_EWCTL), + emac_ctrl_read(EMAC_CTRL_EWINTTCNT)); + } dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n", emac_read(EMAC_TXIDVER), ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"), -- 1.6.2.4 From srk at ti.com Thu Jul 29 07:33:59 2010 From: srk at ti.com (Sriramakrishnan) Date: Thu, 29 Jul 2010 18:03:59 +0530 Subject: [PATCH 2/3] TI DaVinci EMAC: Fix asymmetric handling of packets in NAPI Poll function. In-Reply-To: <1280406840-27393-1-git-send-email-srk@ti.com> References: <1280406840-27393-1-git-send-email-srk@ti.com> Message-ID: <1280406840-27393-2-git-send-email-srk@ti.com> The current implementation of NAPI poll function in the driver does not service Rx packets, error condition even if a single Tx packet gets serviced in the napi poll call. This behavior severely affects performance for specific use cases. This patch modifies the poll function implementation to service tx/rx packets in an identical manner. Signed-off-by: Sriramakrishnan --- drivers/net/davinci_emac.c | 21 ++++++++------------- 1 files changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index bc1b270..4ee9af6 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -2266,7 +2266,7 @@ static int emac_poll(struct napi_struct *napi, int budget) struct net_device *ndev = priv->ndev; struct device *emac_dev = &ndev->dev; u32 status = 0; - u32 num_pkts = 0; + u32 num_tx_pkts = 0, num_rx_pkts = 0; /* Check interrupt vectors and call packet processing */ status = emac_read(EMAC_MACINVECTOR); @@ -2277,27 +2277,19 @@ static int emac_poll(struct napi_struct *napi, int budget) mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; if (status & mask) { - num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, + num_tx_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, EMAC_DEF_TX_MAX_SERVICE); } /* TX processing */ - if (num_pkts) - return budget; - mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; if (priv->version == EMAC_VERSION_2) mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; if (status & mask) { - num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget); + num_rx_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget); } /* RX processing */ - if (num_pkts < budget) { - napi_complete(napi); - emac_int_enable(priv); - } - mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; if (priv->version == EMAC_VERSION_2) mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; @@ -2328,9 +2320,12 @@ static int emac_poll(struct napi_struct *napi, int budget) dev_err(emac_dev, "RX Host error %s on ch=%d\n", &emac_rxhost_errcodes[cause][0], ch); } - } /* Host error processing */ + } else if (num_rx_pkts < budget) { + napi_complete(napi); + emac_int_enable(priv); + } - return num_pkts; + return num_rx_pkts; } #ifdef CONFIG_NET_POLL_CONTROLLER -- 1.6.2.4 From luna.id at gmail.com Thu Jul 29 08:18:10 2010 From: luna.id at gmail.com (Nicolas Luna) Date: Thu, 29 Jul 2010 09:18:10 -0400 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> <1280403790.22713.8.camel@sax-lx> Message-ID: Todd, Is it possible that the problem occurs because the driver is using polling and it polls the PMIC to fast and it cannot handles all commands received so it returns NACK? Thanks Nicolas On Thu, Jul 29, 2010 at 8:24 AM, Nicolas Luna wrote: > Todd, > > Yes the polling is not such a problem because 2% is not that much. Probably > that the bitbang will be more than that it's why I would like to avoid it. > If there is a hardware mod to correct NACK problem I'll be glad to apply it. > > Thanks, > > Nicolas > > > > > > On Thu, Jul 29, 2010 at 7:43 AM, Todd Fischer wrote: > >> Nicolas, >> >> Also, due to another hardware limitation, the touch screen driver using >> polling instead of interrupts. I heard a hardware change that will allow >> for interrupts to be used is planned as well. The polling overhead costs >> around 2% ARM CPU. >> >> Todd >> >> >> On Thu, 2010-07-29 at 10:42 +0530, Nori, Sekhar wrote: >> >> Hi Nicolas, >> >> On Thu, Jul 29, 2010 at 02:16:16, Nicolas Luna wrote: >> > Todd, >> > >> > What do I need to change if I want to use the bitbang i2c driver and >> > stop to get those error messages. >> >> You can try the patch here: http://arago-project.org/git/projects/?p=linux-omapl1.git;a=commit;h=7d8accda275fdbe6e727e7ac02ae5a92f5695326 >> >> This issue should be fixed in future revisions of Logic EVMs so this patch >> wont be needed afterward. >> >> Thanks, >> Sekhar >> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From lamiaposta71 at gmail.com Thu Jul 29 09:53:04 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Thu, 29 Jul 2010 16:53:04 +0200 Subject: [PATCH v2] DaVinci: dm365: Added clockout2 management. In-Reply-To: References: <1279709510-6213-1-git-send-email-lamiaposta71@gmail.com> Message-ID: Hi Nori, > > --- a/arch/arm/mach-davinci/clock.c > > > +++ b/arch/arm/mach-davinci/clock.c > > > @@ -254,7 +254,15 @@ static unsigned long > > clk_sysclk_recalc(struct clk *clk) > > > u32 v, plldiv; > > > struct pll_data *pll; > > > unsigned long rate = clk->rate; > > > + struct clk *parent = clk; > > > > > > + if (clk == NULL || IS_ERR(clk)) > > > + return -EINVAL; > > > + while (parent->parent->parent) > > > + parent = parent->parent; > > > + > > > + if (parent == clk) > > > + return -EPERM; > > > > > > It is not clear to me why this change in needed. It is not > > described in the patch description as well. Most likely this > > needs to be carved into a separate patch as well describing > > what is wrong with the existing clk_sysclk_recalc() routine. > > > > > > > > > > now, whith the last check, we don't need that modifications, but only > > > > /* Otherwise, the parent must be a PLL */ > > - if (WARN_ON(!parent->pll_data)) > > + if (!clk->parent->pll_data) > > > > clkout2 is a sub-divider and so its parent is not a pll. > > This function is meant to recalculate the rate for a sysclk. > For clkout2, a new recalculate function should be written. > Due to the fact that clkout2 is after the second divider I guess I'll have to semplify the recalc function. I'll try. > > [...] > > > > +int dm365_clkout2_set_rate(unsigned long rate) > > > > > > Is clockout2 specific to DM365? DM355/DM6446 manuals mention > > clkout signal as well. If this routine can cater to more SoCs > > with simple modifications, you can attempt to generalize it. > > > > > > > > we check in dm355 and clkout2 is really a different clock. > > it seems difficult to integrate. > > we'd prefer not to do it. > > Okay. > :) > > [...] > > > > > > + > > > + /* check all possibilities to get best fitting for the > > required freq */ > > > > > + i_min_err = min_err = INT_MAX; > > > + for (i = 0x0F; i > 0; i--) { > > > + if (clk->parent->set_rate) { > > > + ret = clk_set_rate(clk->parent, rate * > > i) ; > > > + err = clk_get_rate(clk->parent) - rate * > > i; > > > + if (min_err > abs(err)) { > > > + min_err = abs(err); > > > + i_min_err = i; > > > + } > > > + } > > > + } > > > > > > Why should the child touch the parent's clock output? Users of > > the > > clock framework should be able to set these rates independently. > > > > > > > > right. > > we tried. > > the problem is that the clkout2 is used for uda1345 system clock. > > without chenig the parent we can't get close. > > the sound is really too fast. > > > > You should be able to change both clocks independently. > Example, in your board code: > > xxx uda135_set_clk_rate(xxx) > { > clk_set_rate(sysclkN, desired_rate); > clk_set_rate(clkout2, desired_rate); > } > Doing like that I should put a logic in that driver. It is not wrong, because I'm writing a cpu_dai, but, anyway, I will change the sysclk9 that, maybe, is used from someone else. Isn't there the possibility to "occupy" a sysclk? > > That should work? > > > > > > > > > Tomorrow, if you agree, I'll send you 2 patches: > > -patch1: clkout2 > > This is fine.. > > > -patch2: removing warn from sysclk recalc > > ... but as I wrote above, still don't see a need for this. > Can't I use clk->flags to have a conditional behaviour of clk_sysclk_recalc if it is called from pll1_sysclk9 or from clkout2 ? Thx, Raffaele -------------- next part -------------- An HTML attachment was scrubbed... URL: From todd.fischer at ridgerun.com Thu Jul 29 10:19:57 2010 From: todd.fischer at ridgerun.com (Todd Fischer) Date: Thu, 29 Jul 2010 09:19:57 -0600 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> <1280403790.22713.8.camel@sax-lx> Message-ID: <1280416797.22713.502.camel@sax-lx> Nicolas, The polling TPS6507x touchscreen driver works without error (just uses 2% of the CPU). It is the hw design when using the I2C silicon module in the L138 that has the problem. Todd On Thu, 2010-07-29 at 09:18 -0400, Nicolas Luna wrote: > Todd, > > > > Is it possible that the problem occurs because the driver is using > polling and it polls the PMIC to fast and it cannot handles all > commands received so it returns NACK? > > > Thanks > > > Nicolas > > > > On Thu, Jul 29, 2010 at 8:24 AM, Nicolas Luna > wrote: > > Todd, > > > > Yes the polling is not such a problem because 2% is not that > much. Probably that the bitbang will be more than that it's > why I would like to avoid it. If there is a hardware mod to > correct NACK problem I'll be glad to apply it. > > > Thanks, > > > Nicolas > > > > > > > > > On Thu, Jul 29, 2010 at 7:43 AM, Todd Fischer > wrote: > > Nicolas, > > Also, due to another hardware limitation, the touch > screen driver using polling instead of interrupts. I > heard a hardware change that will allow for interrupts > to be used is planned as well. The polling overhead > costs around 2% ARM CPU. > > Todd > > > > > On Thu, 2010-07-29 at 10:42 +0530, Nori, Sekhar > wrote: > > > Hi Nicolas, > > > > On Thu, Jul 29, 2010 at 02:16:16, Nicolas Luna wrote: > > > Todd, > > > > > > What do I need to change if I want to use the bitbang i2c driver and > > > stop to get those error messages. > > > > You can try the patch here: http://arago-project.org/git/projects/?p=linux-omapl1.git;a=commit;h=7d8accda275fdbe6e727e7ac02ae5a92f5695326 > > > > This issue should be fixed in future revisions of Logic EVMs so this patch > > wont be needed afterward. > > > > Thanks, > > Sekhar > > > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From luna.id at gmail.com Thu Jul 29 13:06:18 2010 From: luna.id at gmail.com (Nicolas Luna) Date: Thu, 29 Jul 2010 14:06:18 -0400 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: <1280416797.22713.502.camel@sax-lx> References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> <1280403790.22713.8.camel@sax-lx> <1280416797.22713.502.camel@sax-lx> Message-ID: Ok it's good to know. Do you know if the problem is solved in AM1808 I2C silicon module? Thanks Nicolas On Thu, Jul 29, 2010 at 11:19 AM, Todd Fischer wrote: > Nicolas, > > The polling TPS6507x touchscreen driver works without error (just uses 2% > of the CPU). It is the hw design when using the I2C silicon module in the > L138 that has the problem. > > Todd > > > On Thu, 2010-07-29 at 09:18 -0400, Nicolas Luna wrote: > > Todd, > > > > Is it possible that the problem occurs because the driver is using > polling and it polls the PMIC to fast and it cannot handles all commands > received so it returns NACK? > > > > Thanks > > > > Nicolas > > > On Thu, Jul 29, 2010 at 8:24 AM, Nicolas Luna wrote: > > Todd, > > > > Yes the polling is not such a problem because 2% is not that much. > Probably that the bitbang will be more than that it's why I would like to > avoid it. If there is a hardware mod to correct NACK problem I'll be glad to > apply it. > > > > Thanks, > > > > Nicolas > > > > > > > > On Thu, Jul 29, 2010 at 7:43 AM, Todd Fischer > wrote: > > Nicolas, > > Also, due to another hardware limitation, the touch screen driver using > polling instead of interrupts. I heard a hardware change that will allow > for interrupts to be used is planned as well. The polling overhead costs > around 2% ARM CPU. > > Todd > > > > > On Thu, 2010-07-29 at 10:42 +0530, Nori, Sekhar wrote: > > Hi Nicolas, > > On Thu, Jul 29, 2010 at 02:16:16, Nicolas Luna wrote: > > Todd, > > > > What do I need to change if I want to use the bitbang i2c driver and > > stop to get those error messages. > > You can try the patch here: http://arago-project.org/git/projects/?p=linux-omapl1.git;a=commit;h=7d8accda275fdbe6e727e7ac02ae5a92f5695326 > > This issue should be fixed in future revisions of Logic EVMs so this patch > wont be needed afterward. > > Thanks, > Sekhar > > > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From rohan_javed at yahoo.co.uk Thu Jul 29 21:42:30 2010 From: rohan_javed at yahoo.co.uk (rohan tabish) Date: Fri, 30 Jul 2010 02:42:30 +0000 (GMT) Subject: Boot time In-Reply-To: Message-ID: <817859.2735.qm@web24102.mail.ird.yahoo.com> set verify=n this will ignore checksum Regard's RT --- On Thu, 29/7/10, Nicolas Luna wrote: From: Nicolas Luna Subject: Boot time To: davinci-linux-open-source at linux.davincidsp.com Date: Thursday, 29 July, 2010, 0:59 Hi guys, I'm trying to make by board boot as quick as possible. I did some optimisation with the "All This For 1 Second Boot" wiki and other website. I would like to reduce a little bit more the boot time and I wonder if you guys could give me some clues. I copied my boot log below. For sure I'll remove the uboot autoboot delay and probably build a new kernel with modules. I putted in bold part that I think it is possible to do more optimisation. 1- See bullet #3.2- The verifying Checksum is about 400 msec is it possible to skip it?3- It takes ~1 sec to start booting the kernel and there is a other ~1 sec delay between the starting kernel and the beginning of the uncompressing. Why it's so long? Ok maybe there is the copy from NOR to RAM but it should not take more than few msec. 4- It takes ~1 sec to the kernel to free 120K memory... I got enought RAM is it possible to remove it? I got custom hardware based on OMAP-L138 with FS (jffs2) and compressed kernel in NOR Flash. Thanks a lot Nicolas ------------------------------------------------------------------------------------- 0.000 0.000: OMAP-L138 initialization passed! 0.000 0.000: Booting TI User Boot Loader0.004 0.004: ? ?UBL Version: 1.650.004 0.000: ? ?UBL Flashtype: NOR0.008 0.004: Starting NOR Copy...0.008 0.000: CFI Query...passed. 0.012 0.004: NOR Initialization:0.012 0.000: ? ?Command Set: Intel0.012 0.000: ? ?Manufacturer: INTEL0.016 0.004: ? ?Size: 0x00000020 MB0.020 0.004: Valid magicnum, 0x55424CBB, found.. 0.184 0.164: ? ?DONE0.188 0.004: Jumping to entry point at 0xC1080000.0.504 0.316:1.548 1.044: Hit any key to stop autoboot: ?02.372 0.824: ## Booting kernel from Legacy Image at c0007fc0 ... 2.372 0.000: ? ?Image Name: ? Linux-2.6.342.380 0.008: ? ?Image Type: ? ARM Linux Kernel Image (uncompressed)2.380 0.000: ? ?Data Size: ? ?1505956 Bytes = ?1.4 MB2.384 0.004: ? ?Load Address: c0008000 2.388 0.004: ? ?Entry Point: ?c00080002.808 0.420: ? ?Verifying Checksum ... OK2.808 0.000: ? ?Loading Kernel Image ... OK2.808 0.000: OK2.808 0.000:2.812 0.004: Starting kernel ... 2.812 0.000:3.860 1.048: Uncompressing Linux... done, booting the kernel.4.264 0.404: Linux version 2.6.34 (id at idt-ubuntu-linux) (gcc version 4.3.3 (Sourcery G++ Lite 2009q1-203) ) #89 PREEMPT Thu Jul 22 15:24:03 EDT 2010 4.268 0.004: CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=000531774.272 0.004: CPU: VIVT data cache, VIVT instruction cache4.276 0.004: Machine: DaVinci DA850/OMAP-L138 EVM4.280 0.004: Memory policy: ECC disabled, Data cache writeback 4.284 0.004: DaVinci da850/omap-l138 variant 0x04.288 0.004: Built 1 zonelists in Zone order, mobility grouping on. ?Total pages: 325124.300 0.012: Kernel command line: lpj=747520 mem=128M console=ttyS2,115200n8 root=/dev/mtdblock2 rootfstype=jffs2 rw ip=off 4.304 0.004: PID hash table entries: 512 (order: -1, 2048 bytes)4.308 0.004: Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)4.316 0.008: Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) 4.316 0.000: Memory: 128MB = 128MB total4.324 0.008: Memory: 126752k/126752k available, 4320k reserved, 0K highmem4.324 0.000: Virtual kernel memory layout:4.332 0.008: ? ? vector ?: 0xffff0000 - 0xffff1000 ? ( ? 4 kB) 4.336 0.004: ? ? fixmap ?: 0xfff00000 - 0xfffe0000 ? ( 896 kB)4.340 0.004: ? ? DMA ? ? : 0xff000000 - 0xffe00000 ? ( ?14 MB)4.344 0.004: ? ? vmalloc : 0xc8800000 - 0xfea00000 ? ( 866 MB) 4.348 0.004: ? ? lowmem ?: 0xc0000000 - 0xc8000000 ? ( 128 MB)4.352 0.004: ? ? modules : 0xbf000000 - 0xc0000000 ? ( ?16 MB)4.356 0.004: ? ? ? .init : 0xc0008000 - 0xc0026000 ? ( 120 kB)4.360 0.004: ? ? ? .text : 0xc0026000 - 0xc02e8000 ? (2824 kB) 4.364 0.004: ? ? ? .data : 0xc02e8000 - 0xc0307a60 ? ( 127 kB)4.372 0.008: SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=14.376 0.004: Hierarchical RCU implementation. 4.376 0.000: NR_IRQS:2454.380 0.004: Console: colour dummy device 80x304.384 0.004: Calibrating delay loop (skipped) preset value.. 149.50 BogoMIPS (lpj=747520)4.388 0.004: Mount-cache hash table entries: 512 4.392 0.004: CPU: Testing write buffer coherency: ok4.396 0.004: DaVinci: 144 gpio irqs4.396 0.000: NET: Registered protocol family 164.400 0.004: bio: create slab at 0 4.404 0.004: SCSI subsystem initialized4.408 0.004: usbcore: registered new interface driver usbfs4.412 0.004: usbcore: registered new interface driver hub4.416 0.004: usbcore: registered new device driver usb 4.416 0.000: Switching to clocksource timer0_14.420 0.004: musb_hdrc: version 6.0, pio, host, debug=04.424 0.004: Waiting for USB PHY clock good...4.428 0.004: musb_hdrc musb_hdrc: MUSB HDRC host driver 4.432 0.004: musb_hdrc musb_hdrc: new USB bus registered, assigned bus number 14.436 0.004: hub 1-0:1.0: USB hub found4.440 0.004: hub 1-0:1.0: 1 port detected4.444 0.004: musb_hdrc musb_hdrc: USB Host mode controller at fee00000 using PIO, IRQ 58 4.448 0.004: NET: Registered protocol family 24.456 0.008: IP route cache hash table entries: 1024 (order: 0, 4096 bytes)4.460 0.004: TCP established hash table entries: 4096 (order: 3, 32768 bytes) 4.464 0.004: TCP bind hash table entries: 4096 (order: 2, 16384 bytes)4.468 0.004: TCP: Hash tables configured (established 4096 bind 4096)4.472 0.004: TCP reno registered4.476 0.004: UDP hash table entries: 256 (order: 0, 4096 bytes) 4.480 0.004: UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)4.484 0.004: NET: Registered protocol family 14.488 0.004: RPC: Registered udp transport module.4.492 0.004: RPC: Registered tcp transport module. 4.496 0.004: RPC: Registered tcp NFSv4.1 backchannel transport module.4.500 0.004: JFFS2 version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc.4.504 0.004: msgmni has been set to 2474.508 0.004: io scheduler noop registered (default) 4.512 0.004: da8xx_lcdc da8xx_lcdc.0: GLCD: Found Sharp_LK043T1DG01 panel4.516 0.004: Console: switching to colour frame buffer device 60x344.520 0.004: Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled 4.528 0.008: serial8250.0: ttyS0 at MMIO 0x1c42000 (irq = 25) is a 16550A4.532 0.004: serial8250.0: ttyS1 at MMIO 0x1d0c000 (irq = 53) is a 16550A4.540 0.008: serial8250.0: ttyS2 at MMIO 0x1d0d000 (irq = 61) is a 16550A 4.540 0.000: console [ttyS2] enabled4.548 0.008: brd: module loaded4.556 0.008: physmap platform flash device: 02000000 at 600000004.564 0.008: physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank 4.568 0.004: ?Intel/Sharp Extended Query Table at 0x010A4.572 0.004: ?Intel/Sharp Extended Query Table at 0x010A4.576 0.004: ?Intel/Sharp Extended Query Table at 0x010A4.580 0.004: ?Intel/Sharp Extended Query Table at 0x010A 4.584 0.004: ?Intel/Sharp Extended Query Table at 0x010A4.588 0.004: Using buffer write method4.588 0.000: Using auto-unlock on power-up/resume4.592 0.004: cfi_cmdset_0001: Erase suspend on write enabled 4.596 0.004: RedBoot partition parsing not available4.600 0.004: Using physmap partition information4.604 0.004: Creating 3 MTD partitions on "physmap-flash.0":4.608 0.004: 0x000000000000-0x000000080000 : "bootloaders + env" 4.620 0.012: 0x000000080000-0x000000280000 : "kernel"4.628 0.008: 0x000000280000-0x000002000000 : "filesystem"4.636 0.008: physmap-flash.0: failed to claim resource 0 4.644 0.008: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron NAND 512MiB 3,3V 8-bit)4.652 0.008: Creating 2 MTD partitions on "davinci_nand.1":4.656 0.004: 0x000000000000-0x000001900000 : "data" 4.664 0.008: 0x000001900000-0x000020000000 : "else"4.672 0.008: davinci_nand davinci_nand.1: controller rev. 2.54.680 0.008: spi_davinci spi_davinci.1: Controller at 0xfef0e000 4.692 0.012: tun: Universal TUN/TAP device driver, 1.64.696 0.004: tun: (C) 1999-2004 Max Krasnyansky 4.704 0.008: ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver 4.708 0.004: ohci ohci.0: DA8xx OHCI4.712 0.004: ohci ohci.0: new USB bus registered, assigned bus number 24.716 0.004: Waiting for USB PHY clock good...4.720 0.004: ohci ohci.0: irq 59, io mem 0x01e25000 4.788 0.068: hub 2-0:1.0: USB hub found4.788 0.000: hub 2-0:1.0: 1 port detected4.796 0.008: Initializing USB Mass Storage driver...4.804 0.008: usbcore: registered new interface driver usb-storage 4.804 0.000: USB Mass Storage support registered.5.804 1.000: i2c_davinci i2c_davinci.1: controller timed out5.808 0.004: i2c_davinci i2c_davinci.1: initiating i2c bus recovery5.812 0.004: tps6507x-ts: probe of tps6507x-ts failed with error -110 5.820 0.008: omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc05.824 0.004: omap_rtc: RTC power up reset detected5.824 0.000: omap_rtc: already running5.828 0.004: i2c /dev entries driver 5.832 0.004: TCP cubic registered5.836 0.004: Clocks: disable unused i2c15.840 0.004: Clocks: disable unused emac5.848 0.008: davinci_emac_probe: using random MAC addr: 72:93:72:ad:15:13 5.852 0.004: emac-mii: probed5.860 0.008: omap_rtc omap_rtc: setting system clock to 2000-01-01 01:34:03 UTC (946690443)6.136 0.276: VFS: Mounted root (jffs2 filesystem) on device 31:2. 6.140 0.004: Freeing init memory: 120K7.356 1.216: Mounting proc -----Inline Attachment Follows----- _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source at linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -------------- next part -------------- An HTML attachment was scrubbed... URL: From nsekhar at ti.com Fri Jul 30 01:33:01 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Fri, 30 Jul 2010 12:03:01 +0530 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> <1280403790.22713.8.camel@sax-lx> <1280416797.22713.502.camel@sax-lx> Message-ID: On Thu, Jul 29, 2010 at 23:36:18, Nicolas Luna wrote: > Ok it's good to know. > > Do you know if the problem is solved in AM1808 I2C silicon module? > By "silicon module" you mean Logic's "System-on-Module (SoM)"? The answer I believe is no. The solution will be implemented in an upcoming Logic EVM revision. Here is the change statement: "The hardware fix for this issue is to remove U24 and R161 and short U24 pins 2 to 4" Due to the high amount of integration on SoM, I am not sure how feasible it is to do such a change in a simple lab setup. Thanks, Sekhar From nsekhar at ti.com Fri Jul 30 01:53:43 2010 From: nsekhar at ti.com (Nori, Sekhar) Date: Fri, 30 Jul 2010 12:23:43 +0530 Subject: [PATCH v2] DaVinci: dm365: Added clockout2 management. In-Reply-To: References: <1279709510-6213-1-git-send-email-lamiaposta71@gmail.com> Message-ID: Hi Raffaele, On Thu, Jul 29, 2010 at 20:23:04, Raffaele Recalcati wrote: > > > > > + > > > + /* check all possibilities to get best fitting > for the > > required freq */ > > > > > + i_min_err = min_err = INT_MAX; > > > + for (i = 0x0F; i > 0; i--) { > > > + if (clk->parent->set_rate) { > > > + ret = clk_set_rate(clk->parent, > rate * > > i) ; > > > + err = clk_get_rate(clk->parent) > - rate * > > i; > > > + if (min_err > abs(err)) { > > > + min_err = abs(err); > > > + i_min_err = i; > > > + } > > > + } > > > + } > > > > > > Why should the child touch the parent's clock output? > Users of > > the > > clock framework should be able to set these rates > independently. > > > > > > > > right. > > we tried. > > the problem is that the clkout2 is used for uda1345 system > clock. > > without chenig the parent we can't get close. > > the sound is really too fast. > > > > > You should be able to change both clocks independently. > Example, in your board code: > > xxx uda135_set_clk_rate(xxx) > { > clk_set_rate(sysclkN, desired_rate); > clk_set_rate(clkout2, desired_rate); > } > > > > > Doing like that I should put a logic in that driver. This code should be in some platform file and abstracted from the driver using clock APIs. > It is not wrong, because I'm writing a cpu_dai, but, anyway, I will > change the sysclk9 that, maybe, is used from someone else. > > Isn't there the possibility to "occupy" a sysclk? No, because the hardware doesn't allow it. Who else is using sysclk9? > Can't I use clk->flags to have a conditional behaviour of > clk_sysclk_recalc if it is called from pll1_sysclk9 or from clkout2 ? > In my opinion overloading clk_sysclk_recalc to recalculate clkout2 clock rate will be confusing. Since the clkout2 code is DM365 specific, it can reside dm365.c itself. Thanks, Sekhar From b.hutchman at gmail.com Fri Jul 30 06:09:36 2010 From: b.hutchman at gmail.com (Brian Hutchinson) Date: Fri, 30 Jul 2010 01:09:36 -1000 Subject: Problems with DaVinci PSP 03.01 GA (r37) Message-ID: Hi, I'm trying to get started with the community kernel/tools and following directions at: http://processors.wiki.ti.com/index.php/DaVinci_PSP_03.01_GA_(r37)_Release_Notes In the section where git checkouts are mentioned as in: $ mkdir $HOME/oe $ cd $HOME/oe $ git clone -n git://arago-project.org/git/arago.git $ cd arago $ git checkout $ cd $HOME/oe $ git clone -n git://arago-project.org/git/arago-oe-dev.git $ cd arago-oe-dev $ git checkout $ cd $HOME/oe $ git clone -n git://arago-project.org/git/arago-bitbake.git $ cd arago-bitbake $ git checkout ... I'm not quite sure what I should be using for for arago-oe-dev and arago-bitbake because when I attempt to do a git checkout DEV.DaVinciPSP.03.XX.00.37 I get a message back that says there is no label associated with that name or something like that and my arago-oe-dev and arago-bitbake directories are empty after doing the clone. So far, using git checkout DEV.DaVinciPSP.03.XX.00.37 has worked for arago and linux-davinci (note instructions say result of clone should be a dir called linux-davinci-staging but for me it was linux-davinci). Anyone know what I'm doing wrong with these git checkout commands? Regards, Brian From b.hutchman at gmail.com Fri Jul 30 09:23:30 2010 From: b.hutchman at gmail.com (Brian Hutchinson) Date: Fri, 30 Jul 2010 04:23:30 -1000 Subject: No DEV.DaVinciPSP.03.XX.00.37 tag on arago-bitbake Message-ID: Hi again, I tried the git repositories again this morning and the only one I have problems with is arago-bitbake. There doesn't appear to be a DEV.DaVinciPSP.03.XX.00.37 tag on that repository. I'm trying to follow these instructions: http://processors.wiki.ti.com/index.php/DaVinci_PSP_03.01_GA_(r37)_Release_Notes ... to setup a environment for DM6446 EVM. There is a DEV.DaVinciPSP.03.01.00.28 tag on the arago-bitbake repository ... should I be using that???? Regards, Brian From c.aeschlimann at acn-group.ch Fri Jul 30 09:48:35 2010 From: c.aeschlimann at acn-group.ch (Christophe Aeschlimann) Date: Fri, 30 Jul 2010 16:48:35 +0200 Subject: No DEV.DaVinciPSP.03.XX.00.37 tag on arago-bitbake In-Reply-To: References: Message-ID: <4C52E643.2040002@acn-group.ch> On 30.07.2010 16:23, Brian Hutchinson wrote: > Hi again, > > I tried the git repositories again this morning and the only one I > have problems with is arago-bitbake. There doesn't appear to be a > DEV.DaVinciPSP.03.XX.00.37 tag on that repository. You're right there isn't one. > I'm trying to follow these instructions: > http://processors.wiki.ti.com/index.php/DaVinci_PSP_03.01_GA_(r37)_Release_Notes > > ... to setup a environment for DM6446 EVM. > > There is a DEV.DaVinciPSP.03.01.00.28 tag on the arago-bitbake > repository ... should I be using that???? bitbake version is probably not _THAT_ important. You should try with master. > > Regards, > > Brian > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > -- Christophe Aeschlimann Embedded Software Engineer Advanced Communications Networks S.A. Rue du Puits-Godet 8a 2000 Neuch?tel, Switzerland T?l. +41 32 724 74 31 c.aeschlimann at acn-group.ch From c.aeschlimann at acn-group.ch Fri Jul 30 09:59:36 2010 From: c.aeschlimann at acn-group.ch (Christophe Aeschlimann) Date: Fri, 30 Jul 2010 16:59:36 +0200 Subject: Problems with DaVinci PSP 03.01 GA (r37) In-Reply-To: References: Message-ID: <4C52E8D8.2060307@acn-group.ch> On 30.07.2010 13:09, Brian Hutchinson wrote: > Hi, > > I'm trying to get started with the community kernel/tools and > following directions at: > http://processors.wiki.ti.com/index.php/DaVinci_PSP_03.01_GA_(r37)_Release_Notes [...] > So far, using git checkout DEV.DaVinciPSP.03.XX.00.37 has worked for > arago and linux-davinci (note instructions say result of clone should > be a dir called linux-davinci-staging but for me it was > linux-davinci). My recommendation would be to read a little bit about OpenEmbedded / BitBake / Git before starting. It seems you lack some background knowledge. But as you noticed there is a typo there. The tar.gz file containing the source is named linux-davinci-staging so if you extract the sources from that file then you would get a linux-davinci-staging folder. git-clone takes an extra parameter if you want to clone to a specific folder. Else it will just use the name of the repository. "linux-davinci" in that case. > Anyone know what I'm doing wrong with these git checkout commands? There is nothing _wrong_ with what you did. > Regards, > > Brian Regards, -- Christophe Aeschlimann Embedded Software Engineer Advanced Communications Networks S.A. Rue du Puits-Godet 8a 2000 Neuch?tel, Switzerland T?l. +41 32 724 74 31 c.aeschlimann at acn-group.ch From luna.id at gmail.com Fri Jul 30 12:35:21 2010 From: luna.id at gmail.com (Nicolas Luna) Date: Fri, 30 Jul 2010 13:35:21 -0400 Subject: Touchscreen - MFD driver for TPS6507x family In-Reply-To: References: <201006081014.33072.caglarakyuz@gmail.com> <1089858925.76837.1275989074229.JavaMail.open-xchange@oxltgw14.schlund.de> <201006081305.15022.caglarakyuz@gmail.com> <903202309.136917.1276073978778.JavaMail.open-xchange@oxltgw02.schlund.de> <1276114677.21486.872.camel@sax-lx> <1280403790.22713.8.camel@sax-lx> <1280416797.22713.502.camel@sax-lx> Message-ID: Sekhar, We do not have this buffer on our custom hardware and we have the NACK problem. SDA and SCL are directly connected from PMIC to OMAP with pull-up. Is Todd right with the silicon issue? Or a I2C driver issue when it is used too much... ? Regards, Nicolas On Fri, Jul 30, 2010 at 2:33 AM, Nori, Sekhar wrote: > On Thu, Jul 29, 2010 at 23:36:18, Nicolas Luna wrote: > > Ok it's good to know. > > > > Do you know if the problem is solved in AM1808 I2C silicon module? > > > > By "silicon module" you mean Logic's "System-on-Module (SoM)"? > > The answer I believe is no. The solution will be implemented in > an upcoming Logic EVM revision. Here is the change statement: > > "The hardware fix for this issue is to remove U24 and R161 and short U24 > pins 2 to 4" > > Due to the high amount of integration on SoM, I am not sure how > feasible it is to do such a change in a simple lab setup. > > Thanks, > Sekhar > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From luna.id at gmail.com Fri Jul 30 15:47:14 2010 From: luna.id at gmail.com (Nicolas Luna) Date: Fri, 30 Jul 2010 16:47:14 -0400 Subject: Boot time In-Reply-To: <817859.2735.qm@web24102.mail.ird.yahoo.com> References: <817859.2735.qm@web24102.mail.ird.yahoo.com> Message-ID: Hi, Thanks guys for your advices, I applied few of them and I save a lot of time, I'm at 3.9 seconds now. I'll also apply the deferred init calls concept later. I have two other questions. I'm not sure to understand how to use EDMA to copy from NOR to RAM in uboot. Every post that I found it is never explain the procedure to apply this patch. Do you guys have a piece of code or something to get started with that? In the same way, after the kernel boot, I have to start an application with QT and it takes 10 seconds to transfert QT lib (libQtCore, libQtGui, libQtNetwork, fonts) from NOR to RAM and start the application. QT stuff is ~20MB, I removed every useless lib to reduce the amount of data to transfert. I also optimised the EMIFA CS2 (I changed EMIFA clock to 150 Mhz and changed CS timing to be at the maximum of my NOR). I probed the NOR chip select and there are big delays between read access. I suppose that is because it is not using EDMA and the CPU is not able to feed the NOR... I would like to reduce this transfert time to ~4 secondes or less and I think that EDMA could maybe help to do it. Do you have any idea how to apply it, or any other ideas? Thanks for your time. Regards, Nicolas On Thu, Jul 29, 2010 at 10:42 PM, rohan tabish wrote: > set verify=n this will ignore checksum > > Regard's > RT > > --- On *Thu, 29/7/10, Nicolas Luna * wrote: > > > From: Nicolas Luna > Subject: Boot time > To: davinci-linux-open-source at linux.davincidsp.com > Date: Thursday, 29 July, 2010, 0:59 > > > Hi guys, > > I'm trying to make by board boot as quick as possible. I did some > optimisation with the "All This For 1 Second Boot" wiki and other website. I > would like to reduce a little bit more the boot time and I wonder if you > guys could give me some clues. > > I copied my boot log below. For sure I'll remove the uboot autoboot delay > and probably build a new kernel with modules. I putted in bold part that I > think it is possible to do more optimisation. > > 1- See bullet #3. > 2- The verifying Checksum is about 400 msec is it possible to skip it? > 3- It takes ~1 sec to start booting the kernel and there is a other ~1 sec > delay between the starting kernel and the beginning of the uncompressing. > Why it's so long? Ok maybe there is the copy from NOR to RAM but it should > not take more than few msec. > 4- It takes ~1 sec to the kernel to free 120K memory... I got enought RAM > is it possible to remove it? > > I got custom hardware based on OMAP-L138 with FS (jffs2) and compressed > kernel in NOR Flash. > > Thanks a lot > > Nicolas > > > ------------------------------------------------------------------------------------- > > 0.000 0.000: OMAP-L138 initialization passed! > 0.000 0.000: Booting TI User Boot Loader > 0.004 0.004: UBL Version: 1.65 > 0.004 0.000: UBL Flashtype: NOR > 0.008 0.004: Starting NOR Copy... > 0.008 0.000: CFI Query...passed. > 0.012 0.004: NOR Initialization: > 0.012 0.000: Command Set: Intel > 0.012 0.000: Manufacturer: INTEL > 0.016 0.004: Size: 0x00000020 MB > 0.020 0.004: Valid magicnum, 0x55424CBB, found.. > 0.184 0.164: DONE > 0.188 0.004: Jumping to entry point at 0xC1080000. > 0.504 0.316: > 1.548 1.044: Hit any key to stop autoboot: 0 > *2.372 0.824: ## Booting kernel from Legacy Image at c0007fc0 ...* > 2.372 0.000: Image Name: Linux-2.6.34 > 2.380 0.008: Image Type: ARM Linux Kernel Image (uncompressed) > 2.380 0.000: Data Size: 1505956 Bytes = 1.4 MB > 2.384 0.004: Load Address: c0008000 > 2.388 0.004: Entry Point: c0008000 > *2.808 0.420: Verifying Checksum ... OK* > 2.808 0.000: Loading Kernel Image ... OK > 2.808 0.000: OK > 2.808 0.000: > *2.812 0.004: Starting kernel ...* > *2.812 0.000:* > *3.860 1.048: Uncompressing Linux... done, booting the kernel.* > 4.264 0.404: Linux version 2.6.34 (id at idt-ubuntu-linux) (gcc version 4.3.3 > (Sourcery G++ Lite 2009q1-203) ) #89 PREEMPT Thu Jul 22 15:24:03 EDT 2010 > 4.268 0.004: CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177 > 4.272 0.004: CPU: VIVT data cache, VIVT instruction cache > 4.276 0.004: Machine: DaVinci DA850/OMAP-L138 EVM > 4.280 0.004: Memory policy: ECC disabled, Data cache writeback > 4.284 0.004: DaVinci da850/omap-l138 variant 0x0 > 4.288 0.004: Built 1 zonelists in Zone order, mobility grouping on. Total > pages: 32512 > 4.300 0.012: Kernel command line: lpj=747520 mem=128M > console=ttyS2,115200n8 root=/dev/mtdblock2 rootfstype=jffs2 rw ip=off > 4.304 0.004: PID hash table entries: 512 (order: -1, 2048 bytes) > 4.308 0.004: Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) > 4.316 0.008: Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) > 4.316 0.000: Memory: 128MB = 128MB total > 4.324 0.008: Memory: 126752k/126752k available, 4320k reserved, 0K highmem > 4.324 0.000: Virtual kernel memory layout: > 4.332 0.008: vector : 0xffff0000 - 0xffff1000 ( 4 kB) > 4.336 0.004: fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) > 4.340 0.004: DMA : 0xff000000 - 0xffe00000 ( 14 MB) > 4.344 0.004: vmalloc : 0xc8800000 - 0xfea00000 ( 866 MB) > 4.348 0.004: lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) > 4.352 0.004: modules : 0xbf000000 - 0xc0000000 ( 16 MB) > 4.356 0.004: .init : 0xc0008000 - 0xc0026000 ( 120 kB) > 4.360 0.004: .text : 0xc0026000 - 0xc02e8000 (2824 kB) > 4.364 0.004: .data : 0xc02e8000 - 0xc0307a60 ( 127 kB) > 4.372 0.008: SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, > CPUs=1, Nodes=1 > 4.376 0.004: Hierarchical RCU implementation. > 4.376 0.000: NR_IRQS:245 > 4.380 0.004: Console: colour dummy device 80x30 > 4.384 0.004: Calibrating delay loop (skipped) preset value.. 149.50 > BogoMIPS (lpj=747520) > 4.388 0.004: Mount-cache hash table entries: 512 > 4.392 0.004: CPU: Testing write buffer coherency: ok > 4.396 0.004: DaVinci: 144 gpio irqs > 4.396 0.000: NET: Registered protocol family 16 > 4.400 0.004: bio: create slab at 0 > 4.404 0.004: SCSI subsystem initialized > 4.408 0.004: usbcore: registered new interface driver usbfs > 4.412 0.004: usbcore: registered new interface driver hub > 4.416 0.004: usbcore: registered new device driver usb > 4.416 0.000: Switching to clocksource timer0_1 > 4.420 0.004: musb_hdrc: version 6.0, pio, host, debug=0 > 4.424 0.004: Waiting for USB PHY clock good... > 4.428 0.004: musb_hdrc musb_hdrc: MUSB HDRC host driver > 4.432 0.004: musb_hdrc musb_hdrc: new USB bus registered, assigned bus > number 1 > 4.436 0.004: hub 1-0:1.0: USB hub found > 4.440 0.004: hub 1-0:1.0: 1 port detected > 4.444 0.004: musb_hdrc musb_hdrc: USB Host mode controller at fee00000 > using PIO, IRQ 58 > 4.448 0.004: NET: Registered protocol family 2 > 4.456 0.008: IP route cache hash table entries: 1024 (order: 0, 4096 bytes) > 4.460 0.004: TCP established hash table entries: 4096 (order: 3, 32768 > bytes) > 4.464 0.004: TCP bind hash table entries: 4096 (order: 2, 16384 bytes) > 4.468 0.004: TCP: Hash tables configured (established 4096 bind 4096) > 4.472 0.004: TCP reno registered > 4.476 0.004: UDP hash table entries: 256 (order: 0, 4096 bytes) > 4.480 0.004: UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) > 4.484 0.004: NET: Registered protocol family 1 > 4.488 0.004: RPC: Registered udp transport module. > 4.492 0.004: RPC: Registered tcp transport module. > 4.496 0.004: RPC: Registered tcp NFSv4.1 backchannel transport module. > 4.500 0.004: JFFS2 version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc. > 4.504 0.004: msgmni has been set to 247 > 4.508 0.004: io scheduler noop registered (default) > 4.512 0.004: da8xx_lcdc da8xx_lcdc.0: GLCD: Found Sharp_LK043T1DG01 panel > 4.516 0.004: Console: switching to colour frame buffer device 60x34 > 4.520 0.004: Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled > 4.528 0.008: serial8250.0: ttyS0 at MMIO 0x1c42000 (irq = 25) is a 16550A > 4.532 0.004: serial8250.0: ttyS1 at MMIO 0x1d0c000 (irq = 53) is a 16550A > 4.540 0.008: serial8250.0: ttyS2 at MMIO 0x1d0d000 (irq = 61) is a 16550A > 4.540 0.000: console [ttyS2] enabled > 4.548 0.008: brd: module loaded > 4.556 0.008: physmap platform flash device: 02000000 at 60000000 > 4.564 0.008: physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank > 4.568 0.004: Intel/Sharp Extended Query Table at 0x010A > 4.572 0.004: Intel/Sharp Extended Query Table at 0x010A > 4.576 0.004: Intel/Sharp Extended Query Table at 0x010A > 4.580 0.004: Intel/Sharp Extended Query Table at 0x010A > 4.584 0.004: Intel/Sharp Extended Query Table at 0x010A > 4.588 0.004: Using buffer write method > 4.588 0.000: Using auto-unlock on power-up/resume > 4.592 0.004: cfi_cmdset_0001: Erase suspend on write enabled > 4.596 0.004: RedBoot partition parsing not available > 4.600 0.004: Using physmap partition information > 4.604 0.004: Creating 3 MTD partitions on "physmap-flash.0": > 4.608 0.004: 0x000000000000-0x000000080000 : "bootloaders + env" > 4.620 0.012: 0x000000080000-0x000000280000 : "kernel" > 4.628 0.008: 0x000000280000-0x000002000000 : "filesystem" > 4.636 0.008: physmap-flash.0: failed to claim resource 0 > 4.644 0.008: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron NAND > 512MiB 3,3V 8-bit) > 4.652 0.008: Creating 2 MTD partitions on "davinci_nand.1": > 4.656 0.004: 0x000000000000-0x000001900000 : "data" > 4.664 0.008: 0x000001900000-0x000020000000 : "else" > 4.672 0.008: davinci_nand davinci_nand.1: controller rev. 2.5 > 4.680 0.008: spi_davinci spi_davinci.1: Controller at 0xfef0e000 > 4.692 0.012: tun: Universal TUN/TAP device driver, 1.6 > 4.696 0.004: tun: (C) 1999-2004 Max Krasnyansky > > > 4.704 0.008: ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver > 4.708 0.004: ohci ohci.0: DA8xx OHCI > 4.712 0.004: ohci ohci.0: new USB bus registered, assigned bus number 2 > 4.716 0.004: Waiting for USB PHY clock good... > 4.720 0.004: ohci ohci.0: irq 59, io mem 0x01e25000 > 4.788 0.068: hub 2-0:1.0: USB hub found > 4.788 0.000: hub 2-0:1.0: 1 port detected > 4.796 0.008: Initializing USB Mass Storage driver... > 4.804 0.008: usbcore: registered new interface driver usb-storage > 4.804 0.000: USB Mass Storage support registered. > 5.804 1.000: i2c_davinci i2c_davinci.1: controller timed out > 5.808 0.004: i2c_davinci i2c_davinci.1: initiating i2c bus recovery > 5.812 0.004: tps6507x-ts: probe of tps6507x-ts failed with error -110 > 5.820 0.008: omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc0 > 5.824 0.004: omap_rtc: RTC power up reset detected > 5.824 0.000: omap_rtc: already running > 5.828 0.004: i2c /dev entries driver > 5.832 0.004: TCP cubic registered > 5.836 0.004: Clocks: disable unused i2c1 > 5.840 0.004: Clocks: disable unused emac > 5.848 0.008: davinci_emac_probe: using random MAC addr: 72:93:72:ad:15:13 > 5.852 0.004: emac-mii: probed > 5.860 0.008: omap_rtc omap_rtc: setting system clock to 2000-01-01 01:34:03 > UTC (946690443) > 6.136 0.276: VFS: Mounted root (jffs2 filesystem) on device 31:2. > *6.140 0.004: Freeing init memory: 120K* > *7.356 1.216: Mounting proc* > > -----Inline Attachment Follows----- > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source at linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From davem at davemloft.net Sat Jul 31 01:56:14 2010 From: davem at davemloft.net (David Miller) Date: Fri, 30 Jul 2010 23:56:14 -0700 (PDT) Subject: [PATCH 1/3] TI DaVinci EMAC : Implement interrupt pacing functionality. In-Reply-To: <1280406840-27393-1-git-send-email-srk@ti.com> References: <1280406840-27393-1-git-send-email-srk@ti.com> Message-ID: <20100730.235614.28817673.davem@davemloft.net> From: Sriramakrishnan Date: Thu, 29 Jul 2010 18:03:58 +0530 > DaVinci EMAC module includes an interrupt pacing block that can > be programmed to throttle the rate at which interrupts are > generated. This patch implements interrupt pacing logic that can > be controlled through the ethtool interface(only rx_coalesce_usecs > param is honored) > > Signed-off-by: Sriramakrishnan Applied. From davem at davemloft.net Sat Jul 31 01:56:19 2010 From: davem at davemloft.net (David Miller) Date: Fri, 30 Jul 2010 23:56:19 -0700 (PDT) Subject: [PATCH 2/3] TI DaVinci EMAC: Fix asymmetric handling of packets in NAPI Poll function. In-Reply-To: <1280406840-27393-2-git-send-email-srk@ti.com> References: <1280406840-27393-1-git-send-email-srk@ti.com> <1280406840-27393-2-git-send-email-srk@ti.com> Message-ID: <20100730.235619.102547507.davem@davemloft.net> From: Sriramakrishnan Date: Thu, 29 Jul 2010 18:03:59 +0530 > The current implementation of NAPI poll function in the driver does not service > Rx packets, error condition even if a single Tx packet gets serviced in > the napi poll call. This behavior severely affects performance for specific use > cases. This patch modifies the poll function implementation to service tx/rx > packets in an identical manner. > > Signed-off-by: Sriramakrishnan Applied. From davem at davemloft.net Sat Jul 31 01:56:26 2010 From: davem at davemloft.net (David Miller) Date: Fri, 30 Jul 2010 23:56:26 -0700 (PDT) Subject: [PATCH 3/3] TI DaVinci EMAC: Fix incorrect reference to EMAC_CTRL registers. In-Reply-To: <1280406840-27393-3-git-send-email-srk@ti.com> References: <1280406840-27393-1-git-send-email-srk@ti.com> <1280406840-27393-2-git-send-email-srk@ti.com> <1280406840-27393-3-git-send-email-srk@ti.com> Message-ID: <20100730.235626.179932800.davem@davemloft.net> From: Sriramakrishnan Date: Thu, 29 Jul 2010 18:04:00 +0530 > The EMAC modules control registers vary as per the version of the > EMAC module. EMAC_CTRL_EWCTL,EMAC_CTRL_EWINTTCNT are available > only on EMAC_VERSION_1. The emac_dump_regs() function accesses > these indiscriminately. This patch fixes the issue. > > Signed-off-by: Sriramakrishnan Also applied, thank you. From lamiaposta71 at gmail.com Sat Jul 31 03:51:30 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Sat, 31 Jul 2010 10:51:30 +0200 Subject: Boot time In-Reply-To: References: <817859.2735.qm@web24102.mail.ird.yahoo.com> Message-ID: You should use qt statically linked. I would like to see the final boot chart . Bye 2010/7/30, Nicolas Luna : > Hi, > > Thanks guys for your advices, I applied few of them and I save a lot of > time, I'm at 3.9 seconds now. I'll also apply the deferred init calls > concept > later. > > I have two other questions. > > I'm not sure to understand how to use EDMA to copy from NOR to RAM in uboot. > Every post that I found it is never explain the procedure to apply this > patch. Do you guys have a piece of code or something to get started with > that? > > In the same way, after the kernel boot, I have to start an application with > QT and it takes 10 seconds to transfert QT lib (libQtCore, libQtGui, > libQtNetwork, fonts) from NOR to RAM and start the application. QT stuff is > ~20MB, I removed every useless lib to reduce the amount of data to > transfert. I also optimised the EMIFA CS2 (I changed EMIFA clock to 150 Mhz > and changed CS timing to be at the maximum of my NOR). I probed the NOR chip > select and there are big delays between read access. I suppose that is > because it is not using EDMA and the CPU is not able to feed the NOR... I > would like to reduce this transfert time to ~4 secondes or less and I think > that EDMA could maybe help to do it. Do you have any idea how to apply it, > or any other ideas? > > Thanks for your time. > > Regards, > > Nicolas > > > On Thu, Jul 29, 2010 at 10:42 PM, rohan tabish > wrote: > >> set verify=n this will ignore checksum >> >> Regard's >> RT >> >> --- On *Thu, 29/7/10, Nicolas Luna * wrote: >> >> >> From: Nicolas Luna >> Subject: Boot time >> To: davinci-linux-open-source at linux.davincidsp.com >> Date: Thursday, 29 July, 2010, 0:59 >> >> >> Hi guys, >> >> I'm trying to make by board boot as quick as possible. I did some >> optimisation with the "All This For 1 Second Boot" wiki and other website. >> I >> would like to reduce a little bit more the boot time and I wonder if you >> guys could give me some clues. >> >> I copied my boot log below. For sure I'll remove the uboot autoboot delay >> and probably build a new kernel with modules. I putted in bold part that I >> think it is possible to do more optimisation. >> >> 1- See bullet #3. >> 2- The verifying Checksum is about 400 msec is it possible to skip it? >> 3- It takes ~1 sec to start booting the kernel and there is a other ~1 sec >> delay between the starting kernel and the beginning of the uncompressing. >> Why it's so long? Ok maybe there is the copy from NOR to RAM but it should >> not take more than few msec. >> 4- It takes ~1 sec to the kernel to free 120K memory... I got enought RAM >> is it possible to remove it? >> >> I got custom hardware based on OMAP-L138 with FS (jffs2) and compressed >> kernel in NOR Flash. >> >> Thanks a lot >> >> Nicolas >> >> >> ------------------------------------------------------------------------------------- >> >> 0.000 0.000: OMAP-L138 initialization passed! >> 0.000 0.000: Booting TI User Boot Loader >> 0.004 0.004: UBL Version: 1.65 >> 0.004 0.000: UBL Flashtype: NOR >> 0.008 0.004: Starting NOR Copy... >> 0.008 0.000: CFI Query...passed. >> 0.012 0.004: NOR Initialization: >> 0.012 0.000: Command Set: Intel >> 0.012 0.000: Manufacturer: INTEL >> 0.016 0.004: Size: 0x00000020 MB >> 0.020 0.004: Valid magicnum, 0x55424CBB, found.. >> 0.184 0.164: DONE >> 0.188 0.004: Jumping to entry point at 0xC1080000. >> 0.504 0.316: >> 1.548 1.044: Hit any key to stop autoboot: 0 >> *2.372 0.824: ## Booting kernel from Legacy Image at c0007fc0 ...* >> 2.372 0.000: Image Name: Linux-2.6.34 >> 2.380 0.008: Image Type: ARM Linux Kernel Image (uncompressed) >> 2.380 0.000: Data Size: 1505956 Bytes = 1.4 MB >> 2.384 0.004: Load Address: c0008000 >> 2.388 0.004: Entry Point: c0008000 >> *2.808 0.420: Verifying Checksum ... OK* >> 2.808 0.000: Loading Kernel Image ... OK >> 2.808 0.000: OK >> 2.808 0.000: >> *2.812 0.004: Starting kernel ...* >> *2.812 0.000:* >> *3.860 1.048: Uncompressing Linux... done, booting the kernel.* >> 4.264 0.404: Linux version 2.6.34 (id at idt-ubuntu-linux) (gcc version 4.3.3 >> (Sourcery G++ Lite 2009q1-203) ) #89 PREEMPT Thu Jul 22 15:24:03 EDT 2010 >> 4.268 0.004: CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177 >> 4.272 0.004: CPU: VIVT data cache, VIVT instruction cache >> 4.276 0.004: Machine: DaVinci DA850/OMAP-L138 EVM >> 4.280 0.004: Memory policy: ECC disabled, Data cache writeback >> 4.284 0.004: DaVinci da850/omap-l138 variant 0x0 >> 4.288 0.004: Built 1 zonelists in Zone order, mobility grouping on. Total >> pages: 32512 >> 4.300 0.012: Kernel command line: lpj=747520 mem=128M >> console=ttyS2,115200n8 root=/dev/mtdblock2 rootfstype=jffs2 rw ip=off >> 4.304 0.004: PID hash table entries: 512 (order: -1, 2048 bytes) >> 4.308 0.004: Dentry cache hash table entries: 16384 (order: 4, 65536 >> bytes) >> 4.316 0.008: Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) >> 4.316 0.000: Memory: 128MB = 128MB total >> 4.324 0.008: Memory: 126752k/126752k available, 4320k reserved, 0K highmem >> 4.324 0.000: Virtual kernel memory layout: >> 4.332 0.008: vector : 0xffff0000 - 0xffff1000 ( 4 kB) >> 4.336 0.004: fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) >> 4.340 0.004: DMA : 0xff000000 - 0xffe00000 ( 14 MB) >> 4.344 0.004: vmalloc : 0xc8800000 - 0xfea00000 ( 866 MB) >> 4.348 0.004: lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) >> 4.352 0.004: modules : 0xbf000000 - 0xc0000000 ( 16 MB) >> 4.356 0.004: .init : 0xc0008000 - 0xc0026000 ( 120 kB) >> 4.360 0.004: .text : 0xc0026000 - 0xc02e8000 (2824 kB) >> 4.364 0.004: .data : 0xc02e8000 - 0xc0307a60 ( 127 kB) >> 4.372 0.008: SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, >> CPUs=1, Nodes=1 >> 4.376 0.004: Hierarchical RCU implementation. >> 4.376 0.000: NR_IRQS:245 >> 4.380 0.004: Console: colour dummy device 80x30 >> 4.384 0.004: Calibrating delay loop (skipped) preset value.. 149.50 >> BogoMIPS (lpj=747520) >> 4.388 0.004: Mount-cache hash table entries: 512 >> 4.392 0.004: CPU: Testing write buffer coherency: ok >> 4.396 0.004: DaVinci: 144 gpio irqs >> 4.396 0.000: NET: Registered protocol family 16 >> 4.400 0.004: bio: create slab at 0 >> 4.404 0.004: SCSI subsystem initialized >> 4.408 0.004: usbcore: registered new interface driver usbfs >> 4.412 0.004: usbcore: registered new interface driver hub >> 4.416 0.004: usbcore: registered new device driver usb >> 4.416 0.000: Switching to clocksource timer0_1 >> 4.420 0.004: musb_hdrc: version 6.0, pio, host, debug=0 >> 4.424 0.004: Waiting for USB PHY clock good... >> 4.428 0.004: musb_hdrc musb_hdrc: MUSB HDRC host driver >> 4.432 0.004: musb_hdrc musb_hdrc: new USB bus registered, assigned bus >> number 1 >> 4.436 0.004: hub 1-0:1.0: USB hub found >> 4.440 0.004: hub 1-0:1.0: 1 port detected >> 4.444 0.004: musb_hdrc musb_hdrc: USB Host mode controller at fee00000 >> using PIO, IRQ 58 >> 4.448 0.004: NET: Registered protocol family 2 >> 4.456 0.008: IP route cache hash table entries: 1024 (order: 0, 4096 >> bytes) >> 4.460 0.004: TCP established hash table entries: 4096 (order: 3, 32768 >> bytes) >> 4.464 0.004: TCP bind hash table entries: 4096 (order: 2, 16384 bytes) >> 4.468 0.004: TCP: Hash tables configured (established 4096 bind 4096) >> 4.472 0.004: TCP reno registered >> 4.476 0.004: UDP hash table entries: 256 (order: 0, 4096 bytes) >> 4.480 0.004: UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) >> 4.484 0.004: NET: Registered protocol family 1 >> 4.488 0.004: RPC: Registered udp transport module. >> 4.492 0.004: RPC: Registered tcp transport module. >> 4.496 0.004: RPC: Registered tcp NFSv4.1 backchannel transport module. >> 4.500 0.004: JFFS2 version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc. >> 4.504 0.004: msgmni has been set to 247 >> 4.508 0.004: io scheduler noop registered (default) >> 4.512 0.004: da8xx_lcdc da8xx_lcdc.0: GLCD: Found Sharp_LK043T1DG01 panel >> 4.516 0.004: Console: switching to colour frame buffer device 60x34 >> 4.520 0.004: Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled >> 4.528 0.008: serial8250.0: ttyS0 at MMIO 0x1c42000 (irq = 25) is a 16550A >> 4.532 0.004: serial8250.0: ttyS1 at MMIO 0x1d0c000 (irq = 53) is a 16550A >> 4.540 0.008: serial8250.0: ttyS2 at MMIO 0x1d0d000 (irq = 61) is a 16550A >> 4.540 0.000: console [ttyS2] enabled >> 4.548 0.008: brd: module loaded >> 4.556 0.008: physmap platform flash device: 02000000 at 60000000 >> 4.564 0.008: physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank >> 4.568 0.004: Intel/Sharp Extended Query Table at 0x010A >> 4.572 0.004: Intel/Sharp Extended Query Table at 0x010A >> 4.576 0.004: Intel/Sharp Extended Query Table at 0x010A >> 4.580 0.004: Intel/Sharp Extended Query Table at 0x010A >> 4.584 0.004: Intel/Sharp Extended Query Table at 0x010A >> 4.588 0.004: Using buffer write method >> 4.588 0.000: Using auto-unlock on power-up/resume >> 4.592 0.004: cfi_cmdset_0001: Erase suspend on write enabled >> 4.596 0.004: RedBoot partition parsing not available >> 4.600 0.004: Using physmap partition information >> 4.604 0.004: Creating 3 MTD partitions on "physmap-flash.0": >> 4.608 0.004: 0x000000000000-0x000000080000 : "bootloaders + env" >> 4.620 0.012: 0x000000080000-0x000000280000 : "kernel" >> 4.628 0.008: 0x000000280000-0x000002000000 : "filesystem" >> 4.636 0.008: physmap-flash.0: failed to claim resource 0 >> 4.644 0.008: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron >> NAND >> 512MiB 3,3V 8-bit) >> 4.652 0.008: Creating 2 MTD partitions on "davinci_nand.1": >> 4.656 0.004: 0x000000000000-0x000001900000 : "data" >> 4.664 0.008: 0x000001900000-0x000020000000 : "else" >> 4.672 0.008: davinci_nand davinci_nand.1: controller rev. 2.5 >> 4.680 0.008: spi_davinci spi_davinci.1: Controller at 0xfef0e000 >> 4.692 0.012: tun: Universal TUN/TAP device driver, 1.6 >> 4.696 0.004: tun: (C) 1999-2004 Max Krasnyansky >> >> > >> 4.704 0.008: ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver >> 4.708 0.004: ohci ohci.0: DA8xx OHCI >> 4.712 0.004: ohci ohci.0: new USB bus registered, assigned bus number 2 >> 4.716 0.004: Waiting for USB PHY clock good... >> 4.720 0.004: ohci ohci.0: irq 59, io mem 0x01e25000 >> 4.788 0.068: hub 2-0:1.0: USB hub found >> 4.788 0.000: hub 2-0:1.0: 1 port detected >> 4.796 0.008: Initializing USB Mass Storage driver... >> 4.804 0.008: usbcore: registered new interface driver usb-storage >> 4.804 0.000: USB Mass Storage support registered. >> 5.804 1.000: i2c_davinci i2c_davinci.1: controller timed out >> 5.808 0.004: i2c_davinci i2c_davinci.1: initiating i2c bus recovery >> 5.812 0.004: tps6507x-ts: probe of tps6507x-ts failed with error -110 >> 5.820 0.008: omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc0 >> 5.824 0.004: omap_rtc: RTC power up reset detected >> 5.824 0.000: omap_rtc: already running >> 5.828 0.004: i2c /dev entries driver >> 5.832 0.004: TCP cubic registered >> 5.836 0.004: Clocks: disable unused i2c1 >> 5.840 0.004: Clocks: disable unused emac >> 5.848 0.008: davinci_emac_probe: using random MAC addr: 72:93:72:ad:15:13 >> 5.852 0.004: emac-mii: probed >> 5.860 0.008: omap_rtc omap_rtc: setting system clock to 2000-01-01 >> 01:34:03 >> UTC (946690443) >> 6.136 0.276: VFS: Mounted root (jffs2 filesystem) on device 31:2. >> *6.140 0.004: Freeing init memory: 120K* >> *7.356 1.216: Mounting proc* >> >> -----Inline Attachment Follows----- >> >> >> _______________________________________________ >> Davinci-linux-open-source mailing list >> Davinci-linux-open-source at linux.davincidsp.com >> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source >> >> >> > -- www.opensurf.it From caglarakyuz at gmail.com Sat Jul 31 04:10:53 2010 From: caglarakyuz at gmail.com (Caglar Akyuz) Date: Sat, 31 Jul 2010 12:10:53 +0300 Subject: Boot time In-Reply-To: References: <817859.2735.qm@web24102.mail.ird.yahoo.com> Message-ID: <201007311210.53529.caglarakyuz@gmail.com> On Friday 30 July 2010 11:47:14 pm Nicolas Luna wrote: > Hi, > > Thanks guys for your advices, I applied few of them and I save a lot of > time, I'm at 3.9 seconds now. I'll also apply the deferred init calls > concept later. > > I have two other questions. > > I'm not sure to understand how to use EDMA to copy from NOR to RAM in > uboot. Every post that I found it is never explain the procedure to apply > this patch. Where is this patch? > Do you guys have a piece of code or something to get started > with that? > I ported edma code from Linux kernel to u-boot(and ubl as well), then I changed memcpy with edma copy function under u-boot where kernel is copied from flash to ram, and later for the relocation in ram. That's all. > In the same way, after the kernel boot, I have to start an application with > QT and it takes 10 seconds to transfert QT lib (libQtCore, libQtGui, > libQtNetwork, fonts) from NOR to RAM and start the application. QT stuff is > ~20MB, I removed every useless lib to reduce the amount of data to > transfert. I also optimised the EMIFA CS2 (I changed EMIFA clock to 150 Mhz > and changed CS timing to be at the maximum of my NOR). I probed the NOR > chip select and there are big delays between read access. I suppose that > is because it is not using EDMA and the CPU is not able to feed the NOR... > I would like to reduce this transfert time to ~4 secondes or less and I > think that EDMA could maybe help to do it. Do you have any idea how to > apply it, or any other ideas? > I think optimizing link time is more important than optimizing transfer time. You can use static linking but then your application needs to be GPL. So I don't think using static linking is an option. In that case you may use prelinking feature of gnu linker [1]. [1] http://people.redhat.com/jakub/prelink.pdf Regards, Caglar > Thanks for your time. > > Regards, > > Nicolas > > On Thu, Jul 29, 2010 at 10:42 PM, rohan tabish wrote: > > set verify=n this will ignore checksum > > > > Regard's > > RT > > > > --- On *Thu, 29/7/10, Nicolas Luna * wrote: > > > > > > From: Nicolas Luna > > Subject: Boot time > > To: davinci-linux-open-source at linux.davincidsp.com > > Date: Thursday, 29 July, 2010, 0:59 > > > > > > Hi guys, > > > > I'm trying to make by board boot as quick as possible. I did some > > optimisation with the "All This For 1 Second Boot" wiki and other > > website. I would like to reduce a little bit more the boot time and I > > wonder if you guys could give me some clues. > > > > I copied my boot log below. For sure I'll remove the uboot autoboot delay > > and probably build a new kernel with modules. I putted in bold part that > > I think it is possible to do more optimisation. > > > > 1- See bullet #3. > > 2- The verifying Checksum is about 400 msec is it possible to skip it? > > 3- It takes ~1 sec to start booting the kernel and there is a other ~1 > > sec delay between the starting kernel and the beginning of the > > uncompressing. Why it's so long? Ok maybe there is the copy from NOR to > > RAM but it should not take more than few msec. > > 4- It takes ~1 sec to the kernel to free 120K memory... I got enought RAM > > is it possible to remove it? > > > > I got custom hardware based on OMAP-L138 with FS (jffs2) and compressed > > kernel in NOR Flash. > > > > Thanks a lot > > > > Nicolas > > > > > > ------------------------------------------------------------------------- > >------------ > > > > 0.000 0.000: OMAP-L138 initialization passed! > > 0.000 0.000: Booting TI User Boot Loader > > 0.004 0.004: UBL Version: 1.65 > > 0.004 0.000: UBL Flashtype: NOR > > 0.008 0.004: Starting NOR Copy... > > 0.008 0.000: CFI Query...passed. > > 0.012 0.004: NOR Initialization: > > 0.012 0.000: Command Set: Intel > > 0.012 0.000: Manufacturer: INTEL > > 0.016 0.004: Size: 0x00000020 MB > > 0.020 0.004: Valid magicnum, 0x55424CBB, found.. > > 0.184 0.164: DONE > > 0.188 0.004: Jumping to entry point at 0xC1080000. > > 0.504 0.316: > > 1.548 1.044: Hit any key to stop autoboot: 0 > > *2.372 0.824: ## Booting kernel from Legacy Image at c0007fc0 ...* > > 2.372 0.000: Image Name: Linux-2.6.34 > > 2.380 0.008: Image Type: ARM Linux Kernel Image (uncompressed) > > 2.380 0.000: Data Size: 1505956 Bytes = 1.4 MB > > 2.384 0.004: Load Address: c0008000 > > 2.388 0.004: Entry Point: c0008000 > > *2.808 0.420: Verifying Checksum ... OK* > > 2.808 0.000: Loading Kernel Image ... OK > > 2.808 0.000: OK > > 2.808 0.000: > > *2.812 0.004: Starting kernel ...* > > *2.812 0.000:* > > *3.860 1.048: Uncompressing Linux... done, booting the kernel.* > > 4.264 0.404: Linux version 2.6.34 (id at idt-ubuntu-linux) (gcc version > > 4.3.3 (Sourcery G++ Lite 2009q1-203) ) #89 PREEMPT Thu Jul 22 15:24:03 > > EDT 2010 4.268 0.004: CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), > > cr=00053177 4.272 0.004: CPU: VIVT data cache, VIVT instruction cache > > 4.276 0.004: Machine: DaVinci DA850/OMAP-L138 EVM > > 4.280 0.004: Memory policy: ECC disabled, Data cache writeback > > 4.284 0.004: DaVinci da850/omap-l138 variant 0x0 > > 4.288 0.004: Built 1 zonelists in Zone order, mobility grouping on. > > Total pages: 32512 > > 4.300 0.012: Kernel command line: lpj=747520 mem=128M > > console=ttyS2,115200n8 root=/dev/mtdblock2 rootfstype=jffs2 rw ip=off > > 4.304 0.004: PID hash table entries: 512 (order: -1, 2048 bytes) > > 4.308 0.004: Dentry cache hash table entries: 16384 (order: 4, 65536 > > bytes) 4.316 0.008: Inode-cache hash table entries: 8192 (order: 3, 32768 > > bytes) 4.316 0.000: Memory: 128MB = 128MB total > > 4.324 0.008: Memory: 126752k/126752k available, 4320k reserved, 0K > > highmem 4.324 0.000: Virtual kernel memory layout: > > 4.332 0.008: vector : 0xffff0000 - 0xffff1000 ( 4 kB) > > 4.336 0.004: fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) > > 4.340 0.004: DMA : 0xff000000 - 0xffe00000 ( 14 MB) > > 4.344 0.004: vmalloc : 0xc8800000 - 0xfea00000 ( 866 MB) > > 4.348 0.004: lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) > > 4.352 0.004: modules : 0xbf000000 - 0xc0000000 ( 16 MB) > > 4.356 0.004: .init : 0xc0008000 - 0xc0026000 ( 120 kB) > > 4.360 0.004: .text : 0xc0026000 - 0xc02e8000 (2824 kB) > > 4.364 0.004: .data : 0xc02e8000 - 0xc0307a60 ( 127 kB) > > 4.372 0.008: SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, > > CPUs=1, Nodes=1 > > 4.376 0.004: Hierarchical RCU implementation. > > 4.376 0.000: NR_IRQS:245 > > 4.380 0.004: Console: colour dummy device 80x30 > > 4.384 0.004: Calibrating delay loop (skipped) preset value.. 149.50 > > BogoMIPS (lpj=747520) > > 4.388 0.004: Mount-cache hash table entries: 512 > > 4.392 0.004: CPU: Testing write buffer coherency: ok > > 4.396 0.004: DaVinci: 144 gpio irqs > > 4.396 0.000: NET: Registered protocol family 16 > > 4.400 0.004: bio: create slab at 0 > > 4.404 0.004: SCSI subsystem initialized > > 4.408 0.004: usbcore: registered new interface driver usbfs > > 4.412 0.004: usbcore: registered new interface driver hub > > 4.416 0.004: usbcore: registered new device driver usb > > 4.416 0.000: Switching to clocksource timer0_1 > > 4.420 0.004: musb_hdrc: version 6.0, pio, host, debug=0 > > 4.424 0.004: Waiting for USB PHY clock good... > > 4.428 0.004: musb_hdrc musb_hdrc: MUSB HDRC host driver > > 4.432 0.004: musb_hdrc musb_hdrc: new USB bus registered, assigned bus > > number 1 > > 4.436 0.004: hub 1-0:1.0: USB hub found > > 4.440 0.004: hub 1-0:1.0: 1 port detected > > 4.444 0.004: musb_hdrc musb_hdrc: USB Host mode controller at fee00000 > > using PIO, IRQ 58 > > 4.448 0.004: NET: Registered protocol family 2 > > 4.456 0.008: IP route cache hash table entries: 1024 (order: 0, 4096 > > bytes) 4.460 0.004: TCP established hash table entries: 4096 (order: 3, > > 32768 bytes) > > 4.464 0.004: TCP bind hash table entries: 4096 (order: 2, 16384 bytes) > > 4.468 0.004: TCP: Hash tables configured (established 4096 bind 4096) > > 4.472 0.004: TCP reno registered > > 4.476 0.004: UDP hash table entries: 256 (order: 0, 4096 bytes) > > 4.480 0.004: UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) > > 4.484 0.004: NET: Registered protocol family 1 > > 4.488 0.004: RPC: Registered udp transport module. > > 4.492 0.004: RPC: Registered tcp transport module. > > 4.496 0.004: RPC: Registered tcp NFSv4.1 backchannel transport module. > > 4.500 0.004: JFFS2 version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc. > > 4.504 0.004: msgmni has been set to 247 > > 4.508 0.004: io scheduler noop registered (default) > > 4.512 0.004: da8xx_lcdc da8xx_lcdc.0: GLCD: Found Sharp_LK043T1DG01 panel > > 4.516 0.004: Console: switching to colour frame buffer device 60x34 > > 4.520 0.004: Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled > > 4.528 0.008: serial8250.0: ttyS0 at MMIO 0x1c42000 (irq = 25) is a 16550A > > 4.532 0.004: serial8250.0: ttyS1 at MMIO 0x1d0c000 (irq = 53) is a 16550A > > 4.540 0.008: serial8250.0: ttyS2 at MMIO 0x1d0d000 (irq = 61) is a 16550A > > 4.540 0.000: console [ttyS2] enabled > > 4.548 0.008: brd: module loaded > > 4.556 0.008: physmap platform flash device: 02000000 at 60000000 > > 4.564 0.008: physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank > > 4.568 0.004: Intel/Sharp Extended Query Table at 0x010A > > 4.572 0.004: Intel/Sharp Extended Query Table at 0x010A > > 4.576 0.004: Intel/Sharp Extended Query Table at 0x010A > > 4.580 0.004: Intel/Sharp Extended Query Table at 0x010A > > 4.584 0.004: Intel/Sharp Extended Query Table at 0x010A > > 4.588 0.004: Using buffer write method > > 4.588 0.000: Using auto-unlock on power-up/resume > > 4.592 0.004: cfi_cmdset_0001: Erase suspend on write enabled > > 4.596 0.004: RedBoot partition parsing not available > > 4.600 0.004: Using physmap partition information > > 4.604 0.004: Creating 3 MTD partitions on "physmap-flash.0": > > 4.608 0.004: 0x000000000000-0x000000080000 : "bootloaders + env" > > 4.620 0.012: 0x000000080000-0x000000280000 : "kernel" > > 4.628 0.008: 0x000000280000-0x000002000000 : "filesystem" > > 4.636 0.008: physmap-flash.0: failed to claim resource 0 > > 4.644 0.008: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron > > NAND 512MiB 3,3V 8-bit) > > 4.652 0.008: Creating 2 MTD partitions on "davinci_nand.1": > > 4.656 0.004: 0x000000000000-0x000001900000 : "data" > > 4.664 0.008: 0x000001900000-0x000020000000 : "else" > > 4.672 0.008: davinci_nand davinci_nand.1: controller rev. 2.5 > > 4.680 0.008: spi_davinci spi_davinci.1: Controller at 0xfef0e000 > > 4.692 0.012: tun: Universal TUN/TAP device driver, 1.6 > > 4.696 0.004: tun: (C) 1999-2004 Max Krasnyansky > > > > > > 4.704 0.008: ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver > > 4.708 0.004: ohci ohci.0: DA8xx OHCI > > 4.712 0.004: ohci ohci.0: new USB bus registered, assigned bus number 2 > > 4.716 0.004: Waiting for USB PHY clock good... > > 4.720 0.004: ohci ohci.0: irq 59, io mem 0x01e25000 > > 4.788 0.068: hub 2-0:1.0: USB hub found > > 4.788 0.000: hub 2-0:1.0: 1 port detected > > 4.796 0.008: Initializing USB Mass Storage driver... > > 4.804 0.008: usbcore: registered new interface driver usb-storage > > 4.804 0.000: USB Mass Storage support registered. > > 5.804 1.000: i2c_davinci i2c_davinci.1: controller timed out > > 5.808 0.004: i2c_davinci i2c_davinci.1: initiating i2c bus recovery > > 5.812 0.004: tps6507x-ts: probe of tps6507x-ts failed with error -110 > > 5.820 0.008: omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc0 > > 5.824 0.004: omap_rtc: RTC power up reset detected > > 5.824 0.000: omap_rtc: already running > > 5.828 0.004: i2c /dev entries driver > > 5.832 0.004: TCP cubic registered > > 5.836 0.004: Clocks: disable unused i2c1 > > 5.840 0.004: Clocks: disable unused emac > > 5.848 0.008: davinci_emac_probe: using random MAC addr: 72:93:72:ad:15:13 > > 5.852 0.004: emac-mii: probed > > 5.860 0.008: omap_rtc omap_rtc: setting system clock to 2000-01-01 > > 01:34:03 UTC (946690443) > > 6.136 0.276: VFS: Mounted root (jffs2 filesystem) on device 31:2. > > *6.140 0.004: Freeing init memory: 120K* > > *7.356 1.216: Mounting proc* > > > > -----Inline Attachment Follows----- > > > > > > _______________________________________________ > > Davinci-linux-open-source mailing list > > Davinci-linux-open-source at linux.davincidsp.com >ci-linux-open-source at linux.davincidsp.com> > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > From amraldo at hotmail.com Wed Jul 21 01:18:17 2010 From: amraldo at hotmail.com (amr ali) Date: Wed, 21 Jul 2010 09:18:17 +0300 Subject: FB problem in arago linux 2.6.3.2-rc2-davinci1 Message-ID: Hi, I am trying to use the kernel stated above from the arago tree. The fb does not work. I have notice during rebooting only I see some figures. During normal operation, nothing appears on the screen. Is this related to the fb device driver? Is there a patch for that? -- Amr Ali Abdel-Naby Embedded Systems Developer www.embedded-tips.blogspot.com _________________________________________________________________ Hotmail: Trusted email with powerful SPAM protection. https://signup.live.com/signup.aspx?id=60969 -------------- next part -------------- An HTML attachment was scrubbed... URL: From lamiaposta71 at gmail.com Wed Jul 21 05:51:49 2010 From: lamiaposta71 at gmail.com (Raffaele Recalcati) Date: Wed, 21 Jul 2010 12:51:49 +0200 Subject: [PATCH v2] DaVinci: dm365: Added clockout2 management. Message-ID: <1279709510-6213-1-git-send-email-lamiaposta71@gmail.com> From: Davide Bonfanti Clockout2 is added as a child of pll1_sysclk9, because they have the same pll divisor. Added dm365_clkout2_set_rate to properly set clockout2 frequency. Modified the davinci_set_sysclk_rate function in order to get the right ancestor. This patch has been developed against the http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git git tree and tested on bmx board. Signed-off-by: Davide Bonfanti Signed-off-by: Raffaele Recalcati --- arch/arm/mach-davinci/clock.c | 32 ++++++++++++---- arch/arm/mach-davinci/clock.h | 5 ++ arch/arm/mach-davinci/dm365.c | 57 ++++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/dm365.h | 1 + 4 files changed, 87 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index f29a526..6e45808 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -254,7 +254,15 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) u32 v, plldiv; struct pll_data *pll; unsigned long rate = clk->rate; + struct clk *parent = clk; + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + while (parent->parent->parent) + parent = parent->parent; + + if (parent == clk) + return -EPERM; /* If this is the PLL base clock, no more calculations needed */ if (clk->pll_data) return rate; @@ -262,13 +270,13 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) if (WARN_ON(!clk->parent)) return rate; - rate = clk->parent->rate; + rate = parent->rate; + /* Otherwise, the parent must be a PLL */ - if (WARN_ON(!clk->parent->pll_data)) + if (WARN_ON(!parent->pll_data)) return rate; - - pll = clk->parent->pll_data; + pll = parent->pll_data; /* If pre-PLL, source clock is before the multiplier and divider(s) */ if (clk->flags & PRE_PLL) @@ -293,26 +301,33 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) struct pll_data *pll; unsigned long input; unsigned ratio = 0; + struct clk *parent = clk; + + /* searching the right ancestor (pll1_clk or pll2_clk) */ + while (parent->parent->parent) + parent = parent->parent; + if (parent == clk) + return -EPERM; /* If this is the PLL base clock, wrong function to call */ if (clk->pll_data) return 0; /* There must be a parent... */ - if (WARN_ON(!clk->parent)) + if (WARN_ON(!parent)) return 0; /* ... the parent must be a PLL... */ - if (WARN_ON(!clk->parent->pll_data)) + if (WARN_ON(!parent->pll_data)) return 0; /* ... and this clock must have a divider. */ if (WARN_ON(!clk->div_reg)) return 0; - pll = clk->parent->pll_data; + pll = parent->pll_data; - input = clk->parent->rate; + input = parent->rate; /* If pre-PLL, source clock is before the multiplier and divider(s) */ if (clk->flags & PRE_PLL) @@ -343,6 +358,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) return 0; } +EXPORT_SYMBOL(davinci_set_sysclk_rate); static unsigned long clk_leafclk_recalc(struct clk *clk) { diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index a717d98..df36d73 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -50,6 +50,11 @@ #define PLLDIV_EN BIT(15) #define PLLDIV_RATIO_MASK 0x1f +#define PERI_CLKCTL 0x48 +#define CLOCKOUT2EN 2 +#define CLOCKOUT1EN 1 +#define CLOCKOUT0EN 0 + /* * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 42fd4a4..902e9a0 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -40,6 +40,11 @@ #include "mux.h" #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ +#define PINMUX0 0x00 +#define PINMUX1 0x04 +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 static struct pll_data pll1_data = { .num = 1, @@ -124,6 +129,7 @@ static struct clk pll1_sysclk6 = { .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV6, + .set_rate = davinci_set_sysclk_rate, }; static struct clk pll1_sysclk7 = { @@ -145,6 +151,14 @@ static struct clk pll1_sysclk9 = { .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV9, + .set_rate = davinci_set_sysclk_rate, +}; + +static struct clk clkout2_clk = { + .name = "clkout2", + .parent = &pll1_sysclk9, + .flags = CLK_PLL, + .set_rate = dm365_clkout2_set_rate, }; static struct clk pll2_clk = { @@ -421,6 +435,7 @@ static struct clk_lookup dm365_clks[] = { CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), + CLK(NULL, "clkout2", &clkout2_clk), CLK(NULL, "pll2", &pll2_clk), CLK(NULL, "pll2_aux", &pll2_aux_clk), CLK(NULL, "clkout1", &clkout1_clk), @@ -657,6 +672,48 @@ static struct resource dm365_spi0_resources[] = { }, }; +int dm365_clkout2_set_rate(unsigned long rate) +{ + int ret = -EINVAL; + int i, err, min_err, i_min_err; + u32 regval; + struct clk *clk; + static void __iomem *system_module_base; + + clk = &clkout2_clk; + system_module_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE, SZ_4K); + regval = __raw_readl(system_module_base + PERI_CLKCTL); + + /* check all possibilities to get best fitting for the required freq */ + i_min_err = min_err = INT_MAX; + for (i = 0x0F; i > 0; i--) { + if (clk->parent->set_rate) { + ret = clk_set_rate(clk->parent, rate * i) ; + err = clk_get_rate(clk->parent) - rate * i; + if (min_err > abs(err)) { + min_err = abs(err); + i_min_err = i; + } + } + } + ret = clk_set_rate(clk->parent, rate * i_min_err) ; + if (ret) + return ret; + + /* setup DIV1 value */ + regval &= ~(0x0F << 3); + regval |= (i_min_err - 1) << 3; + + /* to make changes work stop CLOCKOUT & start it again */ + regval |= 1 << CLOCKOUT2EN; + __raw_writel(regval, system_module_base + PERI_CLKCTL); + regval &= ~(1 << CLOCKOUT2EN); + __raw_writel(regval, system_module_base + PERI_CLKCTL); + + return ret; +} +EXPORT_SYMBOL(dm365_clkout2_set_rate); + static struct platform_device dm365_spi0_device = { .name = "spi_davinci", .id = 0, diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h index ea5df3b..f59741f 100644 --- a/arch/arm/mach-davinci/include/mach/dm365.h +++ b/arch/arm/mach-davinci/include/mach/dm365.h @@ -49,4 +49,5 @@ void dm365_init_spi0(unsigned chipselect_mask, struct spi_board_info *info, unsigned len); void dm365_set_vpfe_config(struct vpfe_config *cfg); +int dm365_clkout2_set_rate(unsigned long rate); #endif /* __ASM_ARCH_DM365_H */ -- 1.7.0.4