From cyril at ti.com  Sat May  1 09:53:27 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat, 01 May 2010 10:53:27 -0400
Subject: [RFC 00/22] Davinci: pre-tnetv107x ioremap() cleanup
In-Reply-To: <87hbmshbi4.fsf@deeprootsystems.com>
References: <1272580062-17663-1-git-send-email-cyril@ti.com>
	<87hbmshbi4.fsf@deeprootsystems.com>
Message-ID: <4BDC4067.2010108@ti.com>

Hi Kevin,

[...]
> Was there supposed to be 22 patches, I only saw 16 and the shortlog below
> only lists 16 as well.

That defect was an unfortunate remnant of my misguided attempts at post
format-patch series hacking. :-)

> Also, can you separate out the GPIO cleanup/rework (patches 2-7) into
> a separate series.  I'm ready to merge that independently of the debug
> macros and this ioremap rework.

Planned for today.

Thanks
Cyril.

From cyril at ti.com  Sat May  1 11:20:03 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat, 01 May 2010 12:20:03 -0400
Subject: [RFC 00/22] Davinci: pre-tnetv107x ioremap() cleanup
In-Reply-To: <874oiseh7f.fsf@deeprootsystems.com>
References: <1272580062-17663-1-git-send-email-cyril@ti.com>
	<874oiseh7f.fsf@deeprootsystems.com>
Message-ID: <4BDC54B3.9000302@ti.com>

Hi Kevin,

[...]
> This is something that's been on my TODO for some time and I've been
> ignoring it.   Thanks a ton for tackling it.

Unless this has been covered elsewhere, what does the davinci TODO list
look like?  Pet peeves with the code?

>> These changes were tested only on the tnetv107x evm platform.
> 
> I tried a boot test on dm355 and da8xx and neither booted, but didn't
> do any more digging, because I want to take off for the weekend on a
> happy note. :)

Ouch.

> Next step is to track the boot problems on dm* and da* and then get
> this merged.  If we take care of it next week, I'd like to queue this
> up for 2.6.35.

Excellent.  I'm desperate to get my claws on a nice internal test setup
with dmx, da8xx and tnetv107x boards. That would substantially simplify
our lives.

> Thanks again Cyril,  and nice work!

Glad to contribute.

Eventually, I'd like to see IO_ADDRESS() disappear altogether.  Is there
a plan to phase this out?

Cheers
-- Cyril.

From sshtylyov at ru.mvista.com  Sat May  1 13:23:18 2010
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Sat, 1 May 2010 22:23:18 +0400
Subject: [PATCH] DAxx: export da8xx_syscfg0_base
Message-ID: <201005012223.18808.sshtylyov@ru.mvista.com>

Otherwise DA8xx/OMAP-L1x OHCI driver module won't load...

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>

---
The patch is against the recent DaVinci tree.

 arch/arm/mach-davinci/devices-da8xx.c |    1 +
 1 file changed, 1 insertion(+)

Index: linux-davinci/arch/arm/mach-davinci/devices-da8xx.c
===================================================================
--- linux-davinci.orig/arch/arm/mach-davinci/devices-da8xx.c
+++ linux-davinci/arch/arm/mach-davinci/devices-da8xx.c
@@ -46,6 +46,7 @@
 
 void __iomem *da8xx_syscfg0_base;
 void __iomem *da8xx_syscfg1_base;
+EXPORT_SYMBOL_GPL(da8xx_syscfg0_base);
 
 static struct plat_serial8250_port da8xx_serial_pdata[] = {
 	{

From cyril at ti.com  Sat May  1 13:35:55 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat, 01 May 2010 14:35:55 -0400
Subject: [PATCH] DAxx: export da8xx_syscfg0_base
In-Reply-To: <201005012223.18808.sshtylyov@ru.mvista.com>
References: <201005012223.18808.sshtylyov@ru.mvista.com>
Message-ID: <4BDC748B.8080908@ti.com>

Hi Sergei,

[...]
>  void __iomem *da8xx_syscfg0_base;
>  void __iomem *da8xx_syscfg1_base;
> +EXPORT_SYMBOL_GPL(da8xx_syscfg0_base);

Would it be an overkill to pass as a resource and ioremap in
usb_hcd_da8xx_probe() instead?

-- Cyril.

From cyril at ti.com  Sat May  1 17:37:50 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:37:50 -0400
Subject: [PATCH v5 0/5] Davinci: pre-tnetv107x gpio series
Message-ID: <1272753475-21727-1-git-send-email-cyril@ti.com>

This patch series brings in several improvements in the davinci gpio code.
This renames gpio related structures and functions to improve readability.
Further, this restructures data structures so that a variety of gpio
controller types can easily fit into the inlined gpio accessor implementation.

This series has been tested on dm355 (thanks to Sandeep) and on tnetv107x
platforms.

Cyril Chemparathy (5):
  Davinci: gpio - minor cleanup
  Davinci: gpio - structs and functions renamed
  Davinci: gpio - register layout invariant inlines
  Davinci: gpio - controller type support
  Davinci: gpio - fine grained locking

 arch/arm/mach-davinci/da830.c               |    2 +
 arch/arm/mach-davinci/da850.c               |    2 +
 arch/arm/mach-davinci/dm355.c               |    1 +
 arch/arm/mach-davinci/dm365.c               |    1 +
 arch/arm/mach-davinci/dm644x.c              |    1 +
 arch/arm/mach-davinci/dm646x.c              |    1 +
 arch/arm/mach-davinci/gpio.c                |  137 +++++++++++++++++----------
 arch/arm/mach-davinci/include/mach/common.h |    5 +
 arch/arm/mach-davinci/include/mach/gpio.h   |   72 +++++++--------
 9 files changed, 133 insertions(+), 89 deletions(-)


From cyril at ti.com  Sat May  1 17:37:53 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:37:53 -0400
Subject: [PATCH v5 3/5] Davinci: gpio - register layout invariant inlines
In-Reply-To: <1272753475-21727-1-git-send-email-cyril@ti.com>
References: <1272753475-21727-1-git-send-email-cyril@ti.com>
Message-ID: <1272753475-21727-4-git-send-email-cyril@ti.com>

This patch renders the inlined gpio accessors in gpio.h independent of the
underlying controller's register layout.  This is done by including three new
fields in davinci_gpio_controller to hold the addresses of the set, clear, and
in data registers.

Other changes:

1. davinci_gpio_regs structure definition moved to gpio.c.  This structure is
no longer common across all davinci socs (davinci_gpio_controller is).

2. controller base address calculation code (gpio2controller()) moved to
gpio.c as this was no longer necessary for the inline implementation.

3. modified inline range checks to use davinci_soc_info.gpio_num instead of
DAVINCI_N_GPIO.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
---
v5: unchanged from v4

 arch/arm/mach-davinci/gpio.c                |   41 ++++++++++++++++-
 arch/arm/mach-davinci/include/mach/common.h |    4 ++
 arch/arm/mach-davinci/include/mach/gpio.h   |   65 +++++++++-----------------
 3 files changed, 65 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index c77683c..d241b4f 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -20,6 +20,19 @@
 
 #include <asm/mach/irq.h>
 
+struct davinci_gpio_regs {
+	u32	dir;
+	u32	out_data;
+	u32	set_data;
+	u32	clr_data;
+	u32	in_data;
+	u32	set_rising;
+	u32	clr_rising;
+	u32	set_falling;
+	u32	clr_falling;
+	u32	intstat;
+};
+
 static DEFINE_SPINLOCK(gpio_lock);
 
 #define chip2controller(chip)	\
@@ -27,10 +40,24 @@ static DEFINE_SPINLOCK(gpio_lock);
 
 static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 
-/* create a non-inlined version */
 static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
 {
-	return __gpio_to_controller(gpio);
+	void __iomem *ptr;
+	void __iomem *base = davinci_soc_info.gpio_base;
+
+	if (gpio < 32 * 1)
+		ptr = base + 0x10;
+	else if (gpio < 32 * 2)
+		ptr = base + 0x38;
+	else if (gpio < 32 * 3)
+		ptr = base + 0x60;
+	else if (gpio < 32 * 4)
+		ptr = base + 0x88;
+	else if (gpio < 32 * 5)
+		ptr = base + 0xb0;
+	else
+		ptr = NULL;
+	return ptr;
 }
 
 static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
@@ -116,6 +143,7 @@ static int __init davinci_gpio_setup(void)
 	int i, base;
 	unsigned ngpio;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
+	struct davinci_gpio_regs *regs;
 
 	/*
 	 * The gpio banks conceptually expose a segmented bitmap,
@@ -144,11 +172,18 @@ static int __init davinci_gpio_setup(void)
 		if (chips[i].chip.ngpio > 32)
 			chips[i].chip.ngpio = 32;
 
-		chips[i].regs = gpio2regs(base);
+		regs = gpio2regs(base);
+		chips[i].regs = regs;
+		chips[i].set_data = &regs->set_data;
+		chips[i].clr_data = &regs->clr_data;
+		chips[i].in_data = &regs->in_data;
 
 		gpiochip_add(&chips[i].chip);
 	}
 
+	soc_info->gpio_ctlrs = chips;
+	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
+
 	davinci_gpio_irq_setup();
 	return 0;
 }
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 884dc72..1d72883 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -37,6 +37,8 @@ struct davinci_timer_info {
 	unsigned int			clocksource_id;
 };
 
+struct davinci_gpio_controller;
+
 /* SoC specific init support */
 struct davinci_soc_info {
 	struct map_desc			*io_desc;
@@ -61,6 +63,8 @@ struct davinci_soc_info {
 	unsigned			gpio_num;
 	unsigned			gpio_irq;
 	unsigned			gpio_unbanked;
+	struct davinci_gpio_controller	*gpio_ctlrs;
+	int				gpio_ctlrs_num;
 	struct platform_device		*serial_dev;
 	struct emac_platform_data	*emac_pdata;
 	dma_addr_t			sram_dma;
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index bdab001..82591d0 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -45,23 +45,13 @@
 /* Convert GPIO signal to GPIO pin number */
 #define GPIO_TO_PIN(bank, gpio)	(16 * (bank) + (gpio))
 
-struct davinci_gpio_regs {
-	u32	dir;
-	u32	out_data;
-	u32	set_data;
-	u32	clr_data;
-	u32	in_data;
-	u32	set_rising;
-	u32	clr_rising;
-	u32	set_falling;
-	u32	clr_falling;
-	u32	intstat;
-};
-
 struct davinci_gpio_controller {
-	struct davinci_gpio_regs __iomem *regs;
 	struct gpio_chip	chip;
 	int			irq_base;
+	void __iomem		*regs;
+	void __iomem		*set_data;
+	void __iomem		*clr_data;
+	void __iomem		*in_data;
 };
 
 /* The __gpio_to_controller() and __gpio_mask() functions inline to constants
@@ -73,25 +63,16 @@ struct davinci_gpio_controller {
  *
  * These are NOT part of the cross-platform GPIO interface
  */
-static inline struct davinci_gpio_regs __iomem *
+static inline struct davinci_gpio_controller *
 __gpio_to_controller(unsigned gpio)
 {
-	void __iomem *ptr;
-	void __iomem *base = davinci_soc_info.gpio_base;
-
-	if (gpio < 32 * 1)
-		ptr = base + 0x10;
-	else if (gpio < 32 * 2)
-		ptr = base + 0x38;
-	else if (gpio < 32 * 3)
-		ptr = base + 0x60;
-	else if (gpio < 32 * 4)
-		ptr = base + 0x88;
-	else if (gpio < 32 * 5)
-		ptr = base + 0xb0;
-	else
-		ptr = NULL;
-	return ptr;
+	struct davinci_gpio_controller *ctlrs = davinci_soc_info.gpio_ctlrs;
+	int index = gpio / 32;
+
+	if (!ctlrs || index >= davinci_soc_info.gpio_ctlrs_num)
+		return NULL;
+
+	return ctlrs + index;
 }
 
 static inline u32 __gpio_mask(unsigned gpio)
@@ -107,16 +88,16 @@ static inline u32 __gpio_mask(unsigned gpio)
  */
 static inline void gpio_set_value(unsigned gpio, int value)
 {
-	if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
-		struct davinci_gpio_regs	__iomem *g;
-		u32			mask;
+	if (__builtin_constant_p(value) && gpio < davinci_soc_info.gpio_num) {
+		struct davinci_gpio_controller *ctlr;
+		u32				mask;
 
-		g = __gpio_to_controller(gpio);
+		ctlr = __gpio_to_controller(gpio);
 		mask = __gpio_mask(gpio);
 		if (value)
-			__raw_writel(mask, &g->set_data);
+			__raw_writel(mask, ctlr->set_data);
 		else
-			__raw_writel(mask, &g->clr_data);
+			__raw_writel(mask, ctlr->clr_data);
 		return;
 	}
 
@@ -134,18 +115,18 @@ static inline void gpio_set_value(unsigned gpio, int value)
  */
 static inline int gpio_get_value(unsigned gpio)
 {
-	struct davinci_gpio_regs	__iomem *g;
+	struct davinci_gpio_controller *ctlr;
 
-	if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
+	if (!__builtin_constant_p(gpio) || gpio >= davinci_soc_info.gpio_num)
 		return __gpio_get_value(gpio);
 
-	g = __gpio_to_controller(gpio);
-	return __gpio_mask(gpio) & __raw_readl(&g->in_data);
+	ctlr = __gpio_to_controller(gpio);
+	return __gpio_mask(gpio) & __raw_readl(ctlr->in_data);
 }
 
 static inline int gpio_cansleep(unsigned gpio)
 {
-	if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO)
+	if (__builtin_constant_p(gpio) && gpio < davinci_soc_info.gpio_num)
 		return 0;
 	else
 		return __gpio_cansleep(gpio);
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:37:51 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:37:51 -0400
Subject: [PATCH v5 1/5] Davinci: gpio - minor cleanup
In-Reply-To: <1272753475-21727-1-git-send-email-cyril@ti.com>
References: <1272753475-21727-1-git-send-email-cyril@ti.com>
Message-ID: <1272753475-21727-2-git-send-email-cyril@ti.com>

macroized repeated container_of()s to improve readability.
unified direction in/out functions.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
---
v5: unchanged from v4

 arch/arm/mach-davinci/gpio.c |   50 ++++++++++++++++++++++-------------------
 1 files changed, 27 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 5476ad1..93f7c68 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -28,6 +28,9 @@ struct davinci_gpio {
 	int			irq_base;
 };
 
+#define chip2controller(chip)	\
+	container_of(chip, struct davinci_gpio, chip)
+
 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 
 /* create a non-inlined version */
@@ -54,21 +57,39 @@ static int __init davinci_gpio_irq_setup(void);
  * needed, and enable the GPIO clock.
  */
 
-static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
+static inline int __davinci_direction(struct gpio_chip *chip,
+			unsigned offset, bool out, int value)
 {
-	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+	struct davinci_gpio *d = chip2controller(chip);
 	struct gpio_controller __iomem *g = d->regs;
 	u32 temp;
+	u32 mask = 1 << offset;
 
 	spin_lock(&gpio_lock);
 	temp = __raw_readl(&g->dir);
-	temp |= (1 << offset);
+	if (out) {
+		temp &= ~mask;
+		__raw_writel(mask, value ? &g->set_data : &g->clr_data);
+	} else {
+		temp |= mask;
+	}
 	__raw_writel(temp, &g->dir);
 	spin_unlock(&gpio_lock);
 
 	return 0;
 }
 
+static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
+{
+	return __davinci_direction(chip, offset, false, 0);
+}
+
+static int
+davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
+{
+	return __davinci_direction(chip, offset, true, value);
+}
+
 /*
  * Read the pin's value (works even if it's set up as output);
  * returns zero/nonzero.
@@ -78,36 +99,19 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
  */
 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+	struct davinci_gpio *d = chip2controller(chip);
 	struct gpio_controller __iomem *g = d->regs;
 
 	return (1 << offset) & __raw_readl(&g->in_data);
 }
 
-static int
-davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
-{
-	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller __iomem *g = d->regs;
-	u32 temp;
-	u32 mask = 1 << offset;
-
-	spin_lock(&gpio_lock);
-	temp = __raw_readl(&g->dir);
-	temp &= ~mask;
-	__raw_writel(mask, value ? &g->set_data : &g->clr_data);
-	__raw_writel(temp, &g->dir);
-	spin_unlock(&gpio_lock);
-	return 0;
-}
-
 /*
  * Assuming the pin is muxed as a gpio output, set its output value.
  */
 static void
 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
-	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+	struct davinci_gpio *d = chip2controller(chip);
 	struct gpio_controller __iomem *g = d->regs;
 
 	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
@@ -262,7 +266,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 
 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 {
-	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+	struct davinci_gpio *d = chip2controller(chip);
 
 	if (d->irq_base >= 0)
 		return d->irq_base + offset;
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:37:55 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:37:55 -0400
Subject: [PATCH v5 5/5] Davinci: gpio - fine grained locking
In-Reply-To: <1272753475-21727-1-git-send-email-cyril@ti.com>
References: <1272753475-21727-1-git-send-email-cyril@ti.com>
Message-ID: <1272753475-21727-6-git-send-email-cyril@ti.com>

This patch eliminates the global gpio_lock, and implements a per-controller
lock instead.  This also switches to irqsave/irqrestore locks in case gpios
are manipulated in isr.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
---
v5: unchanged from v4

 arch/arm/mach-davinci/gpio.c              |    9 +++++----
 arch/arm/mach-davinci/include/mach/gpio.h |    3 +++
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index e422cd3..b62d5e2 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -33,8 +33,6 @@ struct davinci_gpio_regs {
 	u32	intstat;
 };
 
-static DEFINE_SPINLOCK(gpio_lock);
-
 #define chip2controller(chip)	\
 	container_of(chip, struct davinci_gpio_controller, chip)
 
@@ -83,10 +81,11 @@ static inline int __davinci_direction(struct gpio_chip *chip,
 {
 	struct davinci_gpio_controller *d = chip2controller(chip);
 	struct davinci_gpio_regs __iomem *g = d->regs;
+	unsigned long flags;
 	u32 temp;
 	u32 mask = 1 << offset;
 
-	spin_lock(&gpio_lock);
+	spin_lock_irqsave(&d->lock, flags);
 	temp = __raw_readl(&g->dir);
 	if (out) {
 		temp &= ~mask;
@@ -95,7 +94,7 @@ static inline int __davinci_direction(struct gpio_chip *chip,
 		temp |= mask;
 	}
 	__raw_writel(temp, &g->dir);
-	spin_unlock(&gpio_lock);
+	spin_unlock_irqrestore(&d->lock, flags);
 
 	return 0;
 }
@@ -175,6 +174,8 @@ static int __init davinci_gpio_setup(void)
 		if (chips[i].chip.ngpio > 32)
 			chips[i].chip.ngpio = 32;
 
+		spin_lock_init(&chips[i].lock);
+
 		regs = gpio2regs(base);
 		chips[i].regs = regs;
 		chips[i].set_data = &regs->set_data;
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 9a71a26..504cc18 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -14,6 +14,8 @@
 #define	__DAVINCI_GPIO_H
 
 #include <linux/io.h>
+#include <linux/spinlock.h>
+
 #include <asm-generic/gpio.h>
 
 #include <mach/irqs.h>
@@ -52,6 +54,7 @@ enum davinci_gpio_type {
 struct davinci_gpio_controller {
 	struct gpio_chip	chip;
 	int			irq_base;
+	spinlock_t		lock;
 	void __iomem		*regs;
 	void __iomem		*set_data;
 	void __iomem		*clr_data;
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:37:52 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:37:52 -0400
Subject: [PATCH v5 2/5] Davinci: gpio - structs and functions renamed
In-Reply-To: <1272753475-21727-1-git-send-email-cyril@ti.com>
References: <1272753475-21727-1-git-send-email-cyril@ti.com>
Message-ID: <1272753475-21727-3-git-send-email-cyril@ti.com>

Renamed gpio types to something more sensible:
	struct gpio_controller	--> struct davinci_gpio_regs
	struct davinci_gpio	--> struct davinci_gpio_controller
	gpio2controller()	--> gpio2regs()
	irq2controller()	--> irq2regs()

This change also moves davinci_gpio_controller definition to gpio.h.
Eventually, the gpio registers structure will be moved to gpio.c and no longer
a common cross-soc definition.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
---
v5: unchanged from v4
v4: renamed irq2controller as per Sergei's comment

 arch/arm/mach-davinci/gpio.c              |   50 +++++++++++++----------------
 arch/arm/mach-davinci/include/mach/gpio.h |   14 ++++++--
 2 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 93f7c68..c77683c 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -22,28 +22,22 @@
 
 static DEFINE_SPINLOCK(gpio_lock);
 
-struct davinci_gpio {
-	struct gpio_chip	chip;
-	struct gpio_controller	__iomem *regs;
-	int			irq_base;
-};
-
 #define chip2controller(chip)	\
-	container_of(chip, struct davinci_gpio, chip)
+	container_of(chip, struct davinci_gpio_controller, chip)
 
-static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
+static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 
 /* create a non-inlined version */
-static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
+static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
 {
 	return __gpio_to_controller(gpio);
 }
 
-static inline struct gpio_controller __iomem *irq2controller(int irq)
+static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
 {
-	struct gpio_controller __iomem *g;
+	struct davinci_gpio_regs __iomem *g;
 
-	g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq);
+	g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
 
 	return g;
 }
@@ -60,8 +54,8 @@ static int __init davinci_gpio_irq_setup(void);
 static inline int __davinci_direction(struct gpio_chip *chip,
 			unsigned offset, bool out, int value)
 {
-	struct davinci_gpio *d = chip2controller(chip);
-	struct gpio_controller __iomem *g = d->regs;
+	struct davinci_gpio_controller *d = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *g = d->regs;
 	u32 temp;
 	u32 mask = 1 << offset;
 
@@ -99,8 +93,8 @@ davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
  */
 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-	struct davinci_gpio *d = chip2controller(chip);
-	struct gpio_controller __iomem *g = d->regs;
+	struct davinci_gpio_controller *d = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *g = d->regs;
 
 	return (1 << offset) & __raw_readl(&g->in_data);
 }
@@ -111,8 +105,8 @@ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 static void
 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
-	struct davinci_gpio *d = chip2controller(chip);
-	struct gpio_controller __iomem *g = d->regs;
+	struct davinci_gpio_controller *d = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *g = d->regs;
 
 	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
 }
@@ -150,7 +144,7 @@ static int __init davinci_gpio_setup(void)
 		if (chips[i].chip.ngpio > 32)
 			chips[i].chip.ngpio = 32;
 
-		chips[i].regs = gpio2controller(base);
+		chips[i].regs = gpio2regs(base);
 
 		gpiochip_add(&chips[i].chip);
 	}
@@ -174,7 +168,7 @@ pure_initcall(davinci_gpio_setup);
 
 static void gpio_irq_disable(unsigned irq)
 {
-	struct gpio_controller __iomem *g = irq2controller(irq);
+	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	__raw_writel(mask, &g->clr_falling);
@@ -183,7 +177,7 @@ static void gpio_irq_disable(unsigned irq)
 
 static void gpio_irq_enable(unsigned irq)
 {
-	struct gpio_controller __iomem *g = irq2controller(irq);
+	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 	u32 mask = (u32) get_irq_data(irq);
 	unsigned status = irq_desc[irq].status;
 
@@ -199,7 +193,7 @@ static void gpio_irq_enable(unsigned irq)
 
 static int gpio_irq_type(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller __iomem *g = irq2controller(irq);
+	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -228,7 +222,7 @@ static struct irq_chip gpio_irqchip = {
 static void
 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-	struct gpio_controller __iomem *g = irq2controller(irq);
+	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 	u32 mask = 0xffff;
 
 	/* we only care about one bank */
@@ -266,7 +260,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 
 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 {
-	struct davinci_gpio *d = chip2controller(chip);
+	struct davinci_gpio_controller *d = chip2controller(chip);
 
 	if (d->irq_base >= 0)
 		return d->irq_base + offset;
@@ -289,7 +283,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 
 static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller __iomem *g = irq2controller(irq);
+	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -318,7 +312,7 @@ static int __init davinci_gpio_irq_setup(void)
 	u32		binten = 0;
 	unsigned	ngpio, bank_irq;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	struct gpio_controller	__iomem *g;
+	struct davinci_gpio_regs	__iomem *g;
 
 	ngpio = soc_info->gpio_num;
 
@@ -367,7 +361,7 @@ static int __init davinci_gpio_irq_setup(void)
 		gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
 
 		/* default trigger: both edges */
-		g = gpio2controller(0);
+		g = gpio2regs(0);
 		__raw_writel(~0, &g->set_falling);
 		__raw_writel(~0, &g->set_rising);
 
@@ -392,7 +386,7 @@ static int __init davinci_gpio_irq_setup(void)
 		unsigned		i;
 
 		/* disabled by default, enabled only as needed */
-		g = gpio2controller(gpio);
+		g = gpio2regs(gpio);
 		__raw_writel(~0, &g->clr_falling);
 		__raw_writel(~0, &g->clr_rising);
 
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 0099e6e..bdab001 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -45,7 +45,7 @@
 /* Convert GPIO signal to GPIO pin number */
 #define GPIO_TO_PIN(bank, gpio)	(16 * (bank) + (gpio))
 
-struct gpio_controller {
+struct davinci_gpio_regs {
 	u32	dir;
 	u32	out_data;
 	u32	set_data;
@@ -58,6 +58,12 @@ struct gpio_controller {
 	u32	intstat;
 };
 
+struct davinci_gpio_controller {
+	struct davinci_gpio_regs __iomem *regs;
+	struct gpio_chip	chip;
+	int			irq_base;
+};
+
 /* The __gpio_to_controller() and __gpio_mask() functions inline to constants
  * with constant parameters; or in outlined code they execute at runtime.
  *
@@ -67,7 +73,7 @@ struct gpio_controller {
  *
  * These are NOT part of the cross-platform GPIO interface
  */
-static inline struct gpio_controller __iomem *
+static inline struct davinci_gpio_regs __iomem *
 __gpio_to_controller(unsigned gpio)
 {
 	void __iomem *ptr;
@@ -102,7 +108,7 @@ static inline u32 __gpio_mask(unsigned gpio)
 static inline void gpio_set_value(unsigned gpio, int value)
 {
 	if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
-		struct gpio_controller	__iomem *g;
+		struct davinci_gpio_regs	__iomem *g;
 		u32			mask;
 
 		g = __gpio_to_controller(gpio);
@@ -128,7 +134,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
  */
 static inline int gpio_get_value(unsigned gpio)
 {
-	struct gpio_controller	__iomem *g;
+	struct davinci_gpio_regs	__iomem *g;
 
 	if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
 		return __gpio_get_value(gpio);
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:37:54 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:37:54 -0400
Subject: [PATCH v5 4/5] Davinci: gpio - controller type support
In-Reply-To: <1272753475-21727-1-git-send-email-cyril@ti.com>
References: <1272753475-21727-1-git-send-email-cyril@ti.com>
Message-ID: <1272753475-21727-5-git-send-email-cyril@ti.com>

This patch allows for gpio controllers that deviate from those found on
traditional davinci socs.  davinci_soc_info has an added field to indicate the
soc-specific gpio controller type.  The gpio initialization code then bails
out if necessary.

More elements (tnetv107x) to be added later into enum davinci_gpio_type.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
---
v5: commit description changed

 arch/arm/mach-davinci/da830.c               |    2 ++
 arch/arm/mach-davinci/da850.c               |    2 ++
 arch/arm/mach-davinci/dm355.c               |    1 +
 arch/arm/mach-davinci/dm365.c               |    1 +
 arch/arm/mach-davinci/dm644x.c              |    1 +
 arch/arm/mach-davinci/dm646x.c              |    1 +
 arch/arm/mach-davinci/gpio.c                |    3 +++
 arch/arm/mach-davinci/include/mach/common.h |    1 +
 arch/arm/mach-davinci/include/mach/gpio.h   |    4 ++++
 9 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 122e61a..68e5233 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -19,6 +19,7 @@
 #include <mach/common.h>
 #include <mach/time.h>
 #include <mach/da8xx.h>
+#include <mach/gpio.h>
 
 #include "clock.h"
 #include "mux.h"
@@ -1199,6 +1200,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.intc_irq_prios		= da830_default_priorities,
 	.intc_irq_num		= DA830_N_CP_INTC_IRQ,
 	.timer_info		= &da830_timer_info,
+	.gpio_type		= GPIO_TYPE_DAVINCI,
 	.gpio_base		= IO_ADDRESS(DA8XX_GPIO_BASE),
 	.gpio_num		= 128,
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index d0fd756..8aefcff 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -27,6 +27,7 @@
 #include <mach/da8xx.h>
 #include <mach/cpufreq.h>
 #include <mach/pm.h>
+#include <mach/gpio.h>
 
 #include "clock.h"
 #include "mux.h"
@@ -1084,6 +1085,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.intc_irq_prios		= da850_default_priorities,
 	.intc_irq_num		= DA850_N_CP_INTC_IRQ,
 	.timer_info		= &da850_timer_info,
+	.gpio_type		= GPIO_TYPE_DAVINCI,
 	.gpio_base		= IO_ADDRESS(DA8XX_GPIO_BASE),
 	.gpio_num		= 144,
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 5efce70..f9a54ff 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -859,6 +859,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.intc_irq_prios		= dm355_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm355_timer_info,
+	.gpio_type		= GPIO_TYPE_DAVINCI,
 	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
 	.gpio_num		= 104,
 	.gpio_irq		= IRQ_DM355_GPIOBNK0,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 1ee3fc8..0566675 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1064,6 +1064,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.intc_irq_prios		= dm365_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm365_timer_info,
+	.gpio_type		= GPIO_TYPE_DAVINCI,
 	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
 	.gpio_num		= 104,
 	.gpio_irq		= IRQ_DM365_GPIO0,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 23cbe9d..4af349e 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -748,6 +748,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.intc_irq_prios 	= dm644x_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm644x_timer_info,
+	.gpio_type		= GPIO_TYPE_DAVINCI,
 	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
 	.gpio_num		= 71,
 	.gpio_irq		= IRQ_GPIOBNK0,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index a0b3739..bdb1ace 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -832,6 +832,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.intc_irq_prios		= dm646x_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm646x_timer_info,
+	.gpio_type		= GPIO_TYPE_DAVINCI,
 	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
 	.gpio_num		= 43, /* Only 33 usable */
 	.gpio_irq		= IRQ_DM646X_GPIOBNK0,
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index d241b4f..e422cd3 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -145,6 +145,9 @@ static int __init davinci_gpio_setup(void)
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	struct davinci_gpio_regs *regs;
 
+	if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
+		return 0;
+
 	/*
 	 * The gpio banks conceptually expose a segmented bitmap,
 	 * and "ngpio" is one more than the largest zero-based
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 1d72883..8ffef5b 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -59,6 +59,7 @@ struct davinci_soc_info {
 	u8				*intc_irq_prios;
 	unsigned long			intc_irq_num;
 	struct davinci_timer_info	*timer_info;
+	int				gpio_type;
 	void __iomem			*gpio_base;
 	unsigned			gpio_num;
 	unsigned			gpio_irq;
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 82591d0..9a71a26 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -21,6 +21,10 @@
 
 #define DAVINCI_GPIO_BASE 0x01C67000
 
+enum davinci_gpio_type {
+	GPIO_TYPE_DAVINCI = 0,
+};
+
 /*
  * basic gpio routines
  *
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:38:27 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:38:27 -0400
Subject: [PATCH v5 1/2] Davinci: eliminate pinmux offset verbosity
In-Reply-To: <1272753508-22549-1-git-send-email-cyril@ti.com>
References: <1272753508-22549-1-git-send-email-cyril@ti.com>
Message-ID: <1272753508-22549-2-git-send-email-cyril@ti.com>

Pinmux registers are sequential, and do not need to be enumerated out as they
currently are.  This reduces code volume and keeps things simple.

If some future SoC comes up with a discontiguous register map, PINMUX() can
then be expanded with local token pasting.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v5: unified PINMUX() definitions

 arch/arm/mach-davinci/dm355.c              |    5 -----
 arch/arm/mach-davinci/dm365.c              |    5 -----
 arch/arm/mach-davinci/dm644x.c             |    3 ---
 arch/arm/mach-davinci/dm646x.c             |    3 ---
 arch/arm/mach-davinci/gpio.c               |    6 +-----
 arch/arm/mach-davinci/include/mach/da8xx.h |   21 ---------------------
 arch/arm/mach-davinci/include/mach/mux.h   |    2 ++
 arch/arm/mach-davinci/mux.h                |    2 +-
 8 files changed, 4 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index f9a54ff..f91e9a1 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -450,11 +450,6 @@ void __init dm355_init_spi0(unsigned chipselect_mask,
 
 /*----------------------------------------------------------------------*/
 
-#define PINMUX0		0x00
-#define PINMUX1		0x04
-#define PINMUX2		0x08
-#define PINMUX3		0x0c
-#define PINMUX4		0x10
 #define INTMUX		0x18
 #define EVTMUX		0x1c
 
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0566675..f2b1d93 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -467,11 +467,6 @@ static struct clk_lookup dm365_clks[] = {
 
 /*----------------------------------------------------------------------*/
 
-#define PINMUX0		0x00
-#define PINMUX1		0x04
-#define PINMUX2		0x08
-#define PINMUX3		0x0c
-#define PINMUX4		0x10
 #define INTMUX		0x18
 #define EVTMUX		0x1c
 
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 4af349e..85c88ec 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -350,9 +350,6 @@ static struct platform_device dm644x_emac_device = {
        .resource	= dm644x_emac_resources,
 };
 
-#define PINMUX0		0x00
-#define PINMUX1		0x04
-
 /*
  * Device specific mux setup
  *
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index bdb1ace..a8189c9 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -401,9 +401,6 @@ static struct platform_device dm646x_emac_device = {
 	.resource	= dm646x_emac_resources,
 };
 
-#define PINMUX0		0x00
-#define PINMUX1		0x04
-
 /*
  * Device specific mux setup
  *
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index b62d5e2..2efb446 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -71,11 +71,7 @@ static int __init davinci_gpio_irq_setup(void);
 
 /*--------------------------------------------------------------------------*/
 
-/*
- * board setup code *MUST* set PINMUX0 and PINMUX1 as
- * needed, and enable the GPIO clock.
- */
-
+/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
 static inline int __davinci_direction(struct gpio_chip *chip,
 			unsigned offset, bool out, int value)
 {
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 33471c9..dbb4ebe 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -64,27 +64,6 @@ extern void __iomem *da8xx_syscfg1_base;
 #define DA8XX_DDR2_CTL_BASE	0xb0000000
 #define DA8XX_ARM_RAM_BASE	0xffff0000
 
-#define PINMUX0			0x00
-#define PINMUX1			0x04
-#define PINMUX2			0x08
-#define PINMUX3			0x0c
-#define PINMUX4			0x10
-#define PINMUX5			0x14
-#define PINMUX6			0x18
-#define PINMUX7			0x1c
-#define PINMUX8			0x20
-#define PINMUX9			0x24
-#define PINMUX10		0x28
-#define PINMUX11		0x2c
-#define PINMUX12		0x30
-#define PINMUX13		0x34
-#define PINMUX14		0x38
-#define PINMUX15		0x3c
-#define PINMUX16		0x40
-#define PINMUX17		0x44
-#define PINMUX18		0x48
-#define PINMUX19		0x4c
-
 void __init da830_init(void);
 void __init da850_init(void);
 
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 923debe..743dbd2 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -1174,6 +1174,8 @@ enum davinci_tnetv107x_index {
 	TNETV107X_TDM0_RX,
 };
 
+#define PINMUX(x)		(4 * (x))
+
 #ifdef CONFIG_DAVINCI_MUX
 /* setup pin muxing */
 extern int davinci_cfg_reg(unsigned long reg_cfg);
diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h
index adc8694..5aad1e7 100644
--- a/arch/arm/mach-davinci/mux.h
+++ b/arch/arm/mach-davinci/mux.h
@@ -20,7 +20,7 @@
 			.name =  #desc,					\
 			.debug = dbg,					\
 			.mux_reg_name = "PINMUX"#muxreg,		\
-			.mux_reg = PINMUX##muxreg,			\
+			.mux_reg = PINMUX(muxreg),			\
 			.mask_offset = mode_offset,			\
 			.mask = mode_mask,				\
 			.mode = mux_mode,				\
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:38:26 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:38:26 -0400
Subject: [PATCH v5 0/2] pre-tnetv107x miscellaneous series
Message-ID: <1272753508-22549-1-git-send-email-cyril@ti.com>

This series contains a couple of pretty unrelated changes that (a) eliminate
redundant PINMUX macro definitions, and (b) allow derivative socs (e.g.
tnetv107x) to implement machine reset schemes using non-Timer64 hardware.

This series has been tested on dm355 (thanks to Sandeep) and tnetv107x
hardware.

Cyril Chemparathy (2):
  Davinci: eliminate pinmux offset verbosity
  Davinci: watchdog reset separation across socs

 arch/arm/mach-davinci/clock.h               |    1 +
 arch/arm/mach-davinci/common.c              |    3 +++
 arch/arm/mach-davinci/da830.c               |    1 +
 arch/arm/mach-davinci/da850.c               |    1 +
 arch/arm/mach-davinci/devices-da8xx.c       |    4 ++--
 arch/arm/mach-davinci/dm355.c               |    6 +-----
 arch/arm/mach-davinci/dm365.c               |    6 +-----
 arch/arm/mach-davinci/dm644x.c              |    4 +---
 arch/arm/mach-davinci/dm646x.c              |    4 +---
 arch/arm/mach-davinci/gpio.c                |    6 +-----
 arch/arm/mach-davinci/include/mach/common.h |    2 ++
 arch/arm/mach-davinci/include/mach/da8xx.h  |   23 ++---------------------
 arch/arm/mach-davinci/include/mach/mux.h    |    2 ++
 arch/arm/mach-davinci/include/mach/system.h |    5 +++--
 arch/arm/mach-davinci/mux.h                 |    2 +-
 arch/arm/mach-davinci/time.c                |    9 ++++++---
 16 files changed, 29 insertions(+), 50 deletions(-)


From cyril at ti.com  Sat May  1 17:38:28 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:38:28 -0400
Subject: [PATCH v5 2/2] Davinci: watchdog reset separation across socs
In-Reply-To: <1272753508-22549-1-git-send-email-cyril@ti.com>
References: <1272753508-22549-1-git-send-email-cyril@ti.com>
Message-ID: <1272753508-22549-3-git-send-email-cyril@ti.com>

The earlier watchdog reset mechanism had a couple of limitations.  First, it
embedded a reference to "davinci_wdt_device" inside common code.  This
forced all derived platforms (da8xx and tnetv107x) to define such a device.
This also would have caused problems in including multiple socs in a single
build due to symbol redefinition.

With this patch, davinci_watchdog_reset() now takes the platform device as an
argument.  The davinci_soc_info struct has been extended to include a reset
function and a watchdog platform_device.  arch_reset() then uses these
elements to reset the system in a SoC specific fashion.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
---
v5: unchanged from v4

 arch/arm/mach-davinci/clock.h               |    1 +
 arch/arm/mach-davinci/common.c              |    3 +++
 arch/arm/mach-davinci/da830.c               |    1 +
 arch/arm/mach-davinci/da850.c               |    1 +
 arch/arm/mach-davinci/devices-da8xx.c       |    4 ++--
 arch/arm/mach-davinci/dm355.c               |    1 +
 arch/arm/mach-davinci/dm365.c               |    1 +
 arch/arm/mach-davinci/dm644x.c              |    1 +
 arch/arm/mach-davinci/dm646x.c              |    1 +
 arch/arm/mach-davinci/include/mach/common.h |    2 ++
 arch/arm/mach-davinci/include/mach/da8xx.h  |    2 ++
 arch/arm/mach-davinci/include/mach/system.h |    5 +++--
 arch/arm/mach-davinci/time.c                |    9 ++++++---
 13 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index ce26015..01e3648 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -120,6 +120,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
 				unsigned int mult, unsigned int postdiv);
 
 extern struct platform_device davinci_wdt_device;
+extern void davinci_watchdog_reset(struct platform_device *);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 94f27cb..f8221c5 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -77,6 +77,9 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
 	local_flush_tlb_all();
 	flush_cache_all();
 
+	if (!davinci_soc_info.reset)
+		davinci_soc_info.reset = davinci_watchdog_reset;
+
 	/*
 	 * We want to check CPU revision early for cpu_is_xxxx() macros.
 	 * IO space mapping must be initialized before we can do that.
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 68e5233..83879f8 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1206,6 +1206,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
 	.serial_dev		= &da8xx_serial_device,
 	.emac_pdata		= &da8xx_emac_pdata,
+	.reset_device		= &da8xx_wdt_device,
 };
 
 void __init da830_init(void)
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 8aefcff..2b6dd59 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1093,6 +1093,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.emac_pdata		= &da8xx_emac_pdata,
 	.sram_dma		= DA8XX_ARM_RAM_BASE,
 	.sram_len		= SZ_8K,
+	.reset_device		= &da8xx_wdt_device,
 };
 
 void __init da850_init(void)
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 0a96791..67a6fbc 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -326,7 +326,7 @@ static struct resource da8xx_watchdog_resources[] = {
 	},
 };
 
-struct platform_device davinci_wdt_device = {
+struct platform_device da8xx_wdt_device = {
 	.name		= "watchdog",
 	.id		= -1,
 	.num_resources	= ARRAY_SIZE(da8xx_watchdog_resources),
@@ -335,7 +335,7 @@ struct platform_device davinci_wdt_device = {
 
 int __init da8xx_register_watchdog(void)
 {
-	return platform_device_register(&davinci_wdt_device);
+	return platform_device_register(&da8xx_wdt_device);
 }
 
 static struct resource da8xx_emac_resources[] = {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index f91e9a1..0c62a68 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -861,6 +861,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.serial_dev		= &dm355_serial_device,
 	.sram_dma		= 0x00010000,
 	.sram_len		= SZ_32K,
+	.reset_device		= &davinci_wdt_device,
 };
 
 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index f2b1d93..ed76450 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1068,6 +1068,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.emac_pdata		= &dm365_emac_pdata,
 	.sram_dma		= 0x00010000,
 	.sram_len		= SZ_32K,
+	.reset_device		= &davinci_wdt_device,
 };
 
 void __init dm365_init_asp(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 85c88ec..7f36c22 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -753,6 +753,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.emac_pdata		= &dm644x_emac_pdata,
 	.sram_dma		= 0x00008000,
 	.sram_len		= SZ_16K,
+	.reset_device		= &davinci_wdt_device,
 };
 
 void __init dm644x_init_asp(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index a8189c9..8dd0afe 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -837,6 +837,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.emac_pdata		= &dm646x_emac_pdata,
 	.sram_dma		= 0x10010000,
 	.sram_len		= SZ_32K,
+	.reset_device		= &davinci_wdt_device,
 };
 
 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 8ffef5b..a58bd88 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -70,6 +70,8 @@ struct davinci_soc_info {
 	struct emac_platform_data	*emac_pdata;
 	dma_addr_t			sram_dma;
 	unsigned			sram_len;
+	struct platform_device		*reset_device;
+	void				(*reset)(struct platform_device *);
 };
 
 extern struct davinci_soc_info davinci_soc_info;
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index dbb4ebe..1b31a9a 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -87,6 +87,8 @@ extern struct emac_platform_data da8xx_emac_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
 
+extern struct platform_device da8xx_wdt_device;
+
 extern const short da830_emif25_pins[];
 extern const short da830_spi0_pins[];
 extern const short da830_spi1_pins[];
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
index 5a7d758..e65629c 100644
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -11,7 +11,7 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-extern void davinci_watchdog_reset(void);
+#include <mach/common.h>
 
 static inline void arch_idle(void)
 {
@@ -20,7 +20,8 @@ static inline void arch_idle(void)
 
 static inline void arch_reset(char mode, const char *cmd)
 {
-	davinci_watchdog_reset();
+	if (davinci_soc_info.reset)
+		davinci_soc_info.reset(davinci_soc_info.reset_device);
 }
 
 #endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index b21f763..e5c598a 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -399,13 +399,16 @@ struct sys_timer davinci_timer = {
 
 
 /* reset board using watchdog timer */
-void davinci_watchdog_reset(void)
+void davinci_watchdog_reset(struct platform_device *pdev)
 {
 	u32 tgcr, wdtcr;
-	struct platform_device *pdev = &davinci_wdt_device;
-	void __iomem *base = IO_ADDRESS(pdev->resource[0].start);
+	void __iomem *base;
 	struct clk *wd_clk;
 
+	base = ioremap(pdev->resource[0].start, SZ_4K);
+	if (WARN_ON(!base))
+		return;
+
 	wd_clk = clk_get(&pdev->dev, NULL);
 	if (WARN_ON(IS_ERR(wd_clk)))
 		return;
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:38:41 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:38:41 -0400
Subject: [PATCH v2 1/8] Davinci: gpio - use ioremap()
In-Reply-To: <1272753528-22981-1-git-send-email-cyril@ti.com>
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
Message-ID: <1272753528-22981-2-git-send-email-cyril@ti.com>

This patch modifies the gpio_base definition in davinci_soc_info to be a
physical address, which is then ioremap()ed by the gpio initialization
function.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v2: fixed raw_write to soc_info->gpio_base 

 arch/arm/mach-davinci/da830.c               |    2 +-
 arch/arm/mach-davinci/da850.c               |    2 +-
 arch/arm/mach-davinci/dm355.c               |    2 +-
 arch/arm/mach-davinci/dm365.c               |    2 +-
 arch/arm/mach-davinci/dm644x.c              |    2 +-
 arch/arm/mach-davinci/dm646x.c              |    2 +-
 arch/arm/mach-davinci/gpio.c                |   18 +++++++++++-------
 arch/arm/mach-davinci/include/mach/common.h |    2 +-
 8 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 83879f8..4f5727f 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1201,7 +1201,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.intc_irq_num		= DA830_N_CP_INTC_IRQ,
 	.timer_info		= &da830_timer_info,
 	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= IO_ADDRESS(DA8XX_GPIO_BASE),
+	.gpio_base		= DA8XX_GPIO_BASE,
 	.gpio_num		= 128,
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
 	.serial_dev		= &da8xx_serial_device,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 2b6dd59..cb7f663 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1086,7 +1086,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.intc_irq_num		= DA850_N_CP_INTC_IRQ,
 	.timer_info		= &da850_timer_info,
 	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= IO_ADDRESS(DA8XX_GPIO_BASE),
+	.gpio_base		= DA8XX_GPIO_BASE,
 	.gpio_num		= 144,
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
 	.serial_dev		= &da8xx_serial_device,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 0c62a68..277041d 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -855,7 +855,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm355_timer_info,
 	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
+	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 104,
 	.gpio_irq		= IRQ_DM355_GPIOBNK0,
 	.serial_dev		= &dm355_serial_device,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index ed76450..ecdbc67 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1060,7 +1060,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm365_timer_info,
 	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
+	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 104,
 	.gpio_irq		= IRQ_DM365_GPIO0,
 	.gpio_unbanked		= 8,	/* really 16 ... skip muxed GPIOs */
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 7f36c22..beb315c 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -746,7 +746,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm644x_timer_info,
 	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
+	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 71,
 	.gpio_irq		= IRQ_GPIOBNK0,
 	.serial_dev		= &dm644x_serial_device,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 8dd0afe..95fc981 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -830,7 +830,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm646x_timer_info,
 	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
+	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 43, /* Only 33 usable */
 	.gpio_irq		= IRQ_DM646X_GPIOBNK0,
 	.serial_dev		= &dm646x_serial_device,
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 2efb446..6fc4e1a 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -37,22 +37,22 @@ struct davinci_gpio_regs {
 	container_of(chip, struct davinci_gpio_controller, chip)
 
 static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
+static void __iomem *gpio_base;
 
 static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
 {
 	void __iomem *ptr;
-	void __iomem *base = davinci_soc_info.gpio_base;
 
 	if (gpio < 32 * 1)
-		ptr = base + 0x10;
+		ptr = gpio_base + 0x10;
 	else if (gpio < 32 * 2)
-		ptr = base + 0x38;
+		ptr = gpio_base + 0x38;
 	else if (gpio < 32 * 3)
-		ptr = base + 0x60;
+		ptr = gpio_base + 0x60;
 	else if (gpio < 32 * 4)
-		ptr = base + 0x88;
+		ptr = gpio_base + 0x88;
 	else if (gpio < 32 * 5)
-		ptr = base + 0xb0;
+		ptr = gpio_base + 0xb0;
 	else
 		ptr = NULL;
 	return ptr;
@@ -157,6 +157,10 @@ static int __init davinci_gpio_setup(void)
 	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
 		ngpio = DAVINCI_N_GPIO;
 
+	gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
+	if (WARN_ON(!gpio_base))
+		return -EINVAL;
+
 	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
 		chips[i].chip.label = "DaVinci";
 
@@ -445,7 +449,7 @@ done:
 	/* BINTEN -- per-bank interrupt enable. genirq would also let these
 	 * bits be set/cleared dynamically.
 	 */
-	__raw_writel(binten, soc_info->gpio_base + 0x08);
+	__raw_writel(binten, gpio_base + 0x08);
 
 	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
 
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index a58bd88..2dd2226 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -60,7 +60,7 @@ struct davinci_soc_info {
 	unsigned long			intc_irq_num;
 	struct davinci_timer_info	*timer_info;
 	int				gpio_type;
-	void __iomem			*gpio_base;
+	u32				gpio_base;
 	unsigned			gpio_num;
 	unsigned			gpio_irq;
 	unsigned			gpio_unbanked;
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:38:40 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:38:40 -0400
Subject: [PATCH v2 0/8] pre-tnetv107x ioremap series
Message-ID: <1272753528-22981-1-git-send-email-cyril@ti.com>

With this patch, various davinci modules (gpio, timer, psc, etc.) now use
ioremap() instead of having virtual addresses passed in via davinci_soc_info.
Based on this cleanup, davinci_ioremap() has been modified to search through
the iotable instead of mapping based on IO_PHYS and IO_VIRT.

This series has been tested on dm355 and tnetv107x platforms.  The dmx boot
problem reported by Kevin has been fixed (see gpio - use ioremap()).

Cyril Chemparathy (8):
  Davinci: gpio - use ioremap()
  Davinci: da8xx: rtc - use ioremap
  Davinci: jtag_id - use ioremap()
  Davinci: timer - use ioremap()
  Davinci: psc - use ioremap()
  Davinci: aintc/cpintc - use ioremap()
  Davinci: pinmux - use ioremap()
  Davinci: iotable based ioremap() interception

 arch/arm/mach-davinci/board-da830-evm.c      |   10 +-----
 arch/arm/mach-davinci/board-da850-evm.c      |   10 +-----
 arch/arm/mach-davinci/board-dm355-evm.c      |    7 +---
 arch/arm/mach-davinci/board-dm355-leopard.c  |    7 +---
 arch/arm/mach-davinci/board-dm365-evm.c      |    7 +---
 arch/arm/mach-davinci/board-dm644x-evm.c     |    7 +---
 arch/arm/mach-davinci/board-dm646x-evm.c     |    9 +----
 arch/arm/mach-davinci/board-neuros-osd2.c    |    7 +---
 arch/arm/mach-davinci/board-sffsdr.c         |    7 +---
 arch/arm/mach-davinci/clock.c                |   14 ++++++--
 arch/arm/mach-davinci/common.c               |   51 ++++++++++++++------------
 arch/arm/mach-davinci/cp_intc.c              |   18 ++++++----
 arch/arm/mach-davinci/da830.c                |   26 +++++--------
 arch/arm/mach-davinci/da850.c                |   27 ++++++--------
 arch/arm/mach-davinci/devices-da8xx.c        |   11 +++++-
 arch/arm/mach-davinci/devices.c              |    4 +-
 arch/arm/mach-davinci/dm355.c                |   12 +++----
 arch/arm/mach-davinci/dm365.c                |   12 +++----
 arch/arm/mach-davinci/dm644x.c               |   12 +++----
 arch/arm/mach-davinci/dm646x.c               |   12 +++----
 arch/arm/mach-davinci/gpio.c                 |   18 ++++++----
 arch/arm/mach-davinci/include/mach/common.h  |   21 +++++++----
 arch/arm/mach-davinci/include/mach/cp_intc.h |    3 +-
 arch/arm/mach-davinci/io.c                   |   20 ++++++++---
 arch/arm/mach-davinci/irq.c                  |    7 +++-
 arch/arm/mach-davinci/mux.c                  |   15 +++++---
 arch/arm/mach-davinci/psc.c                  |    7 +++-
 arch/arm/mach-davinci/time.c                 |   22 +++++++----
 28 files changed, 188 insertions(+), 195 deletions(-)


From cyril at ti.com  Sat May  1 17:38:43 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:38:43 -0400
Subject: [PATCH v2 3/8] Davinci: jtag_id - use ioremap()
In-Reply-To: <1272753528-22981-1-git-send-email-cyril@ti.com>
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
Message-ID: <1272753528-22981-4-git-send-email-cyril@ti.com>

This patch replaces the jtag id base info in davinci_soc_info with a physical
address which is then ioremap()ed within common code.

This patch (in combination with a similar change for PSC) will allow us to
eliminate the SYSCFG nastiness in DA8xx code.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v2: fixed return value on ioremap failure

 arch/arm/mach-davinci/common.c              |   49 +++++++++++++++-----------
 arch/arm/mach-davinci/da830.c               |    3 +-
 arch/arm/mach-davinci/da850.c               |    3 +-
 arch/arm/mach-davinci/dm355.c               |    2 +-
 arch/arm/mach-davinci/dm365.c               |    2 +-
 arch/arm/mach-davinci/dm644x.c              |    2 +-
 arch/arm/mach-davinci/dm646x.c              |    2 +-
 arch/arm/mach-davinci/include/mach/common.h |    2 +-
 8 files changed, 35 insertions(+), 30 deletions(-)

diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index f8221c5..ddbd57b 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -37,26 +37,42 @@ void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context)
 		pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
 }
 
-static struct davinci_id * __init davinci_get_id(u32 jtag_id)
+static int __init davinci_init_id(struct davinci_soc_info *soc_info)
 {
-	int i;
-	struct davinci_id *dip;
-	u8 variant = (jtag_id & 0xf0000000) >> 28;
-	u16 part_no = (jtag_id & 0x0ffff000) >> 12;
+	int			i;
+	struct davinci_id	*dip;
+	u8			variant;
+	u16			part_no;
+	void __iomem		*base;
+
+	base = ioremap(davinci_soc_info.jtag_id_reg, SZ_4K);
+	if (!base) {
+		pr_err("Unable to map JTAG ID register\n");
+		return -ENOMEM;
+	}
+
+	soc_info->jtag_id = __raw_readl(base);
+	iounmap(base);
+
+	variant = (soc_info->jtag_id & 0xf0000000) >> 28;
+	part_no = (soc_info->jtag_id & 0x0ffff000) >> 12;
 
 	for (i = 0, dip = davinci_soc_info.ids; i < davinci_soc_info.ids_num;
 			i++, dip++)
 		/* Don't care about the manufacturer right now */
-		if ((dip->part_no == part_no) && (dip->variant == variant))
-			return dip;
-
-	return NULL;
+		if ((dip->part_no == part_no) && (dip->variant == variant)) {
+			soc_info->cpu_id = dip->cpu_id;
+			pr_info("DaVinci %s variant 0x%x\n", dip->name, dip->variant);
+			return 0;
+		}
+
+	pr_err("Unknown DaVinci JTAG ID 0x%x\n", soc_info->jtag_id);
+	return -EINVAL;
 }
 
 void __init davinci_common_init(struct davinci_soc_info *soc_info)
 {
 	int ret;
-	struct davinci_id *dip;
 
 	if (!soc_info) {
 		ret = -EINVAL;
@@ -84,18 +100,9 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
 	 * We want to check CPU revision early for cpu_is_xxxx() macros.
 	 * IO space mapping must be initialized before we can do that.
 	 */
-	davinci_soc_info.jtag_id = __raw_readl(davinci_soc_info.jtag_id_base);
-
-	dip = davinci_get_id(davinci_soc_info.jtag_id);
-	if (!dip) {
-		ret = -EINVAL;
-		pr_err("Unknown DaVinci JTAG ID 0x%x\n",
-						davinci_soc_info.jtag_id);
+	ret = davinci_init_id(&davinci_soc_info);
+	if (ret < 0)
 		goto err;
-	}
-
-	davinci_soc_info.cpu_id = dip->cpu_id;
-	pr_info("DaVinci %s variant 0x%x\n", dip->name, dip->variant);
 
 	if (davinci_soc_info.cpu_clks) {
 		ret = davinci_clk_init(davinci_soc_info.cpu_clks);
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 4f5727f..115f791 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1188,6 +1188,7 @@ static struct davinci_timer_info da830_timer_info = {
 static struct davinci_soc_info davinci_soc_info_da830 = {
 	.io_desc		= da830_io_desc,
 	.io_desc_num		= ARRAY_SIZE(da830_io_desc),
+	.jtag_id_reg		= DA8XX_JTAG_ID_REG,
 	.ids			= da830_ids,
 	.ids_num		= ARRAY_SIZE(da830_ids),
 	.cpu_clks		= da830_clks,
@@ -1215,8 +1216,6 @@ void __init da830_init(void)
 	if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
 		return;
 
-	davinci_soc_info_da830.jtag_id_base =
-					DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
 	davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
 
 	davinci_common_init(&davinci_soc_info_da830);
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index cb7f663..7c0ce45 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1073,6 +1073,7 @@ no_ddrpll_mem:
 static struct davinci_soc_info davinci_soc_info_da850 = {
 	.io_desc		= da850_io_desc,
 	.io_desc_num		= ARRAY_SIZE(da850_io_desc),
+	.jtag_id_reg		= DA8XX_JTAG_ID_REG,
 	.ids			= da850_ids,
 	.ids_num		= ARRAY_SIZE(da850_ids),
 	.cpu_clks		= da850_clks,
@@ -1108,8 +1109,6 @@ void __init da850_init(void)
 	if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
 		return;
 
-	davinci_soc_info_da850.jtag_id_base =
-					DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
 	davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
 
 	davinci_common_init(&davinci_soc_info_da850);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 277041d..228b6d1 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -840,7 +840,7 @@ static struct platform_device dm355_serial_device = {
 static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.io_desc		= dm355_io_desc,
 	.io_desc_num		= ARRAY_SIZE(dm355_io_desc),
-	.jtag_id_base		= IO_ADDRESS(0x01c40028),
+	.jtag_id_reg		= 0x01c40028,
 	.ids			= dm355_ids,
 	.ids_num		= ARRAY_SIZE(dm355_ids),
 	.cpu_clks		= dm355_clks,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index ecdbc67..b396d58 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1045,7 +1045,7 @@ static struct platform_device dm365_serial_device = {
 static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.io_desc		= dm365_io_desc,
 	.io_desc_num		= ARRAY_SIZE(dm365_io_desc),
-	.jtag_id_base		= IO_ADDRESS(0x01c40028),
+	.jtag_id_reg		= 0x01c40028,
 	.ids			= dm365_ids,
 	.ids_num		= ARRAY_SIZE(dm365_ids),
 	.cpu_clks		= dm365_clks,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index beb315c..9859567 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -731,7 +731,7 @@ static struct platform_device dm644x_serial_device = {
 static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.io_desc		= dm644x_io_desc,
 	.io_desc_num		= ARRAY_SIZE(dm644x_io_desc),
-	.jtag_id_base		= IO_ADDRESS(0x01c40028),
+	.jtag_id_reg		= 0x01c40028,
 	.ids			= dm644x_ids,
 	.ids_num		= ARRAY_SIZE(dm644x_ids),
 	.cpu_clks		= dm644x_clks,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 95fc981..f9a8cc4 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -815,7 +815,7 @@ static struct platform_device dm646x_serial_device = {
 static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.io_desc		= dm646x_io_desc,
 	.io_desc_num		= ARRAY_SIZE(dm646x_io_desc),
-	.jtag_id_base		= IO_ADDRESS(0x01c40028),
+	.jtag_id_reg		= 0x01c40028,
 	.ids			= dm646x_ids,
 	.ids_num		= ARRAY_SIZE(dm646x_ids),
 	.cpu_clks		= dm646x_clks,
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 2dd2226..1078458 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -45,7 +45,7 @@ struct davinci_soc_info {
 	unsigned long			io_desc_num;
 	u32				cpu_id;
 	u32				jtag_id;
-	void __iomem			*jtag_id_base;
+	u32				jtag_id_reg;
 	struct davinci_id		*ids;
 	unsigned long			ids_num;
 	struct clk_lookup		*cpu_clks;
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:38:44 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:38:44 -0400
Subject: [PATCH v2 4/8] Davinci: timer - use ioremap()
In-Reply-To: <1272753528-22981-1-git-send-email-cyril@ti.com>
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
Message-ID: <1272753528-22981-5-git-send-email-cyril@ti.com>

This patch eliminates IO_ADDRESS() usage for Davinci timer definitions.  The
timer code has correspondingly been modified to ioremap() MMRs instead.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v2: unchanged from v1

 arch/arm/mach-davinci/da830.c               |    4 ++--
 arch/arm/mach-davinci/da850.c               |    8 ++++----
 arch/arm/mach-davinci/devices.c             |    4 ++--
 arch/arm/mach-davinci/include/mach/common.h |    2 +-
 arch/arm/mach-davinci/time.c                |   22 ++++++++++++++--------
 5 files changed, 23 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 115f791..5933df4 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1159,14 +1159,14 @@ static struct davinci_id da830_ids[] = {
 
 static struct davinci_timer_instance da830_timer_instance[2] = {
 	{
-		.base		= IO_ADDRESS(DA8XX_TIMER64P0_BASE),
+		.base		= DA8XX_TIMER64P0_BASE,
 		.bottom_irq	= IRQ_DA8XX_TINT12_0,
 		.top_irq	= IRQ_DA8XX_TINT34_0,
 		.cmp_off	= DA830_CMP12_0,
 		.cmp_irq	= IRQ_DA830_T12CMPINT0_0,
 	},
 	{
-		.base		= IO_ADDRESS(DA8XX_TIMER64P1_BASE),
+		.base		= DA8XX_TIMER64P1_BASE,
 		.bottom_irq	= IRQ_DA8XX_TINT12_1,
 		.top_irq	= IRQ_DA8XX_TINT34_1,
 		.cmp_off	= DA830_CMP12_0,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 7c0ce45..e3d2cb0 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -800,22 +800,22 @@ static struct davinci_id da850_ids[] = {
 
 static struct davinci_timer_instance da850_timer_instance[4] = {
 	{
-		.base		= IO_ADDRESS(DA8XX_TIMER64P0_BASE),
+		.base		= DA8XX_TIMER64P0_BASE,
 		.bottom_irq	= IRQ_DA8XX_TINT12_0,
 		.top_irq	= IRQ_DA8XX_TINT34_0,
 	},
 	{
-		.base		= IO_ADDRESS(DA8XX_TIMER64P1_BASE),
+		.base		= DA8XX_TIMER64P1_BASE,
 		.bottom_irq	= IRQ_DA8XX_TINT12_1,
 		.top_irq	= IRQ_DA8XX_TINT34_1,
 	},
 	{
-		.base		= IO_ADDRESS(DA850_TIMER64P2_BASE),
+		.base		= DA850_TIMER64P2_BASE,
 		.bottom_irq	= IRQ_DA850_TINT12_2,
 		.top_irq	= IRQ_DA850_TINT34_2,
 	},
 	{
-		.base		= IO_ADDRESS(DA850_TIMER64P3_BASE),
+		.base		= DA850_TIMER64P3_BASE,
 		.bottom_irq	= IRQ_DA850_TINT12_3,
 		.top_irq	= IRQ_DA850_TINT34_3,
 	},
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index d9c82ee..8b7201e 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -297,12 +297,12 @@ static void davinci_init_wdt(void)
 
 struct davinci_timer_instance davinci_timer_instance[2] = {
 	{
-		.base		= IO_ADDRESS(DAVINCI_TIMER0_BASE),
+		.base		= DAVINCI_TIMER0_BASE,
 		.bottom_irq	= IRQ_TINT0_TINT12,
 		.top_irq	= IRQ_TINT0_TINT34,
 	},
 	{
-		.base		= IO_ADDRESS(DAVINCI_TIMER1_BASE),
+		.base		= DAVINCI_TIMER1_BASE,
 		.bottom_irq	= IRQ_TINT1_TINT12,
 		.top_irq	= IRQ_TINT1_TINT34,
 	},
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 1078458..2e15464 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -24,7 +24,7 @@ extern void __iomem *davinci_intc_base;
 extern int davinci_intc_type;
 
 struct davinci_timer_instance {
-	void __iomem	*base;
+	u32		base;
 	u32		bottom_irq;
 	u32		top_irq;
 	unsigned long	cmp_off;
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index e5c598a..0f21c36 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -197,32 +197,36 @@ static void __init timer_init(void)
 {
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
+	void __iomem *base[2];
 	int i;
 
 	/* Global init of each 64-bit timer as a whole */
 	for(i=0; i<2; i++) {
 		u32 tgcr;
-		void __iomem *base = dtip[i].base;
+
+		base[i] = ioremap(dtip[i].base, SZ_4K);
+		if (WARN_ON(!base[i]))
+			continue;
 
 		/* Disabled, Internal clock source */
-		__raw_writel(0, base + TCR);
+		__raw_writel(0, base[i] + TCR);
 
 		/* reset both timers, no pre-scaler for timer34 */
 		tgcr = 0;
-		__raw_writel(tgcr, base + TGCR);
+		__raw_writel(tgcr, base[i] + TGCR);
 
 		/* Set both timers to unchained 32-bit */
 		tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
-		__raw_writel(tgcr, base + TGCR);
+		__raw_writel(tgcr, base[i] + TGCR);
 
 		/* Unreset timers */
 		tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
 			(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
-		__raw_writel(tgcr, base + TGCR);
+		__raw_writel(tgcr, base[i] + TGCR);
 
 		/* Init both counters to zero */
-		__raw_writel(0, base + TIM12);
-		__raw_writel(0, base + TIM34);
+		__raw_writel(0, base[i] + TIM12);
+		__raw_writel(0, base[i] + TIM34);
 	}
 
 	/* Init of each timer as a 32-bit timer */
@@ -231,7 +235,9 @@ static void __init timer_init(void)
 		int timer = ID_TO_TIMER(t->id);
 		u32 irq;
 
-		t->base = dtip[timer].base;
+		t->base = base[timer];
+		if (!t->base)
+			continue;
 
 		if (IS_TIMER_BOT(t->id)) {
 			t->enamode_shift = 6;
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:38:45 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:38:45 -0400
Subject: [PATCH v2 5/8] Davinci: psc - use ioremap()
In-Reply-To: <1272753528-22981-1-git-send-email-cyril@ti.com>
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
Message-ID: <1272753528-22981-6-git-send-email-cyril@ti.com>

This patch modifies the psc and clock control code to use ioremap()ed
registers.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v2: bug --> warn

 arch/arm/mach-davinci/clock.c               |   14 +++++++++++---
 arch/arm/mach-davinci/da830.c               |    5 +----
 arch/arm/mach-davinci/da850.c               |    5 +----
 arch/arm/mach-davinci/dm355.c               |    4 +---
 arch/arm/mach-davinci/dm365.c               |    4 +---
 arch/arm/mach-davinci/dm644x.c              |    4 +---
 arch/arm/mach-davinci/dm646x.c              |    4 +---
 arch/arm/mach-davinci/include/mach/common.h |    2 +-
 arch/arm/mach-davinci/psc.c                 |    7 +++++--
 9 files changed, 23 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 868cb76..054c303 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -302,7 +302,6 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
 	struct pll_data *pll = clk->pll_data;
 	unsigned long rate = clk->rate;
 
-	pll->base = IO_ADDRESS(pll->phys_base);
 	ctrl = __raw_readl(pll->base + PLLCTL);
 	rate = pll->input_rate = clk->parent->rate;
 
@@ -458,8 +457,17 @@ int __init davinci_clk_init(struct clk_lookup *clocks)
 				clk->recalc = clk_leafclk_recalc;
 		}
 
-		if (clk->pll_data && !clk->pll_data->div_ratio_mask)
-			clk->pll_data->div_ratio_mask = PLLDIV_RATIO_MASK;
+		if (clk->pll_data) {
+			struct pll_data *pll = clk->pll_data;
+
+			if (!pll->div_ratio_mask)
+				pll->div_ratio_mask = PLLDIV_RATIO_MASK;
+
+			if (pll->phys_base && !pll->base) {
+				pll->base = ioremap(pll->phys_base, SZ_4K);
+				WARN_ON(!pll->base);
+			}
+		}
 
 		if (clk->recalc)
 			clk->rate = clk->recalc(clk);
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 5933df4..a0cf8e8 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1127,10 +1127,7 @@ static struct map_desc da830_io_desc[] = {
 	},
 };
 
-static void __iomem *da830_psc_bases[] = {
-	IO_ADDRESS(DA8XX_PSC0_BASE),
-	IO_ADDRESS(DA8XX_PSC1_BASE),
-};
+static u32 da830_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
 
 /* Contents of JTAG ID register used to identify exact cpu type */
 static struct davinci_id da830_ids[] = {
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index e3d2cb0..11b8261 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -782,10 +782,7 @@ static struct map_desc da850_io_desc[] = {
 	},
 };
 
-static void __iomem *da850_psc_bases[] = {
-	IO_ADDRESS(DA8XX_PSC0_BASE),
-	IO_ADDRESS(DA8XX_PSC1_BASE),
-};
+static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
 
 /* Contents of JTAG ID register used to identify exact cpu type */
 static struct davinci_id da850_ids[] = {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 228b6d1..70a1827 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -783,9 +783,7 @@ static struct davinci_id dm355_ids[] = {
 	},
 };
 
-static void __iomem *dm355_psc_bases[] = {
-	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
-};
+static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 
 /*
  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index b396d58..451a4ef 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1002,9 +1002,7 @@ static struct davinci_id dm365_ids[] = {
 	},
 };
 
-static void __iomem *dm365_psc_bases[] = {
-	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
-};
+static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 
 static struct davinci_timer_info dm365_timer_info = {
 	.timers		= davinci_timer_instance,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 9859567..ee654de 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -674,9 +674,7 @@ static struct davinci_id dm644x_ids[] = {
 	},
 };
 
-static void __iomem *dm644x_psc_bases[] = {
-	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
-};
+static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 
 /*
  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index f9a8cc4..4c98ef0 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -758,9 +758,7 @@ static struct davinci_id dm646x_ids[] = {
 	},
 };
 
-static void __iomem *dm646x_psc_bases[] = {
-	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
-};
+static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 
 /*
  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 2e15464..6efa93f 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -49,7 +49,7 @@ struct davinci_soc_info {
 	struct davinci_id		*ids;
 	unsigned long			ids_num;
 	struct clk_lookup		*cpu_clks;
-	void __iomem			**psc_bases;
+	u32	 			*psc_bases;
 	unsigned long			psc_bases_num;
 	void __iomem			*pinmux_base;
 	const struct mux_config		*pinmux_pins;
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index d7cb438..1b15dbd 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -38,8 +38,9 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
 		return 0;
 	}
 
-	psc_base = soc_info->psc_bases[ctlr];
+	psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
 	mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
+	iounmap(psc_base);
 
 	/* if clocked, state can be "Enable" or "SyncReset" */
 	return mdstat & BIT(12);
@@ -59,7 +60,7 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
 		return;
 	}
 
-	psc_base = soc_info->psc_bases[ctlr];
+	psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
 
 	mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
 	mdctl &= ~MDSTAT_STATE_MASK;
@@ -99,4 +100,6 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
 	do {
 		mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
 	} while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
+
+	iounmap(psc_base);
 }
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:38:42 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:38:42 -0400
Subject: [PATCH v2 2/8] Davinci: da8xx: rtc - use ioremap
In-Reply-To: <1272753528-22981-1-git-send-email-cyril@ti.com>
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
Message-ID: <1272753528-22981-3-git-send-email-cyril@ti.com>

This patch modifies the RTC unlock code to use ioremap() maps instead of
IO_ADDRESS() translation.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v2: unchanged from v1

 arch/arm/mach-davinci/devices-da8xx.c |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 67a6fbc..e8b263b 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -584,10 +584,17 @@ static struct platform_device da8xx_rtc_device = {
 int da8xx_register_rtc(void)
 {
 	int ret;
+	void __iomem *base;
+
+	base = ioremap(DA8XX_RTC_BASE, SZ_4K);
+	if (WARN_ON(!base))
+		return -EINVAL;
 
 	/* Unlock the rtc's registers */
-	__raw_writel(0x83e70b13, IO_ADDRESS(DA8XX_RTC_BASE + 0x6c));
-	__raw_writel(0x95a4f1e0, IO_ADDRESS(DA8XX_RTC_BASE + 0x70));
+	__raw_writel(0x83e70b13, base + 0x6c);
+	__raw_writel(0x95a4f1e0, base + 0x70);
+
+	iounmap(base);
 
 	ret = platform_device_register(&da8xx_rtc_device);
 	if (!ret)
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:38:46 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:38:46 -0400
Subject: [PATCH v2 6/8] Davinci: aintc/cpintc - use ioremap()
In-Reply-To: <1272753528-22981-1-git-send-email-cyril@ti.com>
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
Message-ID: <1272753528-22981-7-git-send-email-cyril@ti.com>

This patch implements the following:

 - interrupt initialization uses ioremap() instead of passing a virtual address
   via davinci_soc_info.

 - machine definitions directly point to cp_intc_init() or davinci_irq_init()

 - davinci_intc_type and davinci_intc_base now get initialized in controller
   specific init functions instead of davinci_common_init()

 - minor fix in davinci_irq_init() to use intc_irq_num instead of
   DAVINCI_N_AINTC_IRQ

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v2: unchanged from v1

 arch/arm/mach-davinci/board-da830-evm.c      |   10 +---------
 arch/arm/mach-davinci/board-da850-evm.c      |   10 +---------
 arch/arm/mach-davinci/board-dm355-evm.c      |    7 +------
 arch/arm/mach-davinci/board-dm355-leopard.c  |    7 +------
 arch/arm/mach-davinci/board-dm365-evm.c      |    7 +------
 arch/arm/mach-davinci/board-dm644x-evm.c     |    7 +------
 arch/arm/mach-davinci/board-dm646x-evm.c     |    9 ++-------
 arch/arm/mach-davinci/board-neuros-osd2.c    |    7 +------
 arch/arm/mach-davinci/board-sffsdr.c         |    7 +------
 arch/arm/mach-davinci/common.c               |    2 --
 arch/arm/mach-davinci/cp_intc.c              |   18 +++++++++++-------
 arch/arm/mach-davinci/da830.c                |    2 +-
 arch/arm/mach-davinci/da850.c                |    2 +-
 arch/arm/mach-davinci/dm355.c                |    2 +-
 arch/arm/mach-davinci/dm365.c                |    2 +-
 arch/arm/mach-davinci/dm644x.c               |    2 +-
 arch/arm/mach-davinci/dm646x.c               |    2 +-
 arch/arm/mach-davinci/include/mach/common.h  |    3 ++-
 arch/arm/mach-davinci/include/mach/cp_intc.h |    3 +--
 arch/arm/mach-davinci/irq.c                  |    7 ++++++-
 20 files changed, 36 insertions(+), 80 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 8f079d2..212d970 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -561,14 +561,6 @@ static int __init da830_evm_console_init(void)
 console_initcall(da830_evm_console_init);
 #endif
 
-static __init void da830_evm_irq_init(void)
-{
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
-
-	cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ,
-			soc_info->intc_irq_prios, NULL);
-}
-
 static void __init da830_evm_map_io(void)
 {
 	da830_init();
@@ -579,7 +571,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM")
 	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params	= (DA8XX_DDR_BASE + 0x100),
 	.map_io		= da830_evm_map_io,
-	.init_irq	= da830_evm_irq_init,
+	.init_irq	= cp_intc_init,
 	.timer		= &davinci_timer,
 	.init_machine	= da830_evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 6c137e0..abd0493 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -736,14 +736,6 @@ static int __init da850_evm_console_init(void)
 console_initcall(da850_evm_console_init);
 #endif
 
-static __init void da850_evm_irq_init(void)
-{
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
-
-	cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ,
-			soc_info->intc_irq_prios, NULL);
-}
-
 static void __init da850_evm_map_io(void)
 {
 	da850_init();
@@ -754,7 +746,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM")
 	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params	= (DA8XX_DDR_BASE + 0x100),
 	.map_io		= da850_evm_map_io,
-	.init_irq	= da850_evm_irq_init,
+	.init_irq	= cp_intc_init,
 	.timer		= &davinci_timer,
 	.init_machine	= da850_evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index a0ad7d9..a319101 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -350,17 +350,12 @@ static __init void dm355_evm_init(void)
 	dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data);
 }
 
-static __init void dm355_evm_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (0x80000100),
 	.map_io	      = dm355_evm_map_io,
-	.init_irq     = dm355_evm_irq_init,
+	.init_irq     = davinci_irq_init,
 	.timer	      = &davinci_timer,
 	.init_machine = dm355_evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index c3d5a70..f1d8132 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -269,17 +269,12 @@ static __init void dm355_leopard_init(void)
 			ARRAY_SIZE(dm355_leopard_spi_info));
 }
 
-static __init void dm355_leopard_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (0x80000100),
 	.map_io	      = dm355_leopard_map_io,
-	.init_irq     = dm355_leopard_irq_init,
+	.init_irq     = davinci_irq_init,
 	.timer	      = &davinci_timer,
 	.init_machine = dm355_leopard_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index b98b35c..98814e6 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -608,17 +608,12 @@ static __init void dm365_evm_init(void)
 			ARRAY_SIZE(dm365_evm_spi_info));
 }
 
-static __init void dm365_evm_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
 	.phys_io	= IO_PHYS,
 	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params	= (0x80000100),
 	.map_io		= dm365_evm_map_io,
-	.init_irq	= dm365_evm_irq_init,
+	.init_irq	= davinci_irq_init,
 	.timer		= &davinci_timer,
 	.init_machine	= dm365_evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 73c0b04..34c8b41 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -704,18 +704,13 @@ static __init void davinci_evm_init(void)
 
 }
 
-static __init void davinci_evm_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
 	/* Maintainer: MontaVista Software <source at mvista.com> */
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (DAVINCI_DDR_BASE + 0x100),
 	.map_io	      = davinci_evm_map_io,
-	.init_irq     = davinci_evm_irq_init,
+	.init_irq     = davinci_irq_init,
 	.timer	      = &davinci_timer,
 	.init_machine = davinci_evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index e2ac06f..6d88893 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -739,11 +739,6 @@ static __init void evm_init(void)
 	soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
 }
 
-static __init void davinci_dm646x_evm_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 #define DM646X_EVM_REF_FREQ		27000000
 #define DM6467T_EVM_REF_FREQ		33000000
 
@@ -760,7 +755,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (0x80000100),
 	.map_io       = davinci_map_io,
-	.init_irq     = davinci_dm646x_evm_irq_init,
+	.init_irq     = davinci_irq_init,
 	.timer        = &davinci_timer,
 	.init_machine = evm_init,
 MACHINE_END
@@ -770,7 +765,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (0x80000100),
 	.map_io       = davinci_map_io,
-	.init_irq     = davinci_dm646x_evm_irq_init,
+	.init_irq     = davinci_irq_init,
 	.timer        = &davinci_timer,
 	.init_machine = evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 875770c..4c30e92 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -273,18 +273,13 @@ static __init void davinci_ntosd2_init(void)
 	davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
 }
 
-static __init void davinci_ntosd2_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
 	/* Maintainer: Neuros Technologies <neuros at groups.google.com> */
 	.phys_io	= IO_PHYS,
 	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params	= (DAVINCI_DDR_BASE + 0x100),
 	.map_io		 = davinci_ntosd2_map_io,
-	.init_irq	= davinci_ntosd2_irq_init,
+	.init_irq	= davinci_irq_init,
 	.timer		= &davinci_timer,
 	.init_machine = davinci_ntosd2_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 1ed0662..23e664a 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -152,18 +152,13 @@ static __init void davinci_sffsdr_init(void)
 	davinci_cfg_reg(DM644X_VLYNQWD);
 }
 
-static __init void davinci_sffsdr_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
 	/* Maintainer: Hugo Villeneuve hugo.villeneuve at lyrtech.com */
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (DAVINCI_DDR_BASE + 0x100),
 	.map_io	      = davinci_sffsdr_map_io,
-	.init_irq     = davinci_sffsdr_irq_init,
+	.init_irq     = davinci_irq_init,
 	.timer	      = &davinci_timer,
 	.init_machine = davinci_sffsdr_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index ddbd57b..252158f 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -111,8 +111,6 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
 			goto err;
 	}
 
-	davinci_intc_base = davinci_soc_info.intc_base;
-	davinci_intc_type = davinci_soc_info.intc_type;
 	return;
 
 err:
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 2a8d26e..28a3cdb 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -13,18 +13,17 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 
+#include <mach/common.h>
 #include <mach/cp_intc.h>
 
-static void __iomem *cp_intc_base;
-
 static inline unsigned int cp_intc_read(unsigned offset)
 {
-	return __raw_readl(cp_intc_base + offset);
+	return __raw_readl(davinci_intc_base + offset);
 }
 
 static inline void cp_intc_write(unsigned long value, unsigned offset)
 {
-	__raw_writel(value, cp_intc_base + offset);
+	__raw_writel(value, davinci_intc_base + offset);
 }
 
 static void cp_intc_ack_irq(unsigned int irq)
@@ -100,13 +99,18 @@ static struct irq_chip cp_intc_irq_chip = {
 	.set_wake	= cp_intc_set_wake,
 };
 
-void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
-			 u8 *irq_prio, u32 *host_map)
+void __init cp_intc_init(void)
 {
+	unsigned long num_irq	= davinci_soc_info.intc_irq_num;
+	u8 *irq_prio		= davinci_soc_info.intc_irq_prios;
+	u32 *host_map		= davinci_soc_info.intc_host_map;
 	unsigned num_reg	= BITS_TO_LONGS(num_irq);
 	int i;
 
-	cp_intc_base = base;
+	davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
+	davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
+	if (WARN_ON(!davinci_intc_base))
+		return;
 
 	cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
 
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index a0cf8e8..f8b7c2a 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1193,7 +1193,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.psc_bases_num		= ARRAY_SIZE(da830_psc_bases),
 	.pinmux_pins		= da830_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(da830_pins),
-	.intc_base		= (void __iomem *)DA8XX_CP_INTC_VIRT,
+	.intc_base		= DA8XX_CP_INTC_BASE,
 	.intc_type		= DAVINCI_INTC_TYPE_CP_INTC,
 	.intc_irq_prios		= da830_default_priorities,
 	.intc_irq_num		= DA830_N_CP_INTC_IRQ,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 11b8261..b2ef7ad 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1078,7 +1078,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.psc_bases_num		= ARRAY_SIZE(da850_psc_bases),
 	.pinmux_pins		= da850_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(da850_pins),
-	.intc_base		= (void __iomem *)DA8XX_CP_INTC_VIRT,
+	.intc_base		= DA8XX_CP_INTC_BASE,
 	.intc_type		= DAVINCI_INTC_TYPE_CP_INTC,
 	.intc_irq_prios		= da850_default_priorities,
 	.intc_irq_num		= DA850_N_CP_INTC_IRQ,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 70a1827..5ab39f6 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -847,7 +847,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 	.pinmux_pins		= dm355_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm355_pins),
-	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+	.intc_base		= DAVINCI_ARM_INTC_BASE,
 	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
 	.intc_irq_prios		= dm355_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 451a4ef..be340ed 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1052,7 +1052,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 	.pinmux_pins		= dm365_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm365_pins),
-	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+	.intc_base		= DAVINCI_ARM_INTC_BASE,
 	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
 	.intc_irq_prios		= dm365_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index ee654de..d3aa1f7 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -738,7 +738,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 	.pinmux_pins		= dm644x_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm644x_pins),
-	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+	.intc_base		= DAVINCI_ARM_INTC_BASE,
 	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
 	.intc_irq_prios 	= dm644x_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 4c98ef0..e0153b3 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -822,7 +822,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 	.pinmux_pins		= dm646x_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm646x_pins),
-	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+	.intc_base		= DAVINCI_ARM_INTC_BASE,
 	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
 	.intc_irq_prios		= dm646x_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 6efa93f..67f1dfe 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -54,10 +54,11 @@ struct davinci_soc_info {
 	void __iomem			*pinmux_base;
 	const struct mux_config		*pinmux_pins;
 	unsigned long			pinmux_pins_num;
-	void __iomem			*intc_base;
+	u32				intc_base;
 	int				intc_type;
 	u8				*intc_irq_prios;
 	unsigned long			intc_irq_num;
+	u32				*intc_host_map;
 	struct davinci_timer_info	*timer_info;
 	int				gpio_type;
 	u32				gpio_base;
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index 121b114..4e8190e 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -51,7 +51,6 @@
 #define CP_INTC_HOST_PRIO_VECTOR(n)	(0x1600 + (n << 2))
 #define CP_INTC_VECTOR_ADDR(n)		(0x2000 + (n << 2))
 
-void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
-			 u8 *irq_prio, u32 *host_map);
+void __init cp_intc_init(void);
 
 #endif	/* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index af92ffe..784ddf3 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -116,6 +116,11 @@ void __init davinci_irq_init(void)
 	unsigned i;
 	const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
 
+	davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
+	davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
+	if (WARN_ON(!davinci_intc_base))
+		return;
+
 	/* Clear all interrupt requests */
 	davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
 	davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
@@ -148,7 +153,7 @@ void __init davinci_irq_init(void)
 	}
 
 	/* set up genirq dispatch for ARM INTC */
-	for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) {
+	for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
 		set_irq_chip(i, &davinci_irq_chip_0);
 		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 		if (i != IRQ_TINT1_TINT34)
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:38:47 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:38:47 -0400
Subject: [PATCH v2 7/8] Davinci: pinmux - use ioremap()
In-Reply-To: <1272753528-22981-1-git-send-email-cyril@ti.com>
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
Message-ID: <1272753528-22981-8-git-send-email-cyril@ti.com>

This patch modifies the pinmux implementation so as to ioremap() the pinmux
register area on first use.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v2: bug --> warn

 arch/arm/mach-davinci/da830.c               |    3 +--
 arch/arm/mach-davinci/da850.c               |    3 +--
 arch/arm/mach-davinci/dm355.c               |    2 +-
 arch/arm/mach-davinci/dm365.c               |    2 +-
 arch/arm/mach-davinci/dm644x.c              |    2 +-
 arch/arm/mach-davinci/dm646x.c              |    2 +-
 arch/arm/mach-davinci/include/mach/common.h |    2 +-
 arch/arm/mach-davinci/mux.c                 |   15 ++++++++++-----
 8 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index f8b7c2a..afcc4ba 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1191,6 +1191,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.cpu_clks		= da830_clks,
 	.psc_bases		= da830_psc_bases,
 	.psc_bases_num		= ARRAY_SIZE(da830_psc_bases),
+	.pinmux_base		= DA8XX_SYSCFG0_BASE + 0x120,
 	.pinmux_pins		= da830_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(da830_pins),
 	.intc_base		= DA8XX_CP_INTC_BASE,
@@ -1213,7 +1214,5 @@ void __init da830_init(void)
 	if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
 		return;
 
-	davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
-
 	davinci_common_init(&davinci_soc_info_da830);
 }
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b2ef7ad..df4b769 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1076,6 +1076,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.cpu_clks		= da850_clks,
 	.psc_bases		= da850_psc_bases,
 	.psc_bases_num		= ARRAY_SIZE(da850_psc_bases),
+	.pinmux_base		= DA8XX_SYSCFG0_BASE + 0x120,
 	.pinmux_pins		= da850_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(da850_pins),
 	.intc_base		= DA8XX_CP_INTC_BASE,
@@ -1106,8 +1107,6 @@ void __init da850_init(void)
 	if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
 		return;
 
-	davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
-
 	davinci_common_init(&davinci_soc_info_da850);
 
 	/*
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 5ab39f6..3834781 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -844,7 +844,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.cpu_clks		= dm355_clks,
 	.psc_bases		= dm355_psc_bases,
 	.psc_bases_num		= ARRAY_SIZE(dm355_psc_bases),
-	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
+	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
 	.pinmux_pins		= dm355_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm355_pins),
 	.intc_base		= DAVINCI_ARM_INTC_BASE,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index be340ed..e5e3dce 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1049,7 +1049,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.cpu_clks		= dm365_clks,
 	.psc_bases		= dm365_psc_bases,
 	.psc_bases_num		= ARRAY_SIZE(dm365_psc_bases),
-	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
+	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
 	.pinmux_pins		= dm365_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm365_pins),
 	.intc_base		= DAVINCI_ARM_INTC_BASE,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index d3aa1f7..7ad1520 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -735,7 +735,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.cpu_clks		= dm644x_clks,
 	.psc_bases		= dm644x_psc_bases,
 	.psc_bases_num		= ARRAY_SIZE(dm644x_psc_bases),
-	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
+	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
 	.pinmux_pins		= dm644x_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm644x_pins),
 	.intc_base		= DAVINCI_ARM_INTC_BASE,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index e0153b3..9404565 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -819,7 +819,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.cpu_clks		= dm646x_clks,
 	.psc_bases		= dm646x_psc_bases,
 	.psc_bases_num		= ARRAY_SIZE(dm646x_psc_bases),
-	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
+	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
 	.pinmux_pins		= dm646x_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm646x_pins),
 	.intc_base		= DAVINCI_ARM_INTC_BASE,
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 67f1dfe..2927a06 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -51,7 +51,7 @@ struct davinci_soc_info {
 	struct clk_lookup		*cpu_clks;
 	u32	 			*psc_bases;
 	unsigned long			psc_bases_num;
-	void __iomem			*pinmux_base;
+	u32				pinmux_base;
 	const struct mux_config		*pinmux_pins;
 	unsigned long			pinmux_pins_num;
 	u32				intc_base;
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index e9d530a..48695ca 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -22,6 +22,8 @@
 #include <mach/mux.h>
 #include <mach/common.h>
 
+static void __iomem *pinmux_base;
+
 /*
  * Sets the DAVINCI MUX register based on the table
  */
@@ -29,14 +31,17 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
 {
 	static DEFINE_SPINLOCK(mux_spin_lock);
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	void __iomem *base = soc_info->pinmux_base;
 	unsigned long flags;
 	const struct mux_config *cfg;
 	unsigned int reg_orig = 0, reg = 0;
 	unsigned int mask, warn = 0;
 
-	if (!soc_info->pinmux_pins)
-		BUG();
+	WARN_ON(!soc_info->pinmux_pins);
+
+	if (!pinmux_base) {
+		pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
+		WARN_ON(!pinmux_base);
+	}
 
 	if (index >= soc_info->pinmux_pins_num) {
 		printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
@@ -57,7 +62,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
 		unsigned	tmp1, tmp2;
 
 		spin_lock_irqsave(&mux_spin_lock, flags);
-		reg_orig = __raw_readl(base + cfg->mux_reg);
+		reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
 
 		mask = (cfg->mask << cfg->mask_offset);
 		tmp1 = reg_orig & mask;
@@ -69,7 +74,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
 		if (tmp1 != tmp2)
 			warn = 1;
 
-		__raw_writel(reg, base + cfg->mux_reg);
+		__raw_writel(reg, pinmux_base + cfg->mux_reg);
 		spin_unlock_irqrestore(&mux_spin_lock, flags);
 	}
 
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:38:48 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat,  1 May 2010 18:38:48 -0400
Subject: [PATCH v2 8/8] Davinci: iotable based ioremap() interception
In-Reply-To: <1272753528-22981-1-git-send-email-cyril@ti.com>
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
Message-ID: <1272753528-22981-9-git-send-email-cyril@ti.com>

This patch allows for a more flexible ioremap() interception based on iotable
contents.

With this patch, the ioremap() interception code can properly translate
addresses only after davinci_soc_info has been initialized.  Consequently,
in soc-specific init functions, davinci_common_init() has to happen before any
ioremap() attempts. The da8xx init sequence has been suitably modified to meet
this restriction.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v2: commit description changed
v2: davinci_soc_info comment added

 arch/arm/mach-davinci/da830.c               |    7 +++----
 arch/arm/mach-davinci/da850.c               |    4 ++--
 arch/arm/mach-davinci/include/mach/common.h |    8 +++++++-
 arch/arm/mach-davinci/io.c                  |   20 +++++++++++++++-----
 4 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index afcc4ba..6804a59 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1210,9 +1210,8 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 
 void __init da830_init(void)
 {
-	da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
-	if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
-		return;
-
 	davinci_common_init(&davinci_soc_info_da830);
+
+	da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
+	WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
 }
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index df4b769..a08cb91 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1099,6 +1099,8 @@ void __init da850_init(void)
 {
 	unsigned int v;
 
+	davinci_common_init(&davinci_soc_info_da850);
+
 	da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
 	if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
 		return;
@@ -1107,8 +1109,6 @@ void __init da850_init(void)
 	if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
 		return;
 
-	davinci_common_init(&davinci_soc_info_da850);
-
 	/*
 	 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
 	 * This helps keeping the peripherals on this domain insulated
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 2927a06..b8aa0b2 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -39,7 +39,13 @@ struct davinci_timer_info {
 
 struct davinci_gpio_controller;
 
-/* SoC specific init support */
+/*
+ * SoC info passed into common davinci modules.
+ *
+ * Base addresses in this structure should be physical and not virtual.
+ * Modules that take such base addresses, should internally ioremap() them to
+ * use.
+ */
 struct davinci_soc_info {
 	struct map_desc			*io_desc;
 	unsigned long			io_desc_num;
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index a1c0b6b..8ea60a8 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -12,19 +12,29 @@
 #include <linux/io.h>
 
 #include <asm/tlb.h>
+#include <asm/mach/map.h>
 
-#define BETWEEN(p, st, sz)	((p) >= (st) && (p) < ((st) + (sz)))
-#define XLATE(p, pst, vst)	((void __iomem *)((p) - (pst) + (vst)))
+#include <mach/common.h>
 
 /*
  * Intercept ioremap() requests for addresses in our fixed mapping regions.
  */
 void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
 {
-	if (BETWEEN(p, IO_PHYS, IO_SIZE))
-		return XLATE(p, IO_PHYS, IO_VIRT);
+	struct map_desc *desc = davinci_soc_info.io_desc;
+	int desc_num = davinci_soc_info.io_desc_num;
+	int i;
 
-	return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
+	for (i = 0; i < desc_num; i++, desc++) {
+		unsigned long iophys = __pfn_to_phys(desc->pfn);
+		unsigned long iosize = desc->length;
+
+		if (p >= iophys && (p + size) <= (iophys + iosize))
+			return __io(desc->virtual + p - iophys);
+	}
+
+	return __arm_ioremap_caller(p, size, type,
+					__builtin_return_address(0));
 }
 EXPORT_SYMBOL(davinci_ioremap);
 
-- 
1.7.0.4


From cyril at ti.com  Sat May  1 17:40:03 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat, 01 May 2010 18:40:03 -0400
Subject: [RFC 00/22] Davinci: pre-tnetv107x ioremap() cleanup
In-Reply-To: <874oiseh7f.fsf@deeprootsystems.com>
References: <1272580062-17663-1-git-send-email-cyril@ti.com>
	<874oiseh7f.fsf@deeprootsystems.com>
Message-ID: <4BDCADC3.5060900@ti.com>

Hi Kevin,

[...]
> So as a next step, lets break out the stuff I mentioned as ready to
> merge into a separate series, and get that applied and in davinci-next
> for 2.6.35.  Then, fixup some of the very minor issues I pointed out
> and get some more testing on your ioremap series for the existing
> platforms as well...

I have sent out the following series over the past few minutes:
  - pre-tnetv107x gpio series
  - pre-tnetv107x miscellaneous series
  - pre-tnetv107x ioremap series

The dmx (and presumably da8xx) boot problem was because of a left-over
raw_write to soc_info->gpio_base, and the fix was included in this burst.

-- Cyril.

From caglarakyuz at gmail.com  Sun May  2 01:52:59 2010
From: caglarakyuz at gmail.com (Caglar Akyuz)
Date: Sun, 2 May 2010 09:52:59 +0300
Subject: UBL Question
In-Reply-To: <s2r66b2b2311004301519pf2622273x53e09e53d1a24853@mail.gmail.com>
References: <o2o66b2b2311004301114m5992da85s156d0ace0e3afec1@mail.gmail.com>
	<E7D5CF88-E988-43FF-B15E-840475F51482@dsicentral.com>
	<s2r66b2b2311004301519pf2622273x53e09e53d1a24853@mail.gmail.com>
Message-ID: <201005020952.59981.caglarakyuz@gmail.com>

On Saturday 01 May 2010 01:19:56 am John Tobias wrote:
> I've used the following commands and didn't get any success.
> 
> 1. nanddump -n -f /ubl.bin /dev/mtd5
> Block size 16384, page size 512, OOB size 16
> Dumping data starting at 0x00000000 and ending at 0x00004000
> 
> 2. flash_erase /dev/mtd1
> 
> 3. nandwrite -n -o /dev/mtd1 /ubl.bin
> 
> 4. flash_erase /dev/mtd5
> 
> Any more idea?
> 

AFAIK, rbl/ubl pair uses different ECC layout than u-boot/Linux pair. For 
instance, I do not use u-boot in some cases and boot Linux directly from UBL  
in which I write Linux to NAND from userspace. In those cases, I read Linux 
without any ECC in UBL. But you do not have any access to RBL so you cannot 
program UBL from userspace without changing Linux ECC handling.

Best Regards,
Caglar

> Thanks,
> 
> John
> 
> On Fri, Apr 30, 2010 at 2:57 PM, Siddharth Choudhuri 
<sid at dsicentral.com>wrote:
> > Does dd also take care of writing the OOB area along with the actual data
> > ? The OOB layout where the ECC is written could be an issue IMO. You
> > might want to look at nandwrite i.e., read using nanddump -> erase ->
> > nandwrite to see if it works. Also, nanddump and nandwrite might have an
> > option to read page data and/or OOB.
> >
> > -sid
> >
> > On Apr 30, 2010, at 1:15 PM, John Tobias wrote:
> >
> > Hi Mike,
> >
> > I've used this two commands to copy the image on block 5 then, copy it
> > over to block 1.
> >
> > dd if=/dev/mtd5 of=/ubl.bin bs=512 count=32
> > dd if=/ubl.bin of=/dev/mtd1 bs=512 count=32
> > (My NAND flash has 512 bytes per page with 32 pages per block or 16Kbytes
> > in  1 block).
> >
> > In order to test the block 1 if it's working, I erased the block 5 and
> > boot my device but, it doesn't work.
> >
> > Any idea?
> >
> > Thanks,
> >
> > John
> >
> > On Fri, Apr 30, 2010 at 11:51 AM, John Tobias <jtobias at viaas.com> wrote:
> >> Hi Mike,
> >>
> >> Yes, that's my plan. I will expose the ubl blocks from linux userspace
> >> and become writable.
> >> And, I like the idea of using dd so no need to worry about the CRC
> >> issue.
> >>
> >> Thanks,
> >>
> >> John
> >>
> >> On Fri, Apr 30, 2010 at 11:34 AM, Mike Williamson <
> >>
> >> michael.williamson at criticallink.com> wrote:
> >>> Hi John,
> >>>
> >>> In the past, we've used the /dev/mtd* devices to write data back to NOR
> >>> (spi / parallel) devices for updating firmware using something like:
> >>>
> >>> dd if=newimage.bin of=/dev/mtd0
> >>>
> >>> Of course, you need to have your kernel configured to have the mtd
> >>> drivers loaded and you need to make these areas writable (most linux
> >>> board packages set these to read-only, given the sizeable gun you have
> >>> pointed at your shoes....)
> >>>
> >>> -Mike
> >>>
> >>> On Fri, Apr 30, 2010 at 2:14 PM, John Tobias <jtobias at viaas.com> wrote:
> >>>> Hi,
> >>>>
> >>>> Does anyone successfully written the UBL image in block 1/5 from linux
> >>>> userspace? I need a way to write the ubl image for the firmware
> >>>> upgrade and the only access that I have is the linux userspace.
> >>>>
> >>>>
> >>>> Thanks,
> >>>>
> >>>> John
> >>>>
> >>>> _______________________________________________
> >>>> Davinci-linux-open-source mailing list
> >>>> Davinci-linux-open-source at linux.davincidsp.com
> >>>> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> >>>
> >>> --
> >>> Michael Williamson
> >>> 315-425-4045x230
> >>> www.criticallink.com
> >
> > _______________________________________________
> > Davinci-linux-open-source mailing list
> > Davinci-linux-open-source at linux.davincidsp.com
> > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> 

From sshtylyov at mvista.com  Sun May  2 04:31:13 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Sun, 02 May 2010 13:31:13 +0400
Subject: [PATCH] DAxx: export da8xx_syscfg0_base
In-Reply-To: <4BDC748B.8080908@ti.com>
References: <201005012223.18808.sshtylyov@ru.mvista.com>
	<4BDC748B.8080908@ti.com>
Message-ID: <4BDD4661.7020701@mvista.com>

Hello.

Cyril Chemparathy wrote:

> Hi Sergei,
>
> [...]
>   
>>  void __iomem *da8xx_syscfg0_base;
>>  void __iomem *da8xx_syscfg1_base;
>> +EXPORT_SYMBOL_GPL(da8xx_syscfg0_base);
>>     
>
> Would it be an overkill to pass as a resource and ioremap in
> usb_hcd_da8xx_probe() instead?
>   

   Passing a resource is certainly an overkill.

WBR, Sergei


From bgr at linespeed.net  Sun May  2 05:09:27 2010
From: bgr at linespeed.net (Brian G Rhodes)
Date: Sun, 02 May 2010 05:09:27 -0500
Subject: UBL Question
In-Reply-To: <s2r66b2b2311004301519pf2622273x53e09e53d1a24853@mail.gmail.com>
References: <o2o66b2b2311004301114m5992da85s156d0ace0e3afec1@mail.gmail.com>	<y2s763e54b1004301134u80ee97c5w249e758c3b64368f@mail.gmail.com>	<j2l66b2b2311004301151u4c6632ddq49f005be818a36b5@mail.gmail.com>	<t2v66b2b2311004301315wdb4652f1me76661bf31c4a9dc@mail.gmail.com>	<E7D5CF88-E988-43FF-B15E-840475F51482@dsicentral.com>
	<s2r66b2b2311004301519pf2622273x53e09e53d1a24853@mail.gmail.com>
Message-ID: <4BDD4F57.4040907@linespeed.net>

John Tobias wrote:
> I've used the following commands and didn't get any success.
>
> 1. nanddump -n -f /ubl.bin /dev/mtd5
> Block size 16384, page size 512, OOB size 16
> Dumping data starting at 0x00000000 and ending at 0x00004000
>
> 2. flash_erase /dev/mtd1
>
> 3. nandwrite -n -o /dev/mtd1 /ubl.bin
>
> 4. flash_erase /dev/mtd5
>
> Any more idea?
>
>

Did you actually create your Linux MTD partitions as individual NAND 
blocks for the ubl?  For example...

    /* TI UBL and spare */
    {
        .name        = "UBL",
        .offset        = MTDPART_OFS_APPEND,
        .size        = SZ_128K + SZ_512K,
        .mask_flags    = 0,
    },

... is my NAND layout for ubl (Your NAND block size may differ).  All of 
the ubl blocks are on Linux mtd1.

nanddump -n /dev/mtd1 >img
nandwrite -n -o /dev/mtd1 img

Those commands work for me from Linux to produce a working system.  I 
can't say it's entirely reliable reading and writing without ECC 
though.  You may want to spend the time to add a routine in the Linux 
davinci NAND driver to write those blocks using rbl's ECC layout and 
save yourself some potential headaches.

If you have a single Linux mtd partition you can use the -s and -l 
options to write an individual block.  Since you are using a 16K page 
NAND part, your Linux partitions (for ubl) would look something like.
{
    .name = "Environment",
    .offset = 0,
    .size = SZ_16K,
    .mask_flags = 0,
},
{
    .name = "UBL1",
    .offset = MTDPART_OFS_APPEND,
    .size = SZ_16K,
    .mask_flags = 0,
},
{
    .name = "UBL2",
    .offset = MTDPART_OFS_APPEND,
    .size = SZ_16K,
    .mask_flags = 0,
},
{
    .name = "UBL3",
    .offset = MTDPART_OFS_APPEND,
    .size = SZ_16K,
    .mask_flags = 0,
},
{
    .name = "UBL4",
    .offset = MTDPART_OFS_APPEND,
    .size = SZ_16K,
    .mask_flags = 0,
},
{
    .name = "UBL5",
    .offset = MTDPART_OFS_APPEND,
    .size = SZ_16K,
    .mask_flags = 0,
},
{
    .name = "U-boot",
    .offset = MTDPART_OFS_APPEND,
    .size = SZ_256K, /* or whatever size you want for uboot.  you can 
place copies in up to 50 blocks though uboot will always consume > 1 
block for you */
    .mask_flags = 0,
}

With that you could access individual ubl copies without offsetting 
start address and specifying length in nanddump/nandwrite.

From mohameeed2010 at hotmail.com  Sun May  2 07:11:07 2010
From: mohameeed2010 at hotmail.com (Mohamed AbdElwahed)
Date: Sun, 2 May 2010 12:11:07 +0000
Subject: How Cache Layout Tool behave !
In-Reply-To: <mailman.1956.1272552814.11996.davinci-linux-open-source@linux.davincidsp.com>
References: <mailman.1956.1272552814.11996.davinci-linux-open-source@linux.davincidsp.com>
Message-ID: <COL106-W12704562B84E74C8820BF5ABF10@phx.gbl>


Hi all,
i developed my application based on the video_copy example and i success to compile it and run the codec using CGT v6.1.13,
now i want some optimizations so i used CGT v7.0.1
i added the option "--gen_profile_info" in "user.bld" file as below
C64P.ccOpts.prefix = "-mv64+ --gen_profile_info";
also i modified the make file that effect linker options as below
$(LINK) -o $@ -m app.map -c $^
Now i can successfully compile but when i try to run my application that utlize the generated codec it run slowly, not an issue now, but after closing my application. i search for the file named "pprofout.ppd" or "pprofout.pdat" but it does not exist.
i want to continue but i can not since next step depend on the generated file.
How to fix this and to have the "pprofout.ppd" or "pprofout.pdat" file

Note that my code call CERuntime_exit(), and ceapp_exit() but still the file does not created
----------------------------- 

any help is highly appreciated
BEST REGARD

 		 	   		  
_________________________________________________________________
Hotmail: Trusted email with Microsoft?s powerful SPAM protection.
https://signup.live.com/signup.aspx?id=60969
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From cyril at ti.com  Sun May  2 13:28:11 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun,  2 May 2010 14:28:11 -0400
Subject: [PATCH v1 0/3] Davinci: pre-tnetv107x serial series
Message-ID: <1272824894-23456-1-git-send-email-cyril@ti.com>

This series implements a few cleanups as a preparation to tnetv107x inclusion.
IO_ADDRESS usage has been eliminated from serial code, and the serial init no
longer assumes the presence of pwremu registers.

This series has been tested on dm355evm and tnetv107x platforms, and stacks on
top of the pre-tnetv107x gpio, misc, and ioremap series.

Cyril Chemparathy (3):
  Davinci: serial - remove unnecessary define
  Davinci: serial - use ioremap()
  Davinci: serial - conditional reset via pwremu

 arch/arm/mach-davinci/include/mach/serial.h |    1 -
 arch/arm/mach-davinci/serial.c              |   34 ++++++++++++++++++++------
 2 files changed, 26 insertions(+), 9 deletions(-)


From cyril at ti.com  Sun May  2 13:28:14 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun,  2 May 2010 14:28:14 -0400
Subject: [PATCH v1 3/3] Davinci: serial - conditional reset via pwremu
In-Reply-To: <1272824894-23456-1-git-send-email-cyril@ti.com>
References: <1272824894-23456-1-git-send-email-cyril@ti.com>
Message-ID: <1272824894-23456-4-git-send-email-cyril@ti.com>

With this patch, AR7 type uart ports are not reset via pwremu registers.  This
allows davinci_serial_init() reuse on tnetv107x soc.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/mach-davinci/serial.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 81af42c..1875740 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -107,7 +107,7 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
 				pr_err("uart regs ioremap failed\n");
 		}
 
-		if (p->membase)
+		if (p->membase && p->type != PORT_AR7)
 			davinci_serial_reset(p);
 	}
 
-- 
1.7.0.4


From cyril at ti.com  Sun May  2 13:28:12 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun,  2 May 2010 14:28:12 -0400
Subject: [PATCH v1 1/3] Davinci: serial - remove unnecessary define
In-Reply-To: <1272824894-23456-1-git-send-email-cyril@ti.com>
References: <1272824894-23456-1-git-send-email-cyril@ti.com>
Message-ID: <1272824894-23456-2-git-send-email-cyril@ti.com>

The uart pdata array is already terminated by a zero flag field.

This patch reuses this terminator and eliminates DAVINCI_MAX_NR_UARTS
definition.  This way, future platforms can have different number of uarts
initialized via davinci_serial_init().

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/mach-davinci/include/mach/serial.h |    1 -
 arch/arm/mach-davinci/serial.c              |    2 +-
 2 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index a584697..f6c4f34 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -13,7 +13,6 @@
 
 #include <mach/hardware.h>
 
-#define DAVINCI_MAX_NR_UARTS	3
 #define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 7ce5ba0..709e1a9 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -77,7 +77,7 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
 	 * Make sure the serial ports are muxed on at this point.
 	 * You have to mux them off in device drivers later on if not needed.
 	 */
-	for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++, p++) {
+	for (i = 0; p->flags; i++, p++) {
 		if (!(info->enabled_uarts & (1 << i)))
 			continue;
 
-- 
1.7.0.4


From cyril at ti.com  Sun May  2 13:28:13 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun,  2 May 2010 14:28:13 -0400
Subject: [PATCH v1 2/3] Davinci: serial - use ioremap()
In-Reply-To: <1272824894-23456-1-git-send-email-cyril@ti.com>
References: <1272824894-23456-1-git-send-email-cyril@ti.com>
Message-ID: <1272824894-23456-3-git-send-email-cyril@ti.com>

This patch implements davinci serial cleanups towards having this code
reusable on tnetv107x.

The change reuses the platform data membase field to hold the remapped space.
By disabling the UPF_IOREMAP flag in the platform data, we prevent
the 8250 driver from repeating the ioremap.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/mach-davinci/serial.c |   32 +++++++++++++++++++++++++-------
 1 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 709e1a9..81af42c 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -35,14 +35,20 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
 					   int offset)
 {
 	offset <<= up->regshift;
-	return (unsigned int)__raw_readl(IO_ADDRESS(up->mapbase) + offset);
+
+	WARN_ONCE(!up->membase, "unmapped read: uart[%d]\n", offset);
+
+	return (unsigned int)__raw_readl(up->membase + offset);
 }
 
 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
 				    int value)
 {
 	offset <<= p->regshift;
-	__raw_writel(value, IO_ADDRESS(p->mapbase) + offset);
+
+	WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset);
+
+	__raw_writel(value, p->membase + offset);
 }
 
 static void __init davinci_serial_reset(struct plat_serial8250_port *p)
@@ -83,14 +89,26 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
 
 		sprintf(name, "uart%d", i);
 		uart_clk = clk_get(dev, name);
-		if (IS_ERR(uart_clk))
+		if (IS_ERR(uart_clk)) {
 			printk(KERN_ERR "%s:%d: failed to get UART%d clock\n",
 					__func__, __LINE__, i);
-		else {
-			clk_enable(uart_clk);
-			p->uartclk = clk_get_rate(uart_clk);
-			davinci_serial_reset(p);
+			continue;
 		}
+
+		clk_enable(uart_clk);
+		p->uartclk = clk_get_rate(uart_clk);
+
+		if (!p->membase && p->mapbase) {
+			p->membase = ioremap(p->mapbase, SZ_4K);
+
+			if (p->membase)
+				p->flags &= ~UPF_IOREMAP;
+			else
+				pr_err("uart regs ioremap failed\n");
+		}
+
+		if (p->membase)
+			davinci_serial_reset(p);
 	}
 
 	return platform_device_register(soc_info->serial_dev);
-- 
1.7.0.4


From Andreas.Gaer at baslerweb.com  Mon May  3 02:06:47 2010
From: Andreas.Gaer at baslerweb.com (Gaer, A.)
Date: Mon, 3 May 2010 09:06:47 +0200
Subject: UBL Question
In-Reply-To: <o2o66b2b2311004301114m5992da85s156d0ace0e3afec1@mail.gmail.com>
References: <o2o66b2b2311004301114m5992da85s156d0ace0e3afec1@mail.gmail.com>
Message-ID: <C5A8FDEFF7647F4C9CB927D7DEB307730682F680@ahr075s.basler.corp>

Hi John,
 
> Does anyone successfully written the UBL image in block 1/5 from linux
userspace? 
 
If you're using NAND, the layout of the ECC checksum data in the OOB of
the flash is different between u-boot/linux and RBL/UBL. If you write
the UBL with linux, the RBL that loads UBL will try to check ECC, but
will load the ECC bytes from the wrong places, so it thinks the page is
bad.
 
Some days ago I did send an email named "Layout of OOB data in NAND
flash" over this list about this ECC layout mess. Unfortunately nobody
could explain to me why it is "designed" this way...
 
Currently I'm investigating two options: 
 
- Change the ECC layout in the davinci_nand.c driver of kernel/u-boot =>
I'm not sure if this works together with JFFS2 or UBI as they also have
their opinions about OOB layout
 
- Writing a special tool that does its own OOB data handling
 
Regards,
 Andreas.
 
 
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From mohameeed2010 at hotmail.com  Mon May  3 07:46:58 2010
From: mohameeed2010 at hotmail.com (Mohamed AbdElwahed)
Date: Mon, 3 May 2010 12:46:58 +0000
Subject: Cache Layout tool help needed
In-Reply-To: <mailman.1.1272819601.29640.davinci-linux-open-source@linux.davincidsp.com>
References: <mailman.1.1272819601.29640.davinci-linux-open-source@linux.davincidsp.com>
Message-ID: <COL106-W219991449D3B1A800919A9ABF20@phx.gbl>


Hi all

based on the video codec example i developed my own project and now i want to use cache layout tool.

i added "--gen_profile_info" in the user.bld file

and i added to the makefile that effect the linker options "--library=rts64plus.lib"

Now i get below error:-

"_TI_stop_pprof_collection" --> Unresolved symbols remain, at the linking step

also note that i do an explicit call to "TI_stop_pprof_collection()" to have the data written to disk file since when i used the run time support exit function named "CERuntime_exit()" it do nothing and no files "pprofout.pdat" created.

any help to get the file "pprofout.pdat" created

----------------

thanks in advance

 
 		 	   		  
_________________________________________________________________
Hotmail: Trusted email with powerful SPAM protection.
https://signup.live.com/signup.aspx?id=60969
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From khilman at deeprootsystems.com  Mon May  3 10:30:59 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 03 May 2010 08:30:59 -0700
Subject: [PATCH] DAxx: export da8xx_syscfg0_base
In-Reply-To: <4BDD4661.7020701@mvista.com> (Sergei Shtylyov's message of "Sun\,
	02 May 2010 13\:31\:13 +0400")
References: <201005012223.18808.sshtylyov@ru.mvista.com>
	<4BDC748B.8080908@ti.com> <4BDD4661.7020701@mvista.com>
Message-ID: <878w8180jw.fsf@deeprootsystems.com>

Sergei Shtylyov <sshtylyov at mvista.com> writes:

> Hello.
>
> Cyril Chemparathy wrote:
>
>> Hi Sergei,
>>
>> [...]
>>   
>>>  void __iomem *da8xx_syscfg0_base;
>>>  void __iomem *da8xx_syscfg1_base;
>>> +EXPORT_SYMBOL_GPL(da8xx_syscfg0_base);
>>>     
>>
>> Would it be an overkill to pass as a resource and ioremap in
>> usb_hcd_da8xx_probe() instead?
>>   
>
>   Passing a resource is certainly an overkill.
>

Disagree.

I would much rather see this as a resource than as a global variable.

What happens if/when this HW block is used on a non-da8xx device?

Kevin


From sshtylyov at mvista.com  Mon May  3 11:22:18 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Mon, 03 May 2010 20:22:18 +0400
Subject: [PATCH] DAxx: export da8xx_syscfg0_base
In-Reply-To: <878w8180jw.fsf@deeprootsystems.com>
References: <201005012223.18808.sshtylyov@ru.mvista.com>	<4BDC748B.8080908@ti.com>
	<4BDD4661.7020701@mvista.com> <878w8180jw.fsf@deeprootsystems.com>
Message-ID: <4BDEF83A.2010307@mvista.com>

Hello

Kevin Hilman wrote:

>>> Hi Sergei,
>>>
>>> [...]
>>>   
>>>       
>>>>  void __iomem *da8xx_syscfg0_base;
>>>>  void __iomem *da8xx_syscfg1_base;
>>>> +EXPORT_SYMBOL_GPL(da8xx_syscfg0_base);
>>>>     
>>>>         
>>> Would it be an overkill to pass as a resource and ioremap in
>>> usb_hcd_da8xx_probe() instead?
>>>   
>>>       
>>   Passing a resource is certainly an overkill.
>>     

   Do you really want me to pass the single CFGCHIP2 register as a 
resource?! Since the rest of the system config. registers don't belong 
to USB...

> Disagree.
>
> I would much rather see this as a resource than as a global variable.
>   

   But it's already a global variable!

> What happens if/when this HW block is used on a non-da8xx device?
>   

   I don't know. Why are you asking?

> Kevin

WBR, Sergei


From khilman at deeprootsystems.com  Mon May  3 11:48:27 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 03 May 2010 09:48:27 -0700
Subject: [PATCH] DAxx: export da8xx_syscfg0_base
In-Reply-To: <4BDEF83A.2010307@mvista.com> (Sergei Shtylyov's message of "Mon\,
	03 May 2010 20\:22\:18 +0400")
References: <201005012223.18808.sshtylyov@ru.mvista.com>
	<4BDC748B.8080908@ti.com> <4BDD4661.7020701@mvista.com>
	<878w8180jw.fsf@deeprootsystems.com> <4BDEF83A.2010307@mvista.com>
Message-ID: <87fx2953tw.fsf@deeprootsystems.com>

Sergei Shtylyov <sshtylyov at mvista.com> writes:

> Hello
>
> Kevin Hilman wrote:
>
>>>> Hi Sergei,
>>>>
>>>> [...]
>>>>         
>>>>>  void __iomem *da8xx_syscfg0_base;
>>>>>  void __iomem *da8xx_syscfg1_base;
>>>>> +EXPORT_SYMBOL_GPL(da8xx_syscfg0_base);
>>>>>             
>>>> Would it be an overkill to pass as a resource and ioremap in
>>>> usb_hcd_da8xx_probe() instead?
>>>>         
>>>   Passing a resource is certainly an overkill.
>>>     
>
>   Do you really want me to pass the single CFGCHIP2 register as a
> resource?! Since the rest of the system config. registers don't belong
> to USB...

Yes.  

More specifically I'd rather see this address/region passed in a more
normal way: use a resource, a platform_data callback etc.  Passing
data from platform code to drivers in a global variables is simply not
acceptable.

>> Disagree.
>>
>> I would much rather see this as a resource than as a global variable.
>>   
>
>   But it's already a global variable!

Yes, and that will hopefully be remedied that can be fixed after
Cyril's ioremap rework.

Just because you can, doesn't mean you should.

Kevin

From sshtylyov at mvista.com  Mon May  3 12:31:12 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Mon, 03 May 2010 21:31:12 +0400
Subject: [PATCH] DAxx: export da8xx_syscfg0_base
In-Reply-To: <87fx2953tw.fsf@deeprootsystems.com>
References: <201005012223.18808.sshtylyov@ru.mvista.com>	<4BDC748B.8080908@ti.com>
	<4BDD4661.7020701@mvista.com>	<878w8180jw.fsf@deeprootsystems.com>
	<4BDEF83A.2010307@mvista.com> <87fx2953tw.fsf@deeprootsystems.com>
Message-ID: <4BDF0860.9020200@mvista.com>

Hello.

Kevin Hilman wrote:

>>>>> Hi Sergei,
>>>>>
>>>>> [...]
>>>>>         
>>>>>           
>>>>>>  void __iomem *da8xx_syscfg0_base;
>>>>>>  void __iomem *da8xx_syscfg1_base;
>>>>>> +EXPORT_SYMBOL_GPL(da8xx_syscfg0_base);
>>>>>>             
>>>>>>             
>>>>> Would it be an overkill to pass as a resource and ioremap in
>>>>> usb_hcd_da8xx_probe() instead?
>>>>>         
>>>>>           
>>>>   Passing a resource is certainly an overkill.
>>>>     
>>>>         
>>   Do you really want me to pass the single CFGCHIP2 register as a
>> resource?! Since the rest of the system config. registers don't belong
>> to USB...
>>     
>
> Yes.
>   

   Oh horror... can't the patch be accepted as a short-term fix at least?

> More specifically I'd rather see this address/region passed in a more
> normal way: use a resource, a platform_data callback etc.  Passing
>   

   Platform data callback won't do -- there is no board specifics here.

> data from platform code to drivers in a global variables is simply not
> acceptable.
>   

   Why? Can you elaborate?..

>>> Disagree.
>>>
>>> I would much rather see this as a resource than as a global variable.
>>>   
>>>       
>>   But it's already a global variable!
>>     
>
> Yes, and that will hopefully be remedied that can be fixed after
> Cyril's ioremap rework.
>   

   How Cyril's ioremap() work can help here? You will still need to 
ioremap() system config. register range...

> Just because you can, doesn't mean you should.
>
> Kevin
>   

WBR, Sergei


From khilman at deeprootsystems.com  Mon May  3 16:12:32 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 03 May 2010 14:12:32 -0700
Subject: [PATCH] DAxx: export da8xx_syscfg0_base
In-Reply-To: <4BDF0860.9020200@mvista.com> (Sergei Shtylyov's message of "Mon\,
	03 May 2010 21\:31\:12 +0400")
References: <201005012223.18808.sshtylyov@ru.mvista.com>
	<4BDC748B.8080908@ti.com> <4BDD4661.7020701@mvista.com>
	<878w8180jw.fsf@deeprootsystems.com> <4BDEF83A.2010307@mvista.com>
	<87fx2953tw.fsf@deeprootsystems.com> <4BDF0860.9020200@mvista.com>
Message-ID: <87tyqowuyn.fsf@deeprootsystems.com>

Sergei Shtylyov <sshtylyov at mvista.com> writes:

> Hello.
>
> Kevin Hilman wrote:
>
>>>>>> Hi Sergei,
>>>>>>
>>>>>> [...]
>>>>>>                   
>>>>>>>  void __iomem *da8xx_syscfg0_base;
>>>>>>>  void __iomem *da8xx_syscfg1_base;
>>>>>>> +EXPORT_SYMBOL_GPL(da8xx_syscfg0_base);
>>>>>>>                         
>>>>>> Would it be an overkill to pass as a resource and ioremap in
>>>>>> usb_hcd_da8xx_probe() instead?
>>>>>>                   
>>>>>   Passing a resource is certainly an overkill.
>>>>>             
>>>   Do you really want me to pass the single CFGCHIP2 register as a
>>> resource?! Since the rest of the system config. registers don't belong
>>> to USB...
>>>     
>>
>> Yes.
>>   
>
>   Oh horror... can't the patch be accepted as a short-term fix at least?

Not by me, sorry.

This kind of "short-term fix" tends to last a really long time, so is
better prevented early.

Also, I don't see the OHCI driver that uses this variable in mainline
or in linux-next.

>> More specifically I'd rather see this address/region passed in a more
>> normal way: use a resource, a platform_data callback etc.  Passing
>>   
>
>   Platform data callback won't do -- there is no board specifics here.
>
>> data from platform code to drivers in a global variables is simply not
>> acceptable.
>>   
>
>   Why? Can you elaborate?..

Because there are existing, established methods for platform/board
code to communicate data to drivers.

>>>> Disagree.
>>>>
>>>> I would much rather see this as a resource than as a global variable.
>>>>         
>>>   But it's already a global variable!
>>>     
>>
>> Yes, and that will hopefully be remedied that can be fixed after
>> Cyril's ioremap rework.
>>   
>
>   How Cyril's ioremap() work can help here? You will still need to
> ioremap() system config. register range...

Yes, but the base address varible will no longer need to be global
since those DA8XX_SYSCFGx_VIRT() macros can disappear.

Kevin

From surfinbum at mac.com  Mon May  3 16:35:50 2010
From: surfinbum at mac.com (Chris)
Date: Mon, 03 May 2010 17:35:50 -0400
Subject: can't detect video input
Message-ID: <91267469800027024439265370340605739929-Webmail@me.com>

Hello,  

After reconfiguring my evm6446 to file share from an NFS host, I am having trouble getting video into the board.

I want to revert to the default bootargs that ship with the board, but I can't find that info anywhere, and I've written over the NAND with new bootargs for the NFS mount.  Does anybody know what the default bootarg string is?  

I am using this at the moment:

setenv bootargs video=davincifb:vid0=0,2500K:vid1=0,2500K:osd0=720x576x16,2025K davinci_enc_mngr.ch0_output=COMPOSITE davinci_enc_mngr.ch0_mode=ntsc console=ttyS0,115200n8 noinitrd rw ip=off root=/dev/hda1 mem=118M

But when I try to run the encode demo, I get the following error message:

Encode demo started.
Error: Failed to detect video standard, video input connected?6/data/videos/demo.
Error: Failed to create video encoder: mpeg4enc

And when I boot, I am getting the following messages:

 Davici AEW Driver cannot be loaded
 VIDEO PORT is not enabledData Flow path from CCDC is disabled

 Davinci AF driver cannot be loaded
 VIDEO PORT is not enabled 
 CCDC needs to be configured<6>i2c /dev entries driver

Can anybody help me???

Thank You, 

Chris Jackson




From Jon.Povey at racelogic.co.uk  Mon May  3 20:21:29 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Tue, 4 May 2010 02:21:29 +0100
Subject: UBL Question
In-Reply-To: <4BDD4F57.4040907@linespeed.net>
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08DE6D0DF9@Cloud.RL.local>

Brian G Rhodes wrote:
> Those commands work for me from Linux to produce a working system.  I
> can't say it's entirely reliable reading and writing without ECC
> though.  You may want to spend the time to add a routine in the Linux
> davinci NAND driver to write those blocks using rbl's ECC layout and
> save yourself some potential headaches.

Some thoughts:

John, I recommend using JTAG to see what is going on inside your NAND chip - lets you read/write/erase blocks with or without OOB and works even when the board won't boot because of bad NAND contents. I use OpenOCD, which includes configs for some davinci EVMs and NAND flash layouts, with an Amontec JTAGKey-Tiny - total cost around 30 euro. Also good for bootloader debug etc.

What DaVinci device are you using? The DM355 RBL ignores ECC completely (see silicon errata document) but uses this wacky OOB layout on large page size NAND.

I am in the position of trying to work out a firmware upgrade path such that git kernel Linux (with "correct" OOB layout) can rewrite UBL (in DM355 RBL "infix" layout format).
The UBL shouldn't need valid ECC on DM355, but if I need it for other things I plan to use a software utility to calculate ECC and format the OOB data, then use the raw+oob write mode of mtd - I think I remember it can do that.. Will find out soon (!).

I am hoping to derive the software ECC calculation util from the GenECC tool described here:
http://processors.wiki.ti.com/index.php/NAND_ECC_Generation_for_DaVinci_Family_of_Devices

HTH,

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network



From Jon.Povey at racelogic.co.uk  Mon May  3 20:27:01 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Tue, 4 May 2010 02:27:01 +0100
Subject: UBL Question
In-Reply-To: <C5A8FDEFF7647F4C9CB927D7DEB307730682F680@ahr075s.basler.corp>
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08DE6D0DFA@Cloud.RL.local>

Hi Andreas,

Gaer, A. wrote:
> Currently I'm investigating two options:
>
> - Change the ECC layout in the davinci_nand.c driver of kernel/u-boot
> => I'm not sure if this works together with JFFS2 or UBI as they also
> have their opinions about OOB layout
>
> - Writing a special tool that does its own OOB data handling

I notice we both seem to be working in the same area. Perhaps we can share notes, I would be happy to. Either on or off-list.

You may have seen some of my mails on the list; I am working with DM355, 2KB page NAND, OpenOCD JTAG and am working on migrating from our in-production product based on the beta SDK with legacy OOB layout, to current git kernel and U-Boot.

I plan to go the route of "special tool that does its own OOB handling", partly because I may need something like that to do field upgrades from one to the other (particularly to translate the BBT and rewrite the u-boot environment).

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network



From Jon.Povey at racelogic.co.uk  Mon May  3 20:31:58 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Tue, 4 May 2010 02:31:58 +0100
Subject: can't detect video input
In-Reply-To: <91267469800027024439265370340605739929-Webmail@me.com>
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08DE6D0DFB@Cloud.RL.local>

Chris wrote:
> I want to revert to the default bootargs that ship with the board,
> but I can't find that info anywhere, and I've written over the NAND
> with new bootargs for the NFS mount.  Does anybody know what the
> default bootarg string is?

With DM355 EVM, I think that info was printed in the getting started or technical reference dead tree guides that came with the EVM. Not sure about 6446. Hope that helps or someone else answers..

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network



From nsekhar at ti.com  Tue May  4 01:07:35 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Tue, 4 May 2010 11:37:35 +0530
Subject: [PATCH] DAxx: export da8xx_syscfg0_base
In-Reply-To: <4BDEF83A.2010307@mvista.com>
References: <201005012223.18808.sshtylyov@ru.mvista.com>
	<4BDC748B.8080908@ti.com>	<4BDD4661.7020701@mvista.com>
	<878w8180jw.fsf@deeprootsystems.com> <4BDEF83A.2010307@mvista.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6CC369A@dbde02.ent.ti.com>

Hi Sergei,

On Mon, May 03, 2010 at 21:52:18, Sergei Shtylyov wrote:
> Hello
>
> Kevin Hilman wrote:
>
> >>> Hi Sergei,
> >>>
> >>> [...]
> >>>
> >>>
> >>>>  void __iomem *da8xx_syscfg0_base;
> >>>>  void __iomem *da8xx_syscfg1_base;
> >>>> +EXPORT_SYMBOL_GPL(da8xx_syscfg0_base);
> >>>>
> >>>>
> >>> Would it be an overkill to pass as a resource and ioremap in
> >>> usb_hcd_da8xx_probe() instead?
> >>>
> >>>
> >>   Passing a resource is certainly an overkill.
> >>
>
>    Do you really want me to pass the single CFGCHIP2 register as a
> resource?! Since the rest of the system config. registers don't belong
> to USB...

You could have platform data callback function pointers
to for the various functionality that CFGCHIP2 provides.

Something like:

pdata->setup_phy_clk()
pdata->phy_{enable|disable}()
...

Future platforms doing these operations in a different manner
can re-define these functions (or not define them at all as the
case may be).

Thanks,
Sekhar


From nsekhar at ti.com  Tue May  4 01:25:19 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Tue, 4 May 2010 11:55:19 +0530
Subject: [RFC 00/22] Davinci: pre-tnetv107x ioremap() cleanup
In-Reply-To: <4BDC54B3.9000302@ti.com>
References: <1272580062-17663-1-git-send-email-cyril@ti.com>
	<874oiseh7f.fsf@deeprootsystems.com> <4BDC54B3.9000302@ti.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6CC36D4@dbde02.ent.ti.com>

On Sat, May 01, 2010 at 21:50:03, Chemparathy, Cyril wrote:
> Hi Kevin,
>
> [...]
> > This is something that's been on my TODO for some time and I've been
> > ignoring it.   Thanks a ton for tackling it.
>
> Unless this has been covered elsewhere, what does the davinci TODO list
> look like?  Pet peeves with the code?

The closest information to what you ask for is here: http://processors.wiki.ti.com/index.php/DaVinci_GIT_Linux_Kernel

Thanks,
Sekhar


From suhas.jain at mavensystems.com  Tue May  4 01:46:46 2010
From: suhas.jain at mavensystems.com (Suhas Jain)
Date: Tue, 4 May 2010 12:16:46 +0530
Subject: can't detect video input
In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE08DE6D0DFB@Cloud.RL.local>
References: <91267469800027024439265370340605739929-Webmail@me.com>
	<70E876B0EA86DD4BAF101844BC814DFE08DE6D0DFB@Cloud.RL.local>
Message-ID: <001001caeb55$9484d040$bd8e70c0$@jain@mavensystems.com>

Hi Chris,

You can find the complete setup for DM6446 EVM board at following link.

http://focus.ti.com/lit/ug/sprue66e/sprue66e.pdf

Regards,
Suhas Jain

-----Original Message-----
From: davinci-linux-open-source-bounces at linux.davincidsp.com
[mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of
Jon Povey
Sent: 04 May 2010 07:02
To: Chris; davinci-linux-open-source at linux.davincidsp.com
Subject: RE: can't detect video input

Chris wrote:
> I want to revert to the default bootargs that ship with the board,
> but I can't find that info anywhere, and I've written over the NAND
> with new bootargs for the NFS mount.  Does anybody know what the
> default bootarg string is?

With DM355 EVM, I think that info was printed in the getting started or
technical reference dead tree guides that came with the EVM. Not sure about
6446. Hope that helps or someone else answers..

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number
2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham,
Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended
by Racelogic Ltd for the use of the named individual or entity to which it
is directed and may contain information that is confidential or privileged.
If you have received this electronic mail transmission in error, please
delete it from your system without copying or forwarding it, and notify the
sender of the error by reply email so that the sender's address records can
be corrected. The views expressed by the sender of this communication do not
necessarily represent those of Racelogic Ltd. Please note that Racelogic
reserves the right to monitor e-mail communications passing through its
network


_______________________________________________
Davinci-linux-open-source mailing list
Davinci-linux-open-source at linux.davincidsp.com
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source


From lamiaposta71 at gmail.com  Tue May  4 03:05:39 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Tue, 4 May 2010 10:05:39 +0200
Subject: UBL Question
In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE08DE6D0DFA@Cloud.RL.local>
References: <C5A8FDEFF7647F4C9CB927D7DEB307730682F680@ahr075s.basler.corp>
	<70E876B0EA86DD4BAF101844BC814DFE08DE6D0DFA@Cloud.RL.local>
Message-ID: <h2gade1bdc1005040105r2aad773r6ef2d7be2cdc01cd@mail.gmail.com>

I'm defining the situation for ubl+u-boot programming.
First of all I haven't yet found a git tree of ubl.
This is not so nice, because I'd like that ubl project could become better
day by day.

From
http://processors.wiki.ti.com/index.php/SD_card_boot_and_flashing_tool_for_DM355_and_DM365I
can't find a project on ubl.

Any suggestion?
-------------- next part --------------
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From jaya.krishnan at samsung.com  Tue May  4 03:14:04 2010
From: jaya.krishnan at samsung.com (Jaya krishnan)
Date: Tue, 04 May 2010 08:14:04 +0000 (GMT)
Subject: DM6467 McASP
Message-ID: <5010611.471081272960844667.JavaMail.weblogic@epml17>


Hi  ,
I want  to use McASP  port  0 for  transmit data  and port 1  to  generate high frequency clock (AHCLKX) (to be used as  master clock for  another audio DAC  in the  system.)  Is there  any  limitation to use  both  ports  simultaneously?Pls  reply
Regards
JK

 
    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  

From Jon.Povey at racelogic.co.uk  Tue May  4 03:18:57 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Tue, 4 May 2010 09:18:57 +0100
Subject: UBL Question
In-Reply-To: <h2gade1bdc1005040105r2aad773r6ef2d7be2cdc01cd@mail.gmail.com>
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08DE6D0E2E@Cloud.RL.local>

Raffaele Recalcati wrote:
> I'm defining the situation for ubl+u-boot programming.
> First of all I haven't yet found a git tree of ubl.
> This is not so nice, because I'd like that ubl project could become
> better day by day.
>
> From
> http://processors.wiki.ti.com/index.php/SD_card_boot_and_flashing_tool_for_DM355_and_DM365
> I can't find a project on ubl.
>
> Any suggestion?

This would be of great interest to me, too. I need to look into this soon.

There are some pointers to UBL versions here:
http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program
But I am not aware of any active "community UBL". I would be interested in contributing to one.

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network



From a.auer at zydacron.com  Tue May  4 03:27:10 2010
From: a.auer at zydacron.com (Andreas Auer)
Date: Tue, 04 May 2010 10:27:10 +0200
Subject: i2c problem with TVP514x
Message-ID: <hrolpl$hl9$1@dough.gmane.org>

Hello,

currently I'm using the 2.6.32 kernel from the arago project on a 
customized board similar to the TI EVM with the DM6446 processor. Right 
now, I have an application running which uses the TVP5146 to capture 
video from an analog camera.
The problem is that I'm getting the message:
        "tvp514x 1-005d: Write: retry ... 1"

I already added the fix to recover the i2c bus. So, after the above 
message the kernel prints:
        "i2c_davinci i2c_davinci.1: initiating i2c bus recovery"

I get the messages very often! Is it possible that some other i2c 
devices (AIC33, MSP430, KSZ8893M Ethernet Switch) cause this problem??

Thanks,
Andreas


From nsekhar at ti.com  Tue May  4 03:41:38 2010
From: nsekhar at ti.com (Sekhar Nori)
Date: Tue,  4 May 2010 14:11:38 +0530
Subject: [PATCH 4/5] davinci: edma: fix coding style issues related to long
	lines
In-Reply-To: <1272962499-18932-4-git-send-email-nsekhar@ti.com>
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
	<1272962499-18932-3-git-send-email-nsekhar@ti.com>
	<1272962499-18932-4-git-send-email-nsekhar@ti.com>
Message-ID: <1272962499-18932-5-git-send-email-nsekhar@ti.com>

In the edma driver, some lines are broken up at really
odd places to meet the 80 chars per line rule. This make
reading those parts particularly difficult.

This patch fixes that by creating a few lines over 80
characters, but I feel it still improves readability over
what is existing currently.

Here are the checkpatch warnings:

WARNING: line over 80 characters
+                                               edma_cc[ctlr]->intr_data[k].data);

WARNING: line over 80 characters
+                                       if (edma_cc[ctlr]->intr_data[k].callback) {

WARNING: line over 80 characters
+                                               edma_cc[ctlr]->intr_data[k].callback(k,

WARNING: line over 80 characters
+                                                       edma_cc[ctlr]->intr_data[k].data);

WARNING: line over 80 characters
+                       count > (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))

Signed-off-by: Sekhar Nori <nsekhar at ti.com>
---
 arch/arm/mach-davinci/dma.c |   22 +++++++++-------------
 1 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 2734de9..3c89dd8 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -376,10 +376,9 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 				edma_shadow0_write_array(ctlr, SH_ICR, j,
 							(1 << i));
 				if (edma_cc[ctlr]->intr_data[k].callback)
-					edma_cc[ctlr]->intr_data[k].callback(
-						k, DMA_COMPLETE,
-						edma_cc[ctlr]->intr_data[k].
-						data);
+					edma_cc[ctlr]->intr_data[k].callback(k,
+						DMA_COMPLETE,
+						edma_cc[ctlr]->intr_data[k].data);
 			}
 		}
 		cnt++;
@@ -430,13 +429,10 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 					/* Clear any SER */
 					edma_shadow0_write_array(ctlr, SH_SECR,
 								j, (1 << i));
-					if (edma_cc[ctlr]->intr_data[k].
-								callback) {
-						edma_cc[ctlr]->intr_data[k].
-						callback(k,
-						DMA_CC_ERROR,
-						edma_cc[ctlr]->intr_data
-						[k].data);
+					if (edma_cc[ctlr]->intr_data[k].callback) {
+						edma_cc[ctlr]->intr_data[k].callback(k,
+							DMA_CC_ERROR,
+							edma_cc[ctlr]->intr_data[k].data);
 					}
 				}
 			}
@@ -825,8 +821,8 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
 	 * and cannot be more than the number of slots minus the number of
 	 * channels
 	 */
-	if (count < 1 || count >
-		(edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
+	if (count < 1 ||
+			count >	(edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
 		return -EINVAL;
 
 	switch (id) {
-- 
1.6.2.4


From nsekhar at ti.com  Tue May  4 03:41:36 2010
From: nsekhar at ti.com (Sekhar Nori)
Date: Tue,  4 May 2010 14:11:36 +0530
Subject: [PATCH 2/5] davinci: edma: fix coding style issue related to usage of
	braces
In-Reply-To: <1272962499-18932-2-git-send-email-nsekhar@ti.com>
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
Message-ID: <1272962499-18932-3-git-send-email-nsekhar@ti.com>

In the edma driver, there are couple of instances where braces
are used for a single statement 'if' construct.

There are other instances where 'else' part of the if-else construct
does not use braces even if the 'if' part is a multi-line statement.

This patch fixes both.

Signed-off-by: Sekhar Nori <nsekhar at ti.com>
---
 arch/arm/mach-davinci/dma.c |   15 +++++++--------
 1 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index b705089..cc5fcda 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -310,10 +310,9 @@ setup_dma_interrupt(unsigned lch,
 	ctlr = EDMA_CTLR(lch);
 	lch = EDMA_CHAN_SLOT(lch);
 
-	if (!callback) {
+	if (!callback)
 		edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
 				(1 << (lch & 0x1f)));
-	}
 
 	edma_cc[ctlr]->intr_data[lch].callback = callback;
 	edma_cc[ctlr]->intr_data[lch].data = data;
@@ -376,12 +375,11 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 				/* Clear the corresponding IPR bits */
 				edma_shadow0_write_array(ctlr, SH_ICR, j,
 							(1 << i));
-				if (edma_cc[ctlr]->intr_data[k].callback) {
+				if (edma_cc[ctlr]->intr_data[k].callback)
 					edma_cc[ctlr]->intr_data[k].callback(
 						k, DMA_COMPLETE,
 						edma_cc[ctlr]->intr_data[k].
 						data);
-				}
 			}
 		}
 		cnt++;
@@ -473,9 +471,8 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 		if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
 		    && (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
 		    && (edma_read(ctlr, EDMA_QEMR) == 0)
-		    && (edma_read(ctlr, EDMA_CCERR) == 0)) {
+		    && (edma_read(ctlr, EDMA_CCERR) == 0))
 			break;
-		}
 		cnt++;
 		if (cnt > 10)
 			break;
@@ -531,8 +528,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
 			if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
 				stop_slot = i;
 				break;
-			} else
+			} else {
 				count = num_slots;
+			}
 		}
 	}
 
@@ -1402,8 +1400,9 @@ static int __init edma_probe(struct platform_device *pdev)
 				break;
 			else
 				return -ENODEV;
-		} else
+		} else {
 			found = 1;
+		}
 
 		len[j] = resource_size(r[j]);
 
-- 
1.6.2.4


From nsekhar at ti.com  Tue May  4 03:41:35 2010
From: nsekhar at ti.com (Sekhar Nori)
Date: Tue,  4 May 2010 14:11:35 +0530
Subject: [PATCH 1/5] davinci: edma: use a more intuitive name for edma_info
In-Reply-To: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
Message-ID: <1272962499-18932-2-git-send-email-nsekhar@ti.com>

'edma_info' structure inside the edma driver represents
a single instance of edma channel controller. Call it
'edma_cc' instead. This also avoids readers confusing
it with an instance of edma_soc_info structre which
carries the platform data for a single channel controller
instance.

Signed-off-by: Sekhar Nori <nsekhar at ti.com>
---
 arch/arm/mach-davinci/dma.c |  158 +++++++++++++++++++++----------------------
 1 files changed, 77 insertions(+), 81 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 0bf290b..b705089 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -243,7 +243,7 @@ struct edma {
 	} intr_data[EDMA_MAX_DMACH];
 };
 
-static struct edma *edma_info[EDMA_MAX_CC];
+static struct edma *edma_cc[EDMA_MAX_CC];
 static int arch_num_cc;
 
 /* dummy param set used to (re)initialize parameter RAM slots */
@@ -261,7 +261,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
 
 	/* default to low priority queue */
 	if (queue_no == EVENTQ_DEFAULT)
-		queue_no = edma_info[ctlr]->default_queue;
+		queue_no = edma_cc[ctlr]->default_queue;
 
 	queue_no &= 7;
 	edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
@@ -315,8 +315,8 @@ setup_dma_interrupt(unsigned lch,
 				(1 << (lch & 0x1f)));
 	}
 
-	edma_info[ctlr]->intr_data[lch].callback = callback;
-	edma_info[ctlr]->intr_data[lch].data = data;
+	edma_cc[ctlr]->intr_data[lch].callback = callback;
+	edma_cc[ctlr]->intr_data[lch].data = data;
 
 	if (callback) {
 		edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
@@ -328,11 +328,10 @@ setup_dma_interrupt(unsigned lch,
 
 static int irq2ctlr(int irq)
 {
-	if (irq >= edma_info[0]->irq_res_start &&
-		irq <= edma_info[0]->irq_res_end)
+	if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
 		return 0;
-	else if (irq >= edma_info[1]->irq_res_start &&
-		irq <= edma_info[1]->irq_res_end)
+	else if (irq >= edma_cc[1]->irq_res_start &&
+		irq <= edma_cc[1]->irq_res_end)
 		return 1;
 
 	return -1;
@@ -377,10 +376,10 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 				/* Clear the corresponding IPR bits */
 				edma_shadow0_write_array(ctlr, SH_ICR, j,
 							(1 << i));
-				if (edma_info[ctlr]->intr_data[k].callback) {
-					edma_info[ctlr]->intr_data[k].callback(
+				if (edma_cc[ctlr]->intr_data[k].callback) {
+					edma_cc[ctlr]->intr_data[k].callback(
 						k, DMA_COMPLETE,
-						edma_info[ctlr]->intr_data[k].
+						edma_cc[ctlr]->intr_data[k].
 						data);
 				}
 			}
@@ -433,12 +432,12 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 					/* Clear any SER */
 					edma_shadow0_write_array(ctlr, SH_SECR,
 								j, (1 << i));
-					if (edma_info[ctlr]->intr_data[k].
+					if (edma_cc[ctlr]->intr_data[k].
 								callback) {
-						edma_info[ctlr]->intr_data[k].
+						edma_cc[ctlr]->intr_data[k].
 						callback(k,
 						DMA_CC_ERROR,
-						edma_info[ctlr]->intr_data
+						edma_cc[ctlr]->intr_data
 						[k].data);
 					}
 				}
@@ -514,9 +513,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
 	int stop_slot = start_slot;
 	DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
 
-	for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) {
+	for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
 		j = EDMA_CHAN_SLOT(i);
-		if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) {
+		if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
 			/* Record our current beginning slot */
 			if (count == num_slots)
 				stop_slot = i;
@@ -543,12 +542,12 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
 	 * of contiguous parameter RAM slots but do not find the exact number
 	 * requested as we may reach the total number of parameter RAM slots
 	 */
-	if (i == edma_info[ctlr]->num_slots)
+	if (i == edma_cc[ctlr]->num_slots)
 		stop_slot = i;
 
 	for (j = start_slot; j < stop_slot; j++)
 		if (test_bit(j, tmp_inuse))
-			clear_bit(j, edma_info[ctlr]->edma_inuse);
+			clear_bit(j, edma_cc[ctlr]->edma_inuse);
 
 	if (count)
 		return -EBUSY;
@@ -570,7 +569,7 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
 				(int)pdev->resource[i].start >= 0) {
 			ctlr = EDMA_CTLR(pdev->resource[i].start);
 			clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
-					edma_info[ctlr]->edma_unused);
+					edma_cc[ctlr]->edma_unused);
 		}
 	}
 
@@ -644,14 +643,13 @@ int edma_alloc_channel(int channel,
 		for (i = 0; i < arch_num_cc; i++) {
 			channel = 0;
 			for (;;) {
-				channel = find_next_bit(edma_info[i]->
-						edma_unused,
-						edma_info[i]->num_channels,
+				channel = find_next_bit(edma_cc[i]->edma_unused,
+						edma_cc[i]->num_channels,
 						channel);
-				if (channel == edma_info[i]->num_channels)
+				if (channel == edma_cc[i]->num_channels)
 					break;
 				if (!test_and_set_bit(channel,
-						edma_info[i]->edma_inuse)) {
+						edma_cc[i]->edma_inuse)) {
 					done = 1;
 					ctlr = i;
 					break;
@@ -663,9 +661,9 @@ int edma_alloc_channel(int channel,
 		}
 		if (!done)
 			return -ENOMEM;
-	} else if (channel >= edma_info[ctlr]->num_channels) {
+	} else if (channel >= edma_cc[ctlr]->num_channels) {
 		return -EINVAL;
-	} else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) {
+	} else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
 		return -EBUSY;
 	}
 
@@ -706,7 +704,7 @@ void edma_free_channel(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel >= edma_info[ctlr]->num_channels)
+	if (channel >= edma_cc[ctlr]->num_channels)
 		return;
 
 	setup_dma_interrupt(channel, NULL, NULL);
@@ -714,7 +712,7 @@ void edma_free_channel(unsigned channel)
 
 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
 			&dummy_paramset, PARM_SIZE);
-	clear_bit(channel, edma_info[ctlr]->edma_inuse);
+	clear_bit(channel, edma_cc[ctlr]->edma_inuse);
 }
 EXPORT_SYMBOL(edma_free_channel);
 
@@ -738,20 +736,19 @@ int edma_alloc_slot(unsigned ctlr, int slot)
 		slot = EDMA_CHAN_SLOT(slot);
 
 	if (slot < 0) {
-		slot = edma_info[ctlr]->num_channels;
+		slot = edma_cc[ctlr]->num_channels;
 		for (;;) {
-			slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse,
-					edma_info[ctlr]->num_slots, slot);
-			if (slot == edma_info[ctlr]->num_slots)
+			slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
+					edma_cc[ctlr]->num_slots, slot);
+			if (slot == edma_cc[ctlr]->num_slots)
 				return -ENOMEM;
-			if (!test_and_set_bit(slot,
-						edma_info[ctlr]->edma_inuse))
+			if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
 				break;
 		}
-	} else if (slot < edma_info[ctlr]->num_channels ||
-			slot >= edma_info[ctlr]->num_slots) {
+	} else if (slot < edma_cc[ctlr]->num_channels ||
+			slot >= edma_cc[ctlr]->num_slots) {
 		return -EINVAL;
-	} else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) {
+	} else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
 		return -EBUSY;
 	}
 
@@ -777,13 +774,13 @@ void edma_free_slot(unsigned slot)
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_channels ||
-		slot >= edma_info[ctlr]->num_slots)
+	if (slot < edma_cc[ctlr]->num_channels ||
+		slot >= edma_cc[ctlr]->num_slots)
 		return;
 
 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
 			&dummy_paramset, PARM_SIZE);
-	clear_bit(slot, edma_info[ctlr]->edma_inuse);
+	clear_bit(slot, edma_cc[ctlr]->edma_inuse);
 }
 EXPORT_SYMBOL(edma_free_slot);
 
@@ -821,8 +818,8 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
 	 * of slots
 	 */
 	if ((id != EDMA_CONT_PARAMS_ANY) &&
-		(slot < edma_info[ctlr]->num_channels ||
-		slot >= edma_info[ctlr]->num_slots))
+		(slot < edma_cc[ctlr]->num_channels ||
+		slot >= edma_cc[ctlr]->num_slots))
 		return -EINVAL;
 
 	/*
@@ -831,13 +828,13 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
 	 * channels
 	 */
 	if (count < 1 || count >
-		(edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels))
+		(edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
 		return -EINVAL;
 
 	switch (id) {
 	case EDMA_CONT_PARAMS_ANY:
 		return reserve_contiguous_slots(ctlr, id, count,
-						 edma_info[ctlr]->num_channels);
+						 edma_cc[ctlr]->num_channels);
 	case EDMA_CONT_PARAMS_FIXED_EXACT:
 	case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
 		return reserve_contiguous_slots(ctlr, id, count, slot);
@@ -869,8 +866,8 @@ int edma_free_cont_slots(unsigned slot, int count)
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_channels ||
-		slot >= edma_info[ctlr]->num_slots ||
+	if (slot < edma_cc[ctlr]->num_channels ||
+		slot >= edma_cc[ctlr]->num_slots ||
 		count < 1)
 		return -EINVAL;
 
@@ -880,7 +877,7 @@ int edma_free_cont_slots(unsigned slot, int count)
 
 		memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
 			&dummy_paramset, PARM_SIZE);
-		clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse);
+		clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
 	}
 
 	return 0;
@@ -910,7 +907,7 @@ void edma_set_src(unsigned slot, dma_addr_t src_port,
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_slots) {
+	if (slot < edma_cc[ctlr]->num_slots) {
 		unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
 
 		if (mode) {
@@ -948,7 +945,7 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port,
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_slots) {
+	if (slot < edma_cc[ctlr]->num_slots) {
 		unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
 
 		if (mode) {
@@ -1008,7 +1005,7 @@ void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_slots) {
+	if (slot < edma_cc[ctlr]->num_slots) {
 		edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
 				0xffff0000, src_bidx);
 		edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
@@ -1034,7 +1031,7 @@ void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_slots) {
+	if (slot < edma_cc[ctlr]->num_slots) {
 		edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
 				0x0000ffff, dest_bidx << 16);
 		edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
@@ -1081,7 +1078,7 @@ void edma_set_transfer_params(unsigned slot,
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_slots) {
+	if (slot < edma_cc[ctlr]->num_slots) {
 		edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
 				0x0000ffff, bcnt_rld << 16);
 		if (sync_mode == ASYNC)
@@ -1111,9 +1108,9 @@ void edma_link(unsigned from, unsigned to)
 	ctlr_to = EDMA_CTLR(to);
 	to = EDMA_CHAN_SLOT(to);
 
-	if (from >= edma_info[ctlr_from]->num_slots)
+	if (from >= edma_cc[ctlr_from]->num_slots)
 		return;
-	if (to >= edma_info[ctlr_to]->num_slots)
+	if (to >= edma_cc[ctlr_to]->num_slots)
 		return;
 	edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
 				PARM_OFFSET(to));
@@ -1134,7 +1131,7 @@ void edma_unlink(unsigned from)
 	ctlr = EDMA_CTLR(from);
 	from = EDMA_CHAN_SLOT(from);
 
-	if (from >= edma_info[ctlr]->num_slots)
+	if (from >= edma_cc[ctlr]->num_slots)
 		return;
 	edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
 }
@@ -1161,7 +1158,7 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param)
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot >= edma_info[ctlr]->num_slots)
+	if (slot >= edma_cc[ctlr]->num_slots)
 		return;
 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
 			PARM_SIZE);
@@ -1183,7 +1180,7 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param)
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot >= edma_info[ctlr]->num_slots)
+	if (slot >= edma_cc[ctlr]->num_slots)
 		return;
 	memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
 			PARM_SIZE);
@@ -1208,7 +1205,7 @@ void edma_pause(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_info[ctlr]->num_channels) {
+	if (channel < edma_cc[ctlr]->num_channels) {
 		unsigned int mask = (1 << (channel & 0x1f));
 
 		edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
@@ -1229,7 +1226,7 @@ void edma_resume(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_info[ctlr]->num_channels) {
+	if (channel < edma_cc[ctlr]->num_channels) {
 		unsigned int mask = (1 << (channel & 0x1f));
 
 		edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
@@ -1255,12 +1252,12 @@ int edma_start(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_info[ctlr]->num_channels) {
+	if (channel < edma_cc[ctlr]->num_channels) {
 		int j = channel >> 5;
 		unsigned int mask = (1 << (channel & 0x1f));
 
 		/* EDMA channels without event association */
-		if (test_bit(channel, edma_info[ctlr]->edma_unused)) {
+		if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
 			pr_debug("EDMA: ESR%d %08x\n", j,
 				edma_shadow0_read_array(ctlr, SH_ESR, j));
 			edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
@@ -1301,7 +1298,7 @@ void edma_stop(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_info[ctlr]->num_channels) {
+	if (channel < edma_cc[ctlr]->num_channels) {
 		int j = channel >> 5;
 		unsigned int mask = (1 << (channel & 0x1f));
 
@@ -1340,7 +1337,7 @@ void edma_clean_channel(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_info[ctlr]->num_channels) {
+	if (channel < edma_cc[ctlr]->num_channels) {
 		int j = (channel >> 5);
 		unsigned int mask = 1 << (channel & 0x1f);
 
@@ -1368,7 +1365,7 @@ void edma_clear_event(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel >= edma_info[ctlr]->num_channels)
+	if (channel >= edma_cc[ctlr]->num_channels)
 		return;
 	if (channel < 32)
 		edma_write(ctlr, EDMA_ECR, 1 << channel);
@@ -1423,38 +1420,37 @@ static int __init edma_probe(struct platform_device *pdev)
 			goto fail1;
 		}
 
-		edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
-		if (!edma_info[j]) {
+		edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
+		if (!edma_cc[j]) {
 			status = -ENOMEM;
 			goto fail1;
 		}
-		memset(edma_info[j], 0, sizeof(struct edma));
+		memset(edma_cc[j], 0, sizeof(struct edma));
 
-		edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel,
+		edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel,
 							EDMA_MAX_DMACH);
-		edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot,
+		edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot,
 							EDMA_MAX_PARAMENTRY);
-		edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc,
-							EDMA_MAX_CC);
+		edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC);
 
-		edma_info[j]->default_queue = info[j].default_queue;
-		if (!edma_info[j]->default_queue)
-			edma_info[j]->default_queue = EVENTQ_1;
+		edma_cc[j]->default_queue = info[j].default_queue;
+		if (!edma_cc[j]->default_queue)
+			edma_cc[j]->default_queue = EVENTQ_1;
 
 		dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
 			edmacc_regs_base[j]);
 
-		for (i = 0; i < edma_info[j]->num_slots; i++)
+		for (i = 0; i < edma_cc[j]->num_slots; i++)
 			memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
 					&dummy_paramset, PARM_SIZE);
 
 		/* Mark all channels as unused */
-		memset(edma_info[j]->edma_unused, 0xff,
-			sizeof(edma_info[j]->edma_unused));
+		memset(edma_cc[j]->edma_unused, 0xff,
+			sizeof(edma_cc[j]->edma_unused));
 
 		sprintf(irq_name, "edma%d", j);
 		irq[j] = platform_get_irq_byname(pdev, irq_name);
-		edma_info[j]->irq_res_start = irq[j];
+		edma_cc[j]->irq_res_start = irq[j];
 		status = request_irq(irq[j], dma_irq_handler, 0, "edma",
 					&pdev->dev);
 		if (status < 0) {
@@ -1465,7 +1461,7 @@ static int __init edma_probe(struct platform_device *pdev)
 
 		sprintf(irq_name, "edma%d_err", j);
 		err_irq[j] = platform_get_irq_byname(pdev, irq_name);
-		edma_info[j]->irq_res_end = err_irq[j];
+		edma_cc[j]->irq_res_end = err_irq[j];
 		status = request_irq(err_irq[j], dma_ccerr_handler, 0,
 					"edma_error", &pdev->dev);
 		if (status < 0) {
@@ -1478,7 +1474,7 @@ static int __init edma_probe(struct platform_device *pdev)
 		 * specified. This way, long transfers on the low priority queue
 		 * started by the codec engine will not cause audio defects.
 		 */
-		for (i = 0; i < edma_info[j]->num_channels; i++)
+		for (i = 0; i < edma_cc[j]->num_channels; i++)
 			map_dmach_queue(j, i, EVENTQ_1);
 
 		queue_tc_mapping = info[j].queue_tc_mapping;
@@ -1541,7 +1537,7 @@ fail1:
 			release_mem_region(r[i]->start, len[i]);
 		if (edmacc_regs_base[i])
 			iounmap(edmacc_regs_base[i]);
-		kfree(edma_info[i]);
+		kfree(edma_cc[i]);
 	}
 	return status;
 }
-- 
1.6.2.4


From nsekhar at ti.com  Tue May  4 03:41:39 2010
From: nsekhar at ti.com (Sekhar Nori)
Date: Tue,  4 May 2010 14:11:39 +0530
Subject: [PATCH 5/5] davinci: edma: use BIT() wherever possible
In-Reply-To: <1272962499-18932-5-git-send-email-nsekhar@ti.com>
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
	<1272962499-18932-3-git-send-email-nsekhar@ti.com>
	<1272962499-18932-4-git-send-email-nsekhar@ti.com>
	<1272962499-18932-5-git-send-email-nsekhar@ti.com>
Message-ID: <1272962499-18932-6-git-send-email-nsekhar@ti.com>

This patch replaces occurences of (1 << x) with
BIT(x) as it makes for much better reading.

Signed-off-by: Sekhar Nori <nsekhar at ti.com>
---
 arch/arm/mach-davinci/dma.c |   42 +++++++++++++++++++++---------------------
 1 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 3c89dd8..3475058 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -312,16 +312,16 @@ setup_dma_interrupt(unsigned lch,
 
 	if (!callback)
 		edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
-				(1 << (lch & 0x1f)));
+				BIT(lch & 0x1f));
 
 	edma_cc[ctlr]->intr_data[lch].callback = callback;
 	edma_cc[ctlr]->intr_data[lch].data = data;
 
 	if (callback) {
 		edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
-				(1 << (lch & 0x1f)));
+				BIT(lch & 0x1f));
 		edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
-				(1 << (lch & 0x1f)));
+				BIT(lch & 0x1f));
 	}
 }
 
@@ -374,7 +374,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 							SH_IER, j) & BIT(i))) {
 				/* Clear the corresponding IPR bits */
 				edma_shadow0_write_array(ctlr, SH_ICR, j,
-							(1 << i));
+							BIT(i));
 				if (edma_cc[ctlr]->intr_data[k].callback)
 					edma_cc[ctlr]->intr_data[k].callback(k,
 						DMA_COMPLETE,
@@ -422,13 +422,13 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 			for (i = 0; i < 32; i++) {
 				int k = (j << 5) + i;
 				if (edma_read_array(ctlr, EDMA_EMR, j) &
-							(1 << i)) {
+							BIT(i)) {
 					/* Clear the corresponding EMR bits */
 					edma_write_array(ctlr, EDMA_EMCR, j,
-							1 << i);
+							BIT(i));
 					/* Clear any SER */
 					edma_shadow0_write_array(ctlr, SH_SECR,
-								j, (1 << i));
+								j, BIT(i));
 					if (edma_cc[ctlr]->intr_data[k].callback) {
 						edma_cc[ctlr]->intr_data[k].callback(k,
 							DMA_CC_ERROR,
@@ -440,11 +440,11 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 			dev_dbg(data, "QEMR %02x\n",
 				edma_read(ctlr, EDMA_QEMR));
 			for (i = 0; i < 8; i++) {
-				if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) {
+				if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
 					/* Clear the corresponding IPR bits */
-					edma_write(ctlr, EDMA_QEMCR, 1 << i);
+					edma_write(ctlr, EDMA_QEMCR, BIT(i));
 					edma_shadow0_write(ctlr, SH_QSECR,
-								(1 << i));
+								BIT(i));
 
 					/* NOTE:  not reported!! */
 				}
@@ -456,9 +456,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 			 * to just write CCERRCLR with CCERR value...
 			 */
 			for (i = 0; i < 8; i++) {
-				if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) {
+				if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
 					/* Clear the corresponding IPR bits */
-					edma_write(ctlr, EDMA_CCERRCLR, 1 << i);
+					edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
 
 					/* NOTE:  not reported!! */
 				}
@@ -662,7 +662,7 @@ int edma_alloc_channel(int channel,
 	}
 
 	/* ensure access through shadow region 0 */
-	edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
+	edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
 
 	/* ensure no events are pending */
 	edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
@@ -1200,7 +1200,7 @@ void edma_pause(unsigned channel)
 	channel = EDMA_CHAN_SLOT(channel);
 
 	if (channel < edma_cc[ctlr]->num_channels) {
-		unsigned int mask = (1 << (channel & 0x1f));
+		unsigned int mask = BIT(channel & 0x1f);
 
 		edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
 	}
@@ -1221,7 +1221,7 @@ void edma_resume(unsigned channel)
 	channel = EDMA_CHAN_SLOT(channel);
 
 	if (channel < edma_cc[ctlr]->num_channels) {
-		unsigned int mask = (1 << (channel & 0x1f));
+		unsigned int mask = BIT(channel & 0x1f);
 
 		edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
 	}
@@ -1248,7 +1248,7 @@ int edma_start(unsigned channel)
 
 	if (channel < edma_cc[ctlr]->num_channels) {
 		int j = channel >> 5;
-		unsigned int mask = (1 << (channel & 0x1f));
+		unsigned int mask = BIT(channel & 0x1f);
 
 		/* EDMA channels without event association */
 		if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
@@ -1294,7 +1294,7 @@ void edma_stop(unsigned channel)
 
 	if (channel < edma_cc[ctlr]->num_channels) {
 		int j = channel >> 5;
-		unsigned int mask = (1 << (channel & 0x1f));
+		unsigned int mask = BIT(channel & 0x1f);
 
 		edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
 		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
@@ -1333,7 +1333,7 @@ void edma_clean_channel(unsigned channel)
 
 	if (channel < edma_cc[ctlr]->num_channels) {
 		int j = (channel >> 5);
-		unsigned int mask = 1 << (channel & 0x1f);
+		unsigned int mask = BIT(channel & 0x1f);
 
 		pr_debug("EDMA: EMR%d %08x\n", j,
 				edma_read_array(ctlr, EDMA_EMR, j));
@@ -1342,7 +1342,7 @@ void edma_clean_channel(unsigned channel)
 		edma_write_array(ctlr, EDMA_EMCR, j, mask);
 		/* Clear any SER */
 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
-		edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3);
+		edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
 	}
 }
 EXPORT_SYMBOL(edma_clean_channel);
@@ -1362,9 +1362,9 @@ void edma_clear_event(unsigned channel)
 	if (channel >= edma_cc[ctlr]->num_channels)
 		return;
 	if (channel < 32)
-		edma_write(ctlr, EDMA_ECR, 1 << channel);
+		edma_write(ctlr, EDMA_ECR, BIT(channel));
 	else
-		edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32));
+		edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
 }
 EXPORT_SYMBOL(edma_clear_event);
 
-- 
1.6.2.4


From nsekhar at ti.com  Tue May  4 03:41:34 2010
From: nsekhar at ti.com (Sekhar Nori)
Date: Tue,  4 May 2010 14:11:34 +0530
Subject: [PATCH 0/5] coding style fixes for edma driver
Message-ID: <1272962499-18932-1-git-send-email-nsekhar@ti.com>

While working on adding resource reservation feature to EDMA
driver, I found some places where the code could be made more
readable. 

The result is this 5 part series which attempts to improve its
readability.

The series is tested on DM6467 EVM using audio playback as edma
usage example.

Sekhar Nori (5):
  davinci: edma: use a more intuitive name for edma_info
  davinci: edma: fix coding style issue related to usage of braces
  davinci: edma: fix coding style issues related to indentation
  davinci: edma: fix coding style issues related to long lines
  davinci: edma: use BIT() wherever possible

 arch/arm/mach-davinci/dma.c |  237 +++++++++++++++++++++----------------------
 1 files changed, 114 insertions(+), 123 deletions(-)


From nsekhar at ti.com  Tue May  4 03:41:37 2010
From: nsekhar at ti.com (Sekhar Nori)
Date: Tue,  4 May 2010 14:11:37 +0530
Subject: [PATCH 3/5] davinci: edma: fix coding style issues related to
	indentation
In-Reply-To: <1272962499-18932-3-git-send-email-nsekhar@ti.com>
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
	<1272962499-18932-3-git-send-email-nsekhar@ti.com>
Message-ID: <1272962499-18932-4-git-send-email-nsekhar@ti.com>

In the edma driver some if statememnts are broken up such that
the condition code is at the same indentation level as the
statement block. This makes reading it particularly difficult.

This patch fixes that issue.

Signed-off-by: Sekhar Nori <nsekhar at ti.com>
---
 arch/arm/mach-davinci/dma.c |   26 +++++++++++++-------------
 1 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index cc5fcda..2734de9 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -330,7 +330,7 @@ static int irq2ctlr(int irq)
 	if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
 		return 0;
 	else if (irq >= edma_cc[1]->irq_res_start &&
-		irq <= edma_cc[1]->irq_res_end)
+				irq <= edma_cc[1]->irq_res_end)
 		return 1;
 
 	return -1;
@@ -352,7 +352,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 	dev_dbg(data, "dma_irq_handler\n");
 
 	if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
-	    && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
+			&& (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
 		return IRQ_NONE;
 
 	while (1) {
@@ -406,9 +406,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 	dev_dbg(data, "dma_ccerr_handler\n");
 
 	if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
-	    (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
-	    (edma_read(ctlr, EDMA_QEMR) == 0) &&
-	    (edma_read(ctlr, EDMA_CCERR) == 0))
+			(edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
+			(edma_read(ctlr, EDMA_QEMR) == 0) &&
+			(edma_read(ctlr, EDMA_CCERR) == 0))
 		return IRQ_NONE;
 
 	while (1) {
@@ -469,9 +469,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 			}
 		}
 		if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
-		    && (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
-		    && (edma_read(ctlr, EDMA_QEMR) == 0)
-		    && (edma_read(ctlr, EDMA_CCERR) == 0))
+				&& (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
+				&& (edma_read(ctlr, EDMA_QEMR) == 0)
+				&& (edma_read(ctlr, EDMA_CCERR) == 0))
 			break;
 		cnt++;
 		if (cnt > 10)
@@ -773,7 +773,7 @@ void edma_free_slot(unsigned slot)
 	slot = EDMA_CHAN_SLOT(slot);
 
 	if (slot < edma_cc[ctlr]->num_channels ||
-		slot >= edma_cc[ctlr]->num_slots)
+			slot >= edma_cc[ctlr]->num_slots)
 		return;
 
 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
@@ -816,8 +816,8 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
 	 * of slots
 	 */
 	if ((id != EDMA_CONT_PARAMS_ANY) &&
-		(slot < edma_cc[ctlr]->num_channels ||
-		slot >= edma_cc[ctlr]->num_slots))
+			(slot < edma_cc[ctlr]->num_channels ||
+			slot >= edma_cc[ctlr]->num_slots))
 		return -EINVAL;
 
 	/*
@@ -865,8 +865,8 @@ int edma_free_cont_slots(unsigned slot, int count)
 	slot = EDMA_CHAN_SLOT(slot);
 
 	if (slot < edma_cc[ctlr]->num_channels ||
-		slot >= edma_cc[ctlr]->num_slots ||
-		count < 1)
+			slot >= edma_cc[ctlr]->num_slots ||
+			count < 1)
 		return -EINVAL;
 
 	for (i = slot; i < slot + count; ++i) {
-- 
1.6.2.4


From nyhetsbrev at dokumera.anp.se  Tue May  4 03:39:05 2010
From: nyhetsbrev at dokumera.anp.se (DokuMera Nyhetsbrev)
Date: Tue, 04 May 2010 10:39:05 +0200
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From nsekhar at ti.com  Tue May  4 03:57:51 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Tue, 4 May 2010 14:27:51 +0530
Subject: UBL Question
In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE08DE6D0E2E@Cloud.RL.local>
References: <h2gade1bdc1005040105r2aad773r6ef2d7be2cdc01cd@mail.gmail.com>
	<70E876B0EA86DD4BAF101844BC814DFE08DE6D0E2E@Cloud.RL.local>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6CC384F@dbde02.ent.ti.com>

Hello,

On Tue, May 04, 2010 at 13:48:57, Jon Povey wrote:
> Raffaele Recalcati wrote:
> > I'm defining the situation for ubl+u-boot programming.
> > First of all I haven't yet found a git tree of ubl.
> > This is not so nice, because I'd like that ubl project could become
> > better day by day.
> >
> > From
> > http://processors.wiki.ti.com/index.php/SD_card_boot_and_flashing_tool_for_DM355_and_DM365
> > I can't find a project on ubl.
> >
> > Any suggestion?
>
> This would be of great interest to me, too. I need to look into this soon.
>
> There are some pointers to UBL versions here:
> http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program
> But I am not aware of any active "community UBL". I would be interested in contributing to one.
>

There is a sourceforge project for UBL and serial flashing tools:

http://sourceforge.net/projects/dvflashutils/

You could join this project to contribute.

Thanks,
Sekhar


From nsekhar at ti.com  Tue May  4 04:02:09 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Tue, 4 May 2010 14:32:09 +0530
Subject: i2c problem with TVP514x
In-Reply-To: <hrolpl$hl9$1@dough.gmane.org>
References: <hrolpl$hl9$1@dough.gmane.org>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6CC385E@dbde02.ent.ti.com>

Hello,

On Tue, May 04, 2010 at 13:57:10, Andreas Auer wrote:
> Hello,
>
> currently I'm using the 2.6.32 kernel from the arago project on a
> customized board similar to the TI EVM with the DM6446 processor. Right
> now, I have an application running which uses the TVP5146 to capture
> video from an analog camera.
> The problem is that I'm getting the message:
>         "tvp514x 1-005d: Write: retry ... 1"
>
> I already added the fix to recover the i2c bus. So, after the above
> message the kernel prints:
>         "i2c_davinci i2c_davinci.1: initiating i2c bus recovery"
>
> I get the messages very often! Is it possible that some other i2c
> devices (AIC33, MSP430, KSZ8893M Ethernet Switch) cause this problem??

I think this can happen because of slave holding
the SCL low for inordinately long periods of time.

Does the problem disappear if the other slaves
aren't accessed at all?

Thanks,
Sekhar

From lamiaposta71 at gmail.com  Tue May  4 04:02:31 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Tue, 4 May 2010 11:02:31 +0200
Subject: UBL Question
In-Reply-To: <B85A65D85D7EB246BE421B3FB0FBB59301E6CC384F@dbde02.ent.ti.com>
References: <h2gade1bdc1005040105r2aad773r6ef2d7be2cdc01cd@mail.gmail.com>
	<70E876B0EA86DD4BAF101844BC814DFE08DE6D0E2E@Cloud.RL.local>
	<B85A65D85D7EB246BE421B3FB0FBB59301E6CC384F@dbde02.ent.ti.com>
Message-ID: <v2yade1bdc1005040202l866f8534lfec7f2a490a285e4@mail.gmail.com>

Hi Nori,

There is a sourceforge project for UBL and serial flashing tools:
>
> http://sourceforge.net/projects/dvflashutils/
>
> You could join this project to contribute.
>
> Thanks,
> Sekhar
>

Is this project good also for dm365?



-- 
www.opensurf.it
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From sshtylyov at mvista.com  Tue May  4 04:27:05 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Tue, 04 May 2010 13:27:05 +0400
Subject: [PATCH 3/5] davinci: edma: fix coding style issues related to
	indentation
In-Reply-To: <1272962499-18932-4-git-send-email-nsekhar@ti.com>
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>	<1272962499-18932-2-git-send-email-nsekhar@ti.com>	<1272962499-18932-3-git-send-email-nsekhar@ti.com>
	<1272962499-18932-4-git-send-email-nsekhar@ti.com>
Message-ID: <4BDFE869.8020705@mvista.com>

Hello.

Sekhar Nori wrote:
> In the edma driver some if statememnts are broken up such that
> the condition code is at the same indentation level as the
> statement block. This makes reading it particularly difficult.
>
> This patch fixes that issue.
>
> Signed-off-by: Sekhar Nori <nsekhar at ti.com>
> ---
>  arch/arm/mach-davinci/dma.c |   26 +++++++++++++-------------
>  1 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
> index cc5fcda..2734de9 100644
> --- a/arch/arm/mach-davinci/dma.c
> +++ b/arch/arm/mach-davinci/dma.c
> @@ -352,7 +352,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
>  	dev_dbg(data, "dma_irq_handler\n");
>  
>  	if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
> -	    && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
>   

   IMHO this level of indentation doesn't affect the readability.

> +			&& (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
>  		return IRQ_NONE;
>  
>  	while (1) {
> @@ -406,9 +406,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
>  	dev_dbg(data, "dma_ccerr_handler\n");
>  
>  	if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
> -	    (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
> -	    (edma_read(ctlr, EDMA_QEMR) == 0) &&
> -	    (edma_read(ctlr, EDMA_CCERR) == 0))
>   

   What's up with these too?

> +			(edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
> +			(edma_read(ctlr, EDMA_QEMR) == 0) &&
> +			(edma_read(ctlr, EDMA_CCERR) == 0))
>   

   Your increased indentation looks rather ugly to me... matter of 
taste, of course.

> @@ -469,9 +469,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
>  			}
>  		}
>  		if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
> -		    && (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
> -		    && (edma_read(ctlr, EDMA_QEMR) == 0)
> -		    && (edma_read(ctlr, EDMA_CCERR) == 0))
>   

   Again, I don't find anything bad about this, except I'd put && at the 
end of lines, no at the start...

> +				&& (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
> +				&& (edma_read(ctlr, EDMA_QEMR) == 0)
> +				&& (edma_read(ctlr, EDMA_CCERR) == 0))

WBR, Sergei


From sshtylyov at mvista.com  Tue May  4 04:33:55 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Tue, 04 May 2010 13:33:55 +0400
Subject: [PATCH] DAxx: export da8xx_syscfg0_base
In-Reply-To: <87tyqowuyn.fsf@deeprootsystems.com>
References: <201005012223.18808.sshtylyov@ru.mvista.com>	<4BDC748B.8080908@ti.com>
	<4BDD4661.7020701@mvista.com>	<878w8180jw.fsf@deeprootsystems.com>
	<4BDEF83A.2010307@mvista.com>	<87fx2953tw.fsf@deeprootsystems.com>
	<4BDF0860.9020200@mvista.com> <87tyqowuyn.fsf@deeprootsystems.com>
Message-ID: <4BDFEA03.5020000@mvista.com>

Hello.

Kevin Hilman wrote:

>>>>>>> Hi Sergei,
>>>>>>>
>>>>>>> [...]
>>>>>>>                   
>>>>>>>               
>>>>>>>>  void __iomem *da8xx_syscfg0_base;
>>>>>>>>  void __iomem *da8xx_syscfg1_base;
>>>>>>>> +EXPORT_SYMBOL_GPL(da8xx_syscfg0_base);
>>>>>>>>                         
>>>>>>>>                 
>>>>>>> Would it be an overkill to pass as a resource and ioremap in
>>>>>>> usb_hcd_da8xx_probe() instead?
>>>>>>>                   
>>>>>>>               
>>>>>>   Passing a resource is certainly an overkill.
>>>>>>             
>>>>>>             
>>>>   Do you really want me to pass the single CFGCHIP2 register as a
>>>> resource?! Since the rest of the system config. registers don't belong
>>>> to USB...
>>>>     
>>>>         
>>> Yes.
>>>   
>>>       
>>   Oh horror... can't the patch be accepted as a short-term fix at least?
>>     
>
> Not by me, sorry.
>
> This kind of "short-term fix" tends to last a really long time, so is
> better prevented early.
>   

   It's too late to prevent it -- I've already used the 
da8xx_syscfg0_base in the OHCI glue. :-)

> Also, I don't see the OHCI driver that uses this variable in mainline
> or in linux-next.
>   

   Look ar drivers/usb/host/ohci-da8xx.c, it's used via 
DA8XX_SYSCFG0_VIRT() macro.

>>> More specifically I'd rather see this address/region passed in a more
>>> normal way: use a resource, a platform_data callback etc.  Passing
>>>   
>>>       
>>   Platform data callback won't do -- there is no board specifics here.

   Well, considering that CFGCHIP2 is shared between MUSB and OHCI, 
passing it as a resource is out of question for me. So, platfrom data 
callback has to be considered.

>>>>> Disagree.
>>>>>
>>>>> I would much rather see this as a resource than as a global variable.
>>>>>         
>>>>>           
>>>>   But it's already a global variable!
>>>>     
>>>>         
>>> Yes, and that will hopefully be remedied that can be fixed after
>>> Cyril's ioremap rework.
>>>   
>>>       
>>   How Cyril's ioremap() work can help here? You will still need to
>> ioremap() system config. register range...
>>     
>
> Yes, but the base address varible will no longer need to be global
> since those DA8XX_SYSCFGx_VIRT() macros can disappear.
>
> Kevin
>   

   Ah, you're going tio kill the macros... OHCI glue should stop using 
them before that can happen.

WBR, Sergei


From pjohn at mvista.com  Tue May  4 04:55:27 2010
From: pjohn at mvista.com (Philby John)
Date: Tue, 04 May 2010 15:25:27 +0530
Subject: i2c problem with TVP514x
In-Reply-To: <hrolpl$hl9$1@dough.gmane.org>
References: <hrolpl$hl9$1@dough.gmane.org>
Message-ID: <4BDFEF0F.5020709@mvista.com>

On 05/04/2010 01:57 PM, Andreas Auer wrote:
> Hello,
>
> currently I'm using the 2.6.32 kernel from the arago project on a
> customized board similar to the TI EVM with the DM6446 processor. Right
> now, I have an application running which uses the TVP5146 to capture
> video from an analog camera.
> The problem is that I'm getting the message:
> "tvp514x 1-005d: Write: retry ... 1"
>
> I already added the fix to recover the i2c bus. So, after the above
> message the kernel prints:
> "i2c_davinci i2c_davinci.1: initiating i2c bus recovery"
>
> I get the messages very often! Is it possible that some other i2c
> devices (AIC33, MSP430, KSZ8893M Ethernet Switch) cause this problem??

Hello,
	I am curious, does the bus recover after a failure? That is, are you 
able to capture video after the "i2c recovery code" does its job? What 
happens without the i2c bus recovery patch?


Regards,
Philby

From kieranbingham at gmail.com  Tue May  4 05:06:38 2010
From: kieranbingham at gmail.com (Kieran Bingham)
Date: Tue, 04 May 2010 11:06:38 +0100
Subject: Codec Stalled on DM365 2.6.32 Kernel
Message-ID: <4BDFF1AE.7070103@gmail.com>

Hi Guys,

I'm trying to get our code running on an arago kernel from the 2.6.18 
Montavista kernel.

We're running a DM365, and an MPEG2 Codec, but the same occurs with the 
H264 codec too.

With CE_TRACE turned on shows the following:

 ENCODE: Ch 0 InBuf 0 OutBuf 0
 ENCODE: pOutBuf->virtAddr 0x46150000
@0x01365d41:[T:0x451aa490] ti.sdo.ce.video1.VIDENC1 - VIDENC1_process> 
Enter (handle=0x29ddb0, inBufs=0x451a9be8, outBufs=0x451a9d4c, 
inArgs=0x451a9d40, outArgs=0x451a9cb8)
@0x01365fb1:[T:0x451aa490] CV - VISA_enter(visa=0x29ddb0): algHandle = 
0x29dde8
@0x01366127:[T:0x451aa490] ti.sdo.ce.alg.Algorithm - Algorithm_activate> 
Enter(alg=0x29dde8)
@0x0136627c:[T:0x451aa490] ti.sdo.ce.osal.SemMP - Entered SemMP_pend> 
sem[0x29d338] timeout[0xffffffff]
@0x013664aa:[T:0x451aa490] ti.sdo.ce.osal.SemMP - Leaving SemMP_pend> 
sem[0x29d338] status[0]
@0x013666e7:[T:0x451aa490] ti.sdo.ce.alg.Algorithm - Algorithm_activate> 
Exit

So I can see that the thread enters the VISA VIDENC1_process call into 
the MPEG2 codec, but never exits.

I've traced this down and can see that it is waiting on an interrupt 
from the co-processor

MPEG2 Encode :
#0  0x4062e27c in ioctl () from /lib/libc.so.6
#1  0x000e7314 in VICP_wait ()
#2  0x000e332c in HDVICPSYNC_wait ()
#3  0x000ddf44 in MPEG2VENC_TI_Encode ()
#4  0x0007c91c in VIDENC1_process ()

I traced this down as Interrupt 10 - and I have verified that the 
interrupt is both enabled - and muxed correctly.

However the interrupt never arrives - - and we're always waiting on 
VICP_wait. :(

Can anyone suggest any reasons why the codec would not be starting on 
the new kernel ?
Would the memory maps of shared DTCM be different and prevent the 
co-processor loading?

Would there be any other muxings that might prevent the co-processor 
running?

I'm stuck - and can't get it to run - so just hoping someone might have 
some ideas !
I don't think there's any way I can debug the state of the codec further 
than the CE_TRACE - so I can't tell why the codec isn't running or 
what's wrong with it.

Regards
Kieran

From nsekhar at ti.com  Tue May  4 05:31:39 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Tue, 4 May 2010 16:01:39 +0530
Subject: [PATCH 3/5] davinci: edma: fix coding style issues related to
	indentation
In-Reply-To: <4BDFE869.8020705@mvista.com>
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
	<1272962499-18932-3-git-send-email-nsekhar@ti.com>
	<1272962499-18932-4-git-send-email-nsekhar@ti.com>
	<4BDFE869.8020705@mvista.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6CC3967@dbde02.ent.ti.com>

Hello,

On Tue, May 04, 2010 at 14:57:05, Sergei Shtylyov wrote:
> Hello.
>
> Sekhar Nori wrote:
> > In the edma driver some if statememnts are broken up such that
> > the condition code is at the same indentation level as the
> > statement block. This makes reading it particularly difficult.
> >
> > This patch fixes that issue.
> >
> > Signed-off-by: Sekhar Nori <nsekhar at ti.com>
> > ---
> >  arch/arm/mach-davinci/dma.c |   26 +++++++++++++-------------
> >  1 files changed, 13 insertions(+), 13 deletions(-)
> >
> > diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
> > index cc5fcda..2734de9 100644
> > --- a/arch/arm/mach-davinci/dma.c
> > +++ b/arch/arm/mach-davinci/dma.c
> > @@ -352,7 +352,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
> >     dev_dbg(data, "dma_irq_handler\n");
> >
> >     if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
> > -       && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
> >
>
>    IMHO this level of indentation doesn't affect the readability.

The original code was indented using spaces so the level of
indentation can change depending on your tabstop setting.

>
> > +                   && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
> >             return IRQ_NONE;
> >
> >     while (1) {
> > @@ -406,9 +406,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
> >     dev_dbg(data, "dma_ccerr_handler\n");
> >
> >     if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
> > -       (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
> > -       (edma_read(ctlr, EDMA_QEMR) == 0) &&
> > -       (edma_read(ctlr, EDMA_CCERR) == 0))
> >
>
>    What's up with these too?
>
> > +                   (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
> > +                   (edma_read(ctlr, EDMA_QEMR) == 0) &&
> > +                   (edma_read(ctlr, EDMA_CCERR) == 0))
> >
>
>    Your increased indentation looks rather ugly to me... matter of
> taste, of course.

Same here, spaces were being used for indentation. I realize
now I should have rather stated this issue in patch description.

Also, broken condition expressions at the same indentation level
as the actual statement are tough to read. Hence the increased
indentation.

>
> > @@ -469,9 +469,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
> >                     }
> >             }
> >             if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
> > -               && (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
> > -               && (edma_read(ctlr, EDMA_QEMR) == 0)
> > -               && (edma_read(ctlr, EDMA_CCERR) == 0))
> >
>
>    Again, I don't find anything bad about this, except I'd put && at the
> end of lines, no at the start...

Spaces at play again. I agree on the && part. But that's
out of scope for $SUBJECT.

Thanks,
Sekhar

From nsekhar at ti.com  Tue May  4 05:41:37 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Tue, 4 May 2010 16:11:37 +0530
Subject: Codec Stalled on DM365 2.6.32 Kernel
In-Reply-To: <4BDFF1AE.7070103@gmail.com>
References: <4BDFF1AE.7070103@gmail.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6CC39D5@dbde02.ent.ti.com>


Hi Kieran,

On Tue, May 04, 2010 at 15:36:38, Kieran Bingham wrote:
> Hi Guys,
>
> I'm trying to get our code running on an arago kernel from the 2.6.18
> Montavista kernel.
>
> We're running a DM365, and an MPEG2 Codec, but the same occurs with the
> H264 codec too.

There is a DVSDK available built on the arago kernel:

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/dvsdk/DVSDK_3_10/latest/index_FDS.html

You could start here instead of starting from ground up.

You can get help regarding the DVSDK from e2e.ti.com

Thanks,
Sekhar


From swami.iyer at ti.com  Tue May  4 05:49:54 2010
From: swami.iyer at ti.com (Subbrathnam, Swaminathan)
Date: Tue, 4 May 2010 16:19:54 +0530
Subject: Bluetooth on Davinci DM355
In-Reply-To: <u2k65b6d8ff1004280449ja71e2bb8o20e522c340d35378@mail.gmail.com>
References: <u2k65b6d8ff1004280449ja71e2bb8o20e522c340d35378@mail.gmail.com>
Message-ID: <FCCFB4CDC6E5564B9182F639FC3560870304F5AA44@dbde02.ent.ti.com>

Kapil,
            Would you try the same scenario on Davinci Staging Git tree

Regards
swami

________________________________
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Kapil Pendse
Sent: Wednesday, April 28, 2010 5:20 PM
To: davinci-linux-open-source at linux.davincidsp.com
Subject: Bluetooth on Davinci DM355


Hello,

I've been trying to get Bluetooth to work with DM355 based board. My kernel is 2.6.10 with patchset PSP 01.20.01.004.

I've compiled BlueZ packages "bluez-libs-2.10" and "bluez-utils-2.10" for the DaVinci. I know this is a very old version of BlueZ, but someone had recommended this one as it doesn't depend on the D-Bus package.

So with this setup, when I connect my old Bluetooth USB dongle to the DM355 board (note that it is not the EVM), the device gets detected as a full speed (12Mbps) USB device, and HCI interface is set up for it as hci0.

root at 192.168.0.4:~# lsusb
Bus 001 Device 013: ID 0a12:0001 Cambridge Silicon Radio, Ltd Bluetooth Dongle
Bus 001 Device 001: ID 04d6:0000 Mentor Graphics

root at 192.168.0.4:~# hciconfig -a
hci0:   Type: USB
        BD Address: 00:10:60:AB:D0:5C ACL MTU: 192:8  SCO MTU: 64:8
        UP RUNNING PSCAN ISCAN
        RX bytes:105 acl:0 sco:0 events:10 errors:0
        TX bytes:42 acl:0 sco:0 commands:10 errors:0
        Features: 0xff 0xff 0x0f 0x00 0x00 0x00 0x00 0x00
        Packet type: DM1 DM3 DM5 DH1 DH3 DH5 HV1 HV2 HV3
        Link policy:
        Link mode: SLAVE ACCEPT
        Name: ''
Can't read class of device on hci0. Connection timed out(110)

But when I try to scan for remote BT devices, I get timeout error like below:

root at 192.168.0.4:~# hcitool scan
Scanning ...
hci_cmd_task: hci0 command tx timeout
hci_usb_rx_complete: hci0 corrupted packet: type 4 count 16

I do remember that the scan DID WORK one or two times. It did manage to detect my cellphone's BT. But that's about it, so I'd say that it is unable to scan for devices 99% of the time.

I've tested this BT dongle on my LinuxMint based host PC, it works fine. So although very old, the BT dongle is just fine. Looks like I need to fix something in the BlueZ kernel modules or userspace libraries.

Could someone help me figure out what is wrong and what would be the way to fix this?

Thanks and best regards,

Kapil

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From surfinbum at mac.com  Tue May  4 07:33:50 2010
From: surfinbum at mac.com (Chris Jackson)
Date: Tue, 04 May 2010 08:33:50 -0400
Subject: can't detect video input
In-Reply-To: <001001caeb55$9484d040$bd8e70c0$%jain@mavensystems.com>
References: <91267469800027024439265370340605739929-Webmail@me.com>
	<70E876B0EA86DD4BAF101844BC814DFE08DE6D0DFB@Cloud.RL.local>
	<001001caeb55$9484d040$bd8e70c0$%jain@mavensystems.com>
Message-ID: <1272976430.13042.17.camel@JaxTechIPL>

thank you suhas, 

I am familiar with that document, and I've worked through it
successfully.

But after changing the bootargs in section 4.3.7, and saveenv
overwriting the original bootargs, I haven't been able to run the encode
demo when booting from the NAND.

I think the problem is where I have changed the video bootargs in 4.3.7,
but I can't find anywhere the default. out of box settings that I can
revert too.  I should have saved that info before overwriting.  

I have successfully run the encode demo before setting up the board to
NFS mount, and now I just want to do that again but I cant seem to get
the board to take video input.  

any ideas???  I still get the following error msg when i run the encode
demo from the command line:

Encode demo started.
Error: Failed to detect video standard, video input
connected?6/data/videos/demo.
Error: Failed to create video encoder: mpeg4enc


thank you, 

Chris Jackson




On Tue, 2010-05-04 at 12:16 +0530, Suhas Jain wrote:
> Hi Chris,
> 
> You can find the complete setup for DM6446 EVM board at following link.
> 
> http://focus.ti.com/lit/ug/sprue66e/sprue66e.pdf
> 
> Regards,
> Suhas Jain
> 
> -----Original Message-----
> From: davinci-linux-open-source-bounces at linux.davincidsp.com
> [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of
> Jon Povey
> Sent: 04 May 2010 07:02
> To: Chris; davinci-linux-open-source at linux.davincidsp.com
> Subject: RE: can't detect video input
> 
> Chris wrote:
> > I want to revert to the default bootargs that ship with the board,
> > but I can't find that info anywhere, and I've written over the NAND
> > with new bootargs for the NFS mount.  Does anybody know what the
> > default bootarg string is?
> 
> With DM355 EVM, I think that info was printed in the getting started or
> technical reference dead tree guides that came with the EVM. Not sure about
> 6446. Hope that helps or someone else answers..
> 
> --
> Jon Povey
> jon.povey at racelogic.co.uk
> 
> Racelogic is a limited company registered in England. Registered number
> 2743719 .
> Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham,
> Bucks, MK18 1TB .
> 
> The information contained in this electronic mail transmission is intended
> by Racelogic Ltd for the use of the named individual or entity to which it
> is directed and may contain information that is confidential or privileged.
> If you have received this electronic mail transmission in error, please
> delete it from your system without copying or forwarding it, and notify the
> sender of the error by reply email so that the sender's address records can
> be corrected. The views expressed by the sender of this communication do not
> necessarily represent those of Racelogic Ltd. Please note that Racelogic
> reserves the right to monitor e-mail communications passing through its
> network
> 
> 
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> 



From vaibhav.bedia at ti.com  Tue May  4 07:38:05 2010
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Tue, 4 May 2010 18:08:05 +0530
Subject: DM6467 McASP
In-Reply-To: <FCCFB4CDC6E5564B9182F639FC3560870304F5A8EE@dbde02.ent.ti.com>
References: <FCCFB4CDC6E5564B9182F639FC3560870304F5A8EE@dbde02.ent.ti.com>
Message-ID: <FCCFB4CDC6E5564B9182F639FC3560870304F5AB16@dbde02.ent.ti.com>

Jayakrishnan,

The McASP transmit bit clock, ACLKX can be either externally sourced or internally generated. 

In case ALCLKX is internally generated from AUXCLK, then you have the option of sending the intermediate high frequency master clock (AHCLKX) to the AHCLKX pin to be used by other devices in the system. In such a situation you don't need to use the 2nd McASP just for generating AHCLKX.

However, if your use-case needs two McASPs that can also be done as both can be used simultaneously.

Regards,
Vaibhav

-----Original Message-----
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Jaya krishnan
Sent: Tuesday, May 04, 2010 1:44 PM
To: davinci-linux-open-source at linux.davincidsp.com
Subject: DM6467 McASP


Hi  ,
I want  to use McASP  port  0 for  transmit data  and port 1  to  generate high frequency clock (AHCLKX) (to be used as  master clock for  another audio DAC  in the  system.)  Is there  any  limitation to use  both  ports  simultaneously?Pls  reply
Regards
JK

 
    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  
_______________________________________________
Davinci-linux-open-source mailing list
Davinci-linux-open-source at linux.davincidsp.com
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source

From kieranbingham at gmail.com  Tue May  4 08:16:48 2010
From: kieranbingham at gmail.com (Kieran Bingham)
Date: Tue, 4 May 2010 14:16:48 +0100
Subject: cppi_dma.c : channel_abort
In-Reply-To: <4BD6DFF4.8020108@mvista.com>
References: <4BD6CA46.7020605@gmail.com> <4BD6DFF4.8020108@mvista.com>
Message-ID: <m2p82bcfa4d1005040616i8609e8f5j70717bc81268f8c6@mail.gmail.com>

Thanks Sergei,

I'm trying to move to the later kernel to see if we can get things
running there - then that patch should be included and also better SD
card performance :)

Not getting very far with it as the Codec's won't encode :( so I may
look to merge those patches into our older kernel.

Thanks for the heads up :)

Regards
 Kieran

On 27 April 2010 14:00, Sergei Shtylyov <sshtylyov at mvista.com> wrote:
> Hello.
>
> Kieran Bingham wrote:
>
>> We're running a DM365, with Montavista 2.6.18_pro500 kernel.
>>
>> With a USB Flash drive, and a USB Connected DVD Drive, we're experiencing
>> kernel lockups
>>
>> Having connected the JTAG, and stepping through the assembly, it would
>> appear that it is cycling through one of the two while loops in the function
>> channel_abort, in drivers/usb/musb/cppi_dma.c
>>
>> Unfortunately its doing this with interrupts off!! and it never leaves!
>>
>> Has anyone else experienced Kernel Lockups with USB devices connected ?
>
> ?See if the following patch can fix it for you:
>
> http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=patch;h=565969237ab6e73ce7192684d00d5b890ee308fa
>
> WBR, Sergei
>
>

From idriss.ghodhbane at gmail.com  Tue May  4 09:01:19 2010
From: idriss.ghodhbane at gmail.com (Idriss Ghodhbane)
Date: Tue, 4 May 2010 16:01:19 +0200
Subject: DM355+MSP430+push buttons
Message-ID: <p2g90d17c5d1005040701p627d41ddmb39b63a14f81ec97@mail.gmail.com>

Hi everybody,

I am stuck at the level of controlling the push buttons of my EVM DM355
(SW10/11/12/13/14).
After searching on the net, I had discovered that I haven't the nexassary
libraries for the microcontroller MSP430 neither integrated in my
DVSDK_2_00_00_22 nor in the LSP "linux-2.6.18_pro500" which is the kernel.
Have you a solution for this issue?
Big thanks

Best Regards
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From surfinbum at mac.com  Tue May  4 09:08:19 2010
From: surfinbum at mac.com (Chris Jackson)
Date: Tue, 04 May 2010 10:08:19 -0400
Subject: can't detect video input
In-Reply-To: <001001caeb55$9484d040$bd8e70c0$%jain@mavensystems.com>
References: <91267469800027024439265370340605739929-Webmail@me.com>
	<70E876B0EA86DD4BAF101844BC814DFE08DE6D0DFB@Cloud.RL.local>
	<001001caeb55$9484d040$bd8e70c0$%jain@mavensystems.com>
Message-ID: <1272982099.13042.19.camel@JaxTechIPL>

thanks for the help all.  the camera that shipped with the board is
defective, therein lies the problem!

chris

On Tue, 2010-05-04 at 12:16 +0530, Suhas Jain wrote:
> Hi Chris,
> 
> You can find the complete setup for DM6446 EVM board at following link.
> 
> http://focus.ti.com/lit/ug/sprue66e/sprue66e.pdf
> 
> Regards,
> Suhas Jain
> 
> -----Original Message-----
> From: davinci-linux-open-source-bounces at linux.davincidsp.com
> [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of
> Jon Povey
> Sent: 04 May 2010 07:02
> To: Chris; davinci-linux-open-source at linux.davincidsp.com
> Subject: RE: can't detect video input
> 
> Chris wrote:
> > I want to revert to the default bootargs that ship with the board,
> > but I can't find that info anywhere, and I've written over the NAND
> > with new bootargs for the NFS mount.  Does anybody know what the
> > default bootarg string is?
> 
> With DM355 EVM, I think that info was printed in the getting started or
> technical reference dead tree guides that came with the EVM. Not sure about
> 6446. Hope that helps or someone else answers..
> 
> --
> Jon Povey
> jon.povey at racelogic.co.uk
> 
> Racelogic is a limited company registered in England. Registered number
> 2743719 .
> Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham,
> Bucks, MK18 1TB .
> 
> The information contained in this electronic mail transmission is intended
> by Racelogic Ltd for the use of the named individual or entity to which it
> is directed and may contain information that is confidential or privileged.
> If you have received this electronic mail transmission in error, please
> delete it from your system without copying or forwarding it, and notify the
> sender of the error by reply email so that the sender's address records can
> be corrected. The views expressed by the sender of this communication do not
> necessarily represent those of Racelogic Ltd. Please note that Racelogic
> reserves the right to monitor e-mail communications passing through its
> network
> 
> 
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> 



From alagusankar at embwise.com  Tue May  4 09:31:12 2010
From: alagusankar at embwise.com (Alagu Sankar)
Date: Tue,  4 May 2010 20:01:12 +0530
Subject: [PATCH 1/1] Davinci SDIO Support
Message-ID: <1272983472-22219-1-git-send-email-alagusankar@embwise.com>

Added SDIO Support for Davinci.  Tested on DM355 EVM with Marvell SD8385 and
SD8686 cards using Libertas SDIO driver. This requires additional patches for
Libertas SDIO interface as indicated in the linux-wireless mailing list and
as referenced in the following links

http://marc.info/?l=linux-wireless&m=127136330220026&w=2
http://marc.info/?l=linux-wireless&m=127136362020814&w=2

Signed-off-by: Alagu Sankar <alagusankar at embwise.com>
---
 drivers/mmc/host/davinci_mmc.c |   98 +++++++++++++++++++++++++++++++++++++--
 1 files changed, 93 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
index e4d1591..4afa6bf 100644
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -66,8 +66,8 @@
 #define DAVINCI_MMCBLNC      0x60
 #define DAVINCI_SDIOCTL      0x64
 #define DAVINCI_SDIOST0      0x68
-#define DAVINCI_SDIOEN       0x6C
-#define DAVINCI_SDIOST       0x70
+#define DAVINCI_SDIOIEN      0x6C
+#define DAVINCI_SDIOIST      0x70
 #define DAVINCI_MMCFIFOCTL   0x74 /* FIFO Control Register             */
 
 /* DAVINCI_MMCCTL definitions */
@@ -135,6 +135,23 @@
 /* MMCSD Init clock in Hz in opendrain mode */
 #define MMCSD_INIT_CLOCK		200000
 
+/* DAVINCI_SDIOCTL definitions */
+#define SDIOCTL_RDWTRQ_SET    BIT(0)
+#define SDIOCTL_RDWTCR_SET    BIT(1)
+
+/* DAVINCI_SDIOST0 definitions */
+#define SDIOST0_DAT1_HI       BIT(0)
+#define SDIOST0_INTPRD        BIT(1)
+#define SDIOST0_RDWTST        BIT(2)
+
+/* DAVINCI_SDIOIEN definitions */
+#define SDIOIEN_IOINTEN       BIT(0)
+#define SDIOIEN_RWSEN         BIT(1)
+
+/* DAVINCI_SDIOIST definitions */
+#define SDIOIST_IOINT         BIT(0)
+#define SDIOIST_RWS           BIT(1)
+
 /*
  * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units,
  * and we handle up to MAX_NR_SG segments.  MMC_BLOCK_BOUNCE kicks in only
@@ -147,6 +164,8 @@
 
 #define MAX_NR_SG	16
 
+#define DAVINCI_SDIO_IRQ(dev_id)	(((dev_id) == 0) ? "sdio0" : "sdio1")
+
 static unsigned rw_threshold = 32;
 module_param(rw_threshold, uint, S_IRUGO);
 MODULE_PARM_DESC(rw_threshold,
@@ -164,7 +183,7 @@ struct mmc_davinci_host {
 	unsigned int mmc_input_clk;
 	void __iomem *base;
 	struct resource *mem_res;
-	int irq;
+	int mmc_irq, sdio_irq;
 	unsigned char bus_mode;
 
 #define DAVINCI_MMC_DATADIR_NONE	0
@@ -184,6 +203,7 @@ struct mmc_davinci_host {
 	u32 rxdma, txdma;
 	bool use_dma;
 	bool do_dma;
+	bool sdio_int;
 
 	/* Scatterlist DMA uses one or more parameter RAM entries:
 	 * the main one (associated with rxdma or txdma) plus zero or
@@ -866,6 +886,19 @@ mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data)
 {
 	host->data = NULL;
 
+	if (host->mmc->caps & MMC_CAP_SDIO_IRQ) {
+		/* SDIO Interrupt Detection work-around as suggested by
+		 * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata
+		 * 2.1.5)
+		 * Signal SDIO interrupt only if it is enabled by core
+		 */
+		if (host->sdio_int && (!((readl(host->base + DAVINCI_SDIOST0))
+					& SDIOST0_DAT1_HI))) {
+			writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
+			mmc_signal_sdio_irq(host->mmc);
+		}
+	}
+
 	if (host->do_dma) {
 		davinci_abort_dma(host);
 
@@ -932,6 +965,22 @@ davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data)
 	mmc_davinci_reset_ctrl(host, 0);
 }
 
+static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id)
+{
+	struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
+	unsigned int status;
+
+	status = readl(host->base + DAVINCI_SDIOIST);
+	if (status & SDIOIST_IOINT) {
+		dev_dbg(mmc_dev(host->mmc),
+				"SDIO interrupt status %x\n", status);
+		writel(status | SDIOIST_IOINT,
+				host->base + DAVINCI_SDIOIST);
+		mmc_signal_sdio_irq(host->mmc);
+	}
+	return IRQ_HANDLED;
+}
+
 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id)
 {
 	struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
@@ -1076,11 +1125,34 @@ static int mmc_davinci_get_ro(struct mmc_host *mmc)
 	return config->get_ro(pdev->id);
 }
 
+static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+	struct mmc_davinci_host *host = mmc_priv(mmc);
+
+	if (enable) {
+		if (!((readl(host->base + DAVINCI_SDIOST0))
+					& SDIOST0_DAT1_HI)) {
+			writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
+			mmc_signal_sdio_irq(host->mmc);
+		} else {
+			host->sdio_int = 1;
+			writel(readl(host->base + DAVINCI_SDIOIEN) |
+				SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN);
+		}
+	} else {
+		host->sdio_int = 0;
+		writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN,
+				host->base + DAVINCI_SDIOIEN);
+	}
+
+}
+
 static struct mmc_host_ops mmc_davinci_ops = {
 	.request	= mmc_davinci_request,
 	.set_ios	= mmc_davinci_set_ios,
 	.get_cd		= mmc_davinci_get_cd,
 	.get_ro		= mmc_davinci_get_ro,
+	.enable_sdio_irq = mmc_davinci_enable_sdio_irq,
 };
 
 /*----------------------------------------------------------------------*/
@@ -1209,7 +1281,8 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev)
 		host->nr_sg = MAX_NR_SG;
 
 	host->use_dma = use_dma;
-	host->irq = irq;
+	host->mmc_irq = irq;
+	host->sdio_irq = platform_get_irq(pdev, 1);
 
 	if (host->use_dma && davinci_acquire_dma_channels(host) != 0)
 		host->use_dma = 0;
@@ -1272,6 +1345,19 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev)
 	if (ret)
 		goto out;
 
+	/* Failures in SDIO IRQ registration are ignored as the driver
+	 * can still work in polled mode.
+	 */
+	if (host->sdio_irq != NO_IRQ) {
+		ret = request_irq(host->sdio_irq,
+				mmc_davinci_sdio_irq, 0,
+				DAVINCI_SDIO_IRQ(pdev->id), host);
+		if (ret == 0) {
+			mmc->caps |= MMC_CAP_SDIO_IRQ;
+			host->sdio_int = 0;
+		}
+	}
+
 	rename_region(mem, mmc_hostname(mmc));
 
 	dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n",
@@ -1315,7 +1401,9 @@ static int __exit davinci_mmcsd_remove(struct platform_device *pdev)
 		mmc_davinci_cpufreq_deregister(host);
 
 		mmc_remove_host(host->mmc);
-		free_irq(host->irq, host);
+		free_irq(host->mmc_irq, host);
+		if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
+			free_irq(host->sdio_irq, host);
 
 		davinci_release_dma_channels(host);
 
-- 
1.6.0.6


From nyhetsbrev at dokumera.anp.se  Tue May  4 09:53:47 2010
From: nyhetsbrev at dokumera.anp.se (=?UTF-8?Q?DokuMera_Nyhetsbrev?=)
Date: Tue, 4 May 2010 16:53:47 +0200
Subject: =?UTF-8?Q?Din_prenumeration_=C3=A4r_avslutad?=
Message-ID: <165760-22010524145347845@dokumera.anp.se>

Du har valt att avprenumerera p? DokuMera Nyhetsbrev till adressen davinci-linux-open-source at linux.davincidsp.com
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From thomas.koeller at baslerweb.com  Tue May  4 12:18:20 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Tue,  4 May 2010 19:18:20 +0200
Subject: [PATCH 0/4] DM365 patches
Message-ID: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

This is an updated patch series for DM365. Patches 0 and 1
are reworked versions of patches submitted earlier, 2 and 3
are new.

Thomas Koeller (4):
  DM365: Make all SPI units SPI0..SPI4 available
  DM365: Add platform resource management
  DAVINCI: Added missing includes
  DM365: Added PINMUX definitions for GPIO30..32

 arch/arm/mach-davinci/Makefile              |   10 +-
 arch/arm/mach-davinci/board-dm365-evm.c     |   47 +++-
 arch/arm/mach-davinci/devices.c             |  108 ++++++---
 arch/arm/mach-davinci/dm365.c               |  216 +++++++++--------
 arch/arm/mach-davinci/dm365_spi.c           |  338 +++++++++++++++++++++++++++
 arch/arm/mach-davinci/dma.c                 |    8 -
 arch/arm/mach-davinci/include/mach/common.h |    3 +
 arch/arm/mach-davinci/include/mach/dm365.h  |    5 +-
 arch/arm/mach-davinci/include/mach/mux.h    |    3 +
 arch/arm/mach-davinci/platform-resources.c  |   90 +++++++
 arch/arm/mach-davinci/platform-resources.h  |   30 +++
 arch/arm/mach-davinci/spi.h                 |   35 +++
 drivers/i2c/busses/i2c-davinci.c            |    9 +-
 drivers/mmc/host/davinci_mmc.c              |    4 +-
 drivers/spi/davinci_spi.c                   |   16 +-
 drivers/watchdog/davinci_wdt.c              |   15 --
 16 files changed, 740 insertions(+), 197 deletions(-)
 create mode 100644 arch/arm/mach-davinci/dm365_spi.c
 create mode 100644 arch/arm/mach-davinci/platform-resources.c
 create mode 100644 arch/arm/mach-davinci/platform-resources.h
 create mode 100644 arch/arm/mach-davinci/spi.h


From thomas.koeller at baslerweb.com  Tue May  4 12:18:21 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Tue,  4 May 2010 19:18:21 +0200
Subject: [PATCH 1/4] DM365: Make all SPI units SPI0..SPI4 available
In-Reply-To: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
References: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <1272993504-1189-2-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

Change the SPI setup code to allow use of all SPI units. Also,
move some resource assignments (DMA channels, interrupts)
to the board code, where they belong. These really should not
be hard-coded in dm365.c.

The spi setup stuff has been moved to a separate file
'arch/arm/mach-davinci/dm365_spi.c' to increase modularity.
I am not currently able to address the DM355, but it should be
easy to write a dm355_spi.c file.

Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
---
 arch/arm/mach-davinci/Makefile             |    2 +-
 arch/arm/mach-davinci/board-dm365-evm.c    |   47 ++++-
 arch/arm/mach-davinci/dm365.c              |   68 -------
 arch/arm/mach-davinci/dm365_spi.c          |  276 ++++++++++++++++++++++++++++
 arch/arm/mach-davinci/include/mach/dm365.h |    5 +-
 arch/arm/mach-davinci/spi.h                |   35 ++++
 6 files changed, 350 insertions(+), 83 deletions(-)
 create mode 100644 arch/arm/mach-davinci/dm365_spi.c
 create mode 100644 arch/arm/mach-davinci/spi.h

diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index f6c7e4c..b9c497c 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -32,6 +32,6 @@ obj-$(CONFIG_MACH_SFFSDR)		+= board-sffsdr.o
 obj-$(CONFIG_MACH_DAVINCI_DM355_EVM)	+= board-dm355-evm.o
 obj-$(CONFIG_MACH_DM355_LEOPARD)	+= board-dm355-leopard.o
 obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)	+= board-dm646x-evm.o cdce949.o
-obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)	+= board-dm365-evm.o
+obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)	+= board-dm365-evm.o dm365_spi.o
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)	+= board-da830-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= board-da850-evm.o
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index ab3b0e2..96dd72f 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -49,6 +49,8 @@
 #include <media/tvp7002.h>
 #include <media/davinci/videohd.h>
 
+#include "spi.h"
+
 
 
 /* have_imager() - Check if we have support for imager interface */
@@ -337,18 +339,18 @@ static struct i2c_driver pca9543a_driver = {
 static void dm365evm_reset_imager(int rst)
 {
 	u8 val;
-	
+
 	/* Reset bit6 of CPLD_IMG_DIR2 */
 	val = __raw_readb(cpld + CPLD_IMG_DIR2) & ~BIT(6);
-	__raw_writeb(val, (cpld + CPLD_IMG_DIR2));	
+	__raw_writeb(val, (cpld + CPLD_IMG_DIR2));
 
 	/* Set bit5 of CPLD_IMG_MUX5 */
 	val = __raw_readb(cpld + CPLD_IMG_MUX5) | BIT(5);
-	__raw_writeb(val, (cpld + CPLD_IMG_MUX5));	
+	__raw_writeb(val, (cpld + CPLD_IMG_MUX5));
 
 	/* Reset bit 0 of CPLD_IMG_MUX5 */
 	val = __raw_readb(cpld + CPLD_IMG_MUX5) & ~BIT(0);
-	__raw_writeb(val, (cpld + CPLD_IMG_MUX5));	
+	__raw_writeb(val, (cpld + CPLD_IMG_MUX5));
 
 	/**
 	 * Configure GPIO40 to be output and high. This has dependency on MMC1
@@ -375,7 +377,7 @@ static int dm365evm_enable_pca9543a(int en)
 			.buf = &val,
 		};
 
-	printk("dm365evm_enable_pca9543a\n");	
+	printk("dm365evm_enable_pca9543a\n");
 	if (!en)
 		val = 0;
 
@@ -385,7 +387,7 @@ static int dm365evm_enable_pca9543a(int en)
 	msg.addr = pca9543a->addr;
 	/* turn i2c switch, pca9543a, on/off */
 	status = i2c_transfer(pca9543a->adapter, &msg, 1);
-	printk("dm365evm_enable_pca9543a, status = %d\n", status);	
+	printk("dm365evm_enable_pca9543a, status = %d\n", status);
 	return status;
 	return 0;
 }
@@ -832,7 +834,7 @@ static struct spi_eeprom at25640 = {
 	.flags		= EE_ADDR2,
 };
 
-static struct spi_board_info dm365_evm_spi_info[] __initconst = {
+static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
 	{
 		.modalias	= "at25",
 		.platform_data	= &at25640,
@@ -840,9 +842,32 @@ static struct spi_board_info dm365_evm_spi_info[] __initconst = {
 		.bus_num	= 0,
 		.chip_select	= 0,
 		.mode		= SPI_MODE_0,
-	},
+	}
+};
+
+static struct davinci_spi_unit_desc dm365_evm_spi_udesc_at25 = {
+	.spi_hwunit	= 0,
+	.chipsel	= BIT(0),
+	.irq		= IRQ_DM365_SPIINT0_0,
+	.dma_tx_chan	= 16,
+	.dma_rx_chan	= 17,
+	.dma_evtq	= EVENTQ_3,
+	.pdata		= {
+		.version 	= SPI_VERSION_1,
+		.num_chipselect = 2,
+		.clk_internal	= 1,
+		.cs_hold	= 1,
+		.intr_level	= 0,
+		.poll_mode	= 1,	/* 0 -> interrupt mode 1-> polling mode */
+		.use_dma	= 1,	/* when 1, value in poll_mode is ignored */
+		.c2tdelay	= 0,
+		.t2cdelay	= 0
+	}
 };
 
+
+
+
 static __init void dm365_evm_init(void)
 {
 	evm_init_i2c();
@@ -861,8 +886,10 @@ static __init void dm365_evm_init(void)
 	dm365_init_rtc();
 	dm365_init_ks(&dm365evm_ks_data);
 
-	dm365_init_spi0(BIT(0), dm365_evm_spi_info,
-			ARRAY_SIZE(dm365_evm_spi_info));
+	davinci_init_spi(&dm365_evm_spi_udesc_at25,
+			 ARRAY_SIZE(dm365_evm_spi_info),
+			 dm365_evm_spi_info);
+	return;
 }
 
 static __init void dm365_evm_irq_init(void)
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index ed6c9c7..30c2327 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -616,74 +616,6 @@ EVT_CFG(DM365,	EVT3_ASP_RX,         1,     1,    0,     false)
 #endif
 };
 
-static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
-
-static struct davinci_spi_platform_data dm365_spi0_pdata = {
-	.version 	= SPI_VERSION_1,
-	.num_chipselect = 2,
-	.clk_internal	= 1,
-	.cs_hold	= 1,
-	.intr_level	= 0,
-	.poll_mode	= 1,	/* 0 -> interrupt mode 1-> polling mode */
-	.use_dma	= 1,	/* when 1, value in poll_mode is ignored */
-	.c2tdelay	= 0,
-	.t2cdelay	= 0,
-};
-
-static struct resource dm365_spi0_resources[] = {
-	{
-		.start = 0x01c66000,
-		.end   = 0x01c667ff,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_DM365_SPIINT0_0,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = 17,
-		.flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
-	},
-	{
-		.start = 16,
-		.flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
-	},
-	{
-		.start = EVENTQ_3,
-		.flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
-	},
-};
-
-static struct platform_device dm365_spi0_device = {
-	.name = "spi_davinci",
-	.id = 0,
-	.dev = {
-		.dma_mask = &dm365_spi0_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-		.platform_data = &dm365_spi0_pdata,
-	},
-	.num_resources = ARRAY_SIZE(dm365_spi0_resources),
-	.resource = dm365_spi0_resources,
-};
-
-void __init dm365_init_spi0(unsigned chipselect_mask,
-		struct spi_board_info *info, unsigned len)
-{
-	davinci_cfg_reg(DM365_SPI0_SCLK);
-	davinci_cfg_reg(DM365_SPI0_SDI);
-	davinci_cfg_reg(DM365_SPI0_SDO);
-
-	/* not all slaves will be wired up */
-	if (chipselect_mask & BIT(0))
-		davinci_cfg_reg(DM365_SPI0_SDENA0);
-	if (chipselect_mask & BIT(1))
-		davinci_cfg_reg(DM365_SPI0_SDENA1);
-
-	spi_register_board_info(info, len);
-
-	platform_device_register(&dm365_spi0_device);
-}
-
 
 /* IPIPEIF device configuration */
 static u64 dm365_ipipeif_dma_mask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-davinci/dm365_spi.c b/arch/arm/mach-davinci/dm365_spi.c
new file mode 100644
index 0000000..e1743d7
--- /dev/null
+++ b/arch/arm/mach-davinci/dm365_spi.c
@@ -0,0 +1,276 @@
+/*
+ * TI DaVinci DM3xx SPI setup
+ *
+ * Copyright (C) 2010 Basler Vision Technologies AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/ioport.h>
+#include <linux/spi/spi.h>
+#include <mach/mux.h>
+
+#include "spi.h"
+
+static u64 davinci_spi_dma_mask = DMA_BIT_MASK(32);
+
+enum davinci_spi_resource_index {
+	spirsrc_iomem,
+	spirsrc_irq,
+	spirsrc_rxdma,
+	spirsrc_txdma,
+	spirsrc_evqdma
+};
+
+
+static struct resource davinci_spi_resources[spirsrc_evqdma + 1][5] = {
+	{
+		[spirsrc_iomem] = {
+			.start	= 0x01c66000,
+			.end	= 0x01c667ff,
+			.flags	= IORESOURCE_MEM,
+		},
+		[spirsrc_irq] = {
+			.flags	= IORESOURCE_IRQ,
+		},
+		[spirsrc_rxdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
+		},
+		[spirsrc_txdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
+		},
+		[spirsrc_evqdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
+		}
+	},
+	{
+		[spirsrc_iomem] = {
+			.start	= 0x01c66800,
+			.end	= 0x01c66fff,
+			.flags	= IORESOURCE_MEM,
+		},
+		[spirsrc_irq] = {
+			.flags	= IORESOURCE_IRQ,
+		},
+		[spirsrc_rxdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
+		},
+		[spirsrc_txdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
+		},
+		[spirsrc_evqdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
+		}
+	},
+	{
+		[spirsrc_iomem] = {
+			.start	= 0x01c67800,
+			.end	= 0x01c67fff,
+			.flags	= IORESOURCE_MEM,
+		},
+		[spirsrc_irq] = {
+			.flags	= IORESOURCE_IRQ,
+		},
+		[spirsrc_rxdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
+		},
+		[spirsrc_txdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
+		},
+		[spirsrc_evqdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
+		}
+	},
+	{
+		[spirsrc_iomem] = {
+			.start	= 0x01c68000,
+			.end	= 0x01c687ff,
+			.flags	= IORESOURCE_MEM,
+		},
+		[spirsrc_irq] = {
+			.flags	= IORESOURCE_IRQ,
+		},
+		[spirsrc_rxdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
+		},
+		[spirsrc_txdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
+		},
+		[spirsrc_evqdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
+		}
+	},
+	{
+		[spirsrc_iomem] = {
+			.start	= 0x01c23000,
+			.end	= 0x01c237ff,
+			.flags	= IORESOURCE_MEM,
+		},
+		[spirsrc_irq] = {
+			.flags	= IORESOURCE_IRQ,
+		},
+		[spirsrc_rxdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
+		},
+		[spirsrc_txdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
+		},
+		[spirsrc_evqdma] = {
+			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
+		}
+	}
+};
+
+static struct platform_device davinci_spi_device[] = {
+	{
+		.name = "spi_davinci",
+		.id = 0,
+		.dev = {
+			.dma_mask = &davinci_spi_dma_mask,
+			.coherent_dma_mask = DMA_BIT_MASK(32),
+		},
+		.num_resources = ARRAY_SIZE(davinci_spi_resources[0]),
+		.resource = davinci_spi_resources[0]
+	},
+	{
+		.name = "spi_davinci",
+		.id = 1,
+		.dev = {
+			.dma_mask = &davinci_spi_dma_mask,
+			.coherent_dma_mask = DMA_BIT_MASK(32),
+		},
+		.num_resources = ARRAY_SIZE(davinci_spi_resources[1]),
+		.resource = davinci_spi_resources[1]
+	},
+	{
+		.name = "spi_davinci",
+		.id = 2,
+		.dev = {
+			.dma_mask = &davinci_spi_dma_mask,
+			.coherent_dma_mask = DMA_BIT_MASK(32),
+		},
+		.num_resources = ARRAY_SIZE(davinci_spi_resources[2]),
+		.resource = davinci_spi_resources[2]
+	},
+	{
+		.name = "spi_davinci",
+		.id = 3,
+		.dev = {
+			.dma_mask = &davinci_spi_dma_mask,
+			.coherent_dma_mask = DMA_BIT_MASK(32),
+		},
+		.num_resources = ARRAY_SIZE(davinci_spi_resources[3]),
+		.resource = davinci_spi_resources[3]
+	},
+	{
+		.name = "spi_davinci",
+		.id = 4,
+		.dev = {
+			.dma_mask = &davinci_spi_dma_mask,
+			.coherent_dma_mask = DMA_BIT_MASK(32),
+		},
+		.num_resources = ARRAY_SIZE(davinci_spi_resources[4]),
+		.resource = davinci_spi_resources[4]
+	}
+};
+
+struct davinci_spi_pins {
+	int	sclk;
+	int	sdi;
+	int	sdo;
+	int	sdena0;
+	int	sdena1;
+};
+
+static const struct davinci_spi_pins davinci_spi_pinmap[] __initconst = {
+	{
+		.sclk	= DM365_SPI0_SCLK,
+		.sdi	= DM365_SPI0_SDI,
+		.sdo	= DM365_SPI0_SDO,
+		.sdena0	= DM365_SPI0_SDENA0,
+		.sdena1	= DM365_SPI0_SDENA1
+	},
+	{
+		.sclk	= DM365_SPI1_SCLK,
+		.sdi	= DM365_SPI1_SDI,
+		.sdo	= DM365_SPI1_SDO,
+		.sdena0	= DM365_SPI1_SDENA0,
+		.sdena1	= DM365_SPI1_SDENA1
+	},
+	{
+		.sclk	= DM365_SPI2_SCLK,
+		.sdi	= DM365_SPI2_SDI,
+		.sdo	= DM365_SPI2_SDO,
+		.sdena0	= DM365_SPI2_SDENA0,
+		.sdena1	= DM365_SPI2_SDENA1
+	},
+	{
+		.sclk	= DM365_SPI3_SCLK,
+		.sdi	= DM365_SPI3_SDI,
+		.sdo	= DM365_SPI3_SDO,
+		.sdena0	= DM365_SPI3_SDENA0,
+		.sdena1	= DM365_SPI3_SDENA1
+	},
+	{
+		.sclk	= DM365_SPI4_SCLK,
+		.sdi	= DM365_SPI4_SDI,
+		.sdo	= DM365_SPI4_SDO,
+		.sdena0	= DM365_SPI4_SDENA0,
+		.sdena1	= DM365_SPI4_SDENA1
+	}
+};
+
+void __init davinci_init_spi(struct davinci_spi_unit_desc *unit,
+			unsigned int ninfo,
+			const struct spi_board_info *info)
+{
+	int err;
+	const unsigned int hwunit = unit->spi_hwunit;
+	const struct davinci_spi_pins * const pins = &davinci_spi_pinmap[hwunit];
+	struct platform_device * const pdev = &davinci_spi_device[hwunit];
+	struct davinci_spi_platform_data * const pdata = &unit->pdata;
+
+	davinci_cfg_reg(pins->sclk);
+	davinci_cfg_reg(pins->sdi);
+	davinci_cfg_reg(pins->sdo);
+
+	/* not all slaves will be wired up */
+	if (unit->chipsel & BIT(0))
+		davinci_cfg_reg(pins->sdena0);
+	if (unit->chipsel & BIT(1))
+		davinci_cfg_reg(pins->sdena1);
+
+	pdev->dev.platform_data = pdata;
+
+	pdev->resource[spirsrc_irq].start =
+	pdev->resource[spirsrc_irq].end = unit->irq;
+	pdev->resource[spirsrc_rxdma].start =
+	pdev->resource[spirsrc_rxdma].end = unit->dma_rx_chan;
+	pdev->resource[spirsrc_txdma].start =
+	pdev->resource[spirsrc_txdma].end = unit->dma_tx_chan;
+	pdev->resource[spirsrc_evqdma].start =
+	pdev->resource[spirsrc_evqdma].end = unit->dma_evtq;
+
+	pr_debug("Creating SPI%u: irq = %u, dma_rx = %u, dma_tx = %u, "
+		"dma_evq = %u",
+		hwunit, unit->irq, unit->dma_rx_chan, unit->dma_tx_chan,
+		unit->dma_evtq);
+
+	err = platform_device_register(pdev);
+	if (unlikely(err))
+		pr_err("Failed to create platform device for SPI%u - error %d",
+			hwunit, err);
+
+	spi_register_board_info(info, ninfo);
+}
+
+
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 44b0cc6..6b48f89 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -19,6 +19,7 @@
 #include <mach/emac.h>
 #include <mach/asp.h>
 #include <mach/keyscan.h>
+#include <mach/spi.h>
 
 #define DM365_EMAC_BASE			(0x01D07000)
 #define DM365_EMAC_CNTRL_OFFSET		(0x0000)
@@ -38,8 +39,4 @@ void __init dm365_init_rtc(void);
 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
 void dm365_set_vpfe_config(struct vpfe_config *cfg);
 
-struct spi_board_info;
-void dm365_init_spi0(unsigned chipselect_mask,
-		struct spi_board_info *info, unsigned len);
-
 #endif /* __ASM_ARCH_DM365_H */
diff --git a/arch/arm/mach-davinci/spi.h b/arch/arm/mach-davinci/spi.h
new file mode 100644
index 0000000..df5bb80
--- /dev/null
+++ b/arch/arm/mach-davinci/spi.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2010 Basler Vision Technologies AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_DAVINCI_SPI_H
+#define __MACH_DAVINCI_SPI_H
+
+#include <mach/spi.h>
+
+struct davinci_spi_unit_desc {
+	unsigned int				spi_hwunit;
+	unsigned int				chipsel;
+	unsigned int				irq;
+	unsigned int				dma_tx_chan;
+	unsigned int				dma_rx_chan;
+	unsigned int				dma_evtq;
+	struct davinci_spi_platform_data	pdata;
+};
+
+struct spi_board_info;
+
+void __init davinci_init_spi(struct davinci_spi_unit_desc *unit,
+			     unsigned int ninfo,
+			     const struct spi_board_info *info);
+
+
+#endif /* __MACH_DAVINCI_SPI_H */
-- 
1.7.0.3


From thomas.koeller at baslerweb.com  Tue May  4 12:18:23 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Tue,  4 May 2010 19:18:23 +0200
Subject: [PATCH 3/4] DAVINCI: Added missing includes
In-Reply-To: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
References: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <1272993504-1189-4-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

linux/compiler.h is required for __iomem
linux/types.h is required u32

Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
---
 arch/arm/mach-davinci/include/mach/common.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 1fd3917..f56fd5a 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -12,6 +12,9 @@
 #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
 #define __ARCH_ARM_MACH_DAVINCI_COMMON_H
 
+#include <linux/compiler.h>
+#include <linux/types.h>
+
 struct sys_timer;
 
 extern struct sys_timer davinci_timer;
-- 
1.7.0.3


From thomas.koeller at baslerweb.com  Tue May  4 12:18:22 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Tue,  4 May 2010 19:18:22 +0200
Subject: [PATCH 2/4] DM365: Add platform resource management
In-Reply-To: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
References: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <1272993504-1189-3-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

Keeping track of resource assignments greatly simplifies
the task of writing board support code. Many drivers for
DaVinci peripherals were using resources that had never
been allocated, with the notable exception of memory
resources.

Non-conflicting resource assignment is a responsibility
of the bus the devices are on, in this case, the platform bus.

The resource management scheme implemented by this patch is not
perfect. The SoC code really has no business managing resources,
it should only provide them to the platform (board support) code.
The board support is the only place where information about the
intended use of the various hardware resources is available.

Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
---
 arch/arm/mach-davinci/Makefile             |    8 +-
 arch/arm/mach-davinci/devices.c            |  108 +++++++++++++++------
 arch/arm/mach-davinci/dm365.c              |  145 ++++++++++++++++++++++------
 arch/arm/mach-davinci/dm365_spi.c          |  126 ++++++++++++++++++------
 arch/arm/mach-davinci/dma.c                |    8 --
 arch/arm/mach-davinci/platform-resources.c |   90 +++++++++++++++++
 arch/arm/mach-davinci/platform-resources.h |   30 ++++++
 drivers/i2c/busses/i2c-davinci.c           |    9 +--
 drivers/mmc/host/davinci_mmc.c             |    4 +-
 drivers/spi/davinci_spi.c                  |   16 +---
 drivers/watchdog/davinci_wdt.c             |   15 ---
 11 files changed, 413 insertions(+), 146 deletions(-)
 create mode 100644 arch/arm/mach-davinci/platform-resources.c
 create mode 100644 arch/arm/mach-davinci/platform-resources.h

diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index b9c497c..2e3d4ff 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -11,10 +11,10 @@ obj-$(CONFIG_DAVINCI_MUX)		+= mux.o
 obj-$(CONFIG_PCI)			+= pci-generic.o
 
 # Chip specific
-obj-$(CONFIG_ARCH_DAVINCI_DM644x)       += dm644x.o devices.o
-obj-$(CONFIG_ARCH_DAVINCI_DM355)        += dm355.o devices.o
-obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o devices.o
-obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= dm365.o devices.o
+obj-$(CONFIG_ARCH_DAVINCI_DM644x)       += dm644x.o devices.o platform-resources.o
+obj-$(CONFIG_ARCH_DAVINCI_DM355)        += dm355.o devices.o platform-resources.o
+obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o devices.o platform-resources.o
+obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= dm365.o devices.o platform-resources.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o
 
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 34dc0e9..53aaeb5 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -27,6 +27,9 @@
 #include <mach/mmc.h>
 #include <mach/time.h>
 
+#include "clock.h"
+#include "platform-resources.h"
+
 #define DAVINCI_I2C_BASE	     0x01C21000
 #define DAVINCI_MMCSD0_BASE	     0x01E10000
 #define DM355_MMCSD0_BASE	     0x01E11000
@@ -34,20 +37,27 @@
 #define DM365_MMCSD0_BASE	     0x01D11000
 #define DM365_MMCSD1_BASE	     0x01D00000
 
+static const char i2c_name[] = "i2c_davinci";
+
 static struct resource i2c_resources[] = {
 	{
+		.parent		= &resource_cfg_root,
+		.name		= i2c_name,
 		.start		= DAVINCI_I2C_BASE,
 		.end		= DAVINCI_I2C_BASE + 0x40,
 		.flags		= IORESOURCE_MEM,
 	},
 	{
+		.parent		= &resource_irq_root,
+		.name		= i2c_name,
 		.start		= IRQ_I2C,
+		.end		= IRQ_I2C,
 		.flags		= IORESOURCE_IRQ,
 	},
 };
 
 static struct platform_device davinci_i2c_device = {
-	.name           = "i2c_davinci",
+	.name           = i2c_name,
 	.id             = 1,
 	.num_resources	= ARRAY_SIZE(i2c_resources),
 	.resource	= i2c_resources,
@@ -58,42 +68,59 @@ void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
 	if (cpu_is_davinci_dm644x())
 		davinci_cfg_reg(DM644X_I2C);
 
-	davinci_i2c_device.dev.platform_data = pdata;
-	(void) platform_device_register(&davinci_i2c_device);
+	if (likely(!alloc_platform_resources(&davinci_i2c_device))) {
+		davinci_i2c_device.dev.platform_data = pdata;
+		(void) platform_device_register(&davinci_i2c_device);
+	}
 }
 
 #if	defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
 
 static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
+static const char mmc_name[] = "davinci_mmc";
 
 static struct resource mmcsd0_resources[] = {
 	{
 		/* different on dm355 */
-		.start = DAVINCI_MMCSD0_BASE,
-		.end   = DAVINCI_MMCSD0_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
+		.parent	= &resource_cfg_root,
+		.name	= mmc_name,
+		.start	= DAVINCI_MMCSD0_BASE,
+		.end	= DAVINCI_MMCSD0_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
 	},
 	/* IRQs:  MMC/SD, then SDIO */
 	{
-		.start = IRQ_MMCINT,
-		.flags = IORESOURCE_IRQ,
+		.parent	= &resource_irq_root,
+		.name	= mmc_name,
+		.start	= IRQ_MMCINT,
+		.end	= IRQ_MMCINT,
+		.flags	= IORESOURCE_IRQ,
 	}, {
 		/* different on dm355 */
-		.start = IRQ_SDIOINT,
-		.flags = IORESOURCE_IRQ,
+		.parent	= &resource_irq_root,
+		.name	= mmc_name,
+		.start	= IRQ_SDIOINT,
+		.end	= IRQ_SDIOINT,
+		.flags	= IORESOURCE_IRQ,
 	},
 	/* DMA channels: RX, then TX */
 	{
-		.start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT),
-		.flags = IORESOURCE_DMA,
+		.parent	= &resource_dma_root,
+		.name	= mmc_name,
+		.start	= EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT),
+		.end	= EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT),
+		.flags	= IORESOURCE_DMA,
 	}, {
-		.start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT),
-		.flags = IORESOURCE_DMA,
+		.parent	= &resource_dma_root,
+		.name	= mmc_name,
+		.start	= EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT),
+		.end	= EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT),
+		.flags	= IORESOURCE_DMA,
 	},
 };
 
 static struct platform_device davinci_mmcsd0_device = {
-	.name = "davinci_mmc",
+	.name = mmc_name,
 	.id = 0,
 	.dev = {
 		.dma_mask = &mmcsd0_dma_mask,
@@ -107,30 +134,42 @@ static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32);
 
 static struct resource mmcsd1_resources[] = {
 	{
-		.start = DM355_MMCSD1_BASE,
-		.end   = DM355_MMCSD1_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
+		.parent	= &resource_cfg_root,
+		.name	= mmc_name,
+		.start	= DM355_MMCSD1_BASE,
+		.end	= DM355_MMCSD1_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
 	},
 	/* IRQs:  MMC/SD, then SDIO */
 	{
-		.start = IRQ_DM355_MMCINT1,
-		.flags = IORESOURCE_IRQ,
+		.parent	= &resource_irq_root,
+		.name	= mmc_name,
+		.start	= IRQ_DM355_MMCINT1,
+		.end	= IRQ_DM355_MMCINT1,
+		.flags	= IORESOURCE_IRQ,
 	}, {
-		.start = IRQ_DM355_SDIOINT1,
-		.flags = IORESOURCE_IRQ,
+		.parent	= &resource_irq_root,
+		.name	= mmc_name,
+		.start	= IRQ_DM355_SDIOINT1,
+		.end	= IRQ_DM355_SDIOINT1,
+		.flags	= IORESOURCE_IRQ,
 	},
 	/* DMA channels: RX, then TX */
 	{
-		.start = EDMA_CTLR_CHAN(0, 30),	/* rx */
-		.flags = IORESOURCE_DMA,
+		.parent	= &resource_dma_root,
+		.name	= mmc_name,
+		.start	= EDMA_CTLR_CHAN(0, 30),	/* rx */
+		.flags	= IORESOURCE_DMA,
 	}, {
-		.start = EDMA_CTLR_CHAN(0, 31),	/* tx */
-		.flags = IORESOURCE_DMA,
+		.parent	= &resource_dma_root,
+		.name	= mmc_name,
+		.start	= EDMA_CTLR_CHAN(0, 31),	/* tx */
+		.flags	= IORESOURCE_DMA,
 	},
 };
 
 static struct platform_device davinci_mmcsd1_device = {
-	.name = "davinci_mmc",
+	.name = mmc_name,
 	.id = 1,
 	.dev = {
 		.dma_mask = &mmcsd1_dma_mask,
@@ -217,8 +256,10 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
 	if (WARN_ON(!pdev))
 		return;
 
-	pdev->dev.platform_data = config;
-	platform_device_register(pdev);
+	if (likely(!alloc_platform_resources(pdev))) {
+		pdev->dev.platform_data = config;
+		platform_device_register(pdev);
+	}
 }
 
 #else
@@ -231,8 +272,12 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
 
 /*-------------------------------------------------------------------------*/
 
+static const char wdt_name[] = "watchdog";
+
 static struct resource wdt_resources[] = {
 	{
+		.parent	= &resource_cfg_root,
+		.name	= wdt_name,
 		.start	= DAVINCI_WDOG_BASE,
 		.end	= DAVINCI_WDOG_BASE + SZ_1K - 1,
 		.flags	= IORESOURCE_MEM,
@@ -240,7 +285,7 @@ static struct resource wdt_resources[] = {
 };
 
 struct platform_device davinci_wdt_device = {
-	.name		= "watchdog",
+	.name		= wdt_name,
 	.id		= -1,
 	.num_resources	= ARRAY_SIZE(wdt_resources),
 	.resource	= wdt_resources,
@@ -248,7 +293,8 @@ struct platform_device davinci_wdt_device = {
 
 static void davinci_init_wdt(void)
 {
-	platform_device_register(&davinci_wdt_device);
+	if (likely(!alloc_platform_resources(&davinci_wdt_device)))
+		platform_device_register(&davinci_wdt_device);
 }
 
 /*-------------------------------------------------------------------------*/
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 30c2327..0aea612 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -41,6 +41,7 @@
 
 #include "clock.h"
 #include "mux.h"
+#include "platform-resources.h"
 
 #define DM365_REF_FREQ		24000000	/* 24 MHz on the DM365 EVM */
 
@@ -621,6 +622,8 @@ EVT_CFG(DM365,	EVT3_ASP_RX,         1,     1,    0,     false)
 static u64 dm365_ipipeif_dma_mask = DMA_BIT_MASK(32);
 static struct resource dm365_ipipeif_resources[] = {
 	{
+		.name		= "IPIPEIF",
+		.parent		= &resource_cfg_root,
 		.start          = 0x01C71200,
 		.end            = 0x01C71200 + 0x60,
 		.flags          = IORESOURCE_MEM,
@@ -648,11 +651,13 @@ static struct davinci_osd_platform_data dm365_osd_pdata = {
 
 static struct resource dm365_osd_resources[] = {
 	{
+		.parent		= &resource_irq_root,
 		.start          = IRQ_VENCINT,
 		.end            = IRQ_VENCINT,
 		.flags          = IORESOURCE_IRQ,
 	},
 	{
+		.parent		= &resource_cfg_root,
 		.start          = DM365_OSD_REG_BASE,
 		.end            = DM365_OSD_REG_BASE + OSD_REG_SIZE,
 		.flags          = IORESOURCE_MEM,
@@ -678,9 +683,12 @@ static struct davinci_venc_platform_data dm365_venc_pdata = {
 	.soc = DM36x,
 };
 
+static const char venc_name[] = "davinci_venc";
 
 static struct resource dm365_venc_resources[] = {
 	{
+		.name		= venc_name,
+		.parent		= &resource_cfg_root,
 		.start          = DM365_VENC_REG_BASE,
 		.end            = DM365_VENC_REG_BASE + 0x180,
 		.flags          = IORESOURCE_MEM,
@@ -688,7 +696,7 @@ static struct resource dm365_venc_resources[] = {
 };
 
 static struct platform_device dm365_venc_dev = {
-	.name		= "davinci_venc",
+	.name		= venc_name,
 	.id		= -1,
 	.num_resources	= ARRAY_SIZE(dm365_venc_resources),
 	.resource	= dm365_venc_resources,
@@ -708,28 +716,40 @@ static struct emac_platform_data dm365_emac_pdata = {
 	.version		= EMAC_VERSION_2,
 };
 
+static const char emac_name[] = "davinci_emac";
+
 static struct resource dm365_emac_resources[] = {
 	{
+		.name	= emac_name,
+		.parent	= &resource_cfg_root,
 		.start	= DM365_EMAC_BASE,
 		.end	= DM365_EMAC_BASE + 0x47ff,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
+		.name	= emac_name,
+		.parent	= &resource_irq_root,
 		.start	= IRQ_DM365_EMAC_RXTHRESH,
 		.end	= IRQ_DM365_EMAC_RXTHRESH,
 		.flags	= IORESOURCE_IRQ,
 	},
 	{
+		.name	= emac_name,
+		.parent	= &resource_irq_root,
 		.start	= IRQ_DM365_EMAC_RXPULSE,
 		.end	= IRQ_DM365_EMAC_RXPULSE,
 		.flags	= IORESOURCE_IRQ,
 	},
 	{
+		.name	= emac_name,
+		.parent	= &resource_irq_root,
 		.start	= IRQ_DM365_EMAC_TXPULSE,
 		.end	= IRQ_DM365_EMAC_TXPULSE,
 		.flags	= IORESOURCE_IRQ,
 	},
 	{
+		.name	= emac_name,
+		.parent	= &resource_irq_root,
 		.start	= IRQ_DM365_EMAC_MISCPULSE,
 		.end	= IRQ_DM365_EMAC_MISCPULSE,
 		.flags	= IORESOURCE_IRQ,
@@ -737,7 +757,7 @@ static struct resource dm365_emac_resources[] = {
 };
 
 static struct platform_device dm365_emac_device = {
-	.name		= "davinci_emac",
+	.name		= emac_name,
 	.id		= 1,
 	.dev = {
 		.platform_data	= &dm365_emac_pdata,
@@ -851,42 +871,51 @@ static struct edma_soc_info dm365_edma_info[] = {
 static struct resource edma_resources[] = {
 	{
 		.name	= "edma_cc0",
+		.parent	= &resource_cfg_root,
 		.start	= 0x01c00000,
 		.end	= 0x01c00000 + SZ_64K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
 		.name	= "edma_tc0",
+		.parent	= &resource_cfg_root,
 		.start	= 0x01c10000,
 		.end	= 0x01c10000 + SZ_1K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
 		.name	= "edma_tc1",
+		.parent	= &resource_cfg_root,
 		.start	= 0x01c10400,
 		.end	= 0x01c10400 + SZ_1K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
 		.name	= "edma_tc2",
+		.parent	= &resource_cfg_root,
 		.start	= 0x01c10800,
 		.end	= 0x01c10800 + SZ_1K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
 		.name	= "edma_tc3",
+		.parent	= &resource_cfg_root,
 		.start	= 0x01c10c00,
 		.end	= 0x01c10c00 + SZ_1K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
 		.name	= "edma0",
+		.parent	= &resource_irq_root,
 		.start	= IRQ_CCINT0,
+		.end	= IRQ_CCINT0,
 		.flags	= IORESOURCE_IRQ,
 	},
 	{
 		.name	= "edma0_err",
+		.parent	= &resource_irq_root,
 		.start	= IRQ_CCERRINT,
+		.end	= IRQ_CCERRINT,
 		.flags	= IORESOURCE_IRQ,
 	},
 	/* not using TC*_ERR */
@@ -900,18 +929,26 @@ static struct platform_device dm365_edma_device = {
 	.resource		= edma_resources,
 };
 
+static const char asp_name[] = "davinci-asp";
+
 static struct resource dm365_asp_resources[] = {
 	{
+		.name	= asp_name,
+		.parent	= &resource_cfg_root,
 		.start	= DAVINCI_DM365_ASP0_BASE,
 		.end	= DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
+		.name	= asp_name,
+		.parent	= &resource_dma_root,
 		.start	= DAVINCI_DMA_ASP0_TX,
 		.end	= DAVINCI_DMA_ASP0_TX,
 		.flags	= IORESOURCE_DMA,
 	},
 	{
+		.name	= asp_name,
+		.parent	= &resource_dma_root,
 		.start	= DAVINCI_DMA_ASP0_RX,
 		.end	= DAVINCI_DMA_ASP0_RX,
 		.flags	= IORESOURCE_DMA,
@@ -919,26 +956,33 @@ static struct resource dm365_asp_resources[] = {
 };
 
 static struct platform_device dm365_asp_device = {
-	.name		= "davinci-asp",
+	.name		= asp_name,
 	.id		= 0,
 	.num_resources	= ARRAY_SIZE(dm365_asp_resources),
 	.resource	= dm365_asp_resources,
 };
 
+static const char rtc_name[] = "rtc_davinci";
+
 static struct resource dm365_rtc_resources[] = {
 	{
-		.start = DM365_RTC_BASE,
-		.end = DM365_RTC_BASE + SZ_1K - 1,
-		.flags = IORESOURCE_MEM,
+		.name	= rtc_name,
+		.parent	= &resource_cfg_root,
+		.start	= DM365_RTC_BASE,
+		.end	= DM365_RTC_BASE + SZ_1K - 1,
+		.flags	= IORESOURCE_MEM,
 	},
 	{
-		.start = IRQ_DM365_RTCINT,
-		.flags = IORESOURCE_IRQ,
+		.name = rtc_name,
+		.parent	= &resource_irq_root,
+		.start	= IRQ_DM365_RTCINT,
+		.end	= IRQ_DM365_RTCINT,
+		.flags	= IORESOURCE_IRQ,
 	},
 };
 
 static struct platform_device dm365_rtc_device = {
-	.name = "rtc_davinci",
+	.name = rtc_name,
 	.id = 0,
 	.num_resources = ARRAY_SIZE(dm365_rtc_resources),
 	.resource = dm365_rtc_resources,
@@ -960,23 +1004,29 @@ static struct map_desc dm365_io_desc[] = {
 	},
 };
 
+static const char ks_name[] = "davinci_keyscan";
+
 static struct resource dm365_ks_resources[] = {
 	{
 		/* registers */
-		.start = DM365_KEYSCAN_BASE,
-		.end = DM365_KEYSCAN_BASE + SZ_1K - 1,
-		.flags = IORESOURCE_MEM,
+		.name	= ks_name,
+		.parent	= &resource_cfg_root,
+		.start	= DM365_KEYSCAN_BASE,
+		.end	= DM365_KEYSCAN_BASE + SZ_1K - 1,
+		.flags	= IORESOURCE_MEM,
 	},
 	{
 		/* interrupt */
-		.start = IRQ_DM365_KEYINT,
-		.end = IRQ_DM365_KEYINT,
-		.flags = IORESOURCE_IRQ,
+		.start	= IRQ_DM365_KEYINT,
+		.parent	= &resource_irq_root,
+		.start	= IRQ_DM365_KEYINT,
+		.end	= IRQ_DM365_KEYINT,
+		.flags	= IORESOURCE_IRQ,
 	},
 };
 
 static struct platform_device dm365_ks_device = {
-	.name		= "davinci_keyscan",
+	.name		= ks_name,
 	.id		= 0,
 	.num_resources	= ARRAY_SIZE(dm365_ks_resources),
 	.resource	= dm365_ks_resources,
@@ -1004,7 +1054,7 @@ static void __iomem *dm365_psc_bases[] = {
 	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 };
 
-struct davinci_timer_info dm365_timer_info = {
+static struct davinci_timer_info dm365_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
@@ -1078,7 +1128,8 @@ void __init dm365_init_asp(struct snd_platform_data *pdata)
 	davinci_cfg_reg(DM365_EVT2_ASP_TX);
 	davinci_cfg_reg(DM365_EVT3_ASP_RX);
 	dm365_asp_device.dev.platform_data = pdata;
-	platform_device_register(&dm365_asp_device);
+	if (!alloc_platform_resources(&dm365_asp_device))
+		platform_device_register(&dm365_asp_device);
 }
 
 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
@@ -1090,7 +1141,8 @@ void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
 void __init dm365_init_rtc(void)
 {
 	davinci_cfg_reg(DM365_INT_PRTCSS);
-	platform_device_register(&dm365_rtc_device);
+	if (!alloc_platform_resources(&dm365_rtc_device))
+		platform_device_register(&dm365_rtc_device);
 }
 
 void __init dm365_init(void)
@@ -1098,17 +1150,21 @@ void __init dm365_init(void)
 	davinci_common_init(&davinci_soc_info_dm365);
 }
 
+static const char vpss_name[] = "vpss";
+
 static struct resource dm365_vpss_resources[] = {
 	{
 		/* VPSS ISP5 Base address */
-		.name           = "vpss",
+		.name           = vpss_name,
+		.parent		= &resource_cfg_root,
 		.start          = 0x01c70000,
 		.end            = 0x01c70000 + 0xff,
 		.flags          = IORESOURCE_MEM,
 	},
 	{
 		/* VPSS CLK Base address */
-		.name           = "vpss",
+		.name           = vpss_name,
+		.parent		= &resource_cfg_root,
 		.start          = 0x01c70200,
 		.end            = 0x01c70200 + 0xff,
 		.flags          = IORESOURCE_MEM,
@@ -1116,20 +1172,26 @@ static struct resource dm365_vpss_resources[] = {
 };
 
 static struct platform_device dm365_vpss_device = {
-       .name                   = "vpss",
+       .name                   = vpss_name,
        .id                     = -1,
        .dev.platform_data      = "dm365_vpss",
        .num_resources          = ARRAY_SIZE(dm365_vpss_resources),
        .resource               = dm365_vpss_resources,
 };
 
+static const char cptr_name[] = CAPTURE_DRV_NAME;
+
 static struct resource vpfe_resources[] = {
 	{
+		.name		= cptr_name,
+		.parent		= &resource_irq_root,
 		.start          = IRQ_VDINT0,
 		.end            = IRQ_VDINT0,
 		.flags          = IORESOURCE_IRQ,
 	},
 	{
+		.name		= cptr_name,
+		.parent		= &resource_irq_root,
 		.start          = IRQ_VDINT1,
 		.end            = IRQ_VDINT1,
 		.flags          = IORESOURCE_IRQ,
@@ -1138,7 +1200,7 @@ static struct resource vpfe_resources[] = {
 
 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 static struct platform_device vpfe_capture_dev = {
-	.name           = CAPTURE_DRV_NAME,
+	.name           = cptr_name,
 	.id             = -1,
 	.num_resources  = ARRAY_SIZE(vpfe_resources),
 	.resource       = vpfe_resources,
@@ -1148,28 +1210,36 @@ static struct platform_device vpfe_capture_dev = {
 	},
 };
 
+static const char isif_name[] = "dm365_isif";
+
 static struct resource isif_resource[] = {
 	/* ISIF Base address */
 	{
+		.name		= isif_name,
+		.parent		= &resource_cfg_root,
 		.start          = 0x01c71000,
 		.end            = 0x01c71000 + 0x1ff,
 		.flags          = IORESOURCE_MEM,
 	},
 	/* ISIF Linearization table 0 */
 	{
+		.name		= isif_name,
+		.parent		= &resource_cfg_root,
 		.start          = 0x1C7C000,
 		.end            = 0x1C7C000 + 0x2ff,
 		.flags          = IORESOURCE_MEM,
 	},
 	/* ISIF Linearization table 1 */
 	{
+		.name		= isif_name,
+		.parent		= &resource_cfg_root,
 		.start          = 0x1C7C400,
 		.end            = 0x1C7C400 + 0x2ff,
 		.flags          = IORESOURCE_MEM,
 	},
 };
 static struct platform_device dm365_isif_dev = {
-	.name           = "dm365_isif",
+	.name           = isif_name,
 	.id             = -1,
 	.num_resources  = ARRAY_SIZE(isif_resource),
 	.resource       = isif_resource,
@@ -1184,24 +1254,35 @@ static int __init dm365_init_devices(void)
 	if (!cpu_is_davinci_dm365())
 		return 0;
 
+	if (request_resource(&iomem_resource, &resource_cfg_root))
+		BUG();
+
 	davinci_cfg_reg(DM365_INT_EDMA_CC);
-	platform_device_register(&dm365_edma_device);
-	platform_device_register(&dm365_emac_device);
+	if (!alloc_platform_resources(&dm365_edma_device))
+		platform_device_register(&dm365_edma_device);
+	if (!alloc_platform_resources(&dm365_emac_device))
+		platform_device_register(&dm365_emac_device);
 
 	/*
 	* setup Mux configuration for vpfe input and register
 	* vpfe capture platform device
 	*/
-	platform_device_register(&dm365_vpss_device);
-	platform_device_register(&dm365_ipipeif_dev);
-	platform_device_register(&dm365_isif_dev);
-	platform_device_register(&vpfe_capture_dev);
+	if (!alloc_platform_resources(&dm365_vpss_device))
+		platform_device_register(&dm365_vpss_device);
+	if (!alloc_platform_resources(&dm365_ipipeif_dev))
+		platform_device_register(&dm365_ipipeif_dev);
+	if (!alloc_platform_resources(&dm365_isif_dev))
+		platform_device_register(&dm365_isif_dev);
+	if (!alloc_platform_resources(&vpfe_capture_dev))
+		platform_device_register(&vpfe_capture_dev);
 
 	/* Register OSD device */
-	platform_device_register(&dm365_osd_dev);
+	if (!alloc_platform_resources(&dm365_osd_dev))
+		platform_device_register(&dm365_osd_dev);
 
 	/* Register VENC device */
-	platform_device_register(&dm365_venc_dev);
+	if (!alloc_platform_resources(&dm365_venc_dev))
+		platform_device_register(&dm365_venc_dev);
 
 	return 0;
 }
diff --git a/arch/arm/mach-davinci/dm365_spi.c b/arch/arm/mach-davinci/dm365_spi.c
index e1743d7..6aeba61 100644
--- a/arch/arm/mach-davinci/dm365_spi.c
+++ b/arch/arm/mach-davinci/dm365_spi.c
@@ -19,11 +19,12 @@
 #include <linux/spi/spi.h>
 #include <mach/mux.h>
 
+#include "platform-resources.h"
 #include "spi.h"
 
-static u64 davinci_spi_dma_mask = DMA_BIT_MASK(32);
+static u64 dm365_spi_dma_mask = DMA_BIT_MASK(32);
 
-enum davinci_spi_resource_index {
+enum dm365_spi_resource_index {
 	spirsrc_iomem,
 	spirsrc_irq,
 	spirsrc_rxdma,
@@ -31,159 +32,217 @@ enum davinci_spi_resource_index {
 	spirsrc_evqdma
 };
 
+static const char
+	spi0_name[] = "SPI0",
+	spi1_name[] = "SPI1",
+	spi2_name[] = "SPI2",
+	spi3_name[] = "SPI3",
+	spi4_name[] = "SPI4";
 
-static struct resource davinci_spi_resources[spirsrc_evqdma + 1][5] = {
-	{
+
+static struct resource
+dm365_spi_resources[spirsrc_evqdma + 1][5] = {
+	[0] = {
 		[spirsrc_iomem] = {
+			.name	= spi0_name,
+			.parent	= &resource_cfg_root,
 			.start	= 0x01c66000,
 			.end	= 0x01c667ff,
 			.flags	= IORESOURCE_MEM,
 		},
 		[spirsrc_irq] = {
+			.name	= spi0_name,
+			.parent	= &resource_irq_root,
 			.flags	= IORESOURCE_IRQ,
 		},
 		[spirsrc_rxdma] = {
+			.name	= spi0_name,
+			.parent	= &resource_dma_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
 		},
 		[spirsrc_txdma] = {
+			.name	= spi0_name,
+			.parent	= &resource_dma_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
 		},
 		[spirsrc_evqdma] = {
+			.name	= spi0_name,
+			.parent	= &resource_evq_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
 		}
 	},
-	{
+	[1] = {
 		[spirsrc_iomem] = {
+			.name	= spi1_name,
+			.parent	= &resource_cfg_root,
 			.start	= 0x01c66800,
 			.end	= 0x01c66fff,
 			.flags	= IORESOURCE_MEM,
 		},
 		[spirsrc_irq] = {
+			.name	= spi1_name,
+			.parent	= &resource_irq_root,
 			.flags	= IORESOURCE_IRQ,
 		},
 		[spirsrc_rxdma] = {
+			.name	= spi1_name,
+			.parent	= &resource_dma_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
 		},
 		[spirsrc_txdma] = {
+			.name	= spi1_name,
+			.parent	= &resource_dma_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
 		},
 		[spirsrc_evqdma] = {
+			.name	= spi1_name,
+			.parent	= &resource_evq_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
 		}
 	},
-	{
+	[2] = {
 		[spirsrc_iomem] = {
+			.name	= spi2_name,
+			.parent	= &resource_cfg_root,
 			.start	= 0x01c67800,
 			.end	= 0x01c67fff,
 			.flags	= IORESOURCE_MEM,
 		},
 		[spirsrc_irq] = {
+			.name	= spi2_name,
+			.parent	= &resource_irq_root,
 			.flags	= IORESOURCE_IRQ,
 		},
 		[spirsrc_rxdma] = {
+			.name	= spi2_name,
+			.parent	= &resource_dma_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
 		},
 		[spirsrc_txdma] = {
+			.name	= spi2_name,
+			.parent	= &resource_dma_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
 		},
 		[spirsrc_evqdma] = {
+			.name	= spi2_name,
+			.parent	= &resource_evq_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
 		}
 	},
-	{
+	[3] = {
 		[spirsrc_iomem] = {
+			.name	= spi3_name,
+			.parent	= &resource_cfg_root,
 			.start	= 0x01c68000,
 			.end	= 0x01c687ff,
 			.flags	= IORESOURCE_MEM,
 		},
 		[spirsrc_irq] = {
+			.name	= spi3_name,
+			.parent	= &resource_irq_root,
 			.flags	= IORESOURCE_IRQ,
 		},
 		[spirsrc_rxdma] = {
+			.name	= spi3_name,
+			.parent	= &resource_dma_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
 		},
 		[spirsrc_txdma] = {
+			.name	= spi3_name,
+			.parent	= &resource_dma_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
 		},
 		[spirsrc_evqdma] = {
+			.name	= spi3_name,
+			.parent	= &resource_evq_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
 		}
 	},
-	{
+	[4] = {
 		[spirsrc_iomem] = {
+			.name	= spi4_name,
+			.parent	= &resource_cfg_root,
 			.start	= 0x01c23000,
 			.end	= 0x01c237ff,
 			.flags	= IORESOURCE_MEM,
 		},
 		[spirsrc_irq] = {
+			.name	= spi4_name,
+			.parent	= &resource_irq_root,
 			.flags	= IORESOURCE_IRQ,
 		},
 		[spirsrc_rxdma] = {
+			.name	= spi4_name,
+			.parent	= &resource_dma_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
 		},
 		[spirsrc_txdma] = {
+			.name	= spi4_name,
+			.parent	= &resource_dma_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
 		},
 		[spirsrc_evqdma] = {
+			.name	= spi4_name,
+			.parent	= &resource_evq_root,
 			.flags	= IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
 		}
 	}
 };
 
-static struct platform_device davinci_spi_device[] = {
+static struct platform_device dm365_spi_device[] = {
 	{
 		.name = "spi_davinci",
 		.id = 0,
 		.dev = {
-			.dma_mask = &davinci_spi_dma_mask,
+			.dma_mask = &dm365_spi_dma_mask,
 			.coherent_dma_mask = DMA_BIT_MASK(32),
 		},
-		.num_resources = ARRAY_SIZE(davinci_spi_resources[0]),
-		.resource = davinci_spi_resources[0]
+		.num_resources = ARRAY_SIZE(dm365_spi_resources[0]),
+		.resource = dm365_spi_resources[0]
 	},
 	{
 		.name = "spi_davinci",
 		.id = 1,
 		.dev = {
-			.dma_mask = &davinci_spi_dma_mask,
+			.dma_mask = &dm365_spi_dma_mask,
 			.coherent_dma_mask = DMA_BIT_MASK(32),
 		},
-		.num_resources = ARRAY_SIZE(davinci_spi_resources[1]),
-		.resource = davinci_spi_resources[1]
+		.num_resources = ARRAY_SIZE(dm365_spi_resources[1]),
+		.resource = dm365_spi_resources[1]
 	},
 	{
 		.name = "spi_davinci",
 		.id = 2,
 		.dev = {
-			.dma_mask = &davinci_spi_dma_mask,
+			.dma_mask = &dm365_spi_dma_mask,
 			.coherent_dma_mask = DMA_BIT_MASK(32),
 		},
-		.num_resources = ARRAY_SIZE(davinci_spi_resources[2]),
-		.resource = davinci_spi_resources[2]
+		.num_resources = ARRAY_SIZE(dm365_spi_resources[2]),
+		.resource = dm365_spi_resources[2]
 	},
 	{
 		.name = "spi_davinci",
 		.id = 3,
 		.dev = {
-			.dma_mask = &davinci_spi_dma_mask,
+			.dma_mask = &dm365_spi_dma_mask,
 			.coherent_dma_mask = DMA_BIT_MASK(32),
 		},
-		.num_resources = ARRAY_SIZE(davinci_spi_resources[3]),
-		.resource = davinci_spi_resources[3]
+		.num_resources = ARRAY_SIZE(dm365_spi_resources[3]),
+		.resource = dm365_spi_resources[3]
 	},
 	{
 		.name = "spi_davinci",
 		.id = 4,
 		.dev = {
-			.dma_mask = &davinci_spi_dma_mask,
+			.dma_mask = &dm365_spi_dma_mask,
 			.coherent_dma_mask = DMA_BIT_MASK(32),
 		},
-		.num_resources = ARRAY_SIZE(davinci_spi_resources[4]),
-		.resource = davinci_spi_resources[4]
+		.num_resources = ARRAY_SIZE(dm365_spi_resources[4]),
+		.resource = dm365_spi_resources[4]
 	}
 };
 
-struct davinci_spi_pins {
+struct dm365_spi_pins {
 	int	sclk;
 	int	sdi;
 	int	sdo;
@@ -191,7 +250,7 @@ struct davinci_spi_pins {
 	int	sdena1;
 };
 
-static const struct davinci_spi_pins davinci_spi_pinmap[] __initconst = {
+static const struct dm365_spi_pins dm365_spi_pinmap[] __initconst = {
 	{
 		.sclk	= DM365_SPI0_SCLK,
 		.sdi	= DM365_SPI0_SDI,
@@ -230,13 +289,13 @@ static const struct davinci_spi_pins davinci_spi_pinmap[] __initconst = {
 };
 
 void __init davinci_init_spi(struct davinci_spi_unit_desc *unit,
-			unsigned int ninfo,
-			const struct spi_board_info *info)
+			     unsigned int ninfo,
+			     const struct spi_board_info *info)
 {
 	int err;
 	const unsigned int hwunit = unit->spi_hwunit;
-	const struct davinci_spi_pins * const pins = &davinci_spi_pinmap[hwunit];
-	struct platform_device * const pdev = &davinci_spi_device[hwunit];
+	const struct dm365_spi_pins * const pins = &dm365_spi_pinmap[hwunit];
+	struct platform_device * const pdev = &dm365_spi_device[hwunit];
 	struct davinci_spi_platform_data * const pdata = &unit->pdata;
 
 	davinci_cfg_reg(pins->sclk);
@@ -260,6 +319,11 @@ void __init davinci_init_spi(struct davinci_spi_unit_desc *unit,
 	pdev->resource[spirsrc_evqdma].start =
 	pdev->resource[spirsrc_evqdma].end = unit->dma_evtq;
 
+	if (alloc_platform_resources(pdev)) {
+		pr_err("Resource allocation failed for SPI%u\n", hwunit);
+		return;
+	};
+
 	pr_debug("Creating SPI%u: irq = %u, dma_rx = %u, dma_tx = %u, "
 		"dma_evq = %u",
 		hwunit, unit->irq, unit->dma_rx_chan, unit->dma_tx_chan,
@@ -272,5 +336,3 @@ void __init davinci_init_spi(struct davinci_spi_unit_desc *unit,
 
 	spi_register_board_info(info, ninfo);
 }
-
-
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 5cd48fa..8abc707 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -1430,14 +1430,6 @@ static int __init edma_probe(struct platform_device *pdev)
 			found = 1;
 
 		len[j] = resource_size(r[j]);
-
-		r[j] = request_mem_region(r[j]->start, len[j],
-			dev_name(&pdev->dev));
-		if (!r[j]) {
-			status = -EBUSY;
-			goto fail1;
-		}
-
 		edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
 		if (!edmacc_regs_base[j]) {
 			status = -EBUSY;
diff --git a/arch/arm/mach-davinci/platform-resources.c b/arch/arm/mach-davinci/platform-resources.c
new file mode 100644
index 0000000..90893d3
--- /dev/null
+++ b/arch/arm/mach-davinci/platform-resources.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2010 Basler Vision Technologies AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Author: Thomas Koeller <thomas.koeller at baslerweb.com>
+ */
+
+#include "platform-resources.h"
+
+/* root resource for configuration register space */
+struct resource resource_cfg_root = {
+	.name	= "DM365 peripherals",
+	.start	= 0x01c00000,
+	.end	= 0x01ffffff,
+	.flags	= IORESOURCE_MEM
+};
+
+/* root resource for DMA channels */
+struct resource resource_dma_root = {
+	.name	= "DM365 DMA",
+	.start	= 0,
+	.end	= 63,
+	.flags	= IORESOURCE_DMA
+};
+
+/* root resource for DMA event queues */
+struct resource resource_evq_root = {
+	.name	= "DM365 EVQ",
+	.start	= 0,
+	.end	= 3,
+	.flags	= IORESOURCE_DMA
+};
+
+/* root resource for IRQ numbers */
+struct resource resource_irq_root = {
+	.name	= "DM365 IRQ",
+	.start	= 0,
+	.end	= 63,
+	.flags	= IORESOURCE_IRQ
+};
+
+/* Allocate resources for platform device */
+int alloc_platform_resources(const struct platform_device *dev)
+{
+	int n;
+
+	for (n = 0; n < dev->num_resources; ++n) {
+		int res;
+		struct resource *rsrc = &dev->resource[n];
+		struct resource *parent;
+
+		/*
+		 * Memory and I/O resources are automatically allocated
+		 * by platform_device_add(), so do not allocate them
+		 * here.
+		 */
+		if (resource_type(rsrc) == IORESOURCE_IO ||
+		    resource_type(rsrc) == IORESOURCE_MEM)
+			continue;
+
+		parent = rsrc->parent;
+		res = request_resource(parent, rsrc);
+		if (likely(!res))
+			continue;
+
+		/* bail out */
+		rsrc->parent = parent;
+		pr_warning("Failed to allocate resource '%s' from '%s'\n",
+			   rsrc->name, parent->name);
+		while (--n >= 0) {
+			/* preserve the parent pointer */
+			rsrc = &dev->resource[n];
+			parent = rsrc->parent;
+			release_resource(rsrc);
+			rsrc->parent = parent;
+		}
+
+		return res;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-davinci/platform-resources.h b/arch/arm/mach-davinci/platform-resources.h
new file mode 100644
index 0000000..0af3fe0
--- /dev/null
+++ b/arch/arm/mach-davinci/platform-resources.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2010 Basler Vision Technologies AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Author: Thomas Koeller <thomas.koeller at baslerweb.com>
+ */
+#ifndef DAVINCI_PLATFORM_RESOURCES_H
+#define DAVINCI_PLATFORM_RESOURCES_H
+
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+
+/* Root resources */
+extern struct resource
+	resource_cfg_root,
+	resource_dma_root,
+	resource_irq_root,
+	resource_evq_root;
+
+int alloc_platform_resources(const struct platform_device *dev);
+
+#endif /* DAVINCI_PLATFORM_RESOURCES_H */
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index 67d88cc..4327ad9 100755
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -520,7 +520,7 @@ static int davinci_i2c_probe(struct platform_device *pdev)
 {
 	struct davinci_i2c_dev *dev;
 	struct i2c_adapter *adap;
-	struct resource *mem, *irq, *ioarea;
+	struct resource *mem, *irq;
 	int r;
 
 	/* NOTE: driver uses the static register mapping */
@@ -536,13 +536,6 @@ static int davinci_i2c_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	ioarea = request_mem_region(mem->start, resource_size(mem),
-				    pdev->name);
-	if (!ioarea) {
-		dev_err(&pdev->dev, "I2C region already claimed\n");
-		return -EBUSY;
-	}
-
 	dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
 	if (!dev) {
 		r = -ENOMEM;
diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
index 1bf0587..cf69c2e 100644
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -1183,9 +1183,7 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev)
 
 	ret = -EBUSY;
 	mem_size = resource_size(r);
-	mem = request_mem_region(r->start, mem_size, pdev->name);
-	if (!mem)
-		goto out;
+	mem = r;
 
 	ret = -ENOMEM;
 	mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev);
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 956f617..456a680 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -868,7 +868,7 @@ static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
 	return ret;
 }
 
-resource_size_t davinci_spi_get_dma_by_flag(struct platform_device *dev,
+static resource_size_t davinci_spi_get_dma_by_flag(struct platform_device *dev,
 		unsigned long flag)
 {
 	struct resource *r;
@@ -901,7 +901,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
 	struct spi_master *master;
 	struct davinci_spi *davinci_spi;
 	struct davinci_spi_platform_data *pdata;
-	struct resource *r, *mem;
+	struct resource *r;
 	resource_size_t dma_rx_chan = DAVINCI_SPI_NO_RESOURCE;
 	resource_size_t	dma_tx_chan = DAVINCI_SPI_NO_RESOURCE;
 	resource_size_t	dma_eventq = DAVINCI_SPI_NO_RESOURCE;
@@ -936,19 +936,11 @@ static int davinci_spi_probe(struct platform_device *pdev)
 	davinci_spi->pbase = r->start;
 	davinci_spi->region_size = resource_size(r);
 	davinci_spi->pdata = pdata;
-
-	mem = request_mem_region(r->start, davinci_spi->region_size,
-					pdev->name);
-	if (mem == NULL) {
-		ret = -EBUSY;
-		goto free_master;
-	}
-
 	davinci_spi->base = (struct davinci_spi_reg __iomem *)
 			ioremap(r->start, davinci_spi->region_size);
 	if (davinci_spi->base == NULL) {
 		ret = -ENOMEM;
-		goto release_region;
+		goto free_master;
 	}
 
 	davinci_spi->irq = platform_get_irq(pdev, 0);
@@ -1088,8 +1080,6 @@ err1:
 	free_irq(davinci_spi->irq, davinci_spi);
 unmap_io:
 	iounmap(davinci_spi->base);
-release_region:
-	release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
 free_master:
 	kfree(master);
 err:
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 9d7520f..2331750 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -68,7 +68,6 @@ static unsigned long wdt_status;
 #define WDT_REGION_INITED 2
 #define WDT_DEVICE_INITED 3
 
-static struct resource	*wdt_mem;
 static void __iomem	*wdt_base;
 struct clk		*wdt_clk;
 
@@ -222,12 +221,6 @@ static int __devinit davinci_wdt_probe(struct platform_device *pdev)
 	}
 
 	size = res->end - res->start + 1;
-	wdt_mem = request_mem_region(res->start, size, pdev->name);
-
-	if (wdt_mem == NULL) {
-		dev_err(dev, "failed to get memory region\n");
-		return -ENOENT;
-	}
 
 	wdt_base = ioremap(res->start, size);
 	if (!wdt_base) {
@@ -238,8 +231,6 @@ static int __devinit davinci_wdt_probe(struct platform_device *pdev)
 	ret = misc_register(&davinci_wdt_miscdev);
 	if (ret < 0) {
 		dev_err(dev, "cannot register misc device\n");
-		release_resource(wdt_mem);
-		kfree(wdt_mem);
 	} else {
 		set_bit(WDT_DEVICE_INITED, &wdt_status);
 	}
@@ -251,12 +242,6 @@ static int __devinit davinci_wdt_probe(struct platform_device *pdev)
 static int __devexit davinci_wdt_remove(struct platform_device *pdev)
 {
 	misc_deregister(&davinci_wdt_miscdev);
-	if (wdt_mem) {
-		release_resource(wdt_mem);
-		kfree(wdt_mem);
-		wdt_mem = NULL;
-	}
-
 	clk_disable(wdt_clk);
 	clk_put(wdt_clk);
 
-- 
1.7.0.3


From thomas.koeller at baslerweb.com  Tue May  4 12:18:24 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Tue,  4 May 2010 19:18:24 +0200
Subject: [PATCH 4/4] DM365: Added PINMUX definitions for GPIO30..32
In-Reply-To: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
References: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <1272993504-1189-5-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
---
 arch/arm/mach-davinci/dm365.c            |    3 +++
 arch/arm/mach-davinci/include/mach/mux.h |    3 +++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0aea612..8fb7578 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -579,6 +579,9 @@ MUX_CFG(DM365,	SPI4_SDENA0,	4,   20,    3,    1,	 false)
 MUX_CFG(DM365,	SPI4_SDENA1,	4,   16,    3,    2,	 false)
 
 MUX_CFG(DM365,	GPIO20,		3,   21,    3,    0,	 false)
+MUX_CFG(DM365,	GPIO30,		4,   6,     3,	  0,	 false)
+MUX_CFG(DM365,	GPIO31,		4,   8,     3,	  0,	 false)
+MUX_CFG(DM365,	GPIO32,		4,   10,    3,	  0,	 false)
 MUX_CFG(DM365,	GPIO33,		4,   12,    3,	  0,	 false)
 MUX_CFG(DM365,	GPIO40,		4,   26,    3,	  0,	 false)
 
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 05e35fa..49a2f57 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -293,6 +293,9 @@ enum davinci_dm365_index {
 
 	/* GPIO */
 	DM365_GPIO20,
+	DM365_GPIO30,
+	DM365_GPIO31,
+	DM365_GPIO32,
 	DM365_GPIO33,
 	DM365_GPIO40,
 
-- 
1.7.0.3


From rtivy at ti.com  Tue May  4 16:57:25 2010
From: rtivy at ti.com (Tivy, Robert)
Date: Tue, 4 May 2010 16:57:25 -0500
Subject: kernel cache APIs
Message-ID: <6B8224E84039B140AA662F0BB0361643012A6B6733@dlee04.ent.ti.com>

I need to port CMEM to the newer 2.6.34 Linux kernel but am having trouble with the cache functions.  This is for the TI ARM, in general.

CMEM provides general capability to user programs to initiate a cache operation, mostly for the purpose of affecting the cache contents pertaining to the CMEM buffers.  CMEM allows the user to specify either a writeback, an invalidate, or a writeback/invalidate.  These operations are always for user virtual addresses.

Previously I was calling dmac_{clean,inv,flush}_range() to do the wb/inv/wbinv, respectively.  Now it seems that only dmac_flush_range() exists (at least, that's the only one of the 3 that doesn't get an "implicit declaration" error when compiling).  There was some talk a while back on this maillist of having to change to use dma_map_single(), but in 2.6.34 that API appears to be much different than before, and not appropriate for just triggering an operation on the cache.

Can anyone please point me to the appropriate cache APIs?  (I don't want to call "all" type operations, just "range" type)

Thanks & Regards,

- Rob
Texas Instruments, Santa Barbara

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From jtobias at viaas.com  Tue May  4 20:36:55 2010
From: jtobias at viaas.com (John Tobias)
Date: Tue, 4 May 2010 18:36:55 -0700
Subject: UBL Question
In-Reply-To: <201005020952.59981.caglarakyuz@gmail.com>
References: <o2o66b2b2311004301114m5992da85s156d0ace0e3afec1@mail.gmail.com>
	<E7D5CF88-E988-43FF-B15E-840475F51482@dsicentral.com>
	<s2r66b2b2311004301519pf2622273x53e09e53d1a24853@mail.gmail.com>
	<201005020952.59981.caglarakyuz@gmail.com>
Message-ID: <y2k66b2b2311005041836se6b5de0chbfc7ef4babbbdb49@mail.gmail.com>

Caglar,

In sprue20c <http://www-s.ti.com/sc/techlit/sprue20.pdf> documentation,
discusses the 3 types of mode. One of them is the NAND Flash mode, which is
the mode  to function the NAND Flash ECC generator.

My question is, if the device is running linux, what mode does the NAND
is?.

I am start playing to add some routines in nand drivers and see how far I
can go. But, need additional information and maybe you can help me.

1. Do you know how the ubl data laid out on the block?.
2.The ubl image should not exist 0x3800 bytes and seems DVFlasher removes
some Srec. Do you know what was the reason?.


Best Regards,

John


On Sat, May 1, 2010 at 11:52 PM, Caglar Akyuz <caglarakyuz at gmail.com> wrote:

> On Saturday 01 May 2010 01:19:56 am John Tobias wrote:
> > I've used the following commands and didn't get any success.
> >
> > 1. nanddump -n -f /ubl.bin /dev/mtd5
> > Block size 16384, page size 512, OOB size 16
> > Dumping data starting at 0x00000000 and ending at 0x00004000
> >
> > 2. flash_erase /dev/mtd1
> >
> > 3. nandwrite -n -o /dev/mtd1 /ubl.bin
> >
> > 4. flash_erase /dev/mtd5
> >
> > Any more idea?
> >
>
> AFAIK, rbl/ubl pair uses different ECC layout than u-boot/Linux pair. For
> instance, I do not use u-boot in some cases and boot Linux directly from
> UBL
> in which I write Linux to NAND from userspace. In those cases, I read Linux
> without any ECC in UBL. But you do not have any access to RBL so you cannot
> program UBL from userspace without changing Linux ECC handling.
>
> Best Regards,
> Caglar
>
> > Thanks,
> >
> > John
> >
> > On Fri, Apr 30, 2010 at 2:57 PM, Siddharth Choudhuri
> <sid at dsicentral.com>wrote:
> > > Does dd also take care of writing the OOB area along with the actual
> data
> > > ? The OOB layout where the ECC is written could be an issue IMO. You
> > > might want to look at nandwrite i.e., read using nanddump -> erase ->
> > > nandwrite to see if it works. Also, nanddump and nandwrite might have
> an
> > > option to read page data and/or OOB.
> > >
> > > -sid
> > >
> > > On Apr 30, 2010, at 1:15 PM, John Tobias wrote:
> > >
> > > Hi Mike,
> > >
> > > I've used this two commands to copy the image on block 5 then, copy it
> > > over to block 1.
> > >
> > > dd if=/dev/mtd5 of=/ubl.bin bs=512 count=32
> > > dd if=/ubl.bin of=/dev/mtd1 bs=512 count=32
> > > (My NAND flash has 512 bytes per page with 32 pages per block or
> 16Kbytes
> > > in  1 block).
> > >
> > > In order to test the block 1 if it's working, I erased the block 5 and
> > > boot my device but, it doesn't work.
> > >
> > > Any idea?
> > >
> > > Thanks,
> > >
> > > John
> > >
> > > On Fri, Apr 30, 2010 at 11:51 AM, John Tobias <jtobias at viaas.com>
> wrote:
> > >> Hi Mike,
> > >>
> > >> Yes, that's my plan. I will expose the ubl blocks from linux userspace
> > >> and become writable.
> > >> And, I like the idea of using dd so no need to worry about the CRC
> > >> issue.
> > >>
> > >> Thanks,
> > >>
> > >> John
> > >>
> > >> On Fri, Apr 30, 2010 at 11:34 AM, Mike Williamson <
> > >>
> > >> michael.williamson at criticallink.com> wrote:
> > >>> Hi John,
> > >>>
> > >>> In the past, we've used the /dev/mtd* devices to write data back to
> NOR
> > >>> (spi / parallel) devices for updating firmware using something like:
> > >>>
> > >>> dd if=newimage.bin of=/dev/mtd0
> > >>>
> > >>> Of course, you need to have your kernel configured to have the mtd
> > >>> drivers loaded and you need to make these areas writable (most linux
> > >>> board packages set these to read-only, given the sizeable gun you
> have
> > >>> pointed at your shoes....)
> > >>>
> > >>> -Mike
> > >>>
> > >>> On Fri, Apr 30, 2010 at 2:14 PM, John Tobias <jtobias at viaas.com>
> wrote:
> > >>>> Hi,
> > >>>>
> > >>>> Does anyone successfully written the UBL image in block 1/5 from
> linux
> > >>>> userspace? I need a way to write the ubl image for the firmware
> > >>>> upgrade and the only access that I have is the linux userspace.
> > >>>>
> > >>>>
> > >>>> Thanks,
> > >>>>
> > >>>> John
> > >>>>
> > >>>> _______________________________________________
> > >>>> Davinci-linux-open-source mailing list
> > >>>> Davinci-linux-open-source at linux.davincidsp.com
> > >>>>
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> > >>>
> > >>> --
> > >>> Michael Williamson
> > >>> 315-425-4045x230
> > >>> www.criticallink.com
> > >
> > > _______________________________________________
> > > Davinci-linux-open-source mailing list
> > > Davinci-linux-open-source at linux.davincidsp.com
> > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> >
>
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From blueskyjb at roadrunner.com  Tue May  4 22:03:46 2010
From: blueskyjb at roadrunner.com (Jimmy Blair)
Date: Tue, 04 May 2010 20:03:46 -0700
Subject: DM365 audio -- bad PLL setting in tlv320aic3x driver
Message-ID: <4BE0E012.1030406@roadrunner.com>

44100 Hz audio plays slightly fast on the DM365.
This is because the tlv320aic3x driver is calculating
invalid PLL parameters for the WCLK.  The parameters
it calculates are:

pll_p = 1, pll_r = 1, pll_j = 3, pll_d = 3450

According to the codec datasheet, the value of J
should be greater than 3.  The datasheet is correct.
The WCLK signal is unstable, bouncing between 44200 and 44500 Hz.

I recalculated the parameters by hand, setting P to 2
and got the following values:

pll_p = 2, pll_r = 1, pll_j = 6, pll_d = 6901

These values gave a clean 44100 WCLK.

From nsekhar at ti.com  Wed May  5 00:29:47 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Wed, 5 May 2010 10:59:47 +0530
Subject: UBL Question
In-Reply-To: <v2yade1bdc1005040202l866f8534lfec7f2a490a285e4@mail.gmail.com>
References: <h2gade1bdc1005040105r2aad773r6ef2d7be2cdc01cd@mail.gmail.com>
	<70E876B0EA86DD4BAF101844BC814DFE08DE6D0E2E@Cloud.RL.local>
	<B85A65D85D7EB246BE421B3FB0FBB59301E6CC384F@dbde02.ent.ti.com>
	<v2yade1bdc1005040202l866f8534lfec7f2a490a285e4@mail.gmail.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6D3D096@dbde02.ent.ti.com>

Hi Raffaele,

On Tue, May 04, 2010 at 14:32:31, Raffaele Recalcati wrote:
> Hi Nori,
>
>
>
>       There is a sourceforge project for UBL and serial flashing
> tools:
>
>       http://sourceforge.net/projects/dvflashutils/
>
>       You could join this project to contribute.
>
>       Thanks,
>       Sekhar
>
>
>
> Is this project good also for dm365?

Hmm, right. I can only find DM355 files here.
DM365 seems missing. Not sure if the files
just aren't showing up or DM365 support is
yet to be added. Let me ask around.

Thanks,
Sekhar


From pratik.joshi at einfochips.com  Wed May  5 01:20:14 2010
From: pratik.joshi at einfochips.com (pratik.joshi)
Date: Wed, 5 May 2010 11:50:14 +0530
Subject: USB driver issue in 2.6.33.2 kernel
Message-ID: <001d01caec1b$0663b3f0$132b1bd0$@joshi@einfochips.com>

Hi All,

 

I am working on integrating wireless USB dongle. I have configured USB
driver to operate in DMA mode. I am working with DVEVM. 

 

Problem statement:

 

As soon as wireless device is up and associated, following errors start
coming.

 

musb_host_rx 1531: RX2 dma busy, csr 2000

musb_host_rx 1531: RX2 dma busy, csr 2020

musb_host_rx 1531: RX2 dma busy, csr 2203

musb_host_rx 1531: RX2 dma busy, csr 2000

musb_host_rx 1531: RX2 dma busy, csr 2000

musb_host_rx 1531: RX2 dma busy, csr 2200

musb_host_rx 1531: RX2 dma busy, csr 2220

BIRIdx(5): RXDMALen not multiple of 4.[6162], BulkInBufLen = 8024)

musb_host_rx 1531: RX2 dma busy, csr 2000

musb_host_rx 1531: RX2 dma busy, csr 2200

musb_host_rx 1531: RX2 dma busy, csr 2000

musb_host_rx 1531: RX2 dma busy, csr 2200

musb_host_rx 1531: RX2 dma busy, csr 2003

musb_host_rx 1531: RX2 dma busy, csr 2003

musb_host_rx 1531: RX2 dma busy, csr 2000

musb_host_rx 1531: RX2 dma busy, csr 2200

musb_host_rx 1531: RX2 dma busy, csr 2220

musb_host_rx 1531: RX2 dma busy, csr 2203

musb_host_rx 1531: RX2 dma busy, csr 2000

musb_host_rx 1531: RX2 dma busy, csr 2020

musb_host_rx 1531: RX2 dma busy, csr 2000

musb_host_rx 1531: RX2 dma busy, csr 2200

musb_host_rx 1531: RX2 dma busy, csr 2000

musb_host_rx 1531: RX2 dma busy, csr 2003

musb_host_rx 1531: RX2 dma busy, csr 2020

musb_host_rx 1531: RX2 dma busy, csr 2000

musb_host_rx 1531: RX2 dma busy, csr 2000

musb_host_rx 1531: RX2 dma busy, csr 2203

musb_host_rx 1531: RX2 dma busy, csr 2000

musb_host_rx 1531: RX2 dma busy, csr 2003

musb_host_rx 1531: RX2 dma busy, csr 2200

musb_host_rx 1531: RX2 dma busy, csr 2200

musb_host_rx 1531: RX2 dma busy, csr 2003

musb_host_rx 1531: RX2 dma busy, csr 2203

musb_host_rx 1531: RX2 dma busy, csr 2003

musb_host_rx 1531: RX2 dma busy, csr 2200

musb_host_rx 1531: RX2 dma busy, csr 2200

musb_host_rx 1531: RX2 dma busy, csr 2200

musb_host_rx 1531: RX2 dma busy, csr 2020

ERROR!!! MlmeEnqueueForRecv: un-recongnized mgmt->subtype=6

musb_host_rx 1531: RX2 dma busy, csr 2200

musb_host_rx 1531: RX2 dma busy, csr 2200

musb_host_rx 1531: RX2 dma busy, csr 2000

BIRIdx(1): RXDMALen not multiple of 4.[255], BulkInBufLen = 7668)

musb_host_rx 1531: RX2 dma busy, csr 2003

musb_host_rx 1531: RX2 dma busy, csr 2203

musb_host_rx 1531: RX2 dma busy, csr 2203

musb_host_rx 1531: RX2 dma busy, csr 2203

 

Any clue what's wrong? 

 

Regards,

Pratik

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From nsekhar at ti.com  Wed May  5 04:32:00 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Wed, 5 May 2010 15:02:00 +0530
Subject: [PATCH 1/4] DM365: Make all SPI units SPI0..SPI4 available
In-Reply-To: <1272993504-1189-2-git-send-email-thomas.koeller@baslerweb.com>
References: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
	<1272993504-1189-2-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6D3D34F@dbde02.ent.ti.com>


Hi Thomas,

On Tue, May 04, 2010 at 22:48:21, thomas.koeller at baslerweb.com wrote:
> From: Thomas Koeller <thomas.koeller at baslerweb.com>
>
> Change the SPI setup code to allow use of all SPI units. Also,
> move some resource assignments (DMA channels, interrupts)
> to the board code, where they belong. These really should not
> be hard-coded in dm365.c.
>
> The spi setup stuff has been moved to a separate file
> 'arch/arm/mach-davinci/dm365_spi.c' to increase modularity.
> I am not currently able to address the DM355, but it should be
> easy to write a dm355_spi.c file.
>
> Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
> ---
>  arch/arm/mach-davinci/Makefile             |    2 +-
>  arch/arm/mach-davinci/board-dm365-evm.c    |   47 ++++-
>  arch/arm/mach-davinci/dm365.c              |   68 -------
>  arch/arm/mach-davinci/dm365_spi.c          |  276 ++++++++++++++++++++++++++++
>  arch/arm/mach-davinci/include/mach/dm365.h |    5 +-
>  arch/arm/mach-davinci/spi.h                |   35 ++++
>  6 files changed, 350 insertions(+), 83 deletions(-)
>  create mode 100644 arch/arm/mach-davinci/dm365_spi.c
>  create mode 100644 arch/arm/mach-davinci/spi.h
>
> diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
> index f6c7e4c..b9c497c 100644
> --- a/arch/arm/mach-davinci/Makefile
> +++ b/arch/arm/mach-davinci/Makefile
> @@ -32,6 +32,6 @@ obj-$(CONFIG_MACH_SFFSDR)           += board-sffsdr.o
>  obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
>  obj-$(CONFIG_MACH_DM355_LEOPARD)     += board-dm355-leopard.o
>  obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)        += board-dm646x-evm.o cdce949.o
> -obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
> +obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o dm365_spi.o
>  obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
>  obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
> diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
> index ab3b0e2..96dd72f 100644
> --- a/arch/arm/mach-davinci/board-dm365-evm.c
> +++ b/arch/arm/mach-davinci/board-dm365-evm.c
> @@ -49,6 +49,8 @@
>  #include <media/tvp7002.h>
>  #include <media/davinci/videohd.h>
>
> +#include "spi.h"
> +
>
>
>  /* have_imager() - Check if we have support for imager interface */
> @@ -337,18 +339,18 @@ static struct i2c_driver pca9543a_driver = {
>  static void dm365evm_reset_imager(int rst)
>  {
>       u8 val;
> -
> +
>       /* Reset bit6 of CPLD_IMG_DIR2 */
>       val = __raw_readb(cpld + CPLD_IMG_DIR2) & ~BIT(6);
> -     __raw_writeb(val, (cpld + CPLD_IMG_DIR2));
> +     __raw_writeb(val, (cpld + CPLD_IMG_DIR2));
>
>       /* Set bit5 of CPLD_IMG_MUX5 */
>       val = __raw_readb(cpld + CPLD_IMG_MUX5) | BIT(5);
> -     __raw_writeb(val, (cpld + CPLD_IMG_MUX5));
> +     __raw_writeb(val, (cpld + CPLD_IMG_MUX5));
>
>       /* Reset bit 0 of CPLD_IMG_MUX5 */
>       val = __raw_readb(cpld + CPLD_IMG_MUX5) & ~BIT(0);
> -     __raw_writeb(val, (cpld + CPLD_IMG_MUX5));
> +     __raw_writeb(val, (cpld + CPLD_IMG_MUX5));
>
>       /**
>        * Configure GPIO40 to be output and high. This has dependency on MMC1
> @@ -375,7 +377,7 @@ static int dm365evm_enable_pca9543a(int en)
>                       .buf = &val,
>               };
>
> -     printk("dm365evm_enable_pca9543a\n");
> +     printk("dm365evm_enable_pca9543a\n");

These look like white space changes unrelated to this patch.
If the original code has whitespace issues, that should be
fixed in another patch that precedes this one.

>       if (!en)
>               val = 0;
>
> @@ -385,7 +387,7 @@ static int dm365evm_enable_pca9543a(int en)
>       msg.addr = pca9543a->addr;
>       /* turn i2c switch, pca9543a, on/off */
>       status = i2c_transfer(pca9543a->adapter, &msg, 1);
> -     printk("dm365evm_enable_pca9543a, status = %d\n", status);
> +     printk("dm365evm_enable_pca9543a, status = %d\n", status);

White space change again.

>       return status;
>       return 0;
>  }
> @@ -832,7 +834,7 @@ static struct spi_eeprom at25640 = {
>       .flags          = EE_ADDR2,
>  };
>
> -static struct spi_board_info dm365_evm_spi_info[] __initconst = {
> +static const struct spi_board_info dm365_evm_spi_info[] __initconst = {

Making this const might be the right thing to do, but is unrelated to
the subject or description.

>       {
>               .modalias       = "at25",
>               .platform_data  = &at25640,
> @@ -840,9 +842,32 @@ static struct spi_board_info dm365_evm_spi_info[] __initconst = {
>               .bus_num        = 0,
>               .chip_select    = 0,
>               .mode           = SPI_MODE_0,
> -     },
> +     }

Why remove the ',' ?

> +};
> +
> +static struct davinci_spi_unit_desc dm365_evm_spi_udesc_at25 = {
> +     .spi_hwunit     = 0,
> +     .chipsel        = BIT(0),
> +     .irq            = IRQ_DM365_SPIINT0_0,
> +     .dma_tx_chan    = 16,
> +     .dma_rx_chan    = 17,
> +     .dma_evtq       = EVENTQ_3,
> +     .pdata          = {
> +             .version        = SPI_VERSION_1,
> +             .num_chipselect = 2,
> +             .clk_internal   = 1,
> +             .cs_hold        = 1,
> +             .intr_level     = 0,
> +             .poll_mode      = 1,    /* 0 -> interrupt mode 1-> polling mode */
> +             .use_dma        = 1,    /* when 1, value in poll_mode is ignored */
> +             .c2tdelay       = 0,
> +             .t2cdelay       = 0
> +     }
>  };
>
> +
> +
> +

Unnecessary empty lines.

>  static __init void dm365_evm_init(void)
>  {
>       evm_init_i2c();
> @@ -861,8 +886,10 @@ static __init void dm365_evm_init(void)
>       dm365_init_rtc();
>       dm365_init_ks(&dm365evm_ks_data);
>
> -     dm365_init_spi0(BIT(0), dm365_evm_spi_info,
> -                     ARRAY_SIZE(dm365_evm_spi_info));
> +     davinci_init_spi(&dm365_evm_spi_udesc_at25,
> +                      ARRAY_SIZE(dm365_evm_spi_info),
> +                      dm365_evm_spi_info);
> +     return;
>  }
>
>  static __init void dm365_evm_irq_init(void)
> diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
> index ed6c9c7..30c2327 100644
> --- a/arch/arm/mach-davinci/dm365.c
> +++ b/arch/arm/mach-davinci/dm365.c
> @@ -616,74 +616,6 @@ EVT_CFG(DM365,   EVT3_ASP_RX,         1,     1,    0,     false)
>  #endif
>  };
>
> -static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
> -
> -static struct davinci_spi_platform_data dm365_spi0_pdata = {
> -     .version        = SPI_VERSION_1,
> -     .num_chipselect = 2,
> -     .clk_internal   = 1,
> -     .cs_hold        = 1,
> -     .intr_level     = 0,
> -     .poll_mode      = 1,    /* 0 -> interrupt mode 1-> polling mode */
> -     .use_dma        = 1,    /* when 1, value in poll_mode is ignored */
> -     .c2tdelay       = 0,
> -     .t2cdelay       = 0,
> -};
> -
> -static struct resource dm365_spi0_resources[] = {
> -     {
> -             .start = 0x01c66000,
> -             .end   = 0x01c667ff,
> -             .flags = IORESOURCE_MEM,
> -     },
> -     {
> -             .start = IRQ_DM365_SPIINT0_0,
> -             .flags = IORESOURCE_IRQ,
> -     },
> -     {
> -             .start = 17,
> -             .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
> -     },
> -     {
> -             .start = 16,
> -             .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
> -     },
> -     {
> -             .start = EVENTQ_3,
> -             .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
> -     },

Have you based your code on the latest of Kevin's tree?
I don't see the additional IORESOURCE_DMA_* flags in the
current tree.

> -};
> -
> -static struct platform_device dm365_spi0_device = {
> -     .name = "spi_davinci",
> -     .id = 0,
> -     .dev = {
> -             .dma_mask = &dm365_spi0_dma_mask,
> -             .coherent_dma_mask = DMA_BIT_MASK(32),
> -             .platform_data = &dm365_spi0_pdata,
> -     },
> -     .num_resources = ARRAY_SIZE(dm365_spi0_resources),
> -     .resource = dm365_spi0_resources,
> -};
> -
> -void __init dm365_init_spi0(unsigned chipselect_mask,
> -             struct spi_board_info *info, unsigned len)
> -{
> -     davinci_cfg_reg(DM365_SPI0_SCLK);
> -     davinci_cfg_reg(DM365_SPI0_SDI);
> -     davinci_cfg_reg(DM365_SPI0_SDO);
> -
> -     /* not all slaves will be wired up */
> -     if (chipselect_mask & BIT(0))
> -             davinci_cfg_reg(DM365_SPI0_SDENA0);
> -     if (chipselect_mask & BIT(1))
> -             davinci_cfg_reg(DM365_SPI0_SDENA1);
> -
> -     spi_register_board_info(info, len);
> -
> -     platform_device_register(&dm365_spi0_device);
> -}
> -
>
>  /* IPIPEIF device configuration */
>  static u64 dm365_ipipeif_dma_mask = DMA_BIT_MASK(32);
> diff --git a/arch/arm/mach-davinci/dm365_spi.c b/arch/arm/mach-davinci/dm365_spi.c
> new file mode 100644
> index 0000000..e1743d7
> --- /dev/null
> +++ b/arch/arm/mach-davinci/dm365_spi.c
> @@ -0,0 +1,276 @@
> +/*
> + * TI DaVinci DM3xx SPI setup
> + *
> + * Copyright (C) 2010 Basler Vision Technologies AG
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/dma-mapping.h>
> +#include <linux/platform_device.h>
> +#include <linux/ioport.h>
> +#include <linux/spi/spi.h>
> +#include <mach/mux.h>
> +
> +#include "spi.h"
> +
> +static u64 davinci_spi_dma_mask = DMA_BIT_MASK(32);
> +
> +enum davinci_spi_resource_index {
> +     spirsrc_iomem,
> +     spirsrc_irq,
> +     spirsrc_rxdma,
> +     spirsrc_txdma,
> +     spirsrc_evqdma
> +};
> +
> +

Unnecessary empty lines.

> +static struct resource davinci_spi_resources[spirsrc_evqdma + 1][5] = {
> +     {
> +             [spirsrc_iomem] = {
> +                     .start  = 0x01c66000,
> +                     .end    = 0x01c667ff,
> +                     .flags  = IORESOURCE_MEM,
> +             },
> +             [spirsrc_irq] = {
> +                     .flags  = IORESOURCE_IRQ,
> +             },
> +             [spirsrc_rxdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
> +             },
> +             [spirsrc_txdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
> +             },
> +             [spirsrc_evqdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,

I guess these are made board specific because of the
INT_MUX and EDMA_MUX logic on DM365. However, instead
of forcing this to be passed from the board file for all
SPI instances, you can statically initialize what is fixed
while allowing the board to override the defaults by passing
a structure which could be NULL in case the board is happy
with the SoC defaults.

This way EVENT_Q can be defaulted to EVENTQ_DEFAULT as well,
and the board has an option to change that in case of a special
use case.

> +             }

Need a ',' for the last element of static initialization.
There are other places in the patch that need this change.

> +     },
> +     {
> +             [spirsrc_iomem] = {
> +                     .start  = 0x01c66800,
> +                     .end    = 0x01c66fff,
> +                     .flags  = IORESOURCE_MEM,
> +             },
> +             [spirsrc_irq] = {
> +                     .flags  = IORESOURCE_IRQ,
> +             },
> +             [spirsrc_rxdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
> +             },
> +             [spirsrc_txdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
> +             },
> +             [spirsrc_evqdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
> +             }
> +     },
> +     {
> +             [spirsrc_iomem] = {
> +                     .start  = 0x01c67800,
> +                     .end    = 0x01c67fff,
> +                     .flags  = IORESOURCE_MEM,
> +             },
> +             [spirsrc_irq] = {
> +                     .flags  = IORESOURCE_IRQ,
> +             },
> +             [spirsrc_rxdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
> +             },
> +             [spirsrc_txdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
> +             },
> +             [spirsrc_evqdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
> +             }
> +     },
> +     {
> +             [spirsrc_iomem] = {
> +                     .start  = 0x01c68000,
> +                     .end    = 0x01c687ff,
> +                     .flags  = IORESOURCE_MEM,
> +             },
> +             [spirsrc_irq] = {
> +                     .flags  = IORESOURCE_IRQ,
> +             },
> +             [spirsrc_rxdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
> +             },
> +             [spirsrc_txdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
> +             },
> +             [spirsrc_evqdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
> +             }
> +     },
> +     {
> +             [spirsrc_iomem] = {
> +                     .start  = 0x01c23000,
> +                     .end    = 0x01c237ff,
> +                     .flags  = IORESOURCE_MEM,
> +             },
> +             [spirsrc_irq] = {
> +                     .flags  = IORESOURCE_IRQ,
> +             },
> +             [spirsrc_rxdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
> +             },
> +             [spirsrc_txdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
> +             },
> +             [spirsrc_evqdma] = {
> +                     .flags  = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
> +             }
> +     }
> +};
> +
> +static struct platform_device davinci_spi_device[] = {
> +     {
> +             .name = "spi_davinci",
> +             .id = 0,
> +             .dev = {
> +                     .dma_mask = &davinci_spi_dma_mask,
> +                     .coherent_dma_mask = DMA_BIT_MASK(32),
> +             },
> +             .num_resources = ARRAY_SIZE(davinci_spi_resources[0]),
> +             .resource = davinci_spi_resources[0]
> +     },
> +     {
> +             .name = "spi_davinci",
> +             .id = 1,
> +             .dev = {
> +                     .dma_mask = &davinci_spi_dma_mask,
> +                     .coherent_dma_mask = DMA_BIT_MASK(32),
> +             },
> +             .num_resources = ARRAY_SIZE(davinci_spi_resources[1]),
> +             .resource = davinci_spi_resources[1]
> +     },
> +     {
> +             .name = "spi_davinci",
> +             .id = 2,
> +             .dev = {
> +                     .dma_mask = &davinci_spi_dma_mask,
> +                     .coherent_dma_mask = DMA_BIT_MASK(32),
> +             },
> +             .num_resources = ARRAY_SIZE(davinci_spi_resources[2]),
> +             .resource = davinci_spi_resources[2]
> +     },
> +     {
> +             .name = "spi_davinci",
> +             .id = 3,
> +             .dev = {
> +                     .dma_mask = &davinci_spi_dma_mask,
> +                     .coherent_dma_mask = DMA_BIT_MASK(32),
> +             },
> +             .num_resources = ARRAY_SIZE(davinci_spi_resources[3]),
> +             .resource = davinci_spi_resources[3]
> +     },
> +     {
> +             .name = "spi_davinci",
> +             .id = 4,
> +             .dev = {
> +                     .dma_mask = &davinci_spi_dma_mask,
> +                     .coherent_dma_mask = DMA_BIT_MASK(32),
> +             },
> +             .num_resources = ARRAY_SIZE(davinci_spi_resources[4]),
> +             .resource = davinci_spi_resources[4]
> +     }
> +};

> +
> +struct davinci_spi_pins {
> +     int     sclk;
> +     int     sdi;
> +     int     sdo;
> +     int     sdena0;
> +     int     sdena1;
> +};
> +
> +static const struct davinci_spi_pins davinci_spi_pinmap[] __initconst = {
> +     {
> +             .sclk   = DM365_SPI0_SCLK,
> +             .sdi    = DM365_SPI0_SDI,
> +             .sdo    = DM365_SPI0_SDO,
> +             .sdena0 = DM365_SPI0_SDENA0,
> +             .sdena1 = DM365_SPI0_SDENA1
> +     },
> +     {
> +             .sclk   = DM365_SPI1_SCLK,
> +             .sdi    = DM365_SPI1_SDI,
> +             .sdo    = DM365_SPI1_SDO,
> +             .sdena0 = DM365_SPI1_SDENA0,
> +             .sdena1 = DM365_SPI1_SDENA1
> +     },
> +     {
> +             .sclk   = DM365_SPI2_SCLK,
> +             .sdi    = DM365_SPI2_SDI,
> +             .sdo    = DM365_SPI2_SDO,
> +             .sdena0 = DM365_SPI2_SDENA0,
> +             .sdena1 = DM365_SPI2_SDENA1
> +     },
> +     {
> +             .sclk   = DM365_SPI3_SCLK,
> +             .sdi    = DM365_SPI3_SDI,
> +             .sdo    = DM365_SPI3_SDO,
> +             .sdena0 = DM365_SPI3_SDENA0,
> +             .sdena1 = DM365_SPI3_SDENA1
> +     },
> +     {
> +             .sclk   = DM365_SPI4_SCLK,
> +             .sdi    = DM365_SPI4_SDI,
> +             .sdo    = DM365_SPI4_SDO,
> +             .sdena0 = DM365_SPI4_SDENA0,
> +             .sdena1 = DM365_SPI4_SDENA1
> +     }
> +};

Having a structure for defining the list of pins
may be an overkill. A pinlist array of the sort
DA8xx code uses should be good enough. The SoC
code can provide the list of mandatory pins and
the board can provide another set of board specific
pins. Cyril's patch [1] adding a davinci_cfg_reg_list()
API should help here.

[1] http://www.mail-archive.com/davinci-linux-open-source at linux.davincidsp.com/msg17182.html

> +
> +void __init davinci_init_spi(struct davinci_spi_unit_desc *unit,
> +                     unsigned int ninfo,
> +                     const struct spi_board_info *info)
> +{
> +     int err;
> +     const unsigned int hwunit = unit->spi_hwunit;
> +     const struct davinci_spi_pins * const pins = &davinci_spi_pinmap[hwunit];
> +     struct platform_device * const pdev = &davinci_spi_device[hwunit];
> +     struct davinci_spi_platform_data * const pdata = &unit->pdata;
> +
> +     davinci_cfg_reg(pins->sclk);
> +     davinci_cfg_reg(pins->sdi);
> +     davinci_cfg_reg(pins->sdo);
> +
> +     /* not all slaves will be wired up */
> +     if (unit->chipsel & BIT(0))
> +             davinci_cfg_reg(pins->sdena0);
> +     if (unit->chipsel & BIT(1))
> +             davinci_cfg_reg(pins->sdena1);
> +
> +     pdev->dev.platform_data = pdata;
> +
> +     pdev->resource[spirsrc_irq].start =
> +     pdev->resource[spirsrc_irq].end = unit->irq;
> +     pdev->resource[spirsrc_rxdma].start =
> +     pdev->resource[spirsrc_rxdma].end = unit->dma_rx_chan;
> +     pdev->resource[spirsrc_txdma].start =
> +     pdev->resource[spirsrc_txdma].end = unit->dma_tx_chan;
> +     pdev->resource[spirsrc_evqdma].start =
> +     pdev->resource[spirsrc_evqdma].end = unit->dma_evtq;
> +
> +     pr_debug("Creating SPI%u: irq = %u, dma_rx = %u, dma_tx = %u, "
> +             "dma_evq = %u",
> +             hwunit, unit->irq, unit->dma_rx_chan, unit->dma_tx_chan,
> +             unit->dma_evtq);
> +
> +     err = platform_device_register(pdev);
> +     if (unlikely(err))
> +             pr_err("Failed to create platform device for SPI%u - error %d",
> +                     hwunit, err);

Should bail out here.

> +
> +     spi_register_board_info(info, ninfo);
> +}
> +
> +
> diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
> index 44b0cc6..6b48f89 100644
> --- a/arch/arm/mach-davinci/include/mach/dm365.h
> +++ b/arch/arm/mach-davinci/include/mach/dm365.h
> @@ -19,6 +19,7 @@
>  #include <mach/emac.h>
>  #include <mach/asp.h>
>  #include <mach/keyscan.h>
> +#include <mach/spi.h>
>
>  #define DM365_EMAC_BASE                      (0x01D07000)
>  #define DM365_EMAC_CNTRL_OFFSET              (0x0000)
> @@ -38,8 +39,4 @@ void __init dm365_init_rtc(void);
>  void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
>  void dm365_set_vpfe_config(struct vpfe_config *cfg);
>
> -struct spi_board_info;
> -void dm365_init_spi0(unsigned chipselect_mask,
> -             struct spi_board_info *info, unsigned len);
> -
>  #endif /* __ASM_ARCH_DM365_H */
> diff --git a/arch/arm/mach-davinci/spi.h b/arch/arm/mach-davinci/spi.h
> new file mode 100644
> index 0000000..df5bb80
> --- /dev/null
> +++ b/arch/arm/mach-davinci/spi.h
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright (C) 2010 Basler Vision Technologies AG
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#ifndef __MACH_DAVINCI_SPI_H
> +#define __MACH_DAVINCI_SPI_H
> +
> +#include <mach/spi.h>
> +
> +struct davinci_spi_unit_desc {
> +     unsigned int                            spi_hwunit;
> +     unsigned int                            chipsel;
> +     unsigned int                            irq;
> +     unsigned int                            dma_tx_chan;
> +     unsigned int                            dma_rx_chan;
> +     unsigned int                            dma_evtq;


Please revisit this to allow SoCs with fixed IRQ/EDMA
resources not to push the definitions to the board files.

Thanks,
Sekhar


From nsekhar at ti.com  Wed May  5 04:35:23 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Wed, 5 May 2010 15:05:23 +0530
Subject: [PATCH 3/4] DAVINCI: Added missing includes
In-Reply-To: <1272993504-1189-4-git-send-email-thomas.koeller@baslerweb.com>
References: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
	<1272993504-1189-4-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6D3D35B@dbde02.ent.ti.com>

On Tue, May 04, 2010 at 22:48:23, thomas.koeller at baslerweb.com wrote:
> From: Thomas Koeller <thomas.koeller at baslerweb.com>
>
> linux/compiler.h is required for __iomem
> linux/types.h is required u32
>
> Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>

Looks like this is already applied by Kevin.
You can drop this from your series now :)

Thanks,
Sekhar


From jtobias at viaas.com  Wed May  5 17:23:10 2010
From: jtobias at viaas.com (John Tobias)
Date: Wed, 5 May 2010 15:23:10 -0700
Subject: UBL Question
In-Reply-To: <y2k66b2b2311005041836se6b5de0chbfc7ef4babbbdb49@mail.gmail.com>
References: <o2o66b2b2311004301114m5992da85s156d0ace0e3afec1@mail.gmail.com>
	<E7D5CF88-E988-43FF-B15E-840475F51482@dsicentral.com>
	<s2r66b2b2311004301519pf2622273x53e09e53d1a24853@mail.gmail.com>
	<201005020952.59981.caglarakyuz@gmail.com>
	<y2k66b2b2311005041836se6b5de0chbfc7ef4babbbdb49@mail.gmail.com>
Message-ID: <m2r66b2b2311005051523v9eeab67ax3bd8a0f818f00496@mail.gmail.com>

Hi Caglar,

I got it working.
Here's what I did. I re-program my device and write the UBL image from block
1 to block5 using DVFlasher.
Then, I booted my device, call nanddump -n to get an image of each block and
save it to a file.

Then, I can use nandwrite -n -o to write the image on the block. But,
there's one rule to follow, the UBL image should be written to the correct
destination block. For example, If the image came from block3, it should be
written to block3,  image4 should be on block4 and so on.

Thanks,

John




>
> Caglar,
>
> In sprue20c <http://www-s.ti.com/sc/techlit/sprue20.pdf> documentation,
> discusses the 3 types of mode. One of them is the NAND Flash mode, which is
> the mode  to function the NAND Flash ECC generator.
>
> My question is, if the device is running linux, what mode does the NAND
> is?.
>
> I am start playing to add some routines in nand drivers and see how far I
> can go. But, need additional information and maybe you can help me.
>
> 1. Do you know how the ubl data laid out on the block?.
> 2.The ubl image should not exist 0x3800 bytes and seems DVFlasher removes
> some Srec. Do you know what was the reason?.
>
>
> Best Regards,
>
> John
>
>
> On Sat, May 1, 2010 at 11:52 PM, Caglar Akyuz <caglarakyuz at gmail.com>
> wrote:
>
> > On Saturday 01 May 2010 01:19:56 am John Tobias wrote:
> > > I've used the following commands and didn't get any success.
> > >
> > > 1. nanddump -n -f /ubl.bin /dev/mtd5
> > > Block size 16384, page size 512, OOB size 16
> > > Dumping data starting at 0x00000000 and ending at 0x00004000
> > >
> > > 2. flash_erase /dev/mtd1
> > >
> > > 3. nandwrite -n -o /dev/mtd1 /ubl.bin
> > >
> > > 4. flash_erase /dev/mtd5
> > >
> > > Any more idea?
> > >
> >
> > AFAIK, rbl/ubl pair uses different ECC layout than u-boot/Linux pair. For
> > instance, I do not use u-boot in some cases and boot Linux directly from
> > UBL
> > in which I write Linux to NAND from userspace. In those cases, I read
> Linux
> > without any ECC in UBL. But you do not have any access to RBL so you
> cannot
> > program UBL from userspace without changing Linux ECC handling.
> >
> > Best Regards,
> > Caglar
> >
> > > Thanks,
> > >
> > > John
> > >
> > > On Fri, Apr 30, 2010 at 2:57 PM, Siddharth Choudhuri
> > <sid at dsicentral.com>wrote:
> > > > Does dd also take care of writing the OOB area along with the actual
> > data
> > > > ? The OOB layout where the ECC is written could be an issue IMO. You
> > > > might want to look at nandwrite i.e., read using nanddump -> erase ->
> > > > nandwrite to see if it works. Also, nanddump and nandwrite might have
> > an
> > > > option to read page data and/or OOB.
> > > >
> > > > -sid
> > > >
> > > > On Apr 30, 2010, at 1:15 PM, John Tobias wrote:
> > > >
> > > > Hi Mike,
> > > >
> > > > I've used this two commands to copy the image on block 5 then, copy
> it
> > > > over to block 1.
> > > >
> > > > dd if=/dev/mtd5 of=/ubl.bin bs=512 count=32
> > > > dd if=/ubl.bin of=/dev/mtd1 bs=512 count=32
> > > > (My NAND flash has 512 bytes per page with 32 pages per block or
> > 16Kbytes
> > > > in  1 block).
> > > >
> > > > In order to test the block 1 if it's working, I erased the block 5
> and
> > > > boot my device but, it doesn't work.
> > > >
> > > > Any idea?
> > > >
> > > > Thanks,
> > > >
> > > > John
> > > >
> > > > On Fri, Apr 30, 2010 at 11:51 AM, John Tobias <jtobias at viaas.com>
> > wrote:
> > > >> Hi Mike,
> > > >>
> > > >> Yes, that's my plan. I will expose the ubl blocks from linux
> userspace
> > > >> and become writable.
> > > >> And, I like the idea of using dd so no need to worry about the CRC
> > > >> issue.
> > > >>
> > > >> Thanks,
> > > >>
> > > >> John
> > > >>
> > > >> On Fri, Apr 30, 2010 at 11:34 AM, Mike Williamson <
> > > >>
> > > >> michael.williamson at criticallink.com> wrote:
> > > >>> Hi John,
> > > >>>
> > > >>> In the past, we've used the /dev/mtd* devices to write data back to
> > NOR
> > > >>> (spi / parallel) devices for updating firmware using something
> like:
> > > >>>
> > > >>> dd if=newimage.bin of=/dev/mtd0
> > > >>>
> > > >>> Of course, you need to have your kernel configured to have the mtd
> > > >>> drivers loaded and you need to make these areas writable (most
> linux
> > > >>> board packages set these to read-only, given the sizeable gun you
> > have
> > > >>> pointed at your shoes....)
> > > >>>
> > > >>> -Mike
> > > >>>
> > > >>> On Fri, Apr 30, 2010 at 2:14 PM, John Tobias <jtobias at viaas.com>
> > wrote:
> > > >>>> Hi,
> > > >>>>
> > > >>>> Does anyone successfully written the UBL image in block 1/5 from
> > linux
> > > >>>> userspace? I need a way to write the ubl image for the firmware
> > > >>>> upgrade and the only access that I have is the linux userspace.
> > > >>>>
> > > >>>>
> > > >>>> Thanks,
> > > >>>>
> > > >>>> John
> > > >>>>
> > > >>>> _______________________________________________
> > > >>>> Davinci-linux-open-source mailing list
> > > >>>> Davinci-linux-open-source at linux.davincidsp.com
> > > >>>>
> > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> > > >>>
> > > >>> --
> > > >>> Michael Williamson
> > > >>> 315-425-4045x230
> > > >>> www.criticallink.com
> > > >
> > > > _______________________________________________
> > > > Davinci-linux-open-source mailing list
> > > > Davinci-linux-open-source at linux.davincidsp.com
> > > >
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> > >
> >
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> >
>
> ------------------------------
>
> Message: 4
> Date: Tue, 04 May 2010 20:03:46 -0700
> From: Jimmy Blair <blueskyjb at roadrunner.com>
> To: davinci-linux-open-source at linux.davincidsp.com
> Subject: DM365 audio -- bad PLL setting in tlv320aic3x driver
> Message-ID: <4BE0E012.1030406 at roadrunner.com>
> Content-Type: text/plain; charset=ISO-8859-1; format=flowed
>
> 44100 Hz audio plays slightly fast on the DM365.
> This is because the tlv320aic3x driver is calculating
> invalid PLL parameters for the WCLK.  The parameters
> it calculates are:
>
> pll_p = 1, pll_r = 1, pll_j = 3, pll_d = 3450
>
> According to the codec datasheet, the value of J
> should be greater than 3.  The datasheet is correct.
> The WCLK signal is unstable, bouncing between 44200 and 44500 Hz.
>
> I recalculated the parameters by hand, setting P to 2
> and got the following values:
>
> pll_p = 2, pll_r = 1, pll_j = 6, pll_d = 6901
>
> These values gave a clean 44100 WCLK.
>
>
> ------------------------------
>
> Message: 5
> Date: Wed, 5 May 2010 10:59:47 +0530
> From: "Nori, Sekhar" <nsekhar at ti.com>
> To: Raffaele Recalcati <lamiaposta71 at gmail.com>
> Cc: "Cobb, Jeff" <jcobb at ti.com>,        davinci-linux-open-source
>        <davinci-linux-open-source at linux.davincidsp.com>,       "Allred,
> Daniel"
>        <d-allred at ti.com>
> Subject: RE: UBL Question
> Message-ID:
>        <B85A65D85D7EB246BE421B3FB0FBB59301E6D3D096 at dbde02.ent.ti.com>
> Content-Type: text/plain; charset="iso-8859-1"
>
> Hi Raffaele,
>
> On Tue, May 04, 2010 at 14:32:31, Raffaele Recalcati wrote:
> > Hi Nori,
> >
> >
> >
> >       There is a sourceforge project for UBL and serial flashing
> > tools:
> >
> >       http://sourceforge.net/projects/dvflashutils/
> >
> >       You could join this project to contribute.
> >
> >       Thanks,
> >       Sekhar
> >
> >
> >
> > Is this project good also for dm365?
>
> Hmm, right. I can only find DM355 files here.
> DM365 seems missing. Not sure if the files
> just aren't showing up or DM365 support is
> yet to be added. Let me ask around.
>
> Thanks,
> Sekhar
>
>
>
> ------------------------------
>
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>
>
> End of Davinci-linux-open-source Digest, Vol 53, Issue 17
> *********************************************************
>
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From jaya.krishnan at samsung.com  Wed May  5 18:08:53 2010
From: jaya.krishnan at samsung.com (Jaya krishnan)
Date: Wed, 05 May 2010 23:08:53 +0000 (GMT)
Subject: DM6467 McASP
Message-ID: <27286074.508171273100933507.JavaMail.weblogic@epml17>



 
Hi  Vaibhav,
Thanks  for the  reply. I have to  use AHCLKX1 as HF  clock  to  another chip.No other option.
But  I am worried  about  the  synchronisation between AUXCLK  to port 0  and  port 1.
Any  comments?
Regards
JK

------- Original Message-------
Sender: Bedia, Vaibhav<vaibhav.bedia at ti.com>
Date: May 04, 2010 21:38 (GMT+09:00)
Title: RE: DM6467 McASP

Jayakrishnan, 

The McASP transmit bit clock, ACLKX can be either externally sourced or internally generated.  

In case ALCLKX is internally generated from AUXCLK, then you have the option of sending the intermediate high frequency master clock (AHCLKX) to the AHCLKX pin to be used by other devices in the system. In such a situation you don't need to use the 2nd McASP just for generating AHCLKX. 

However, if your use-case needs two McASPs that can also be done as both can be used simultaneously. 

Regards, 
Vaibhav 

-----Original Message----- 
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Jaya krishnan 
Sent: Tuesday, May 04, 2010 1:44 PM 
To: davinci-linux-open-source at linux.davincidsp.com 
Subject: DM6467 McASP 


Hi  , 
I want  to use McASP  port  0 for  transmit data  and port 1  to  generate high frequency clock (AHCLKX) (to be used as  master clock for  another audio DAC  in the  system.)  Is there  any  limitation to use  both  ports  simultaneously?Pls  reply 
Regards 
JK 

  
     
Jayakrishnan M M 
Research Engineer 
R&D Team-2 , Group-5 
Security Solutions  Division 
SAMSUNG TECHWIN CO.,LTD 

TEL +82-70-7147-8482 
FAX +82-31-8018-3712 
Mobile +82-10-6409-3619 
E-mail:jaya.krishnan at samsung.com 
  
   
_______________________________________________ 
Davinci-linux-open-source mailing list 
Davinci-linux-open-source at linux.davincidsp.com 
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source 

 
    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  
 
 

From ng at max01.eu  Thu May  6 02:10:20 2010
From: ng at max01.eu (ng at max01.eu)
Date: Thu, 6 May 2010 09:10:20 +0200 (CEST)
Subject: How to set priorities for VGA on OMAP-L1xx on Linux 2.6.34-rc5 ?
Message-ID: <1721130017.845189.1273129820479.JavaMail.open-xchange@oxltgw14.schlund.de>

Hello

we try to get a VGA-TFT-Display running on a OMAP-L138 exp-board with a Linux
2.6.34-rc5 GIT-kernel
(url = git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git).
This kernel is patched to get our display running.

The linux-logo after bootup is fine so far, but when starting a graphic
application there is some trouble
(the screen is not centered).

We noticed the article http://processors.wiki.ti.com/index.php/OMAP-L1x_VGA
(Modifications for LCD driver to support VGA mode ).

We still raised the LCD interrupt priority slightly:

--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -705,7 +705,7 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
??????? [IRQ_DA8XX_GPIO7]?????????????? = 7,
??????? [IRQ_DA8XX_GPIO8]?????????????? = 7,
??????? [IRQ_DA8XX_I2CINT1]???????????? = 7,
-?????? [IRQ_DA8XX_LCDINT]????????????? = 7,
+?????? [IRQ_DA8XX_LCDINT]????????????? = 5,
??????? [IRQ_DA8XX_UARTINT1]??????????? = 7,
??????? [IRQ_DA8XX_MCASPINT]??????????? = 7,
??????? [IRQ_DA8XX_ALLINT1]???????????? = 7,



The question is now:

How to proper set the priorities for lcd and edma in this kernel?

Thank you very much!

Regards,
Bastian.
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From thomas.koeller at baslerweb.com  Thu May  6 04:15:16 2010
From: thomas.koeller at baslerweb.com (Thomas Koeller)
Date: Thu, 6 May 2010 11:15:16 +0200
Subject: [PATCH 1/4] DM365: Make all SPI units SPI0..SPI4 available
In-Reply-To: <B85A65D85D7EB246BE421B3FB0FBB59301E6D3D34F@dbde02.ent.ti.com>
References: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
	<1272993504-1189-2-git-send-email-thomas.koeller@baslerweb.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E6D3D34F@dbde02.ent.ti.com>
Message-ID: <201005061115.16291.thomas.koeller@baslerweb.com>

On Wednesday 05 May 2010 11:32:00 Nori, Sekhar wrote:
> Have you based your code on the latest of Kevin's tree?
> I don't see the additional IORESOURCE_DMA_* flags in the
> current tree.

No, all my patches are against the 'arago-project.org/git/projects/linux-davinci.git'
repository, because that is what I am working with.

Thomas


From caglarakyuz at gmail.com  Thu May  6 05:25:38 2010
From: caglarakyuz at gmail.com (Caglar Akyuz)
Date: Thu, 6 May 2010 13:25:38 +0300
Subject: How to set priorities for VGA on OMAP-L1xx on Linux 2.6.34-rc5 ?
In-Reply-To: <1721130017.845189.1273129820479.JavaMail.open-xchange@oxltgw14.schlund.de>
References: <1721130017.845189.1273129820479.JavaMail.open-xchange@oxltgw14.schlund.de>
Message-ID: <201005061325.38497.caglarakyuz@gmail.com>

On Thursday 06 May 2010 10:10:20 am ng at max01.eu wrote:
> Hello
> 
> we try to get a VGA-TFT-Display running on a OMAP-L138 exp-board with a
>  Linux 2.6.34-rc5 GIT-kernel
> (url =
>  git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git).
>  This kernel is patched to get our display running.
> 
> The linux-logo after bootup is fine so far, but when starting a graphic
> application there is some trouble
> (the screen is not centered).
> 
> We noticed the article http://processors.wiki.ti.com/index.php/OMAP-L1x_VGA
> (Modifications for LCD driver to support VGA mode ).
> 
> We still raised the LCD interrupt priority slightly:
> 
> --- a/arch/arm/mach-davinci/da850.c
> +++ b/arch/arm/mach-davinci/da850.c
> @@ -705,7 +705,7 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ]
>  = { [IRQ_DA8XX_GPIO7]               = 7,
>         [IRQ_DA8XX_GPIO8]               = 7,
>         [IRQ_DA8XX_I2CINT1]             = 7,
> -       [IRQ_DA8XX_LCDINT]              = 7,
> +       [IRQ_DA8XX_LCDINT]              = 5,
>         [IRQ_DA8XX_UARTINT1]            = 7,
>         [IRQ_DA8XX_MCASPINT]            = 7,
>         [IRQ_DA8XX_ALLINT1]             = 7,
> 
> 
> 
> The question is now:
> 
> How to proper set the priorities for lcd and edma in this kernel?
> 

Hello,

Maybe you can try adjusting priorities in u-boot like:

 mw.l 0x01c14110 0x44442222 1
 mw.l 0x01c14114 0x44400000 1
 mw.l 0x01c14118 0x04604404 1

Somehow equivalent kernel code is attached at the end (taken from Hawkboard 
board code)

OTH, I have no idea if these two have the same effect with adjusting 
'da850_default_priorities' or not.

Best Regards,
Caglar

__________________________________________________________________

static int da850_lcd_hw_init(void)
{
	void __iomem *cfg_mstpri2_base;
	u32 val;

	/*
	 * Reconfigure the LCDC priority to the highest to ensure that
	 * the throughput/latency requirements for the LCDC are met.
	 */
	cfg_mstpri2_base = DA8XX_SYSCFG0_VIRT(DA8XX_MSTPRI2_REG);

	val = __raw_readl(cfg_mstpri2_base);
	val &= 0x0fffffff;
	__raw_writel(val, cfg_mstpri2_base);

	return 0;
}


> Thank you very much!
> 
> Regards,
> Bastian.
> 

From vaibhav.bedia at ti.com  Thu May  6 07:17:56 2010
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Thu, 6 May 2010 17:47:56 +0530
Subject: DM6467 McASP
In-Reply-To: <27286074.508171273100933507.JavaMail.weblogic@epml17>
References: <27286074.508171273100933507.JavaMail.weblogic@epml17>
Message-ID: <FCCFB4CDC6E5564B9182F639FC356087030500CEB3@dbde02.ent.ti.com>

Jayakrishnan,

Since AUXCLK for both McASP0 and McASP1 come from the same source there won't be sync issues there.

Regards,
Vaibhav

-----Original Message-----
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com] 
Sent: Thursday, May 06, 2010 4:39 AM
To: Bedia, Vaibhav; davinci-linux-open-source at linux.davincidsp.com
Cc: Srinivasan, Nageswari; Pasupathy, Visuvanadan
Subject: RE: DM6467 McASP



 
Hi  Vaibhav,
Thanks  for the  reply. I have to  use AHCLKX1 as HF  clock  to  another chip.No other option.
But  I am worried  about  the  synchronisation between AUXCLK  to port 0  and  port 1.
Any  comments?
Regards
JK

------- Original Message-------
Sender: Bedia, Vaibhav<vaibhav.bedia at ti.com>
Date: May 04, 2010 21:38 (GMT+09:00)
Title: RE: DM6467 McASP

Jayakrishnan, 

The McASP transmit bit clock, ACLKX can be either externally sourced or internally generated.  

In case ALCLKX is internally generated from AUXCLK, then you have the option of sending the intermediate high frequency master clock (AHCLKX) to the AHCLKX pin to be used by other devices in the system. In such a situation you don't need to use the 2nd McASP just for generating AHCLKX. 

However, if your use-case needs two McASPs that can also be done as both can be used simultaneously. 

Regards, 
Vaibhav 

-----Original Message----- 
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Jaya krishnan 
Sent: Tuesday, May 04, 2010 1:44 PM 
To: davinci-linux-open-source at linux.davincidsp.com 
Subject: DM6467 McASP 


Hi  , 
I want  to use McASP  port  0 for  transmit data  and port 1  to  generate high frequency clock (AHCLKX) (to be used as  master clock for  another audio DAC  in the  system.)  Is there  any  limitation to use  both  ports  simultaneously?Pls  reply 
Regards 
JK 

  
     
Jayakrishnan M M 
Research Engineer 
R&D Team-2 , Group-5 
Security Solutions  Division 
SAMSUNG TECHWIN CO.,LTD 

TEL +82-70-7147-8482 
FAX +82-31-8018-3712 
Mobile +82-10-6409-3619 
E-mail:jaya.krishnan at samsung.com 
  
   
_______________________________________________ 
Davinci-linux-open-source mailing list 
Davinci-linux-open-source at linux.davincidsp.com 
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source 

 
    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  
 
 

From cyril at ti.com  Thu May  6 12:55:02 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu,  6 May 2010 13:55:02 -0400
Subject: [PATCH v5 0/6] Davinci: initial tnetv107x patch series
Message-ID: <1273168508-5990-1-git-send-email-cyril@ti.com>

This patch series adds support for TNETV107X - a Texas Instruments SOC that
shares a number of common features with the Davinci architecture.

These changes (including earlier gpio, misc, and ioremap series) were tested
on tnetv107x evm. dm355 evm, and da850 evm.


Cyril Chemparathy (6):
  Davinci: generalized debug macros
  Davinci: tnetv107x decompresser uart definitions
  Davinci: tnetv107x soc support
  Davinci: tnetv107x initial gpio support
  Davinci: tnetv107x evm board initial support
  Davinci: tnetv107x default configuration

 arch/arm/configs/tnetv107x_defconfig             | 1741 ++++++++++++++++++++++
 arch/arm/mach-davinci/Kconfig                    |   12 +
 arch/arm/mach-davinci/Makefile                   |    3 +
 arch/arm/mach-davinci/board-tnetv107x-evm.c      |  174 +++
 arch/arm/mach-davinci/devices-tnetv107x.c        |  318 ++++
 arch/arm/mach-davinci/gpio-tnetv107x.c           |  205 +++
 arch/arm/mach-davinci/include/mach/debug-macro.S |   50 +-
 arch/arm/mach-davinci/include/mach/gpio.h        |    1 +
 arch/arm/mach-davinci/include/mach/serial.h      |   21 +
 arch/arm/mach-davinci/include/mach/tnetv107x.h   |   56 +
 arch/arm/mach-davinci/include/mach/uncompress.h  |   87 +-
 arch/arm/mach-davinci/tnetv107x.c                |  753 ++++++++++
 12 files changed, 3389 insertions(+), 32 deletions(-)
 create mode 100644 arch/arm/configs/tnetv107x_defconfig
 create mode 100644 arch/arm/mach-davinci/board-tnetv107x-evm.c
 create mode 100644 arch/arm/mach-davinci/devices-tnetv107x.c
 create mode 100644 arch/arm/mach-davinci/gpio-tnetv107x.c
 create mode 100644 arch/arm/mach-davinci/include/mach/tnetv107x.h
 create mode 100644 arch/arm/mach-davinci/tnetv107x.c


From cyril at ti.com  Thu May  6 12:55:03 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu,  6 May 2010 13:55:03 -0400
Subject: [PATCH v5 1/6] Davinci: generalized debug macros
In-Reply-To: <1273168508-5990-1-git-send-email-cyril@ti.com>
References: <1273168508-5990-1-git-send-email-cyril@ti.com>
Message-ID: <1273168508-5990-2-git-send-email-cyril@ti.com>

This patch adopts a debug uart selection similar to the OMAP model.  During
the boot process, the uncompress code determines the physical and virtual base
addresses of the board-specific debug uart.  These addresses are then passed
on to the in-kernel debug macros through a small chunk of memory placed just
below the page tables (@0x80003ff8).

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v5: removed redundant mmu enable check
v4: unchanged from v3

 arch/arm/mach-davinci/include/mach/debug-macro.S |   50 +++++++++++---
 arch/arm/mach-davinci/include/mach/serial.h      |   13 ++++
 arch/arm/mach-davinci/include/mach/uncompress.h  |   80 ++++++++++++++++------
 3 files changed, 111 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index 3cd93a8..f761dfd 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -17,22 +17,50 @@
  */
 
 #include <linux/serial_reg.h>
+
+#include <asm/memory.h>
+
+#include <mach/serial.h>
+
 #define UART_SHIFT	2
 
+		.pushsection .data
+davinci_uart_phys:	.word	0
+davinci_uart_virt:	.word	0
+		.popsection
+
 		.macro addruart, rx, tmp
+
+		/* Use davinci_uart_phys/virt if already configured */
+10:		mrc	p15, 0, \rx, c1, c0
+		tst	\rx, #1			@ MMU enabled?
+		ldreq	\rx, =__virt_to_phys(davinci_uart_phys)
+		ldrne	\rx, =davinci_uart_virt
+		ldr	\rx, [\rx]
+		cmp	\rx, #0			@ is port configured?
+		bne	99f			@ already configured
+
 		mrc	p15, 0, \rx, c1, c0
 		tst	\rx, #1			@ MMU enabled?
-		moveq	\rx, #0x01000000	@ physical base address
-		movne	\rx, #0xfe000000	@ virtual base
-#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
-#error Cannot enable DaVinci and DA8XX platforms concurrently
-#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \
-	defined(CONFIG_MACH_DAVINCI_DA850_EVM)
-		orr	\rx, \rx, #0x00d00000	@ physical base address
-		orr	\rx, \rx, #0x0000d000	@ of UART 2
-#else
-		orr	\rx, \rx, #0x00c20000   @ UART 0
-#endif
+
+		/* Copy uart phys address from decompressor uart info */
+		ldreq	\tmp, =__virt_to_phys(davinci_uart_phys)
+		ldrne	\tmp, =davinci_uart_phys
+		ldreq	\rx, =DAVINCI_UART_INFO
+		ldrne	\rx, =__phys_to_virt(DAVINCI_UART_INFO)
+		ldr	\rx, [\rx, #0]
+		str	\rx, [\tmp]
+
+		/* Copy uart virt address from decompressor uart info */
+		ldreq	\tmp, =__virt_to_phys(davinci_uart_virt)
+		ldrne	\tmp, =davinci_uart_virt
+		ldreq	\rx, =DAVINCI_UART_INFO
+		ldrne	\rx, =__phys_to_virt(DAVINCI_UART_INFO)
+		ldr	\rx, [\rx, #4]
+		str	\rx, [\tmp]
+
+		b	10b
+99:
 		.endm
 
 		.macro	senduart,rd,rx
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index f6c4f34..b21ec22 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -11,8 +11,19 @@
 #ifndef __ASM_ARCH_SERIAL_H
 #define __ASM_ARCH_SERIAL_H
 
+#include <asm/memory.h>
+
 #include <mach/hardware.h>
 
+/*
+ * Stolen area that contains debug uart physical and virtual addresses.  These
+ * addresses are filled in by the uncompress.h code, and are used by the debug
+ * macros in debug-macro.S.
+ *
+ * This area sits just below the page tables (see arch/arm/kernel/head.S).
+ */
+#define DAVINCI_UART_INFO	(PHYS_OFFSET + 0x3ff8)
+
 #define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
@@ -26,11 +37,13 @@
 #define UART_DM646X_SCR			0x10
 #define UART_DM646X_SCR_TX_WATERMARK	0x08
 
+#ifndef __ASSEMBLY__
 struct davinci_uart_config {
 	/* Bit field of UARTs present; bit 0 --> UART1 */
 	unsigned int enabled_uarts;
 };
 
 extern int davinci_serial_init(struct davinci_uart_config *);
+#endif
 
 #endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 33796b4..20c23a3 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -1,8 +1,17 @@
 /*
  * Serial port stubs for kernel decompress status messages
  *
- *  Author:     Anant Gole
- * (C) Copyright (C) 2006, Texas Instruments, Inc
+ * Initially based on:
+ * arch/arm/plat-omap/include/mach/uncompress.h
+ *
+ * Original copyrights follow.
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon at ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source at mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2. This program is licensed "as is" without any warranty of any
@@ -11,30 +20,17 @@
 
 #include <linux/types.h>
 #include <linux/serial_reg.h>
-#include <mach/serial.h>
 
 #include <asm/mach-types.h>
 
-extern unsigned int __machine_arch_type;
+#include <mach/serial.h>
 
 static u32 *uart;
-
-static u32 *get_uart_base(void)
-{
-	if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM ||
-		__machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM)
-		return (u32 *)DA8XX_UART2_BASE;
-	else
-		return (u32 *)DAVINCI_UART0_BASE;
-}
+static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
 
 /* PORT_16C550A, in polled non-fifo mode */
-
 static void putc(char c)
 {
-	if (!uart)
-		uart = get_uart_base();
-
 	while (!(uart[UART_LSR] & UART_LSR_THRE))
 		barrier();
 	uart[UART_TX] = c;
@@ -42,12 +38,54 @@ static void putc(char c)
 
 static inline void flush(void)
 {
-	if (!uart)
-		uart = get_uart_base();
-
 	while (!(uart[UART_LSR] & UART_LSR_THRE))
 		barrier();
 }
 
-#define arch_decomp_setup()
+static inline void set_uart_info(u32 phys, void * __iomem virt)
+{
+	uart = (u32 *)phys;
+	uart_info[0] = phys;
+	uart_info[1] = (u32)virt;
+}
+
+#define _DEBUG_LL_ENTRY(machine, phys, virt)			\
+	if (machine_is_##machine()) {				\
+		set_uart_info(phys, virt);			\
+		break;						\
+	}
+
+#define DEBUG_LL_DAVINCI(machine, port)				\
+	_DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE,	\
+			IO_ADDRESS(DAVINCI_UART##port##_BASE))
+
+#define DEBUG_LL_DA8XX(machine, port)				\
+	_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE,	\
+			IO_ADDRESS(DA8XX_UART##port##_BASE))
+
+static inline void __arch_decomp_setup(unsigned long arch_id)
+{
+	/*
+	 * Initialize the port based on the machine ID from the bootloader.
+	 * Note that we're using macros here instead of switch statement
+	 * as machine_is functions are optimized out for the boards that
+	 * are not selected.
+	 */
+	do {
+		/* Davinci boards */
+		DEBUG_LL_DAVINCI(davinci_evm,		0);
+		DEBUG_LL_DAVINCI(sffsdr,		0);
+		DEBUG_LL_DAVINCI(neuros_osd2,		0);
+		DEBUG_LL_DAVINCI(davinci_dm355_evm,	0);
+		DEBUG_LL_DAVINCI(dm355_leopard,		0);
+		DEBUG_LL_DAVINCI(davinci_dm6467_evm,	0);
+		DEBUG_LL_DAVINCI(davinci_dm365_evm,	0);
+
+		/* DA8xx boards */
+		DEBUG_LL_DA8XX(davinci_da830_evm,	2);
+		DEBUG_LL_DA8XX(davinci_da850_evm,	2);
+	} while (0);
+}
+
+#define arch_decomp_setup()	__arch_decomp_setup(arch_id)
 #define arch_decomp_wdog()
-- 
1.7.0.4


From cyril at ti.com  Thu May  6 12:55:04 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu,  6 May 2010 13:55:04 -0400
Subject: [PATCH v5 2/6] Davinci: tnetv107x decompresser uart definitions
In-Reply-To: <1273168508-5990-1-git-send-email-cyril@ti.com>
References: <1273168508-5990-1-git-send-email-cyril@ti.com>
Message-ID: <1273168508-5990-3-git-send-email-cyril@ti.com>

Added definitions for tnetv107x uart base addresses, and modified base address
selection for kernel decompressor to check for tnetv107x machine type.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v5: unchanged from v4
v4: unchanged from v3
v3: migrated to uncompress.h based implementation added earlier in this series

 arch/arm/mach-davinci/include/mach/serial.h     |    8 ++++++++
 arch/arm/mach-davinci/include/mach/uncompress.h |    7 +++++++
 2 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index b21ec22..56cc338 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -32,6 +32,14 @@
 #define DA8XX_UART1_BASE	(IO_PHYS + 0x10c000)
 #define DA8XX_UART2_BASE	(IO_PHYS + 0x10d000)
 
+#define TNETV107X_UART0_BASE	(0x08108100)
+#define TNETV107X_UART1_BASE	(0x08088400)
+#define TNETV107X_UART2_BASE	(0x08108300)
+
+#define TNETV107X_UART0_VIRT	IOMEM(0xfee08100)
+#define TNETV107X_UART1_VIRT	IOMEM(0xfed88400)
+#define TNETV107X_UART2_VIRT	IOMEM(0xfee08300)
+
 /* DaVinci UART register offsets */
 #define UART_DAVINCI_PWREMU		0x0c
 #define UART_DM646X_SCR			0x10
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 20c23a3..15a6192 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -63,6 +63,10 @@ static inline void set_uart_info(u32 phys, void * __iomem virt)
 	_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE,	\
 			IO_ADDRESS(DA8XX_UART##port##_BASE))
 
+#define DEBUG_LL_TNETV107X(machine, port)			\
+	_DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE,	\
+			TNETV107X_UART##port##_VIRT)
+
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
 	/*
@@ -84,6 +88,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 		/* DA8xx boards */
 		DEBUG_LL_DA8XX(davinci_da830_evm,	2);
 		DEBUG_LL_DA8XX(davinci_da850_evm,	2);
+
+		/* TNETV107x boards */
+		DEBUG_LL_TNETV107X(tnetv107x,		1);
 	} while (0);
 }
 
-- 
1.7.0.4


From cyril at ti.com  Thu May  6 12:55:06 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu,  6 May 2010 13:55:06 -0400
Subject: [PATCH v5 4/6] Davinci: tnetv107x initial gpio support
In-Reply-To: <1273168508-5990-1-git-send-email-cyril@ti.com>
References: <1273168508-5990-1-git-send-email-cyril@ti.com>
Message-ID: <1273168508-5990-5-git-send-email-cyril@ti.com>

This patch adds support for the tnetv107x gpio controller.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v5: changes as per ioremap patch series, gpio base is no longer virt
v4: range check against number of tnetv107x gpios
v3: switched to spin_lock_irq from local_irq_save/restore
v3: migrated to restructured gpio framework from earlier patches in this
    series

 arch/arm/mach-davinci/Makefile            |    1 +
 arch/arm/mach-davinci/gpio-tnetv107x.c    |  205 +++++++++++++++++++++++++++++
 arch/arm/mach-davinci/include/mach/gpio.h |    1 +
 3 files changed, 207 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-davinci/gpio-tnetv107x.c

diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 1c7bcfe..62c5116 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= dm365.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += tnetv107x.o devices-tnetv107x.o
+obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += gpio-tnetv107x.o
 
 obj-$(CONFIG_AINTC)			+= irq.o
 obj-$(CONFIG_CP_INTC)			+= cp_intc.o
diff --git a/arch/arm/mach-davinci/gpio-tnetv107x.c b/arch/arm/mach-davinci/gpio-tnetv107x.c
new file mode 100644
index 0000000..d102986
--- /dev/null
+++ b/arch/arm/mach-davinci/gpio-tnetv107x.c
@@ -0,0 +1,205 @@
+/*
+ * Texas Instruments TNETV107X GPIO Controller
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <mach/common.h>
+#include <mach/tnetv107x.h>
+
+struct tnetv107x_gpio_regs {
+	u32	idver;
+	u32	data_in[3];
+	u32	data_out[3];
+	u32	direction[3];
+	u32	enable[3];
+};
+
+#define gpio_reg_index(gpio)	((gpio) >> 5)
+#define gpio_reg_bit(gpio)	BIT((gpio) & 0x1f)
+
+#define gpio_reg_rmw(reg, mask, val)	\
+	__raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg))
+
+#define gpio_reg_set_bit(reg, gpio)	\
+	gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio))
+
+#define gpio_reg_clear_bit(reg, gpio)	\
+	gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0)
+
+#define gpio_reg_get_bit(reg, gpio)	\
+	(__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio))
+
+#define chip2controller(chip)		\
+	container_of(chip, struct davinci_gpio_controller, chip)
+
+#define TNETV107X_GPIO_CTLRS	DIV_ROUND_UP(TNETV107X_N_GPIO, 32)
+
+static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS];
+
+static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	gpio_reg_set_bit(&regs->enable, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+
+	return 0;
+}
+
+static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	gpio_reg_clear_bit(&regs->enable, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+}
+
+static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	gpio_reg_set_bit(&regs->direction, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+
+	return 0;
+}
+
+static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
+		unsigned offset, int value)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	if (value)
+		gpio_reg_set_bit(&regs->data_out, gpio);
+	else
+		gpio_reg_clear_bit(&regs->data_out, gpio);
+
+	gpio_reg_clear_bit(&regs->direction, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+
+	return 0;
+}
+
+static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	int ret;
+
+	ret = gpio_reg_get_bit(&regs->data_in, gpio);
+
+	return ret ? 1 : 0;
+}
+
+static void tnetv107x_gpio_set(struct gpio_chip *chip,
+		unsigned offset, int value)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	if (value)
+		gpio_reg_set_bit(&regs->data_out, gpio);
+	else
+		gpio_reg_clear_bit(&regs->data_out, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+}
+
+static int __init tnetv107x_gpio_setup(void)
+{
+	int i, base;
+	unsigned ngpio;
+	struct davinci_soc_info *soc_info = &davinci_soc_info;
+	struct tnetv107x_gpio_regs *regs;
+	struct davinci_gpio_controller *ctlr;
+
+	if (soc_info->gpio_type != GPIO_TYPE_TNETV107X)
+		return 0;
+
+	ngpio = soc_info->gpio_num;
+	if (ngpio == 0) {
+		pr_err("GPIO setup:  how many GPIOs?\n");
+		return -EINVAL;
+	}
+
+	if (WARN_ON(TNETV107X_N_GPIO < ngpio))
+		ngpio = TNETV107X_N_GPIO;
+
+	regs = ioremap(soc_info->gpio_base, SZ_4K);
+	if (WARN_ON(!regs))
+		return -EINVAL;
+
+	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
+		ctlr = &chips[i];
+
+		ctlr->chip.label	= "tnetv107x";
+		ctlr->chip.can_sleep	= 0;
+		ctlr->chip.base		= base;
+		ctlr->chip.ngpio	= ngpio - base;
+		if (ctlr->chip.ngpio > 32)
+			ctlr->chip.ngpio = 32;
+
+		ctlr->chip.request		= tnetv107x_gpio_request;
+		ctlr->chip.free			= tnetv107x_gpio_free;
+		ctlr->chip.direction_input	= tnetv107x_gpio_dir_in;
+		ctlr->chip.get			= tnetv107x_gpio_get;
+		ctlr->chip.direction_output	= tnetv107x_gpio_dir_out;
+		ctlr->chip.set			= tnetv107x_gpio_set;
+
+		spin_lock_init(&ctlr->lock);
+
+		ctlr->regs	= regs;
+		ctlr->set_data	= &regs->data_out[i];
+		ctlr->clr_data	= &regs->data_out[i];
+		ctlr->in_data	= &regs->data_in[i];
+
+		gpiochip_add(&ctlr->chip);
+	}
+
+	soc_info->gpio_ctlrs = chips;
+	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
+	return 0;
+}
+pure_initcall(tnetv107x_gpio_setup);
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 504cc18..411da55 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -25,6 +25,7 @@
 
 enum davinci_gpio_type {
 	GPIO_TYPE_DAVINCI = 0,
+	GPIO_TYPE_TNETV107X,
 };
 
 /*
-- 
1.7.0.4


From cyril at ti.com  Thu May  6 12:55:07 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu,  6 May 2010 13:55:07 -0400
Subject: [PATCH v5 5/6] Davinci: tnetv107x evm board initial support
In-Reply-To: <1273168508-5990-1-git-send-email-cyril@ti.com>
References: <1273168508-5990-1-git-send-email-cyril@ti.com>
Message-ID: <1273168508-5990-6-git-send-email-cyril@ti.com>

Added support for tnetv107x evaluation module.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v5: modifications as per ioremap patch series for cpintc
v5: add comments to clarify nand chipselect and mmc controller instance
v5: enable nand bad block table
v4: updated copyrights
v4: squashed relevant gpio pins into sdio1 pin list
v4: eliminated platform device definitions, moved to tnetv107x_devices_init()
    implementation instead
v4: platform devices moved out to devices-tnetv107x.c
v3: moved some base address and edma channel definitions here
v3: minor formatting changes

 arch/arm/mach-davinci/Kconfig               |    7 +
 arch/arm/mach-davinci/Makefile              |    1 +
 arch/arm/mach-davinci/board-tnetv107x-evm.c |  174 +++++++++++++++++++++++++++
 3 files changed, 182 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-davinci/board-tnetv107x-evm.c

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a67b47b..71f90f8 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -178,6 +178,13 @@ config DA850_UI_RMII
 
 endchoice
 
+config MACH_TNETV107X
+	bool "TI TNETV107X Reference Platform"
+	default ARCH_DAVINCI_TNETV107X
+	depends on ARCH_DAVINCI_TNETV107X
+	help
+	  Say Y here to select the TI TNETV107X Evaluation Module.
+
 config DAVINCI_MUX
 	bool "DAVINCI multiplexing support"
 	depends on ARCH_DAVINCI
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 62c5116..eab4c0f 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)	+= board-dm646x-evm.o cdce949.o
 obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)	+= board-dm365-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)	+= board-da830-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= board-da850-evm.o
+obj-$(CONFIG_MACH_TNETV107X)		+= board-tnetv107x-evm.o
 
 # Power Management
 obj-$(CONFIG_CPU_FREQ)			+= cpufreq.o
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
new file mode 100644
index 0000000..fe2a9d9
--- /dev/null
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -0,0 +1,174 @@
+/*
+ * Texas Instruments TNETV107X EVM Board Support
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/ratelimit.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/irqs.h>
+#include <mach/edma.h>
+#include <mach/mux.h>
+#include <mach/cp_intc.h>
+#include <mach/tnetv107x.h>
+
+#define EVM_MMC_WP_GPIO		21
+#define EVM_MMC_CD_GPIO		24
+
+static int initialize_gpio(int gpio, char *desc)
+{
+	int ret;
+
+	ret = gpio_request(gpio, desc);
+	if (ret < 0) {
+		pr_err_ratelimited("cannot open %s gpio\n", desc);
+		return -ENOSYS;
+	}
+	gpio_direction_input(gpio);
+	return gpio;
+}
+
+static int mmc_get_cd(int index)
+{
+	static int gpio;
+
+	if (!gpio)
+		gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect");
+
+	if (gpio < 0)
+		return gpio;
+
+	return gpio_get_value(gpio) ? 0 : 1;
+}
+
+static int mmc_get_ro(int index)
+{
+	static int gpio;
+
+	if (!gpio)
+		gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect");
+
+	if (gpio < 0)
+		return gpio;
+
+	return gpio_get_value(gpio) ? 1 : 0;
+}
+
+static struct davinci_mmc_config mmc_config = {
+	.get_cd		= mmc_get_cd,
+	.get_ro		= mmc_get_ro,
+	.wires		= 4,
+	.max_freq	= 50000000,
+	.caps		= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+	.version	= MMC_CTLR_VERSION_1,
+};
+
+static const short sdio1_pins[] __initdata = {
+	TNETV107X_SDIO1_CLK_1,		TNETV107X_SDIO1_CMD_1,
+	TNETV107X_SDIO1_DATA0_1,	TNETV107X_SDIO1_DATA1_1,
+	TNETV107X_SDIO1_DATA2_1,	TNETV107X_SDIO1_DATA3_1,
+	TNETV107X_GPIO21,		TNETV107X_GPIO24,
+	-1
+};
+
+static const short uart1_pins[] __initdata = {
+	TNETV107X_UART1_RD,		TNETV107X_UART1_TD,
+	-1
+};
+
+static struct mtd_partition nand_partitions[] = {
+	/* bootloader (U-Boot, etc) in first 12 sectors */
+	{
+		.name		= "bootloader",
+		.offset		= 0,
+		.size		= (12*SZ_128K),
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	/* bootloader params in the next sector */
+	{
+		.name		= "params",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	/* kernel */
+	{
+		.name		= "kernel",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= SZ_4M,
+		.mask_flags	= 0,
+	},
+	/* file system */
+	{
+		.name		= "filesystem",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= MTDPART_SIZ_FULL,
+		.mask_flags	= 0,
+	}
+};
+
+static struct davinci_nand_pdata nand_config = {
+	.mask_cle	= 0x4000,
+	.mask_ale	= 0x2000,
+	.parts		= nand_partitions,
+	.nr_parts	= ARRAY_SIZE(nand_partitions),
+	.ecc_mode	= NAND_ECC_HW,
+	.options	= NAND_USE_FLASH_BBT,
+	.ecc_bits	= 1,
+};
+
+static struct davinci_uart_config serial_config __initconst = {
+	.enabled_uarts	= BIT(1),
+};
+
+static struct tnetv107x_device_info evm_device_info __initconst = {
+	.serial_config		= &serial_config,
+	.mmc_config[1]		= &mmc_config,	/* controller 1 */
+	.nand_config[0]		= &nand_config,	/* chip select 0 */
+};
+
+static __init void tnetv107x_evm_board_init(void)
+{
+	davinci_cfg_reg_list(sdio1_pins);
+	davinci_cfg_reg_list(uart1_pins);
+
+	tnetv107x_devices_init(&evm_device_info);
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+static int __init tnetv107x_evm_console_init(void)
+{
+	return add_preferred_console("ttyS", 0, "115200");
+}
+console_initcall(tnetv107x_evm_console_init);
+#endif
+
+MACHINE_START(TNETV107X, "TNETV107X EVM")
+	.phys_io	= TNETV107X_IO_BASE,
+	.io_pg_offst	= (TNETV107X_IO_VIRT >> 18) & 0xfffc,
+	.boot_params	= (TNETV107X_DDR_BASE + 0x100),
+	.map_io		= tnetv107x_init,
+	.init_irq	= cp_intc_init,
+	.timer		= &davinci_timer,
+	.init_machine	= tnetv107x_evm_board_init,
+MACHINE_END
-- 
1.7.0.4


From cyril at ti.com  Thu May  6 12:55:05 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu,  6 May 2010 13:55:05 -0400
Subject: [PATCH v5 3/6] Davinci: tnetv107x soc support
In-Reply-To: <1273168508-5990-1-git-send-email-cyril@ti.com>
References: <1273168508-5990-1-git-send-email-cyril@ti.com>
Message-ID: <1273168508-5990-4-git-send-email-cyril@ti.com>

TNETV107X is a Texas Instruments SOC that shares a number of common features
with the Davinci architecture.  Some of the key differences between
traditional Davincis and this new SOC are as follow:

1. The SOCs clock architecture includes a new spread-spectrum PLL.  Some
elements of the clock architecture are reused from Davinci (e.g. LPSC), but
the PLL related code is overridden using existing interfaces in "struct clk".

2. The MMR layout on this SOC is substantially different from Davinci.
Consequently, the fixed I/O map is a whole lot more convoluted (more so than
DA8xx).  The net impact here is that IO_ADDRESS() will not work on this SoC,
and therefore all mappings have to be through ioremap().

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v5: simplified watchdog reset code
v5: removed edma iotable entry
v5: updated soc_info interface according to ioremap patch series
v5: reuse davinci serial init code, now that it is generalized enough
v5: allow boards to use nand device on any emif chip select
v5: sorted base address definitions
v4: macroized clock definitions to reduce code volume
v4: moved to new davinci_io_init() mechanism (earlier in this series)
v4: squashed tnetv107x.h header and watchdog reset patches into this
v4: moved all platform_device definitions into soc code, accessible to board
    specific code via tnetv107x_devices_init()
v3: eliminated recalc routines for pll and leaf clocks
v3: stripped "clk_" prefix from clock names
v3: use newly added div_ratio_mask functionality (earlier in this series)
v3: move from fixed_ioremap to __davinci_ioremap() implementation (earlier in
    this series

 arch/arm/mach-davinci/Kconfig                  |    5 +
 arch/arm/mach-davinci/Makefile                 |    1 +
 arch/arm/mach-davinci/devices-tnetv107x.c      |  318 ++++++++++
 arch/arm/mach-davinci/include/mach/tnetv107x.h |   56 ++
 arch/arm/mach-davinci/tnetv107x.c              |  753 ++++++++++++++++++++++++
 5 files changed, 1133 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-davinci/devices-tnetv107x.c
 create mode 100644 arch/arm/mach-davinci/include/mach/tnetv107x.h
 create mode 100644 arch/arm/mach-davinci/tnetv107x.c

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0316e20..a67b47b 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -50,6 +50,11 @@ config ARCH_DAVINCI_DM365
 	select AINTC
 	select ARCH_DAVINCI_DMx
 
+config ARCH_DAVINCI_TNETV107X
+	select CPU_V6
+	select CP_INTC
+	bool "TNETV107X based system"
+
 comment "DaVinci Board Type"
 
 config MACH_DAVINCI_EVM
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 6aac880..1c7bcfe 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= dm365.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o
+obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += tnetv107x.o devices-tnetv107x.o
 
 obj-$(CONFIG_AINTC)			+= irq.o
 obj-$(CONFIG_CP_INTC)			+= cp_intc.o
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
new file mode 100644
index 0000000..4eef6cc
--- /dev/null
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -0,0 +1,318 @@
+/*
+ * Texas Instruments TNETV107X SoC devices
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/edma.h>
+#include <mach/tnetv107x.h>
+
+#include "clock.h"
+
+/* Base addresses for on-chip devices */
+#define TNETV107X_TPCC_BASE			0x01c00000
+#define TNETV107X_TPTC0_BASE			0x01c10000
+#define TNETV107X_TPTC1_BASE			0x01c10400
+#define TNETV107X_WDOG_BASE			0x08086700
+#define TNETV107X_SDIO0_BASE			0x08088700
+#define TNETV107X_SDIO1_BASE			0x08088800
+#define TNETV107X_ASYNC_EMIF_CNTRL_BASE		0x08200000
+#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE	0x30000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE	0x40000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE	0x44000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
+
+/* TNETV107X specific EDMA3 information */
+#define EDMA_TNETV107X_NUM_DMACH	64
+#define EDMA_TNETV107X_NUM_TCC		64
+#define EDMA_TNETV107X_NUM_PARAMENTRY	128
+#define EDMA_TNETV107X_NUM_EVQUE	2
+#define EDMA_TNETV107X_NUM_TC		2
+#define EDMA_TNETV107X_CHMAP_EXIST	0
+#define EDMA_TNETV107X_NUM_REGIONS	4
+#define TNETV107X_DMACH2EVENT_MAP0	0x3C0CE000u
+#define TNETV107X_DMACH2EVENT_MAP1	0x000FFFFFu
+
+#define TNETV107X_DMACH_SDIO0_RX		26
+#define TNETV107X_DMACH_SDIO0_TX		27
+#define TNETV107X_DMACH_SDIO1_RX		28
+#define TNETV107X_DMACH_SDIO1_TX		29
+
+static const s8 edma_tc_mapping[][2] = {
+	/* event queue no	TC no	*/
+	{	 0,		 0	},
+	{	 1,		 1	},
+	{	-1,		-1	}
+};
+
+static const s8 edma_priority_mapping[][2] = {
+	/* event queue no	Prio	*/
+	{	 0,		 3	},
+	{	 1,		 7	},
+	{	-1,		-1	}
+};
+
+static struct edma_soc_info edma_info[] = {
+	{
+		.n_channel		= EDMA_TNETV107X_NUM_DMACH,
+		.n_region		= EDMA_TNETV107X_NUM_REGIONS,
+		.n_slot			= EDMA_TNETV107X_NUM_PARAMENTRY,
+		.n_tc			= EDMA_TNETV107X_NUM_TC,
+		.n_cc			= 1,
+		.queue_tc_mapping	= edma_tc_mapping,
+		.queue_priority_mapping	= edma_priority_mapping,
+	},
+};
+
+static struct resource edma_resources[] = {
+	{
+		.name	= "edma_cc0",
+		.start	= TNETV107X_TPCC_BASE,
+		.end	= TNETV107X_TPCC_BASE + SZ_32K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma_tc0",
+		.start	= TNETV107X_TPTC0_BASE,
+		.end	= TNETV107X_TPTC0_BASE + SZ_1K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma_tc1",
+		.start	= TNETV107X_TPTC1_BASE,
+		.end	= TNETV107X_TPTC1_BASE + SZ_1K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma0",
+		.start	= IRQ_TNETV107X_TPCC,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "edma0_err",
+		.start	= IRQ_TNETV107X_TPCC_ERR,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device edma_device = {
+	.name		= "edma",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(edma_resources),
+	.resource	= edma_resources,
+	.dev.platform_data = edma_info,
+};
+
+static struct plat_serial8250_port serial_data[] = {
+	{
+		.mapbase	= TNETV107X_UART0_BASE,
+		.irq		= IRQ_TNETV107X_UART0,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.mapbase	= TNETV107X_UART1_BASE,
+		.irq		= IRQ_TNETV107X_UART1,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.mapbase	= TNETV107X_UART2_BASE,
+		.irq		= IRQ_TNETV107X_UART2,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.flags	= 0,
+	},
+};
+
+struct platform_device tnetv107x_serial_device = {
+	.name			= "serial8250",
+	.id			= PLAT8250_DEV_PLATFORM,
+	.dev.platform_data	= serial_data,
+};
+
+static struct resource mmc0_resources[] = {
+	{ /* Memory mapped registers */
+		.start	= TNETV107X_SDIO0_BASE,
+		.end	= TNETV107X_SDIO0_BASE + 0x0ff,
+		.flags	= IORESOURCE_MEM
+	},
+	{ /* MMC interrupt */
+		.start	= IRQ_TNETV107X_MMC0,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* SDIO interrupt */
+		.start	= IRQ_TNETV107X_SDIO0,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* DMA RX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX),
+		.flags	= IORESOURCE_DMA
+	},
+	{ /* DMA TX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX),
+		.flags	= IORESOURCE_DMA
+	},
+};
+
+static struct resource mmc1_resources[] = {
+	{ /* Memory mapped registers */
+		.start	= TNETV107X_SDIO1_BASE,
+		.end	= TNETV107X_SDIO1_BASE + 0x0ff,
+		.flags	= IORESOURCE_MEM
+	},
+	{ /* MMC interrupt */
+		.start	= IRQ_TNETV107X_MMC1,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* SDIO interrupt */
+		.start	= IRQ_TNETV107X_SDIO1,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* DMA RX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX),
+		.flags	= IORESOURCE_DMA
+	},
+	{ /* DMA TX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX),
+		.flags	= IORESOURCE_DMA
+	},
+};
+
+static u64 mmc0_dma_mask = DMA_BIT_MASK(32);
+static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device mmc_devices[2] = {
+	{
+		.name		= "davinci_mmc",
+		.id		= 0,
+		.dev		= {
+			.dma_mask		= &mmc0_dma_mask,
+			.coherent_dma_mask	= DMA_BIT_MASK(32),
+		},
+		.num_resources	= ARRAY_SIZE(mmc0_resources),
+		.resource	= mmc0_resources
+	},
+	{
+		.name		= "davinci_mmc",
+		.id		= 1,
+		.dev		= {
+			.dma_mask		= &mmc1_dma_mask,
+			.coherent_dma_mask	= DMA_BIT_MASK(32),
+		},
+		.num_resources	= ARRAY_SIZE(mmc1_resources),
+		.resource	= mmc1_resources
+	},
+};
+
+static const u32 emif_windows[] = {
+	TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE,
+	TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE,
+};
+
+static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M };
+
+static struct resource wdt_resources[] = {
+	{
+		.start	= TNETV107X_WDOG_BASE,
+		.end	= TNETV107X_WDOG_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device tnetv107x_wdt_device = {
+	.name		= "tnetv107x_wdt",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(wdt_resources),
+	.resource	= wdt_resources,
+};
+
+static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
+{
+	struct resource res[2];
+	struct platform_device *pdev;
+	u32	range;
+	int	ret;
+
+	/* Figure out the resource range from the ale/cle masks */
+	range = max(data->mask_cle, data->mask_ale);
+	range = PAGE_ALIGN(range + 4) - 1;
+
+	if (range >= emif_window_sizes[chipsel])
+		return -EINVAL;
+
+	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+	if (!pdev)
+		return -ENOMEM;
+
+	pdev->name		= "davinci_nand";
+	pdev->id		= chipsel;
+	pdev->dev.platform_data	= data;
+
+	memset(res, 0, sizeof(res));
+
+	res[0].start	= emif_windows[chipsel];
+	res[0].end	= res[0].start + range;
+	res[0].flags	= IORESOURCE_MEM;
+
+	res[1].start	= TNETV107X_ASYNC_EMIF_CNTRL_BASE;
+	res[1].end	= res[1].start + SZ_4K - 1;
+	res[1].flags	= IORESOURCE_MEM;
+
+	ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
+	if (ret < 0) {
+		kfree(pdev);
+		return ret;
+	}
+
+	return platform_device_register(pdev);
+}
+
+void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
+{
+	int i;
+
+	platform_device_register(&edma_device);
+	platform_device_register(&tnetv107x_wdt_device);
+
+	if (info->serial_config)
+		davinci_serial_init(info->serial_config);
+
+	for (i = 0; i < 2; i++)
+		if (info->mmc_config[i]) {
+			mmc_devices[i].dev.platform_data = info->mmc_config[i];
+			platform_device_register(&mmc_devices[i]);
+		}
+
+	for (i = 0; i < 4; i++)
+		if (info->nand_config[i])
+			nand_init(i, info->nand_config[i]);
+}
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
new file mode 100644
index 0000000..cc44678
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -0,0 +1,56 @@
+/*
+ * Texas Instruments TNETV107X SoC Specific Defines
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
+#define __ASM_ARCH_DAVINCI_TNETV107X_H
+
+#include <asm/sizes.h>
+
+#define TNETV107X_DDR_BASE	0x80000000
+
+/*
+ * Fixed mapping for early init starts here. If low-level debug is enabled,
+ * this area also gets mapped via io_pg_offset and io_phys by the boot code.
+ * To fit in with the io_pg_offset calculation, the io base address selected
+ * here _must_ be a multiple of 2^20.
+ */
+#define TNETV107X_IO_BASE	0x08000000
+#define TNETV107X_IO_VIRT	(IO_VIRT + SZ_1M)
+
+#define PINMUX(x)		(4 * (x))
+#define TNETV107X_N_GPIO	65
+
+#ifndef __ASSEMBLY__
+
+#include <linux/serial_8250.h>
+#include <mach/mmc.h>
+#include <mach/nand.h>
+#include <mach/serial.h>
+
+struct tnetv107x_device_info {
+	struct davinci_uart_config	*serial_config;
+	struct davinci_mmc_config	*mmc_config[2];  /* 2 controllers */
+	struct davinci_nand_pdata	*nand_config[4]; /* 4 chipsels */
+};
+
+extern struct platform_device tnetv107x_wdt_device;
+extern struct platform_device tnetv107x_serial_device;
+
+extern void __init tnetv107x_init(void);
+extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
+extern void __init tnetv107x_irq_init(void);
+
+#endif
+
+#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
new file mode 100644
index 0000000..864e604
--- /dev/null
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -0,0 +1,753 @@
+/*
+ * Texas Instruments TNETV107X SoC Support
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/common.h>
+#include <mach/time.h>
+#include <mach/cputype.h>
+#include <mach/psc.h>
+#include <mach/cp_intc.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#include <mach/hardware.h>
+#include <mach/tnetv107x.h>
+
+#include "clock.h"
+#include "mux.h"
+
+/* Base addresses for on-chip devices */
+#define TNETV107X_INTC_BASE			0x03000000
+#define TNETV107X_TIMER0_BASE			0x08086500
+#define TNETV107X_TIMER1_BASE			0x08086600
+#define TNETV107X_CHIP_CFG_BASE			0x08087000
+#define TNETV107X_GPIO_BASE			0x08088000
+#define TNETV107X_CLOCK_CONTROL_BASE		0x0808a000
+#define TNETV107X_PSC_BASE			0x0808b000
+
+/* Reference clock frequencies */
+#define OSC_FREQ_ONCHIP		(24000 * 1000)
+#define OSC_FREQ_OFFCHIP_SYS	(25000 * 1000)
+#define OSC_FREQ_OFFCHIP_ETH	(25000 * 1000)
+#define OSC_FREQ_OFFCHIP_TDM	(19200 * 1000)
+
+#define N_PLLS	3
+
+/* Clock Control Registers */
+struct clk_ctrl_regs {
+	u32	pll_bypass;
+	u32	_reserved0;
+	u32	gem_lrst;
+	u32	_reserved1;
+	u32	pll_unlock_stat;
+	u32	sys_unlock;
+	u32	eth_unlock;
+	u32	tdm_unlock;
+};
+
+/* SSPLL Registers */
+struct sspll_regs {
+	u32	modes;
+	u32	post_div;
+	u32	pre_div;
+	u32	mult_factor;
+	u32	divider_range;
+	u32	bw_divider;
+	u32	spr_amount;
+	u32	spr_rate_div;
+	u32	diag;
+};
+
+/* Watchdog Timer Registers */
+struct wdt_regs {
+	u32	kick_lock;
+	u32	kick;
+	u32	change_lock;
+	u32	change ;
+	u32	disable_lock;
+	u32	disable;
+	u32	prescale_lock;
+	u32	prescale;
+};
+
+static struct clk_ctrl_regs __iomem *clk_ctrl_regs;
+
+static struct sspll_regs __iomem *sspll_regs[N_PLLS];
+static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 };
+
+/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */
+static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) };
+
+/* offchip (external) reference clock frequencies */
+static u32 pll_ext_freq[] = {
+	OSC_FREQ_OFFCHIP_SYS,
+	OSC_FREQ_OFFCHIP_TDM,
+	OSC_FREQ_OFFCHIP_ETH
+};
+
+/* PSC control registers */
+static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE };
+
+/* Host map for interrupt controller */
+static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 };
+
+static unsigned long clk_sspll_recalc(struct clk *clk);
+
+/* Level 1 - the PLLs */
+#define define_pll_clk(cname, pll, divmask, base)	\
+	static struct pll_data pll_##cname##_data = {	\
+		.num		= pll,			\
+		.div_ratio_mask	= divmask,		\
+		.phys_base	= base +		\
+			TNETV107X_CLOCK_CONTROL_BASE,	\
+	};						\
+	static struct clk pll_##cname##_clk = {		\
+		.name		= "pll_" #cname "_clk",	\
+		.pll_data	= &pll_##cname##_data,	\
+		.flags		= CLK_PLL,		\
+		.recalc		= clk_sspll_recalc,	\
+	}
+
+define_pll_clk(sys, 0, 0x1ff, 0x600);
+define_pll_clk(tdm, 1, 0x0ff, 0x200);
+define_pll_clk(eth, 2, 0x0ff, 0x400);
+
+/* Level 2 - divided outputs from the PLLs */
+#define define_pll_div_clk(pll, cname, div)		\
+	static struct clk pll##_##cname##_clk = {	\
+		.name		= #pll "_" #cname "_clk",\
+		.parent		= &pll_##pll##_clk,	\
+		.flags		= CLK_PLL,		\
+		.div_reg	= PLLDIV##div,		\
+	}
+
+define_pll_div_clk(sys, arm1176,	1);
+define_pll_div_clk(sys, dsp,		2);
+define_pll_div_clk(sys, ddr,		3);
+define_pll_div_clk(sys, full,		4);
+define_pll_div_clk(sys, lcd,		5);
+define_pll_div_clk(sys, vlynq_ref,	6);
+define_pll_div_clk(sys, tsc,		7);
+define_pll_div_clk(sys, half,		8);
+
+define_pll_div_clk(eth, 5mhz,		1);
+define_pll_div_clk(eth, 50mhz,		2);
+define_pll_div_clk(eth, 125mhz,		3);
+define_pll_div_clk(eth, 250mhz,		4);
+define_pll_div_clk(eth, 25mhz,		5);
+
+define_pll_div_clk(tdm, 0,		1);
+define_pll_div_clk(tdm, extra,		2);
+define_pll_div_clk(tdm, 1,		3);
+
+
+/* Level 3 - LPSC gated clocks */
+#define __lpsc_clk(cname, _parent, mod, flg)		\
+	static struct clk clk_##cname = {		\
+		.name		= #cname,		\
+		.parent		= &_parent,		\
+		.lpsc		= TNETV107X_LPSC_##mod,\
+		.flags		= flg,			\
+	}
+
+#define lpsc_clk_enabled(cname, parent, mod)		\
+	__lpsc_clk(cname, parent, mod, ALWAYS_ENABLED)
+
+#define lpsc_clk(cname, parent, mod)			\
+	__lpsc_clk(cname, parent, mod, 0)
+
+lpsc_clk_enabled(arm,		sys_arm1176_clk, ARM);
+lpsc_clk_enabled(gem,		sys_dsp_clk,	GEM);
+lpsc_clk_enabled(ddr2_phy,	sys_ddr_clk,	DDR2_PHY);
+lpsc_clk_enabled(tpcc,		sys_full_clk,	TPCC);
+lpsc_clk_enabled(tptc0,		sys_full_clk,	TPTC0);
+lpsc_clk_enabled(tptc1,		sys_full_clk,	TPTC1);
+lpsc_clk_enabled(ram,		sys_full_clk,	RAM);
+lpsc_clk_enabled(aemif,		sys_full_clk,	AEMIF);
+lpsc_clk_enabled(chipcfg,	sys_half_clk,	CHIP_CFG);
+lpsc_clk_enabled(rom,		sys_half_clk,	ROM);
+lpsc_clk_enabled(secctl,	sys_half_clk,	SECCTL);
+lpsc_clk_enabled(keymgr,	sys_half_clk,	KEYMGR);
+lpsc_clk_enabled(gpio,		sys_half_clk,	GPIO);
+lpsc_clk_enabled(debugss,	sys_half_clk,	DEBUGSS);
+lpsc_clk_enabled(system,	sys_half_clk,	SYSTEM);
+lpsc_clk_enabled(ddr2_vrst,	sys_ddr_clk,	DDR2_EMIF1_VRST);
+lpsc_clk_enabled(ddr2_vctl_rst,	sys_ddr_clk,	DDR2_EMIF2_VCTL_RST);
+lpsc_clk_enabled(wdt_arm,	sys_half_clk,	WDT_ARM);
+
+lpsc_clk(mbx_lite,	sys_arm1176_clk,	MBX_LITE);
+lpsc_clk(ethss,		eth_125mhz_clk,		ETHSS);
+lpsc_clk(tsc,		sys_tsc_clk,		TSC);
+lpsc_clk(uart0,		sys_half_clk,		UART0);
+lpsc_clk(uart1,		sys_half_clk,		UART1);
+lpsc_clk(uart2,		sys_half_clk,		UART2);
+lpsc_clk(pktsec,	sys_half_clk,		PKTSEC);
+lpsc_clk(keypad,	sys_half_clk,		KEYPAD);
+lpsc_clk(mdio,		sys_half_clk,		MDIO);
+lpsc_clk(sdio0,		sys_half_clk,		SDIO0);
+lpsc_clk(sdio1,		sys_half_clk,		SDIO1);
+lpsc_clk(timer0,	sys_half_clk,		TIMER0);
+lpsc_clk(timer1,	sys_half_clk,		TIMER1);
+lpsc_clk(wdt_dsp,	sys_half_clk,		WDT_DSP);
+lpsc_clk(ssp,		sys_half_clk,		SSP);
+lpsc_clk(tdm0,		tdm_0_clk,		TDM0);
+lpsc_clk(tdm1,		tdm_1_clk,		TDM1);
+lpsc_clk(vlynq,		sys_vlynq_ref_clk,	VLYNQ);
+lpsc_clk(mcdma,		sys_half_clk,		MCDMA);
+lpsc_clk(usb0,		sys_half_clk,		USB0);
+lpsc_clk(usb1,		sys_half_clk,		USB1);
+lpsc_clk(usbss,		sys_half_clk,		USBSS);
+lpsc_clk(ethss_rgmii,	eth_250mhz_clk,		ETHSS_RGMII);
+lpsc_clk(imcop,		sys_dsp_clk,		IMCOP);
+lpsc_clk(spare,		sys_half_clk,		SPARE);
+
+/* LCD needs a full power down to clear controller state */
+__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE);
+
+
+/* Level 4 - leaf clocks for LPSC modules shared across drivers */
+static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec };
+static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec };
+
+static struct clk_lookup clks[] = {
+	CLK(NULL,		"pll_sys_clk",		&pll_sys_clk),
+	CLK(NULL,		"pll_eth_clk",		&pll_eth_clk),
+	CLK(NULL,		"pll_tdm_clk",		&pll_tdm_clk),
+	CLK(NULL,		"sys_arm1176_clk",	&sys_arm1176_clk),
+	CLK(NULL,		"sys_dsp_clk",		&sys_dsp_clk),
+	CLK(NULL,		"sys_ddr_clk",		&sys_ddr_clk),
+	CLK(NULL,		"sys_full_clk",		&sys_full_clk),
+	CLK(NULL,		"sys_lcd_clk",		&sys_lcd_clk),
+	CLK(NULL,		"sys_vlynq_ref_clk",	&sys_vlynq_ref_clk),
+	CLK(NULL,		"sys_tsc_clk",		&sys_tsc_clk),
+	CLK(NULL,		"sys_half_clk",		&sys_half_clk),
+	CLK(NULL,		"eth_5mhz_clk",		&eth_5mhz_clk),
+	CLK(NULL,		"eth_50mhz_clk",	&eth_50mhz_clk),
+	CLK(NULL,		"eth_125mhz_clk",	&eth_125mhz_clk),
+	CLK(NULL,		"eth_250mhz_clk",	&eth_250mhz_clk),
+	CLK(NULL,		"eth_25mhz_clk",	&eth_25mhz_clk),
+	CLK(NULL,		"tdm_0_clk",		&tdm_0_clk),
+	CLK(NULL,		"tdm_extra_clk",	&tdm_extra_clk),
+	CLK(NULL,		"tdm_1_clk",		&tdm_1_clk),
+	CLK(NULL,		"clk_arm",		&clk_arm),
+	CLK(NULL,		"clk_gem",		&clk_gem),
+	CLK(NULL,		"clk_ddr2_phy",		&clk_ddr2_phy),
+	CLK(NULL,		"clk_tpcc",		&clk_tpcc),
+	CLK(NULL,		"clk_tptc0",		&clk_tptc0),
+	CLK(NULL,		"clk_tptc1",		&clk_tptc1),
+	CLK(NULL,		"clk_ram",		&clk_ram),
+	CLK(NULL,		"clk_mbx_lite",		&clk_mbx_lite),
+	CLK("tnetv107x-fb.0",	NULL,			&clk_lcd),
+	CLK(NULL,		"clk_ethss",		&clk_ethss),
+	CLK(NULL,		"aemif",		&clk_aemif),
+	CLK(NULL,		"clk_chipcfg",		&clk_chipcfg),
+	CLK("tnetv107x-ts.0",	NULL,			&clk_tsc),
+	CLK(NULL,		"clk_rom",		&clk_rom),
+	CLK(NULL,		"uart2",		&clk_uart2),
+	CLK(NULL,		"clk_pktsec",		&clk_pktsec),
+	CLK("tnetv107x-rng.0",	NULL,			&clk_rng),
+	CLK("tnetv107x-pka.0",	NULL,			&clk_pka),
+	CLK(NULL,		"clk_secctl",		&clk_secctl),
+	CLK(NULL,		"clk_keymgr",		&clk_keymgr),
+	CLK("tnetv107x-keypad.0", NULL,			&clk_keypad),
+	CLK(NULL,		"clk_gpio",		&clk_gpio),
+	CLK(NULL,		"clk_mdio",		&clk_mdio),
+	CLK("davinci_mmc.0",	NULL,			&clk_sdio0),
+	CLK(NULL,		"uart0",		&clk_uart0),
+	CLK(NULL,		"uart1",		&clk_uart1),
+	CLK(NULL,		"timer0",		&clk_timer0),
+	CLK(NULL,		"timer1",		&clk_timer1),
+	CLK("tnetv107x_wdt.0",	NULL,			&clk_wdt_arm),
+	CLK(NULL,		"clk_wdt_dsp",		&clk_wdt_dsp),
+	CLK("ti-ssp.0",		NULL,			&clk_ssp),
+	CLK(NULL,		"clk_tdm0",		&clk_tdm0),
+	CLK(NULL,		"clk_vlynq",		&clk_vlynq),
+	CLK(NULL,		"clk_mcdma",		&clk_mcdma),
+	CLK(NULL,		"clk_usb0",		&clk_usb0),
+	CLK(NULL,		"clk_tdm1",		&clk_tdm1),
+	CLK(NULL,		"clk_debugss",		&clk_debugss),
+	CLK(NULL,		"clk_ethss_rgmii",	&clk_ethss_rgmii),
+	CLK(NULL,		"clk_system",		&clk_system),
+	CLK(NULL,		"clk_imcop",		&clk_imcop),
+	CLK(NULL,		"clk_spare",		&clk_spare),
+	CLK("davinci_mmc.1",	NULL,			&clk_sdio1),
+	CLK(NULL,		"clk_usb1",		&clk_usb1),
+	CLK(NULL,		"clk_usbss",		&clk_usbss),
+	CLK(NULL,		"clk_ddr2_vrst",	&clk_ddr2_vrst),
+	CLK(NULL,		"clk_ddr2_vctl_rst",	&clk_ddr2_vctl_rst),
+	CLK(NULL,		NULL,			NULL),
+};
+
+static const struct mux_config pins[] = {
+#ifdef CONFIG_DAVINCI_MUX
+	MUX_CFG(TNETV107X, ASR_A00,		0, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO32,		0, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A01,		0, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO33,		0, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A02,		0, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO34,		0, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A03,		0, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO35,		0, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A04,		0, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO36,		0, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A05,		0, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO37,		0, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A06,		1, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO38,		1, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A07,		1, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO39,		1, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A08,		1, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO40,		1, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A09,		1, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO41,		1, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A10,		1, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO42,		1, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A11,		1, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_0,		1, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A12,		2, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_1,		2, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A13,		2, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO43,		2, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A14,		2, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO44,		2, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A15,		2, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO45,		2, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A16,		2, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO46,		2, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A17,		2, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO47,		2, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A18,		3, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO48,		3, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA3_0,	3, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A19,		3, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO49,		3, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA2_0,	3, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A20,		3, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO50,		3, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA1_0,	3, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A21,		3, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO51,		3, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA0_0,	3, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A22,		3, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO52,		3, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_CMD_0,		3, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A23,		3, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO53,		3, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_CLK_0,		3, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_BA_1,		4, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO54,		4, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SYS_PLL_CLK,		4, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_CS0,		4, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_CS1,		4, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_CS2,		4, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM_PLL_CLK,		4, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_CS3,		4, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ETH_PHY_CLK,		4, 20, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, ASR_D00,		4, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO55,		4, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D01,		5, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO56,		5, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D02,		5, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO57,		5, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D03,		5, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO58,		5, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D04,		5, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO59_0,		5, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D05,		5, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO60_0,		5, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D06,		5, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO61_0,		5, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D07,		6, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO62_0,		6, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D08,		6, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO63_0,		6, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D09,		6, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO64_0,		6, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D10,		6, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA3_1,	6, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D11,		6, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA2_1,	6, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D12,		6, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA1_1,	6, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D13,		7, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA0_1,	7, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D14,		7, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_CMD_1,		7, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D15,		7, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_CLK_1,		7, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_OE,		7, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_2,		7, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_RNW,		7, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO29_0,		7, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_WAIT,		7, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO30_0,		7, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_WE,		8, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_3,		8, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_WE_DQM0,		8, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO31,		8, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD17_0,		8, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_WE_DQM1,		8, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_BA0_0,		8, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, VLYNQ_CLK,		9, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO14,		9, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD19_0,		9, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_RXD0,		9, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO15,		9, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD20_0,		9, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_RXD1,		9, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO16,		9, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD21_0,		9, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_TXD0,		9, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO17,		9, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD22_0,		9, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_TXD1,		9, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO18,		9, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD23_0,		9, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, SDIO0_CLK,		10, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO19,		10, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_CMD,		10, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO20,		10, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA0,		10, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO21,		10, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA1,		10, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO22,		10, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA2,		10, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO23,		10, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA3,		10, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO24,		10, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, EMU0,		11, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, EMU1,		11, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, RTCK,		12, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TRST_N,		12, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TCK,			12, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDI,			12, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDO,			12, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TMS,			12, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_CLK,		13, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_RX,		13, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_TX,		13, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_FS,		13, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R0,		14, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R1,		14, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R2,		14, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R3,		14, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R4,		14, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R5,		14, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R6,		15, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO12,		15, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, KEYPAD_R7,		15, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO10,		15, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, KEYPAD_C0,		15, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C1,		15, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C2,		15, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C3,		15, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C4,		16, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C5,		16, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C6,		16, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO13,		16, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, TEST_CLK_IN,		16, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, KEYPAD_C7,		16, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO11,		16, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SSP0_0,		17, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_DCLK,		17, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD20_1,		17, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP0_1,		17, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_CS_N,		17, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD21_1,		17, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP0_2,		17, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_D,		17, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD22_1,		17, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP0_3,		17, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_RESETN,		17, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD23_1,		17, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_0,		18, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO25,		18, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_CTS,		18, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_1,		18, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO26,		18, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_RD,		18, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_2,		18, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO27,		18, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_RTS,		18, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_3,		18, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO28,		18, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_TD,		18, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, UART0_CTS,		19, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART0_RD,		19, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART0_RTS,		19, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART0_TD,		19, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART1_RD,		19, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART1_TD,		19, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_AC_NCS,		20, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_HSYNC_RNW,	20, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_VSYNC_A0,	20, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_MCLK,		20, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD16_0,		20, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PCLK_E,		20, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD00,		20, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD01,		21, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD02,		21, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD03,		21, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD04,		21, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD05,		21, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD06,		21, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD07,		22, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD08,		22, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO59_1,		22, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD09,		22, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO60_1,		22, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD10,		22, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_BA0_1,		22, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO61_1,		22, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD11,		22, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO62_1,		22, 20, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD12,		22, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO63_1,		22, 25, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD13,		23, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO64_1,		23, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD14,		23, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO29_1,		23, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD15,		23, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO30_1,		23, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, EINT0,		24, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO08,		24, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, EINT1,		24, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO09,		24, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO00,		24, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD20_2,		24, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, TDM_CLK_IN_2,	24, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO01,		24, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD21_2,		24, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, 24M_CLK_OUT_1,	24, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO02,		24, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD22_2,		24, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO03,		24, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD23_2,		24, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO04,		25, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD16_1,		25, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, USB0_RXERR,		25, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO05,		25, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD17_1,		25, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, TDM_CLK_IN_1,	25, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO06,		25, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD18,		25, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, 24M_CLK_OUT_2,	25, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO07,		25, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD19_1,		25, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, USB1_RXERR,		25, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, ETH_PLL_CLK,		25, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, MDIO,		26, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, MDC,			26, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, AIC_MUTE_STAT_N,	26, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_CLK,		26, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, AIC_HNS_EN_N,	26, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_FS,		26, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N,	26, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_TX,		26, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N,	26, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_RX,		26, 25, 0x1f, 0x04, false)
+#endif
+};
+
+/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
+static u8 irq_prios[TNETV107X_N_CP_INTC_IRQ] = {
+	/* fill in default priority 7 */
+	[0 ... (TNETV107X_N_CP_INTC_IRQ - 1)]	= 7,
+	/* now override as needed, e.g. [xxx] = 5 */
+};
+
+/* Contents of JTAG ID register used to identify exact cpu type */
+static struct davinci_id ids[] = {
+	{
+		.variant	= 0x0,
+		.part_no	= 0xb8a1,
+		.manufacturer	= 0x017,
+		.cpu_id		= DAVINCI_CPU_ID_TNETV107X,
+		.name		= "tnetv107x rev1.0",
+	},
+};
+
+static struct davinci_timer_instance timer_instance[2] = {
+	{
+		.base		= TNETV107X_TIMER0_BASE,
+		.bottom_irq	= IRQ_TNETV107X_TIMER_0_TINT12,
+		.top_irq	= IRQ_TNETV107X_TIMER_0_TINT34,
+	},
+	{
+		.base		= TNETV107X_TIMER1_BASE,
+		.bottom_irq	= IRQ_TNETV107X_TIMER_1_TINT12,
+		.top_irq	= IRQ_TNETV107X_TIMER_1_TINT34,
+	},
+};
+
+static struct davinci_timer_info timer_info = {
+	.timers		= timer_instance,
+	.clockevent_id	= T0_BOT,
+	.clocksource_id	= T0_TOP,
+};
+
+/*
+ * TNETV107X platforms do not use the static mappings from Davinci
+ * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses,
+ * and changing IO_PHYS would break away from existing Davinci SOCs.
+ *
+ * The primary impact of the current model is that IO_ADDRESS() is not to be
+ * used to map registers on TNETV107X.
+ *
+ * 1.	The first chunk is for INTC:  This needs to be mapped in via iotable
+ *	because ioremap() does not seem to be operational at the time when
+ *	irqs are initialized.  Without this, consistent dma init bombs.
+ *
+ * 2.	The second chunk maps in register areas that need to be populated into
+ *	davinci_soc_info.  Note that alignment restrictions come into play if
+ *	low-level debug is enabled (see note in <mach/tnetv107x.h>).
+ */
+static struct map_desc io_desc[] = {
+	{	/* INTC */
+		.virtual	= IO_VIRT,
+		.pfn		= __phys_to_pfn(TNETV107X_INTC_BASE),
+		.length		= SZ_16K,
+		.type		= MT_DEVICE
+	},
+	{	/* Most of the rest */
+		.virtual	= TNETV107X_IO_VIRT,
+		.pfn		= __phys_to_pfn(TNETV107X_IO_BASE),
+		.length		= IO_SIZE - SZ_1M,
+		.type		= MT_DEVICE
+	},
+};
+
+static unsigned long clk_sspll_recalc(struct clk *clk)
+{
+	int		pll;
+	unsigned long	mult = 0, prediv = 1, postdiv = 1;
+	unsigned long	ref = OSC_FREQ_ONCHIP, ret;
+	u32		tmp;
+
+	if (WARN_ON(!clk->pll_data))
+		return clk->rate;
+
+	if (!clk_ctrl_regs) {
+		void __iomem *tmp;
+
+		tmp = ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K);
+
+		if (WARN(!tmp, "failed ioremap for clock control regs\n"))
+			return clk->parent ? clk->parent->rate : 0;
+
+		for (pll = 0; pll < N_PLLS; pll++)
+			sspll_regs[pll] = tmp + sspll_regs_base[pll];
+
+		clk_ctrl_regs = tmp;
+	}
+
+	pll = clk->pll_data->num;
+
+	tmp = __raw_readl(&clk_ctrl_regs->pll_bypass);
+	if (!(tmp & bypass_mask[pll])) {
+		mult	= __raw_readl(&sspll_regs[pll]->mult_factor);
+		prediv	= __raw_readl(&sspll_regs[pll]->pre_div) + 1;
+		postdiv	= __raw_readl(&sspll_regs[pll]->post_div) + 1;
+	}
+
+	tmp = __raw_readl(clk->pll_data->base + PLLCTL);
+	if (tmp & PLLCTL_CLKMODE)
+		ref = pll_ext_freq[pll];
+
+	clk->pll_data->input_rate = ref;
+
+	tmp = __raw_readl(clk->pll_data->base + PLLCTL);
+	if (!(tmp & PLLCTL_PLLEN))
+		return ref;
+
+	ret = ref;
+	if (mult)
+		ret += ((unsigned long long)ref * mult) / 256;
+
+	ret /= (prediv * postdiv);
+
+	return ret;
+}
+
+static void tnetv107x_watchdog_reset(struct platform_device *pdev)
+{
+	struct wdt_regs __iomem *regs;
+
+	regs = ioremap(pdev->resource[0].start, SZ_4K);
+
+	/* disable watchdog */
+	__raw_writel(0x7777, &regs->disable_lock);
+	__raw_writel(0xcccc, &regs->disable_lock);
+	__raw_writel(0xdddd, &regs->disable_lock);
+	__raw_writel(0, &regs->disable);
+
+	/* program prescale */
+	__raw_writel(0x5a5a, &regs->prescale_lock);
+	__raw_writel(0xa5a5, &regs->prescale_lock);
+	__raw_writel(0, &regs->prescale);
+
+	/* program countdown */
+	__raw_writel(0x6666, &regs->change_lock);
+	__raw_writel(0xbbbb, &regs->change_lock);
+	__raw_writel(1, &regs->change);
+
+	/* enable watchdog */
+	__raw_writel(0x7777, &regs->disable_lock);
+	__raw_writel(0xcccc, &regs->disable_lock);
+	__raw_writel(0xdddd, &regs->disable_lock);
+	__raw_writel(1, &regs->disable);
+
+	/* kick */
+	__raw_writel(0x5555, &regs->kick_lock);
+	__raw_writel(0xaaaa, &regs->kick_lock);
+	__raw_writel(1, &regs->kick);
+}
+
+static struct davinci_soc_info tnetv107x_soc_info = {
+	.io_desc		= io_desc,
+	.io_desc_num		= ARRAY_SIZE(io_desc),
+	.ids			= ids,
+	.ids_num		= ARRAY_SIZE(ids),
+	.jtag_id_reg		= TNETV107X_CHIP_CFG_BASE + 0x018,
+	.cpu_clks		= clks,
+	.psc_bases		= psc_regs,
+	.psc_bases_num		= ARRAY_SIZE(psc_regs),
+	.pinmux_base		= TNETV107X_CHIP_CFG_BASE + 0x150,
+	.pinmux_pins		= pins,
+	.pinmux_pins_num	= ARRAY_SIZE(pins),
+	.intc_type		= DAVINCI_INTC_TYPE_CP_INTC,
+	.intc_base		= TNETV107X_INTC_BASE,
+	.intc_irq_prios		= irq_prios,
+	.intc_irq_num		= TNETV107X_N_CP_INTC_IRQ,
+	.intc_host_map		= intc_host_map,
+	.gpio_base		= TNETV107X_GPIO_BASE,
+	.gpio_type		= GPIO_TYPE_TNETV107X,
+	.gpio_num		= TNETV107X_N_GPIO,
+	.timer_info		= &timer_info,
+	.serial_dev		= &tnetv107x_serial_device,
+	.reset			= tnetv107x_watchdog_reset,
+	.reset_device		= &tnetv107x_wdt_device,
+};
+
+void __init tnetv107x_init(void)
+{
+	davinci_common_init(&tnetv107x_soc_info);
+}
-- 
1.7.0.4


From cyril at ti.com  Thu May  6 12:55:08 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu,  6 May 2010 13:55:08 -0400
Subject: [PATCH v5 6/6] Davinci: tnetv107x default configuration
In-Reply-To: <1273168508-5990-1-git-send-email-cyril@ti.com>
References: <1273168508-5990-1-git-send-email-cyril@ti.com>
Message-ID: <1273168508-5990-7-git-send-email-cyril@ti.com>

Added default configuration for tnetv107x platforms.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/configs/tnetv107x_defconfig | 1741 ++++++++++++++++++++++++++++++++++
 1 files changed, 1741 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/configs/tnetv107x_defconfig

diff --git a/arch/arm/configs/tnetv107x_defconfig b/arch/arm/configs/tnetv107x_defconfig
new file mode 100644
index 0000000..efc101f
--- /dev/null
+++ b/arch/arm/configs/tnetv107x_defconfig
@@ -0,0 +1,1741 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.34-rc5
+# Sun May  2 15:05:52 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+CONFIG_ARCH_DAVINCI=y
+# CONFIG_ARCH_OMAP is not set
+CONFIG_CP_INTC=y
+
+#
+# TI DaVinci Implementations
+#
+
+#
+# DaVinci Core Type
+#
+# CONFIG_ARCH_DAVINCI_DM644x is not set
+# CONFIG_ARCH_DAVINCI_DM355 is not set
+# CONFIG_ARCH_DAVINCI_DM646x is not set
+# CONFIG_ARCH_DAVINCI_DA830 is not set
+# CONFIG_ARCH_DAVINCI_DA850 is not set
+# CONFIG_ARCH_DAVINCI_DM365 is not set
+CONFIG_ARCH_DAVINCI_TNETV107X=y
+
+#
+# DaVinci Board Type
+#
+CONFIG_MACH_TNETV107X=y
+CONFIG_DAVINCI_MUX=y
+CONFIG_DAVINCI_MUX_DEBUG=y
+CONFIG_DAVINCI_MUX_WARNINGS=y
+CONFIG_DAVINCI_RESET_CLOCKS=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_V6=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_ARM_ERRATA_411920 is not set
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_LEDS=y
+# CONFIG_LEDS_CPU is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=m
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=m
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI_AMDSTD=m
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=m
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=m
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_DAVINCI=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IWMC3200TOP is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=m
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_TI_DAVINCI_EMAC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+CONFIG_INPUT_SPARSEKMAP=m
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVBUG=m
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=m
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+CONFIG_KEYBOARD_XTKBD=m
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+# CONFIG_VT_CONSOLE is not set
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_DAVINCI_WATCHDOG=m
+# CONFIG_MAX63XX_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=m
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_DAVINCI_SOC=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_3M_PCT is not set
+CONFIG_HID_A4TECH=m
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+# CONFIG_HID_DRAGONRISE is not set
+CONFIG_HID_EZKEY=m
+# CONFIG_HID_KYE is not set
+CONFIG_HID_GYRATION=m
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+CONFIG_HID_LOGITECH=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGIG940_FF is not set
+CONFIG_HID_MICROSOFT=m
+# CONFIG_HID_MOSART is not set
+CONFIG_HID_MONTEREY=m
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+CONFIG_HID_PANTHERLORD=m
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=m
+# CONFIG_HID_QUANTA is not set
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+# CONFIG_HID_STANTUM is not set
+CONFIG_HID_SUNPLUS=m
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=m
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_SOC=y
+
+#
+# DaVinci 35x and 644x USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+CONFIG_USB_MUSB_PERIPHERAL=y
+# CONFIG_USB_MUSB_OTG is not set
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_MUSB_PIO_ONLY=y
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_MASS_STORAGE is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+# CONFIG_USB_G_NOKIA is not set
+# CONFIG_USB_G_MULTI is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+CONFIG_NOP_USB_XCEIV=m
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_DAVINCI=y
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=m
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=m
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=m
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
-- 
1.7.0.4


From cyril at ti.com  Thu May  6 12:57:34 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu, 06 May 2010 13:57:34 -0400
Subject: [PATCH v5 0/6] Davinci: initial tnetv107x patch series
In-Reply-To: <1273168508-5990-1-git-send-email-cyril@ti.com>
References: <1273168508-5990-1-git-send-email-cyril@ti.com>
Message-ID: <4BE3030E.5050107@ti.com>

Hi,

Correction:
> These changes (including earlier gpio, misc, and ioremap series) were tested
> on tnetv107x evm. dm355 evm, and da850 evm.

da8xx has not been tested yet.

Regards
Cyril.

From khilman at deeprootsystems.com  Thu May  6 15:54:35 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 13:54:35 -0700
Subject: [PATCH v5 0/5] Davinci: pre-tnetv107x gpio series
In-Reply-To: <1272753475-21727-1-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Sat\, 1 May 2010 18\:37\:50 -0400")
References: <1272753475-21727-1-git-send-email-cyril@ti.com>
Message-ID: <87d3x8rbsk.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This patch series brings in several improvements in the davinci gpio code.
> This renames gpio related structures and functions to improve readability.
> Further, this restructures data structures so that a variety of gpio
> controller types can easily fit into the inlined gpio accessor implementation.
>
> This series has been tested on dm355 (thanks to Sandeep) and on tnetv107x
> platforms.

Thanks, applying this series.   queuing for 2.6.35 in davinci-next

Kevin


From khilman at deeprootsystems.com  Thu May  6 15:54:50 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 13:54:50 -0700
Subject: [PATCH v5 0/2] pre-tnetv107x miscellaneous series
In-Reply-To: <1272753508-22549-1-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Sat\, 1 May 2010 18\:38\:26 -0400")
References: <1272753508-22549-1-git-send-email-cyril@ti.com>
Message-ID: <878w7wrbs5.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This series contains a couple of pretty unrelated changes that (a) eliminate
> redundant PINMUX macro definitions, and (b) allow derivative socs (e.g.
> tnetv107x) to implement machine reset schemes using non-Timer64 hardware.
>
> This series has been tested on dm355 (thanks to Sandeep) and tnetv107x
> hardware.
>
> Cyril Chemparathy (2):
>   Davinci: eliminate pinmux offset verbosity
>   Davinci: watchdog reset separation across socs

Thanks, applying this series.   queuing for 2.6.35 in davinci-next

Kevin

From khilman at deeprootsystems.com  Thu May  6 16:07:37 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 14:07:37 -0700
Subject: [PATCH v2 1/8] Davinci: gpio - use ioremap()
In-Reply-To: <1272753528-22981-2-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Sat\, 1 May 2010 18\:38\:41 -0400")
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
	<1272753528-22981-2-git-send-email-cyril@ti.com>
Message-ID: <874oikrb6u.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This patch modifies the gpio_base definition in davinci_soc_info to be a
> physical address, which is then ioremap()ed by the gpio initialization
> function.
>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> ---
> v2: fixed raw_write to soc_info->gpio_base 

[...]

> @@ -157,6 +157,10 @@ static int __init davinci_gpio_setup(void)
>  	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
>  		ngpio = DAVINCI_N_GPIO;
>  
> +	gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
> +	if (WARN_ON(!gpio_base))
> +		return -EINVAL;

-ENOMEM please

Kevin

From khilman at deeprootsystems.com  Thu May  6 16:07:59 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 14:07:59 -0700
Subject: [PATCH v2 2/8] Davinci: da8xx: rtc - use ioremap
In-Reply-To: <1272753528-22981-3-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Sat\, 1 May 2010 18\:38\:42 -0400")
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
	<1272753528-22981-3-git-send-email-cyril@ti.com>
Message-ID: <87zl0cpwls.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This patch modifies the RTC unlock code to use ioremap() maps instead of
> IO_ADDRESS() translation.
>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> ---
> v2: unchanged from v1
>
>  arch/arm/mach-davinci/devices-da8xx.c |   11 +++++++++--
>  1 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
> index 67a6fbc..e8b263b 100644
> --- a/arch/arm/mach-davinci/devices-da8xx.c
> +++ b/arch/arm/mach-davinci/devices-da8xx.c
> @@ -584,10 +584,17 @@ static struct platform_device da8xx_rtc_device = {
>  int da8xx_register_rtc(void)
>  {
>  	int ret;
> +	void __iomem *base;
> +
> +	base = ioremap(DA8XX_RTC_BASE, SZ_4K);
> +	if (WARN_ON(!base))
> +		return -EINVAL;

-ENOMEM

Kevin

From khilman at deeprootsystems.com  Thu May  6 16:11:46 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 14:11:46 -0700
Subject: [PATCH v2 7/8] Davinci: pinmux - use ioremap()
In-Reply-To: <1272753528-22981-8-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Sat\, 1 May 2010 18\:38\:47 -0400")
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
	<1272753528-22981-8-git-send-email-cyril@ti.com>
Message-ID: <87tyqkpwfh.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This patch modifies the pinmux implementation so as to ioremap() the pinmux
> register area on first use.
>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> ---
> v2: bug --> warn
>

[...]

> @@ -29,14 +31,17 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
>  {
>  	static DEFINE_SPINLOCK(mux_spin_lock);
>  	struct davinci_soc_info *soc_info = &davinci_soc_info;
> -	void __iomem *base = soc_info->pinmux_base;
>  	unsigned long flags;
>  	const struct mux_config *cfg;
>  	unsigned int reg_orig = 0, reg = 0;
>  	unsigned int mask, warn = 0;
>  
> -	if (!soc_info->pinmux_pins)
> -		BUG();
> +	WARN_ON(!soc_info->pinmux_pins);
> +
> +	if (!pinmux_base) {
> +		pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
> +		WARN_ON(!pinmux_base);

probably should fail gracefully here, otherwise... 

> +	}
>  
>  	if (index >= soc_info->pinmux_pins_num) {
>  		printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
> @@ -57,7 +62,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
>  		unsigned	tmp1, tmp2;
>  
>  		spin_lock_irqsave(&mux_spin_lock, flags);
> -		reg_orig = __raw_readl(base + cfg->mux_reg);
> +		reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);

accesses like this will fault.

Kevin

From sshtylyov at mvista.com  Thu May  6 16:11:43 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 07 May 2010 01:11:43 +0400
Subject: [PATCH 1/4] DM365: Make all SPI units SPI0..SPI4 available
In-Reply-To: <201005061115.16291.thomas.koeller@baslerweb.com>
References: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>	<1272993504-1189-2-git-send-email-thomas.koeller@baslerweb.com>	<B85A65D85D7EB246BE421B3FB0FBB59301E6D3D34F@dbde02.ent.ti.com>
	<201005061115.16291.thomas.koeller@baslerweb.com>
Message-ID: <4BE3308F.4070409@mvista.com>

Hello.

Thomas Koeller wrote:

> On Wednesday 05 May 2010 11:32:00 Nori, Sekhar wrote:
>   
>> Have you based your code on the latest of Kevin's tree?
>> I don't see the additional IORESOURCE_DMA_* flags in the
>> current tree.
>>     
>
> No, all my patches are against the 'arago-project.org/git/projects/linux-davinci.git'
> repository, because that is what I am working with.
>   

   You should have noted that when posting the patches. The Arago trees 
are usually far beyond the official linux.davinci tree. Usually, patches 
against those tree are not posted here (TI commits them without posting 
anywhere :-)...

WBR, Sergei


From khilman at deeprootsystems.com  Thu May  6 16:39:32 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 14:39:32 -0700
Subject: [RFC 00/22] Davinci: pre-tnetv107x ioremap() cleanup
In-Reply-To: <4BDCADC3.5060900@ti.com> (Cyril Chemparathy's message of "Sat\,
	01 May 2010 18\:40\:03 -0400")
References: <1272580062-17663-1-git-send-email-cyril@ti.com>
	<874oiseh7f.fsf@deeprootsystems.com> <4BDCADC3.5060900@ti.com>
Message-ID: <87mxwcpv57.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> Hi Kevin,
>
> [...]
>> So as a next step, lets break out the stuff I mentioned as ready to
>> merge into a separate series, and get that applied and in davinci-next
>> for 2.6.35.  Then, fixup some of the very minor issues I pointed out
>> and get some more testing on your ioremap series for the existing
>> platforms as well...
>
> I have sent out the following series over the past few minutes:
>   - pre-tnetv107x gpio series
>   - pre-tnetv107x miscellaneous series
>   - pre-tnetv107x ioremap series
>
> The dmx (and presumably da8xx) boot problem was because of a left-over
> raw_write to soc_info->gpio_base, and the fix was included in this burst.

With new series,

Boot test OK on dmx (tested on dm355, dm6446 and dm6467)

Boot test fails on da850, more on this in a bit...

Kevin


From khilman at deeprootsystems.com  Thu May  6 16:46:57 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 14:46:57 -0700
Subject: [PATCH v2 3/8] Davinci: jtag_id - use ioremap()
In-Reply-To: <1272753528-22981-4-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Sat\, 1 May 2010 18\:38\:43 -0400")
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
	<1272753528-22981-4-git-send-email-cyril@ti.com>
Message-ID: <87fx24pusu.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This patch replaces the jtag id base info in davinci_soc_info with a physical
> address which is then ioremap()ed within common code.
>
> This patch (in combination with a similar change for PSC) will allow us to
> eliminate the SYSCFG nastiness in DA8xx code.
>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> ---
> v2: fixed return value on ioremap failure

This one was failing on da8xx...

>  arch/arm/mach-davinci/common.c              |   49 +++++++++++++++-----------
>  arch/arm/mach-davinci/da830.c               |    3 +-
>  arch/arm/mach-davinci/da850.c               |    3 +-
>  arch/arm/mach-davinci/dm355.c               |    2 +-
>  arch/arm/mach-davinci/dm365.c               |    2 +-
>  arch/arm/mach-davinci/dm644x.c              |    2 +-
>  arch/arm/mach-davinci/dm646x.c              |    2 +-
>  arch/arm/mach-davinci/include/mach/common.h |    2 +-
>  8 files changed, 35 insertions(+), 30 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
> index f8221c5..ddbd57b 100644
> --- a/arch/arm/mach-davinci/common.c
> +++ b/arch/arm/mach-davinci/common.c
> @@ -37,26 +37,42 @@ void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context)
>  		pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
>  }
>  
> -static struct davinci_id * __init davinci_get_id(u32 jtag_id)
> +static int __init davinci_init_id(struct davinci_soc_info *soc_info)
>  {
> -	int i;
> -	struct davinci_id *dip;
> -	u8 variant = (jtag_id & 0xf0000000) >> 28;
> -	u16 part_no = (jtag_id & 0x0ffff000) >> 12;
> +	int			i;
> +	struct davinci_id	*dip;
> +	u8			variant;
> +	u16			part_no;
> +	void __iomem		*base;
> +
> +	base = ioremap(davinci_soc_info.jtag_id_reg, SZ_4K);

...because here you're assuming this value is an absolute physical address...

[...]

> diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
> index 4f5727f..115f791 100644
> --- a/arch/arm/mach-davinci/da830.c
> +++ b/arch/arm/mach-davinci/da830.c
> @@ -1188,6 +1188,7 @@ static struct davinci_timer_info da830_timer_info = {
>  static struct davinci_soc_info davinci_soc_info_da830 = {
>  	.io_desc		= da830_io_desc,
>  	.io_desc_num		= ARRAY_SIZE(da830_io_desc),
> +	.jtag_id_reg		= DA8XX_JTAG_ID_REG,

and here it is set as just the offset.

>  	.ids			= da830_ids,
>  	.ids_num		= ARRAY_SIZE(da830_ids),
>  	.cpu_clks		= da830_clks,
> @@ -1215,8 +1216,6 @@ void __init da830_init(void)
>  	if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
>  		return;
>  
> -	davinci_soc_info_da830.jtag_id_base =
> -					DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
>  	davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
>  
>  	davinci_common_init(&davinci_soc_info_da830);
> diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
> index cb7f663..7c0ce45 100644
> --- a/arch/arm/mach-davinci/da850.c
> +++ b/arch/arm/mach-davinci/da850.c
> @@ -1073,6 +1073,7 @@ no_ddrpll_mem:
>  static struct davinci_soc_info davinci_soc_info_da850 = {
>  	.io_desc		= da850_io_desc,
>  	.io_desc_num		= ARRAY_SIZE(da850_io_desc),
> +	.jtag_id_reg		= DA8XX_JTAG_ID_REG,

Here too.


Fold the patch below into this patch and it boots on da8xx.


Kevin


diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 6804a59..3a7a96f 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1185,7 +1185,7 @@ static struct davinci_timer_info da830_timer_info = {
 static struct davinci_soc_info davinci_soc_info_da830 = {
 	.io_desc		= da830_io_desc,
 	.io_desc_num		= ARRAY_SIZE(da830_io_desc),
-	.jtag_id_reg		= DA8XX_JTAG_ID_REG,
+	.jtag_id_reg		= DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
 	.ids			= da830_ids,
 	.ids_num		= ARRAY_SIZE(da830_ids),
 	.cpu_clks		= da830_clks,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index a08cb91..6b8331b 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1070,7 +1070,7 @@ no_ddrpll_mem:
 static struct davinci_soc_info davinci_soc_info_da850 = {
 	.io_desc		= da850_io_desc,
 	.io_desc_num		= ARRAY_SIZE(da850_io_desc),
-	.jtag_id_reg		= DA8XX_JTAG_ID_REG,
+	.jtag_id_reg		= DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
 	.ids			= da850_ids,
 	.ids_num		= ARRAY_SIZE(da850_ids),
 	.cpu_clks		= da850_clks,

From khilman at deeprootsystems.com  Thu May  6 16:48:22 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 14:48:22 -0700
Subject: [PATCH v2 3/8] Davinci: jtag_id - use ioremap()
In-Reply-To: <1272753528-22981-4-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Sat\, 1 May 2010 18\:38\:43 -0400")
References: <1272753528-22981-1-git-send-email-cyril@ti.com>
	<1272753528-22981-4-git-send-email-cyril@ti.com>
Message-ID: <87aascpuqh.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This patch replaces the jtag id base info in davinci_soc_info with a physical
> address which is then ioremap()ed within common code.
>
> This patch (in combination with a similar change for PSC) will allow us to
> eliminate the SYSCFG nastiness in DA8xx code.
>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> ---
> v2: fixed return value on ioremap failure

one other minor comment/question:

>  arch/arm/mach-davinci/common.c              |   49 +++++++++++++++-----------
>  arch/arm/mach-davinci/da830.c               |    3 +-
>  arch/arm/mach-davinci/da850.c               |    3 +-
>  arch/arm/mach-davinci/dm355.c               |    2 +-
>  arch/arm/mach-davinci/dm365.c               |    2 +-
>  arch/arm/mach-davinci/dm644x.c              |    2 +-
>  arch/arm/mach-davinci/dm646x.c              |    2 +-
>  arch/arm/mach-davinci/include/mach/common.h |    2 +-
>  8 files changed, 35 insertions(+), 30 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
> index f8221c5..ddbd57b 100644
> --- a/arch/arm/mach-davinci/common.c
> +++ b/arch/arm/mach-davinci/common.c
> @@ -37,26 +37,42 @@ void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context)
>  		pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
>  }
>  
> -static struct davinci_id * __init davinci_get_id(u32 jtag_id)
> +static int __init davinci_init_id(struct davinci_soc_info *soc_info)
>  {
> -	int i;
> -	struct davinci_id *dip;
> -	u8 variant = (jtag_id & 0xf0000000) >> 28;
> -	u16 part_no = (jtag_id & 0x0ffff000) >> 12;
> +	int			i;
> +	struct davinci_id	*dip;
> +	u8			variant;
> +	u16			part_no;
> +	void __iomem		*base;
> +
> +	base = ioremap(davinci_soc_info.jtag_id_reg, SZ_4K);

not sure that it matters at this point, but should you be using
the soc_info ptr passed in here instead of the global one?

If there's no difference, for readabiliy sake, using the passed in
value would be less confusing.

Kevin

From khilman at deeprootsystems.com  Thu May  6 17:01:18 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 15:01:18 -0700
Subject: [PATCH v1 0/3] Davinci: pre-tnetv107x serial series
In-Reply-To: <1272824894-23456-1-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Sun\, 2 May 2010 14\:28\:11 -0400")
References: <1272824894-23456-1-git-send-email-cyril@ti.com>
Message-ID: <871vdopu4x.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This series implements a few cleanups as a preparation to tnetv107x inclusion.
> IO_ADDRESS usage has been eliminated from serial code, and the serial init no
> longer assumes the presence of pwremu registers.
>
> This series has been tested on dm355evm and tnetv107x platforms, and stacks on
> top of the pre-tnetv107x gpio, misc, and ioremap series.

Looks great.

I also tested without the ioremap series and it worked fine on dmx and da8xx so
applying this series and adding to davinci-next for 2.6.35.

Kevin

From khilman at deeprootsystems.com  Thu May  6 17:17:35 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 15:17:35 -0700
Subject: [PATCH 1/5] davinci: edma: use a more intuitive name for edma_info
In-Reply-To: <1272962499-18932-2-git-send-email-nsekhar@ti.com> (Sekhar Nori's
	message of "Tue\, 4 May 2010 14\:11\:35 +0530")
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
Message-ID: <87vdb0oetc.fsf@deeprootsystems.com>

Sekhar Nori <nsekhar at ti.com> writes:

> 'edma_info' structure inside the edma driver represents
> a single instance of edma channel controller. Call it
> 'edma_cc' instead. This also avoids readers confusing
> it with an instance of edma_soc_info structre which
> carries the platform data for a single channel controller
> instance.
>
> Signed-off-by: Sekhar Nori <nsekhar at ti.com>

ok, applying, queueing for 2.6.35 in davinci-next.

Kevin

From khilman at deeprootsystems.com  Thu May  6 17:18:00 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 15:18:00 -0700
Subject: [PATCH 2/5] davinci: edma: fix coding style issue related to
	usage of braces
In-Reply-To: <1272962499-18932-3-git-send-email-nsekhar@ti.com> (Sekhar Nori's
	message of "Tue\, 4 May 2010 14\:11\:36 +0530")
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
	<1272962499-18932-3-git-send-email-nsekhar@ti.com>
Message-ID: <87r5looesn.fsf@deeprootsystems.com>

Sekhar Nori <nsekhar at ti.com> writes:

> In the edma driver, there are couple of instances where braces
> are used for a single statement 'if' construct.
>
> There are other instances where 'else' part of the if-else construct
> does not use braces even if the 'if' part is a multi-line statement.
>
> This patch fixes both.
>
> Signed-off-by: Sekhar Nori <nsekhar at ti.com>

ok, applying.  queuing for 2.6.35 in davinci-next.

Kevin

From khilman at deeprootsystems.com  Thu May  6 17:25:36 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 15:25:36 -0700
Subject: [PATCH 3/5] davinci: edma: fix coding style issues related to
	indentation
In-Reply-To: <1272962499-18932-4-git-send-email-nsekhar@ti.com> (Sekhar Nori's
	message of "Tue\, 4 May 2010 14\:11\:37 +0530")
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
	<1272962499-18932-3-git-send-email-nsekhar@ti.com>
	<1272962499-18932-4-git-send-email-nsekhar@ti.com>
Message-ID: <877hngoefz.fsf@deeprootsystems.com>

Sekhar Nori <nsekhar at ti.com> writes:

> In the edma driver some if statememnts are broken up such that
> the condition code is at the same indentation level as the
> statement block. This makes reading it particularly difficult.
>
> This patch fixes that issue.
>
> Signed-off-by: Sekhar Nori <nsekhar at ti.com>

Hmm, I'm with Sergei on this one...

> ---
>  arch/arm/mach-davinci/dma.c |   26 +++++++++++++-------------
>  1 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
> index cc5fcda..2734de9 100644
> --- a/arch/arm/mach-davinci/dma.c
> +++ b/arch/arm/mach-davinci/dma.c
> @@ -330,7 +330,7 @@ static int irq2ctlr(int irq)
>  	if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
>  		return 0;
>  	else if (irq >= edma_cc[1]->irq_res_start &&
> -		irq <= edma_cc[1]->irq_res_end)
> +				irq <= edma_cc[1]->irq_res_end)

I much prefer the former style.  IMO, all that's needed here is adding
one space on the 2nd line so both 'irq's align.

In Emacs with (c-set-style "linux"), just hitting TAB to get
indentation will get you this style, without having to worry about
tabs/spaces etc.

>  		return 1;
>  
>  	return -1;
> @@ -352,7 +352,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
>  	dev_dbg(data, "dma_irq_handler\n");
>  
>  	if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
> -	    && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
> +			&& (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))

and here, the '&&' should be moved up and the second line aligned with
the first (e.g. the 'edma_shaadow0_read_array' calls aligned.


>  		return IRQ_NONE;
>  
>  	while (1) {
> @@ -406,9 +406,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
>  	dev_dbg(data, "dma_ccerr_handler\n");
>  
>  	if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
> -	    (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
> -	    (edma_read(ctlr, EDMA_QEMR) == 0) &&
> -	    (edma_read(ctlr, EDMA_CCERR) == 0))
> +			(edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
> +			(edma_read(ctlr, EDMA_QEMR) == 0) &&
> +			(edma_read(ctlr, EDMA_CCERR) == 0))

I prefer the former: TAB + some extra spaces to handle readable
alignment.

>  		return IRQ_NONE;
>  
>  	while (1) {
> @@ -469,9 +469,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
>  			}
>  		}
>  		if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
> -		    && (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
> -		    && (edma_read(ctlr, EDMA_QEMR) == 0)
> -		    && (edma_read(ctlr, EDMA_CCERR) == 0))
> +				&& (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
> +				&& (edma_read(ctlr, EDMA_QEMR) == 0)
> +				&& (edma_read(ctlr, EDMA_CCERR) == 0))

and here, I would just make it look like the hunk above.

>  			break;
>  		cnt++;
>  		if (cnt > 10)
> @@ -773,7 +773,7 @@ void edma_free_slot(unsigned slot)
>  	slot = EDMA_CHAN_SLOT(slot);
>  
>  	if (slot < edma_cc[ctlr]->num_channels ||
> -		slot >= edma_cc[ctlr]->num_slots)
> +			slot >= edma_cc[ctlr]->num_slots)

again the 'slot' should align using a TAB plus extra spaces.

[...]

I think you get the point, so I wont keep going.

But really, just use Emacs, set add (c-set-style "linux") to your
~/.emacs, then just hit 'TAB' and you'll get (at least I think is)
proper indentation.

Kevin


From khilman at deeprootsystems.com  Thu May  6 17:27:41 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 15:27:41 -0700
Subject: [PATCH 4/5] davinci: edma: fix coding style issues related to
	long lines
In-Reply-To: <1272962499-18932-5-git-send-email-nsekhar@ti.com> (Sekhar Nori's
	message of "Tue\, 4 May 2010 14\:11\:38 +0530")
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
	<1272962499-18932-3-git-send-email-nsekhar@ti.com>
	<1272962499-18932-4-git-send-email-nsekhar@ti.com>
	<1272962499-18932-5-git-send-email-nsekhar@ti.com>
Message-ID: <87zl0cmzs2.fsf@deeprootsystems.com>

Sekhar Nori <nsekhar at ti.com> writes:

> In the edma driver, some lines are broken up at really
> odd places to meet the 80 chars per line rule. This make
> reading those parts particularly difficult.
>
> This patch fixes that by creating a few lines over 80
> characters, but I feel it still improves readability over
> what is existing currently.

This version is more readable (barring similar alignmen comments from
previous patch) but...  this code really needs some subroutines
(inlines?) to make it so that there aren't lines > 80 characters. 

That would solve all the problems, although requiring a little more
work on your part.

Kevin

From khilman at deeprootsystems.com  Thu May  6 17:28:23 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 15:28:23 -0700
Subject: [PATCH 5/5] davinci: edma: use BIT() wherever possible
In-Reply-To: <1272962499-18932-6-git-send-email-nsekhar@ti.com> (Sekhar Nori's
	message of "Tue\, 4 May 2010 14\:11\:39 +0530")
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
	<1272962499-18932-3-git-send-email-nsekhar@ti.com>
	<1272962499-18932-4-git-send-email-nsekhar@ti.com>
	<1272962499-18932-5-git-send-email-nsekhar@ti.com>
	<1272962499-18932-6-git-send-email-nsekhar@ti.com>
Message-ID: <87tyqkmzqw.fsf@deeprootsystems.com>

Sekhar Nori <nsekhar at ti.com> writes:

> This patch replaces occurences of (1 << x) with
> BIT(x) as it makes for much better reading.
>
> Signed-off-by: Sekhar Nori <nsekhar at ti.com>

This one is fine, but depends on the previous 2 which I didn't like, so
holding off on this one for now.

Kevin

From khilman at deeprootsystems.com  Thu May  6 17:36:07 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 15:36:07 -0700
Subject: [PATCH 1/1] Davinci SDIO Support
In-Reply-To: <1272983472-22219-1-git-send-email-alagusankar@embwise.com>
	(Alagu Sankar's message of "Tue\, 4 May 2010 20\:01\:12 +0530")
References: <1272983472-22219-1-git-send-email-alagusankar@embwise.com>
Message-ID: <87k4rgmze0.fsf@deeprootsystems.com>

Alagu Sankar <alagusankar at embwise.com> writes:

> Added SDIO Support for Davinci.  Tested on DM355 EVM with Marvell SD8385 and
> SD8686 cards using Libertas SDIO driver. This requires additional patches for
> Libertas SDIO interface as indicated in the linux-wireless mailing list and
> as referenced in the following links
>
> http://marc.info/?l=linux-wireless&m=127136330220026&w=2
> http://marc.info/?l=linux-wireless&m=127136362020814&w=2
>
> Signed-off-by: Alagu Sankar <alagusankar at embwise.com>

This driver should be posted to linux-mmc as well as this list Cc'd.

Some minor comments below...

> ---
>  drivers/mmc/host/davinci_mmc.c |   98 +++++++++++++++++++++++++++++++++++++--
>  1 files changed, 93 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
> index e4d1591..4afa6bf 100644
> --- a/drivers/mmc/host/davinci_mmc.c
> +++ b/drivers/mmc/host/davinci_mmc.c
> @@ -66,8 +66,8 @@
>  #define DAVINCI_MMCBLNC      0x60
>  #define DAVINCI_SDIOCTL      0x64
>  #define DAVINCI_SDIOST0      0x68
> -#define DAVINCI_SDIOEN       0x6C
> -#define DAVINCI_SDIOST       0x70
> +#define DAVINCI_SDIOIEN      0x6C
> +#define DAVINCI_SDIOIST      0x70
>  #define DAVINCI_MMCFIFOCTL   0x74 /* FIFO Control Register             */
>  
>  /* DAVINCI_MMCCTL definitions */
> @@ -135,6 +135,23 @@
>  /* MMCSD Init clock in Hz in opendrain mode */
>  #define MMCSD_INIT_CLOCK		200000
>  
> +/* DAVINCI_SDIOCTL definitions */
> +#define SDIOCTL_RDWTRQ_SET    BIT(0)
> +#define SDIOCTL_RDWTCR_SET    BIT(1)
> +
> +/* DAVINCI_SDIOST0 definitions */
> +#define SDIOST0_DAT1_HI       BIT(0)
> +#define SDIOST0_INTPRD        BIT(1)
> +#define SDIOST0_RDWTST        BIT(2)
> +
> +/* DAVINCI_SDIOIEN definitions */
> +#define SDIOIEN_IOINTEN       BIT(0)
> +#define SDIOIEN_RWSEN         BIT(1)
> +
> +/* DAVINCI_SDIOIST definitions */
> +#define SDIOIST_IOINT         BIT(0)
> +#define SDIOIST_RWS           BIT(1)
> +
>  /*
>   * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units,
>   * and we handle up to MAX_NR_SG segments.  MMC_BLOCK_BOUNCE kicks in only
> @@ -147,6 +164,8 @@
>  
>  #define MAX_NR_SG	16
>  
> +#define DAVINCI_SDIO_IRQ(dev_id)	(((dev_id) == 0) ? "sdio0" : "sdio1")
> +
>  static unsigned rw_threshold = 32;
>  module_param(rw_threshold, uint, S_IRUGO);
>  MODULE_PARM_DESC(rw_threshold,
> @@ -164,7 +183,7 @@ struct mmc_davinci_host {
>  	unsigned int mmc_input_clk;
>  	void __iomem *base;
>  	struct resource *mem_res;
> -	int irq;
> +	int mmc_irq, sdio_irq;
>  	unsigned char bus_mode;
>  
>  #define DAVINCI_MMC_DATADIR_NONE	0
> @@ -184,6 +203,7 @@ struct mmc_davinci_host {
>  	u32 rxdma, txdma;
>  	bool use_dma;
>  	bool do_dma;
> +	bool sdio_int;
>  
>  	/* Scatterlist DMA uses one or more parameter RAM entries:
>  	 * the main one (associated with rxdma or txdma) plus zero or
> @@ -866,6 +886,19 @@ mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data)
>  {
>  	host->data = NULL;
>  
> +	if (host->mmc->caps & MMC_CAP_SDIO_IRQ) {
> +		/* SDIO Interrupt Detection work-around as suggested by
> +		 * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata
> +		 * 2.1.5)
> +		 * Signal SDIO interrupt only if it is enabled by core
> +		 */

please fix multi-line comment style.  Search for 'multi-line' in 
Documentation/CodingStyle.

> +		if (host->sdio_int && (!((readl(host->base + DAVINCI_SDIOST0))
> +					& SDIOST0_DAT1_HI))) {
> +			writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
> +			mmc_signal_sdio_irq(host->mmc);
> +		}
> +	}
> +
>  	if (host->do_dma) {
>  		davinci_abort_dma(host);
>  
> @@ -932,6 +965,22 @@ davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data)
>  	mmc_davinci_reset_ctrl(host, 0);
>  }
>  
> +static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id)
> +{
> +	struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
> +	unsigned int status;
> +
> +	status = readl(host->base + DAVINCI_SDIOIST);
> +	if (status & SDIOIST_IOINT) {
> +		dev_dbg(mmc_dev(host->mmc),
> +				"SDIO interrupt status %x\n", status);
> +		writel(status | SDIOIST_IOINT,
> +				host->base + DAVINCI_SDIOIST);
> +		mmc_signal_sdio_irq(host->mmc);
> +	}
> +	return IRQ_HANDLED;
> +}
> +
>  static irqreturn_t mmc_davinci_irq(int irq, void *dev_id)
>  {
>  	struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
> @@ -1076,11 +1125,34 @@ static int mmc_davinci_get_ro(struct mmc_host *mmc)
>  	return config->get_ro(pdev->id);
>  }
>  
> +static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable)
> +{
> +	struct mmc_davinci_host *host = mmc_priv(mmc);
> +
> +	if (enable) {
> +		if (!((readl(host->base + DAVINCI_SDIOST0))
> +					& SDIOST0_DAT1_HI)) {
> +			writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
> +			mmc_signal_sdio_irq(host->mmc);
> +		} else {
> +			host->sdio_int = 1;
> +			writel(readl(host->base + DAVINCI_SDIOIEN) |
> +				SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN);
> +		}
> +	} else {
> +		host->sdio_int = 0;
> +		writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN,
> +				host->base + DAVINCI_SDIOIEN);
> +	}
> +
> +}
> +
>  static struct mmc_host_ops mmc_davinci_ops = {
>  	.request	= mmc_davinci_request,
>  	.set_ios	= mmc_davinci_set_ios,
>  	.get_cd		= mmc_davinci_get_cd,
>  	.get_ro		= mmc_davinci_get_ro,
> +	.enable_sdio_irq = mmc_davinci_enable_sdio_irq,
>  };
>  
>  /*----------------------------------------------------------------------*/
> @@ -1209,7 +1281,8 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev)
>  		host->nr_sg = MAX_NR_SG;
>  
>  	host->use_dma = use_dma;
> -	host->irq = irq;
> +	host->mmc_irq = irq;
> +	host->sdio_irq = platform_get_irq(pdev, 1);
>  
>  	if (host->use_dma && davinci_acquire_dma_channels(host) != 0)
>  		host->use_dma = 0;
> @@ -1272,6 +1345,19 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev)
>  	if (ret)
>  		goto out;
>  
> +	/* Failures in SDIO IRQ registration are ignored as the driver
> +	 * can still work in polled mode.
> +	 */

multi-line comment style

Also, even if failures can still function, maybe a warning would be
helpful here?

> +	if (host->sdio_irq != NO_IRQ) {
> +		ret = request_irq(host->sdio_irq,
> +				mmc_davinci_sdio_irq, 0,
> +				DAVINCI_SDIO_IRQ(pdev->id), host);
> +		if (ret == 0) {
> +			mmc->caps |= MMC_CAP_SDIO_IRQ;
> +			host->sdio_int = 0;
> +		}
> +	}
> +
>  	rename_region(mem, mmc_hostname(mmc));
>  
>  	dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n",
> @@ -1315,7 +1401,9 @@ static int __exit davinci_mmcsd_remove(struct platform_device *pdev)
>  		mmc_davinci_cpufreq_deregister(host);
>  
>  		mmc_remove_host(host->mmc);
> -		free_irq(host->irq, host);
> +		free_irq(host->mmc_irq, host);
> +		if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
> +			free_irq(host->sdio_irq, host);
>  
>  		davinci_release_dma_channels(host);

Kevin

From khilman at deeprootsystems.com  Thu May  6 17:44:26 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 15:44:26 -0700
Subject: [PATCH 1/4] DM365: Make all SPI units SPI0..SPI4 available
In-Reply-To: <4BE3308F.4070409@mvista.com> (Sergei Shtylyov's message of "Fri\,
	07 May 2010 01\:11\:43 +0400")
References: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
	<1272993504-1189-2-git-send-email-thomas.koeller@baslerweb.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E6D3D34F@dbde02.ent.ti.com>
	<201005061115.16291.thomas.koeller@baslerweb.com>
	<4BE3308F.4070409@mvista.com>
Message-ID: <87aascmz05.fsf@deeprootsystems.com>

Sergei Shtylyov <sshtylyov at mvista.com> writes:

> Hello.
>
> Thomas Koeller wrote:
>
>> On Wednesday 05 May 2010 11:32:00 Nori, Sekhar wrote:
>>   
>>> Have you based your code on the latest of Kevin's tree?
>>> I don't see the additional IORESOURCE_DMA_* flags in the
>>> current tree.
>>>     
>>
>> No, all my patches are against the 'arago-project.org/git/projects/linux-davinci.git'
>> repository, because that is what I am working with.
>>   
>
>   You should have noted that when posting the patches. 

Yes please.  Anytime patches are not against mainline or davinci git
master, the baseline should be noted.

> are usually far beyond the official linux.davinci tree. Usually,
> patches against those tree are not posted here

Also, the likelihood of me reviewing them when they don't apply to
davinci git master branch is low.  The likelihood of them being merged
is even lower due to dependences on Arago tree.

Kevin

From khilman at deeprootsystems.com  Thu May  6 17:48:28 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 15:48:28 -0700
Subject: [PATCH 4/4] DM365: Added PINMUX definitions for GPIO30..32
In-Reply-To: <1272993504-1189-5-git-send-email-thomas.koeller@baslerweb.com>
	(thomas koeller's message of "Tue\, 4 May 2010 19\:18\:24 +0200")
References: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
	<1272993504-1189-5-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <8739y4mytf.fsf@deeprootsystems.com>

thomas.koeller at baslerweb.com writes:

> From: Thomas Koeller <thomas.koeller at baslerweb.com>

This one needs a changelog.

Yes, it's a simple change and can be understood mostly from subject,
but is missing the answer to the question: why?

Kevin

> Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
> ---
>  arch/arm/mach-davinci/dm365.c            |    3 +++
>  arch/arm/mach-davinci/include/mach/mux.h |    3 +++
>  2 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
> index 0aea612..8fb7578 100644
> --- a/arch/arm/mach-davinci/dm365.c
> +++ b/arch/arm/mach-davinci/dm365.c
> @@ -579,6 +579,9 @@ MUX_CFG(DM365,	SPI4_SDENA0,	4,   20,    3,    1,	 false)
>  MUX_CFG(DM365,	SPI4_SDENA1,	4,   16,    3,    2,	 false)
>  
>  MUX_CFG(DM365,	GPIO20,		3,   21,    3,    0,	 false)
> +MUX_CFG(DM365,	GPIO30,		4,   6,     3,	  0,	 false)
> +MUX_CFG(DM365,	GPIO31,		4,   8,     3,	  0,	 false)
> +MUX_CFG(DM365,	GPIO32,		4,   10,    3,	  0,	 false)
>  MUX_CFG(DM365,	GPIO33,		4,   12,    3,	  0,	 false)
>  MUX_CFG(DM365,	GPIO40,		4,   26,    3,	  0,	 false)
>  
> diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
> index 05e35fa..49a2f57 100644
> --- a/arch/arm/mach-davinci/include/mach/mux.h
> +++ b/arch/arm/mach-davinci/include/mach/mux.h
> @@ -293,6 +293,9 @@ enum davinci_dm365_index {
>  
>  	/* GPIO */
>  	DM365_GPIO20,
> +	DM365_GPIO30,
> +	DM365_GPIO31,
> +	DM365_GPIO32,
>  	DM365_GPIO33,
>  	DM365_GPIO40,
>  
> -- 
> 1.7.0.3
>
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source

From khilman at deeprootsystems.com  Thu May  6 17:51:39 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 15:51:39 -0700
Subject: [PATCH 2/4] DM365: Add platform resource management
In-Reply-To: <1272993504-1189-3-git-send-email-thomas.koeller@baslerweb.com>
	(thomas koeller's message of "Tue\, 4 May 2010 19\:18\:22 +0200")
References: <1272993504-1189-1-git-send-email-thomas.koeller@baslerweb.com>
	<1272993504-1189-3-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <87tyqklk3o.fsf@deeprootsystems.com>

thomas.koeller at baslerweb.com writes:

> From: Thomas Koeller <thomas.koeller at baslerweb.com>
>
> Keeping track of resource assignments greatly simplifies the task of
> writing board support code.  Many drivers for DaVinci peripherals
> were using resources that had never been allocated, with the notable
> exception of memory resources.

This is common practice across the entire kernel, and personally, I
have no interest in making davinci the first platform to make use
of resources to track things at this level.

Kevin


> Non-conflicting resource assignment is a responsibility
> of the bus the devices are on, in this case, the platform bus.
>
> The resource management scheme implemented by this patch is not
> perfect. The SoC code really has no business managing resources,
> it should only provide them to the platform (board support) code.
> The board support is the only place where information about the
> intended use of the various hardware resources is available.
>
> Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>


From khilman at deeprootsystems.com  Thu May  6 18:04:21 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 16:04:21 -0700
Subject: [PATCH v5 0/6] Davinci: initial tnetv107x patch series
In-Reply-To: <4BE3030E.5050107@ti.com> (Cyril Chemparathy's message of "Thu\,
	06 May 2010 13\:57\:34 -0400")
References: <1273168508-5990-1-git-send-email-cyril@ti.com>
	<4BE3030E.5050107@ti.com>
Message-ID: <87pr18ljii.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> Hi,
>
> Correction:
>> These changes (including earlier gpio, misc, and ioremap series) were tested
>> on tnetv107x evm. dm355 evm, and da850 evm.
>
> da8xx has not been tested yet.

fyi... boot tested fine on da850 for me (leaving ARCH_DAVINCI_TNETV107X=n)

Kevin


From khilman at deeprootsystems.com  Thu May  6 18:12:46 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 06 May 2010 16:12:46 -0700
Subject: [PATCH v5 4/6] Davinci: tnetv107x initial gpio support
In-Reply-To: <1273168508-5990-5-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Thu\, 6 May 2010 13\:55\:06 -0400")
References: <1273168508-5990-1-git-send-email-cyril@ti.com>
	<1273168508-5990-5-git-send-email-cyril@ti.com>
Message-ID: <87d3x8lj4h.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This patch adds support for the tnetv107x gpio controller.

Should have a better changelog here.

This would be a good spot for a brief summary of the differences between
the two types of controllers.

Otherwise, looks ok.

Kevin


From khilman at deeprootsystems.com  Thu May  6 18:23:51 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:23:51 -0700
Subject: [PATCH 00/34] davinci updates for 2.6.35
Message-ID: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>

This series of updates to the TI DaVinci family is targetted for 2.6.35.

The bulk of the changes are some restructuring work to make room from
some new SoCs in this family (tnetv107x) that needed a little more
flexibility in some areas.

These are also currently included in linux-next and are available as
the davinci-next branch of the davinci git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git

Kevin



Anuj Aggarwal (1):
  davinci: edma: clear interrupt status for interrupt enabled channels
    only

Cyril Chemparathy (20):
  Davinci: allow SOCs based on other ARM CPUs
  Davinci: enable timer clock before use
  Davinci: cpintc host map configuration
  Davinci: support LPSC SwRstDisable state
  Davinci: promote da8xx_pinmux_setup()
  Davinci: tnetv107x pin list
  Davinci: tnetv107x LPSC modules
  Davinci: tnetv107x IRQ definitions
  Davinci: tnetv107x cpu types
  Davinci: configurable pll divider mask
  Davinci: gpio - minor cleanup
  Davinci: gpio - structs and functions renamed
  Davinci: gpio - register layout invariant inlines
  Davinci: gpio - controller type support
  Davinci: gpio - fine grained locking
  Davinci: eliminate pinmux offset verbosity
  Davinci: watchdog reset separation across socs
  Davinci: serial - remove unnecessary define
  Davinci: serial - use ioremap()
  Davinci: serial - conditional reset via pwremu

Kevin Hilman (2):
  davinci: misc cleanups from sparse
  davinci: sparse: gpio: void casting

Miguel Aguilar (1):
  RTC: DaVinci RTC driver

Sekhar Nori (3):
  rtc: omap: let device wakeup capability be configured from chip init
    logic
  davinci: edma: use a more intuitive name for edma_info
  davinci: edma: fix coding style issue related to usage of braces

Sergei Shtylyov (3):
  DaVinci: move AEMIF #define's to the proper headers
  DA830 EVM: use DA8XX_AEMIF_*_BASE #define's
  DaVinci: move IDE platform device to its proper place

Thomas Koeller (2):
  davinci: DM365: Allow use of GPIO64_57
  davinci: mach/common.h: add missing includes

Vipin Bhandari (2):
  davinci: da830/omap-l137 evm: add support for GPIO based MMC/SD card
    detection
  davinci: da830/omap-l137 evm: use 8-wire MMC/SD card support

 arch/arm/Kconfig                             |    1 -
 arch/arm/mach-davinci/Kconfig                |    2 +
 arch/arm/mach-davinci/board-da830-evm.c      |   44 ++-
 arch/arm/mach-davinci/board-da850-evm.c      |   20 +-
 arch/arm/mach-davinci/board-dm355-evm.c      |   11 +-
 arch/arm/mach-davinci/board-dm355-leopard.c  |   11 +-
 arch/arm/mach-davinci/board-dm365-evm.c      |    5 -
 arch/arm/mach-davinci/board-dm644x-evm.c     |   53 +--
 arch/arm/mach-davinci/board-dm646x-evm.c     |   13 +-
 arch/arm/mach-davinci/board-neuros-osd2.c    |   47 +--
 arch/arm/mach-davinci/board-sffsdr.c         |   13 +-
 arch/arm/mach-davinci/cdce949.c              |    1 +
 arch/arm/mach-davinci/clock.c                |   22 +-
 arch/arm/mach-davinci/clock.h                |    9 +-
 arch/arm/mach-davinci/common.c               |    3 +
 arch/arm/mach-davinci/cp_intc.c              |    6 +-
 arch/arm/mach-davinci/da830.c                |    3 +
 arch/arm/mach-davinci/da850.c                |    3 +
 arch/arm/mach-davinci/devices-da8xx.c        |    4 +-
 arch/arm/mach-davinci/devices.c              |   46 ++
 arch/arm/mach-davinci/dm355.c                |    9 +-
 arch/arm/mach-davinci/dm365.c                |   10 +-
 arch/arm/mach-davinci/dm644x.c               |    9 +-
 arch/arm/mach-davinci/dm646x.c               |   41 +--
 arch/arm/mach-davinci/dma.c                  |  182 ++++----
 arch/arm/mach-davinci/gpio.c                 |  154 ++++---
 arch/arm/mach-davinci/include/mach/common.h  |   11 +
 arch/arm/mach-davinci/include/mach/cp_intc.h |    2 +-
 arch/arm/mach-davinci/include/mach/cputype.h |    8 +
 arch/arm/mach-davinci/include/mach/da8xx.h   |   29 +-
 arch/arm/mach-davinci/include/mach/dm355.h   |    3 +
 arch/arm/mach-davinci/include/mach/dm365.h   |    4 +
 arch/arm/mach-davinci/include/mach/dm644x.h  |    6 +
 arch/arm/mach-davinci/include/mach/dm646x.h  |    4 +-
 arch/arm/mach-davinci/include/mach/gpio.h    |   72 ++--
 arch/arm/mach-davinci/include/mach/irqs.h    |   97 ++++
 arch/arm/mach-davinci/include/mach/mux.h     |  277 +++++++++++
 arch/arm/mach-davinci/include/mach/psc.h     |   55 ++-
 arch/arm/mach-davinci/include/mach/serial.h  |    1 -
 arch/arm/mach-davinci/include/mach/system.h  |    5 +-
 arch/arm/mach-davinci/mux.c                  |    2 +-
 arch/arm/mach-davinci/mux.h                  |    2 +-
 arch/arm/mach-davinci/psc.c                  |    3 +-
 arch/arm/mach-davinci/serial.c               |   34 +-
 arch/arm/mach-davinci/time.c                 |   15 +-
 drivers/rtc/Kconfig                          |   10 +
 drivers/rtc/Makefile                         |    1 +
 drivers/rtc/rtc-davinci.c                    |  673 ++++++++++++++++++++++++++
 drivers/rtc/rtc-omap.c                       |   12 +-
 49 files changed, 1591 insertions(+), 457 deletions(-)
 create mode 100644 drivers/rtc/rtc-davinci.c


From khilman at deeprootsystems.com  Thu May  6 18:23:52 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:23:52 -0700
Subject: [PATCH 01/34] davinci: misc cleanups from sparse
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-2-git-send-email-khilman@deeprootsystems.com>

- Convert data/functions to static
- include headers for missing declarations
- pointer cleanups:  struct foo *__iomem f --> struct foo __iomem *f;

Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/board-dm644x-evm.c  |    2 +-
 arch/arm/mach-davinci/board-neuros-osd2.c |    2 +-
 arch/arm/mach-davinci/board-sffsdr.c      |    2 +-
 arch/arm/mach-davinci/cdce949.c           |    1 +
 arch/arm/mach-davinci/clock.c             |    1 +
 arch/arm/mach-davinci/devices.c           |    2 ++
 arch/arm/mach-davinci/dm355.c             |    2 +-
 arch/arm/mach-davinci/dm365.c             |    2 +-
 arch/arm/mach-davinci/dm644x.c            |    4 ++--
 arch/arm/mach-davinci/dm646x.c            |    6 +++---
 arch/arm/mach-davinci/gpio.c              |   24 ++++++++++++------------
 arch/arm/mach-davinci/include/mach/gpio.h |    8 ++++----
 arch/arm/mach-davinci/mux.c               |    1 +
 13 files changed, 31 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 976e11b..95cef1f 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -111,7 +111,7 @@ static struct platform_device davinci_evm_norflash_device = {
  * It may used instead of the (default) NOR chip to boot, using TI's
  * tools to install the secondary boot loader (UBL) and U-Boot.
  */
-struct mtd_partition davinci_evm_nandflash_partition[] = {
+static struct mtd_partition davinci_evm_nandflash_partition[] = {
 	/* Bootloader layout depends on whose u-boot is installed, but we
 	 * can hide all the details.
 	 *  - block 0 for u-boot environment ... in mainline u-boot
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index bd9ca07..1fadc68 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -60,7 +60,7 @@
 
 #define NAND_BLOCK_SIZE		SZ_128K
 
-struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
+static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
 	{
 		/* UBL (a few copies) plus U-Boot */
 		.name		= "bootloader",
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 08d373b..a7cf810 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -48,7 +48,7 @@
 #define DAVINCI_ASYNC_EMIF_CONTROL_BASE   0x01e00000
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
 
-struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
+static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
 	/* U-Boot Environment: Block 0
 	 * UBL:                Block 1
 	 * U-Boot:             Blocks 6-7 (256 kb)
diff --git a/arch/arm/mach-davinci/cdce949.c b/arch/arm/mach-davinci/cdce949.c
index aec3756..ba8b12b 100644
--- a/arch/arm/mach-davinci/cdce949.c
+++ b/arch/arm/mach-davinci/cdce949.c
@@ -19,6 +19,7 @@
 #include <linux/i2c.h>
 
 #include <mach/clock.h>
+#include <mach/cdce949.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index bf6218e..058c77f 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -22,6 +22,7 @@
 
 #include <mach/hardware.h>
 
+#include <mach/clock.h>
 #include <mach/psc.h>
 #include <mach/cputype.h>
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 1479496..ef28080 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -23,6 +23,8 @@
 #include <mach/mmc.h>
 #include <mach/time.h>
 
+#include "clock.h"
+
 #define DAVINCI_I2C_BASE	     0x01C21000
 #define DAVINCI_MMCSD0_BASE	     0x01E10000
 #define DM355_MMCSD0_BASE	     0x01E11000
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 3dc0a88..5efce70 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -798,7 +798,7 @@ static void __iomem *dm355_psc_bases[] = {
  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
  * T1_TOP: Timer 1, top   :  <unused>
  */
-struct davinci_timer_info dm355_timer_info = {
+static struct davinci_timer_info dm355_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0d6ee58..871be5a 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1010,7 +1010,7 @@ static void __iomem *dm365_psc_bases[] = {
 	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 };
 
-struct davinci_timer_info dm365_timer_info = {
+static struct davinci_timer_info dm365_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 2f2ae8b..23cbe9d 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -277,7 +277,7 @@ static struct clk timer2_clk = {
 	.usecount = 1,              /* REVISIT: why cant' this be disabled? */
 };
 
-struct clk_lookup dm644x_clks[] = {
+static struct clk_lookup dm644x_clks[] = {
 	CLK(NULL, "ref", &ref_clk),
 	CLK(NULL, "pll1", &pll1_clk),
 	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@@ -687,7 +687,7 @@ static void __iomem *dm644x_psc_bases[] = {
  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
  * T1_TOP: Timer 1, top   :  <unused>
  */
-struct davinci_timer_info dm644x_timer_info = {
+static struct davinci_timer_info dm644x_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 893baf4..b67b997 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -311,7 +311,7 @@ static struct clk vpif1_clk = {
 	.flags = ALWAYS_ENABLED,
 };
 
-struct clk_lookup dm646x_clks[] = {
+static struct clk_lookup dm646x_clks[] = {
 	CLK(NULL, "ref", &ref_clk),
 	CLK(NULL, "aux", &aux_clkin),
 	CLK(NULL, "pll1", &pll1_clk),
@@ -797,7 +797,7 @@ static void __iomem *dm646x_psc_bases[] = {
  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
  * T1_TOP: Timer 1, top   :  <unused>
  */
-struct davinci_timer_info dm646x_timer_info = {
+static struct davinci_timer_info dm646x_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
@@ -867,7 +867,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.sram_len		= SZ_32K,
 };
 
-void __init dm646x_init_ide()
+void __init dm646x_init_ide(void)
 {
 	davinci_cfg_reg(DM646X_ATAEN);
 	platform_device_register(&ide_dev);
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 744755b..3f77062 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -24,14 +24,14 @@ static DEFINE_SPINLOCK(gpio_lock);
 
 struct davinci_gpio {
 	struct gpio_chip	chip;
-	struct gpio_controller	*__iomem regs;
+	struct gpio_controller	__iomem *regs;
 	int			irq_base;
 };
 
 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 
 /* create a non-inlined version */
-static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
+static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
 {
 	return __gpio_to_controller(gpio);
 }
@@ -48,7 +48,7 @@ static int __init davinci_gpio_irq_setup(void);
 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
 {
 	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller *__iomem g = d->regs;
+	struct gpio_controller __iomem *g = d->regs;
 	u32 temp;
 
 	spin_lock(&gpio_lock);
@@ -70,7 +70,7 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
 	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller *__iomem g = d->regs;
+	struct gpio_controller __iomem *g = d->regs;
 
 	return (1 << offset) & __raw_readl(&g->in_data);
 }
@@ -79,7 +79,7 @@ static int
 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
 {
 	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller *__iomem g = d->regs;
+	struct gpio_controller __iomem *g = d->regs;
 	u32 temp;
 	u32 mask = 1 << offset;
 
@@ -99,7 +99,7 @@ static void
 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
 	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller *__iomem g = d->regs;
+	struct gpio_controller __iomem *g = d->regs;
 
 	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
 }
@@ -161,7 +161,7 @@ pure_initcall(davinci_gpio_setup);
 
 static void gpio_irq_disable(unsigned irq)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	__raw_writel(mask, &g->clr_falling);
@@ -170,7 +170,7 @@ static void gpio_irq_disable(unsigned irq)
 
 static void gpio_irq_enable(unsigned irq)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = (u32) get_irq_data(irq);
 	unsigned status = irq_desc[irq].status;
 
@@ -186,7 +186,7 @@ static void gpio_irq_enable(unsigned irq)
 
 static int gpio_irq_type(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -215,7 +215,7 @@ static struct irq_chip gpio_irqchip = {
 static void
 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = 0xffff;
 
 	/* we only care about one bank */
@@ -276,7 +276,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 
 static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -305,7 +305,7 @@ static int __init davinci_gpio_irq_setup(void)
 	u32		binten = 0;
 	unsigned	ngpio, bank_irq;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	struct gpio_controller	*__iomem g;
+	struct gpio_controller	__iomem *g;
 
 	ngpio = soc_info->gpio_num;
 
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index f3b8ef8..0099e6e 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -67,10 +67,10 @@ struct gpio_controller {
  *
  * These are NOT part of the cross-platform GPIO interface
  */
-static inline struct gpio_controller *__iomem
+static inline struct gpio_controller __iomem *
 __gpio_to_controller(unsigned gpio)
 {
-	void *__iomem ptr;
+	void __iomem *ptr;
 	void __iomem *base = davinci_soc_info.gpio_base;
 
 	if (gpio < 32 * 1)
@@ -102,7 +102,7 @@ static inline u32 __gpio_mask(unsigned gpio)
 static inline void gpio_set_value(unsigned gpio, int value)
 {
 	if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
-		struct gpio_controller	*__iomem g;
+		struct gpio_controller	__iomem *g;
 		u32			mask;
 
 		g = __gpio_to_controller(gpio);
@@ -128,7 +128,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
  */
 static inline int gpio_get_value(unsigned gpio)
 {
-	struct gpio_controller	*__iomem g;
+	struct gpio_controller	__iomem *g;
 
 	if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
 		return __gpio_get_value(gpio);
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index f757e83..c942c89 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -21,6 +21,7 @@
 
 #include <mach/mux.h>
 #include <mach/common.h>
+#include <mach/da8xx.h>
 
 /*
  * Sets the DAVINCI MUX register based on the table
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:23:53 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:23:53 -0700
Subject: [PATCH 02/34] davinci: sparse: gpio: void casting
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-3-git-send-email-khilman@deeprootsystems.com>

Cleanup usage of void pointers when using genirq.  genirq API
takes and returns void *, where this GPIO API is using those
as __iomem pointers.

Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/gpio.c |   27 ++++++++++++++++++---------
 1 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 3f77062..5476ad1 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -36,6 +36,15 @@ static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
 	return __gpio_to_controller(gpio);
 }
 
+static inline struct gpio_controller __iomem *irq2controller(int irq)
+{
+	struct gpio_controller __iomem *g;
+
+	g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq);
+
+	return g;
+}
+
 static int __init davinci_gpio_irq_setup(void);
 
 /*--------------------------------------------------------------------------*/
@@ -161,7 +170,7 @@ pure_initcall(davinci_gpio_setup);
 
 static void gpio_irq_disable(unsigned irq)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	__raw_writel(mask, &g->clr_falling);
@@ -170,7 +179,7 @@ static void gpio_irq_disable(unsigned irq)
 
 static void gpio_irq_enable(unsigned irq)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = (u32) get_irq_data(irq);
 	unsigned status = irq_desc[irq].status;
 
@@ -186,7 +195,7 @@ static void gpio_irq_enable(unsigned irq)
 
 static int gpio_irq_type(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -215,7 +224,7 @@ static struct irq_chip gpio_irqchip = {
 static void
 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = 0xffff;
 
 	/* we only care about one bank */
@@ -276,7 +285,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 
 static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -362,7 +371,7 @@ static int __init davinci_gpio_irq_setup(void)
 		for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
 			set_irq_chip(irq, &gpio_irqchip_unbanked);
 			set_irq_data(irq, (void *) __gpio_mask(gpio));
-			set_irq_chip_data(irq, g);
+			set_irq_chip_data(irq, (__force void *) g);
 			irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
 		}
 
@@ -385,12 +394,12 @@ static int __init davinci_gpio_irq_setup(void)
 
 		/* set up all irqs in this bank */
 		set_irq_chained_handler(bank_irq, gpio_irq_handler);
-		set_irq_chip_data(bank_irq, g);
-		set_irq_data(bank_irq, (void *)irq);
+		set_irq_chip_data(bank_irq, (__force void *) g);
+		set_irq_data(bank_irq, (void *) irq);
 
 		for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
 			set_irq_chip(irq, &gpio_irqchip);
-			set_irq_chip_data(irq, g);
+			set_irq_chip_data(irq, (__force void *) g);
 			set_irq_data(irq, (void *) __gpio_mask(gpio));
 			set_irq_handler(irq, handle_simple_irq);
 			set_irq_flags(irq, IRQF_VALID);
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:23:54 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:23:54 -0700
Subject: [PATCH 03/34] davinci: da830/omap-l137 evm: add support for GPIO
	based MMC/SD card detection
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-4-git-send-email-khilman@deeprootsystems.com>

From: Vipin Bhandari <vipin.bhandari at ti.com>

The DA830/OMAP-L137 EVM has GPIO based card detection logic, but the current
code does not use it.

Add support for GPIO based card detection to avoid reading the card to see
if a card is present or not.

Signed-off-by: Vipin Bhandari <vipin.bhandari at ti.com>
Signed-off-by: Sekhar Nori <nsekhar at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/board-da830-evm.c |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index dc19870..8e67037 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -229,14 +229,21 @@ static const short da830_evm_mmc_sd_pins[] = {
 };
 
 #define DA830_MMCSD_WP_PIN		GPIO_TO_PIN(2, 1)
+#define DA830_MMCSD_CD_PIN		GPIO_TO_PIN(2, 2)
 
 static int da830_evm_mmc_get_ro(int index)
 {
 	return gpio_get_value(DA830_MMCSD_WP_PIN);
 }
 
+static int da830_evm_mmc_get_cd(int index)
+{
+	return !gpio_get_value(DA830_MMCSD_CD_PIN);
+}
+
 static struct davinci_mmc_config da830_evm_mmc_config = {
 	.get_ro			= da830_evm_mmc_get_ro,
+	.get_cd			= da830_evm_mmc_get_cd,
 	.wires			= 4,
 	.max_freq		= 50000000,
 	.caps			= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
@@ -262,6 +269,14 @@ static inline void da830_evm_init_mmc(void)
 	}
 	gpio_direction_input(DA830_MMCSD_WP_PIN);
 
+	ret = gpio_request(DA830_MMCSD_CD_PIN, "MMC CD\n");
+	if (ret) {
+		pr_warning("da830_evm_init: can not open GPIO %d\n",
+			   DA830_MMCSD_CD_PIN);
+		return;
+	}
+	gpio_direction_input(DA830_MMCSD_CD_PIN);
+
 	ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
 	if (ret) {
 		pr_warning("da830_evm_init: mmc/sd registration failed: %d\n",
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:23:55 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:23:55 -0700
Subject: [PATCH 04/34] davinci: da830/omap-l137 evm: use 8-wire MMC/SD card
	support
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-5-git-send-email-khilman@deeprootsystems.com>

From: Vipin Bhandari <vipin.bhandari at ti.com>

The merge for 2.6.34 brings in 8-bit support to the DaVinci MMC/SD driver.

This patch updates the platform data for DA830/OMAP-L137 EVM to use 8-wire
support available in the driver.

Signed-off-by: Vipin Bhandari <vipin.bhandari at ti.com>
Signed-off-by: Sekhar Nori <nsekhar at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/board-da830-evm.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 8e67037..ea293b8 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -244,7 +244,7 @@ static int da830_evm_mmc_get_cd(int index)
 static struct davinci_mmc_config da830_evm_mmc_config = {
 	.get_ro			= da830_evm_mmc_get_ro,
 	.get_cd			= da830_evm_mmc_get_cd,
-	.wires			= 4,
+	.wires			= 8,
 	.max_freq		= 50000000,
 	.caps			= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
 	.version		= MMC_CTLR_VERSION_2,
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:23:56 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:23:56 -0700
Subject: [PATCH 05/34] davinci: edma: clear interrupt status for interrupt
	enabled channels only
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-6-git-send-email-khilman@deeprootsystems.com>

From: Anuj Aggarwal <anuj.aggarwal at ti.com>

Currently, the ISR in the EDMA driver clears the pending interrupt for all
channels without regard to whether that channel has a registered callback
or not.

This causes problems for devices like DM355/DM365 where the multimedia
accelerator uses EDMA by polling on the interrupt pending bits of some of the
EDMA channels. Since these channels are actually allocated through the Linux
EDMA driver (by an out-of-kernel module), the same shadow region is used by
Linux and accelerator. There a race between the Linux ISR and the polling code
running on the accelerator on the IPR (interrupt pending register).

This patch fixes the issue by making the ISR clear the interrupts only for
those channels which have interrupt enabled. The channels which are allocated
for the purpose of being polled on by the accelerator will not have a callback
function provided and so will not have IER (interrupt enable register) bits set.

Tested on DM365 and OMAP-L137/L138 with audio and MMC/SD (as EDMA users).

Signed-off-by: Anuj Aggarwal <anuj.aggarwal at ti.com>
Signed-off-by: Sekhar Nori <nsekhar at ti.com>
CC: Archith John Bency <archith at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/dma.c |   11 +++++++----
 1 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 5313738..0bf290b 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -359,9 +359,11 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 
 	while (1) {
 		int j;
-		if (edma_shadow0_read_array(ctlr, SH_IPR, 0))
+		if (edma_shadow0_read_array(ctlr, SH_IPR, 0) &
+				edma_shadow0_read_array(ctlr, SH_IER, 0))
 			j = 0;
-		else if (edma_shadow0_read_array(ctlr, SH_IPR, 1))
+		else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) &
+				edma_shadow0_read_array(ctlr, SH_IER, 1))
 			j = 1;
 		else
 			break;
@@ -369,8 +371,9 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 				edma_shadow0_read_array(ctlr, SH_IPR, j));
 		for (i = 0; i < 32; i++) {
 			int k = (j << 5) + i;
-			if (edma_shadow0_read_array(ctlr, SH_IPR, j) &
-							(1 << i)) {
+			if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i))
+					&& (edma_shadow0_read_array(ctlr,
+							SH_IER, j) & BIT(i))) {
 				/* Clear the corresponding IPR bits */
 				edma_shadow0_write_array(ctlr, SH_ICR, j,
 							(1 << i));
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:23:57 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:23:57 -0700
Subject: [PATCH 06/34] RTC: DaVinci RTC driver
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-7-git-send-email-khilman@deeprootsystems.com>

From: Miguel Aguilar <miguel.aguilar at ridgerun.com>

This driver features:

* Alarm support.
* Periodic interrupt by using a timer include into the RTC module.
* The update interrupt is not supported by this RTC module.

This driver was tested on a DM365 EVM by using the rtc-test application
from the Documentation/rtc.txt.

Signed-off-by: Miguel Aguilar <miguel.aguilar at ridgerun.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
Acked-by: Alessandro Zummo <a.zummo at towertech.it>
---
 drivers/rtc/Kconfig       |   10 +
 drivers/rtc/Makefile      |    1 +
 drivers/rtc/rtc-davinci.c |  673 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 684 insertions(+), 0 deletions(-)
 create mode 100644 drivers/rtc/rtc-davinci.c

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 6a13037..50ac047 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -620,6 +620,16 @@ config RTC_DRV_NUC900
 
 comment "on-CPU RTC drivers"
 
+config RTC_DRV_DAVINCI
+	tristate "TI DaVinci RTC"
+	depends on ARCH_DAVINCI_DM365
+	help
+	  If you say yes here you get support for the RTC on the
+	  DaVinci platforms (DM365).
+
+	  This driver can also be built as a module. If so, the module
+	  will be called rtc-davinci.
+
 config RTC_DRV_OMAP
 	tristate "TI OMAP1"
 	depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 44ef194..245311a 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_RTC_DRV_BQ32K)	+= rtc-bq32k.o
 obj-$(CONFIG_RTC_DRV_BQ4802)	+= rtc-bq4802.o
 obj-$(CONFIG_RTC_DRV_CMOS)	+= rtc-cmos.o
 obj-$(CONFIG_RTC_DRV_COH901331)	+= rtc-coh901331.o
+obj-$(CONFIG_RTC_DRV_DAVINCI)	+= rtc-davinci.o
 obj-$(CONFIG_RTC_DRV_DM355EVM)	+= rtc-dm355evm.o
 obj-$(CONFIG_RTC_DRV_DS1216)	+= rtc-ds1216.o
 obj-$(CONFIG_RTC_DRV_DS1286)	+= rtc-ds1286.o
diff --git a/drivers/rtc/rtc-davinci.c b/drivers/rtc/rtc-davinci.c
new file mode 100644
index 0000000..92a8f6c
--- /dev/null
+++ b/drivers/rtc/rtc-davinci.c
@@ -0,0 +1,673 @@
+/*
+ * DaVinci Power Management and Real Time Clock Driver for TI platforms
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc
+ *
+ * Author: Miguel Aguilar <miguel.aguilar at ridgerun.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/rtc.h>
+#include <linux/bcd.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+/*
+ * The DaVinci RTC is a simple RTC with the following
+ * Sec: 0 - 59 : BCD count
+ * Min: 0 - 59 : BCD count
+ * Hour: 0 - 23 : BCD count
+ * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
+ */
+
+/* PRTC interface registers */
+#define DAVINCI_PRTCIF_PID		0x00
+#define PRTCIF_CTLR			0x04
+#define PRTCIF_LDATA			0x08
+#define PRTCIF_UDATA			0x0C
+#define PRTCIF_INTEN			0x10
+#define PRTCIF_INTFLG			0x14
+
+/* PRTCIF_CTLR bit fields */
+#define PRTCIF_CTLR_BUSY		BIT(31)
+#define PRTCIF_CTLR_SIZE		BIT(25)
+#define PRTCIF_CTLR_DIR			BIT(24)
+#define PRTCIF_CTLR_BENU_MSB		BIT(23)
+#define PRTCIF_CTLR_BENU_3RD_BYTE	BIT(22)
+#define PRTCIF_CTLR_BENU_2ND_BYTE	BIT(21)
+#define PRTCIF_CTLR_BENU_LSB		BIT(20)
+#define PRTCIF_CTLR_BENU_MASK		(0x00F00000)
+#define PRTCIF_CTLR_BENL_MSB		BIT(19)
+#define PRTCIF_CTLR_BENL_3RD_BYTE	BIT(18)
+#define PRTCIF_CTLR_BENL_2ND_BYTE	BIT(17)
+#define PRTCIF_CTLR_BENL_LSB		BIT(16)
+#define PRTCIF_CTLR_BENL_MASK		(0x000F0000)
+
+/* PRTCIF_INTEN bit fields */
+#define PRTCIF_INTEN_RTCSS		BIT(1)
+#define PRTCIF_INTEN_RTCIF		BIT(0)
+#define PRTCIF_INTEN_MASK		(PRTCIF_INTEN_RTCSS \
+					| PRTCIF_INTEN_RTCIF)
+
+/* PRTCIF_INTFLG bit fields */
+#define PRTCIF_INTFLG_RTCSS		BIT(1)
+#define PRTCIF_INTFLG_RTCIF		BIT(0)
+#define PRTCIF_INTFLG_MASK		(PRTCIF_INTFLG_RTCSS \
+					| PRTCIF_INTFLG_RTCIF)
+
+/* PRTC subsystem registers */
+#define PRTCSS_RTC_INTC_EXTENA1		(0x0C)
+#define PRTCSS_RTC_CTRL			(0x10)
+#define PRTCSS_RTC_WDT			(0x11)
+#define PRTCSS_RTC_TMR0			(0x12)
+#define PRTCSS_RTC_TMR1			(0x13)
+#define PRTCSS_RTC_CCTRL		(0x14)
+#define PRTCSS_RTC_SEC			(0x15)
+#define PRTCSS_RTC_MIN			(0x16)
+#define PRTCSS_RTC_HOUR			(0x17)
+#define PRTCSS_RTC_DAY0			(0x18)
+#define PRTCSS_RTC_DAY1			(0x19)
+#define PRTCSS_RTC_AMIN			(0x1A)
+#define PRTCSS_RTC_AHOUR		(0x1B)
+#define PRTCSS_RTC_ADAY0		(0x1C)
+#define PRTCSS_RTC_ADAY1		(0x1D)
+#define PRTCSS_RTC_CLKC_CNT		(0x20)
+
+/* PRTCSS_RTC_INTC_EXTENA1 */
+#define PRTCSS_RTC_INTC_EXTENA1_MASK	(0x07)
+
+/* PRTCSS_RTC_CTRL bit fields */
+#define PRTCSS_RTC_CTRL_WDTBUS		BIT(7)
+#define PRTCSS_RTC_CTRL_WEN		BIT(6)
+#define PRTCSS_RTC_CTRL_WDRT		BIT(5)
+#define PRTCSS_RTC_CTRL_WDTFLG		BIT(4)
+#define PRTCSS_RTC_CTRL_TE		BIT(3)
+#define PRTCSS_RTC_CTRL_TIEN		BIT(2)
+#define PRTCSS_RTC_CTRL_TMRFLG		BIT(1)
+#define PRTCSS_RTC_CTRL_TMMD		BIT(0)
+
+/* PRTCSS_RTC_CCTRL bit fields */
+#define PRTCSS_RTC_CCTRL_CALBUSY	BIT(7)
+#define PRTCSS_RTC_CCTRL_DAEN		BIT(5)
+#define PRTCSS_RTC_CCTRL_HAEN		BIT(4)
+#define PRTCSS_RTC_CCTRL_MAEN		BIT(3)
+#define PRTCSS_RTC_CCTRL_ALMFLG		BIT(2)
+#define PRTCSS_RTC_CCTRL_AIEN		BIT(1)
+#define PRTCSS_RTC_CCTRL_CAEN		BIT(0)
+
+static DEFINE_SPINLOCK(davinci_rtc_lock);
+
+struct davinci_rtc {
+	struct rtc_device 		*rtc;
+	void __iomem			*base;
+	resource_size_t			pbase;
+	size_t				base_size;
+	int				irq;
+};
+
+static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
+			       u32 val, u32 addr)
+{
+	writel(val, davinci_rtc->base + addr);
+}
+
+static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
+{
+	return readl(davinci_rtc->base + addr);
+}
+
+static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
+{
+	while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
+		cpu_relax();
+}
+
+static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
+			       unsigned long val, u8 addr)
+{
+	rtcif_wait(davinci_rtc);
+
+	rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
+	rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
+
+	rtcif_wait(davinci_rtc);
+}
+
+static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
+{
+	rtcif_wait(davinci_rtc);
+
+	rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
+		    PRTCIF_CTLR);
+
+	rtcif_wait(davinci_rtc);
+
+	return rtcif_read(davinci_rtc, PRTCIF_LDATA);
+}
+
+static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
+{
+	while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
+	       PRTCSS_RTC_CCTRL_CALBUSY)
+		cpu_relax();
+}
+
+static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
+{
+	struct davinci_rtc *davinci_rtc = class_dev;
+	unsigned long events = 0;
+	u32 irq_flg;
+	u8 alm_irq, tmr_irq;
+	u8 rtc_ctrl, rtc_cctrl;
+	int ret = IRQ_NONE;
+
+	irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
+		  PRTCIF_INTFLG_RTCSS;
+
+	alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
+		  PRTCSS_RTC_CCTRL_ALMFLG;
+
+	tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
+		  PRTCSS_RTC_CTRL_TMRFLG;
+
+	if (irq_flg) {
+		if (alm_irq) {
+			events |= RTC_IRQF | RTC_AF;
+			rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
+			rtc_cctrl |=  PRTCSS_RTC_CCTRL_ALMFLG;
+			rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
+		} else if (tmr_irq) {
+			events |= RTC_IRQF | RTC_PF;
+			rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
+			rtc_ctrl |=  PRTCSS_RTC_CTRL_TMRFLG;
+			rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
+		}
+
+		rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
+				    PRTCIF_INTFLG);
+		rtc_update_irq(davinci_rtc->rtc, 1, events);
+
+		ret = IRQ_HANDLED;
+	}
+
+	return ret;
+}
+
+static int
+davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	u8 rtc_ctrl;
+	unsigned long flags;
+	int ret = 0;
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
+
+	switch (cmd) {
+	case RTC_WIE_ON:
+		rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
+		break;
+	case RTC_WIE_OFF:
+		rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
+		break;
+	case RTC_UIE_OFF:
+	case RTC_UIE_ON:
+		ret = -ENOTTY;
+		break;
+	default:
+		ret = -ENOIOCTLCMD;
+	}
+
+	rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	return ret;
+}
+
+static int convertfromdays(u16 days, struct rtc_time *tm)
+{
+	int tmp_days, year, mon;
+
+	for (year = 2000;; year++) {
+		tmp_days = rtc_year_days(1, 12, year);
+		if (days >= tmp_days)
+			days -= tmp_days;
+		else {
+			for (mon = 0;; mon++) {
+				tmp_days = rtc_month_days(mon, year);
+				if (days >= tmp_days) {
+					days -= tmp_days;
+				} else {
+					tm->tm_year = year - 1900;
+					tm->tm_mon = mon;
+					tm->tm_mday = days + 1;
+					break;
+				}
+			}
+			break;
+		}
+	}
+	return 0;
+}
+
+static int convert2days(u16 *days, struct rtc_time *tm)
+{
+	int i;
+	*days = 0;
+
+	/* epoch == 1900 */
+	if (tm->tm_year < 100 || tm->tm_year > 199)
+		return -EINVAL;
+
+	for (i = 2000; i < 1900 + tm->tm_year; i++)
+		*days += rtc_year_days(1, 12, i);
+
+	*days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
+
+	return 0;
+}
+
+static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	u16 days = 0;
+	u8 day0, day1;
+	unsigned long flags;
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	days |= day1;
+	days <<= 8;
+	days |= day0;
+
+	if (convertfromdays(days, tm) < 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	u16 days;
+	u8 rtc_cctrl;
+	unsigned long flags;
+
+	if (convert2days(&days, tm) < 0)
+		return -EINVAL;
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
+
+	rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
+	rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
+	rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	return 0;
+}
+
+static int davinci_rtc_alarm_irq_enable(struct device *dev,
+					unsigned int enabled)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	unsigned long flags;
+	u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	if (enabled)
+		rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
+			     PRTCSS_RTC_CCTRL_HAEN |
+			     PRTCSS_RTC_CCTRL_MAEN |
+			     PRTCSS_RTC_CCTRL_ALMFLG |
+			     PRTCSS_RTC_CCTRL_AIEN;
+	else
+		rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	return 0;
+}
+
+static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	u16 days = 0;
+	u8 day0, day1;
+	unsigned long flags;
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+	days |= day1;
+	days <<= 8;
+	days |= day0;
+
+	if (convertfromdays(days, &alm->time) < 0)
+		return -EINVAL;
+
+	alm->pending = !!(rtcss_read(davinci_rtc,
+			  PRTCSS_RTC_CCTRL) &
+			PRTCSS_RTC_CCTRL_AIEN);
+	alm->enabled = alm->pending && device_may_wakeup(dev);
+
+	return 0;
+}
+
+static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	unsigned long flags;
+	u16 days;
+
+	if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
+	    && alm->time.tm_year < 0) {
+		struct rtc_time tm;
+		unsigned long now, then;
+
+		davinci_rtc_read_time(dev, &tm);
+		rtc_tm_to_time(&tm, &now);
+
+		alm->time.tm_mday = tm.tm_mday;
+		alm->time.tm_mon = tm.tm_mon;
+		alm->time.tm_year = tm.tm_year;
+		rtc_tm_to_time(&alm->time, &then);
+
+		if (then < now) {
+			rtc_time_to_tm(now + 24 * 60 * 60, &tm);
+			alm->time.tm_mday = tm.tm_mday;
+			alm->time.tm_mon = tm.tm_mon;
+			alm->time.tm_year = tm.tm_year;
+		}
+	}
+
+	if (convert2days(&days, &alm->time) < 0)
+		return -EINVAL;
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
+
+	davinci_rtcss_calendar_wait(davinci_rtc);
+	rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	return 0;
+}
+
+static int davinci_rtc_irq_set_state(struct device *dev, int enabled)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	unsigned long flags;
+	u8 rtc_ctrl;
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
+
+	if (enabled) {
+		while (rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL)
+		       & PRTCSS_RTC_CTRL_WDTBUS)
+			cpu_relax();
+
+		rtc_ctrl |= PRTCSS_RTC_CTRL_TE;
+		rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
+
+		rtcss_write(davinci_rtc, 0x0, PRTCSS_RTC_CLKC_CNT);
+
+		rtc_ctrl |= PRTCSS_RTC_CTRL_TIEN |
+			    PRTCSS_RTC_CTRL_TMMD |
+			    PRTCSS_RTC_CTRL_TMRFLG;
+	} else
+		rtc_ctrl &= ~PRTCSS_RTC_CTRL_TIEN;
+
+	rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	return 0;
+}
+
+static int davinci_rtc_irq_set_freq(struct device *dev, int freq)
+{
+	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
+	unsigned long flags;
+	u16 tmr_counter = (0x8000 >> (ffs(freq) - 1));
+
+	spin_lock_irqsave(&davinci_rtc_lock, flags);
+
+	rtcss_write(davinci_rtc, tmr_counter & 0xFF, PRTCSS_RTC_TMR0);
+	rtcss_write(davinci_rtc, (tmr_counter & 0xFF00) >> 8, PRTCSS_RTC_TMR1);
+
+	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
+
+	return 0;
+}
+
+static struct rtc_class_ops davinci_rtc_ops = {
+	.ioctl			= davinci_rtc_ioctl,
+	.read_time		= davinci_rtc_read_time,
+	.set_time		= davinci_rtc_set_time,
+	.alarm_irq_enable	= davinci_rtc_alarm_irq_enable,
+	.read_alarm		= davinci_rtc_read_alarm,
+	.set_alarm		= davinci_rtc_set_alarm,
+	.irq_set_state		= davinci_rtc_irq_set_state,
+	.irq_set_freq		= davinci_rtc_irq_set_freq,
+};
+
+static int __init davinci_rtc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct davinci_rtc *davinci_rtc;
+	struct resource *res, *mem;
+	int ret = 0;
+
+	davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL);
+	if (!davinci_rtc) {
+		dev_dbg(dev, "could not allocate memory for private data\n");
+		return -ENOMEM;
+	}
+
+	davinci_rtc->irq = platform_get_irq(pdev, 0);
+	if (davinci_rtc->irq < 0) {
+		dev_err(dev, "no RTC irq\n");
+		ret = davinci_rtc->irq;
+		goto fail1;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "no mem resource\n");
+		ret = -EINVAL;
+		goto fail1;
+	}
+
+	davinci_rtc->pbase = res->start;
+	davinci_rtc->base_size = resource_size(res);
+
+	mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size,
+				 pdev->name);
+	if (!mem) {
+		dev_err(dev, "RTC registers at %08x are not free\n",
+			davinci_rtc->pbase);
+		ret = -EBUSY;
+		goto fail1;
+	}
+
+	davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size);
+	if (!davinci_rtc->base) {
+		dev_err(dev, "unable to ioremap MEM resource\n");
+		ret = -ENOMEM;
+		goto fail2;
+	}
+
+	davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
+				    &davinci_rtc_ops, THIS_MODULE);
+	if (IS_ERR(davinci_rtc->rtc)) {
+		dev_err(dev, "unable to register RTC device, err %ld\n",
+				PTR_ERR(davinci_rtc->rtc));
+		goto fail3;
+	}
+
+	rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
+	rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
+	rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
+
+	rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
+	rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
+
+	ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt,
+			  IRQF_DISABLED, "davinci_rtc", davinci_rtc);
+	if (ret < 0) {
+		dev_err(dev, "unable to register davinci RTC interrupt\n");
+		goto fail4;
+	}
+
+	/* Enable interrupts */
+	rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
+	rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
+			    PRTCSS_RTC_INTC_EXTENA1);
+
+	rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
+
+	platform_set_drvdata(pdev, davinci_rtc);
+
+	device_init_wakeup(&pdev->dev, 0);
+
+	return 0;
+
+fail4:
+	rtc_device_unregister(davinci_rtc->rtc);
+fail3:
+	iounmap(davinci_rtc->base);
+fail2:
+	release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
+fail1:
+	kfree(davinci_rtc);
+
+	return ret;
+}
+
+static int __devexit davinci_rtc_remove(struct platform_device *pdev)
+{
+	struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
+
+	device_init_wakeup(&pdev->dev, 0);
+
+	rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
+
+	free_irq(davinci_rtc->irq, davinci_rtc);
+
+	rtc_device_unregister(davinci_rtc->rtc);
+
+	iounmap(davinci_rtc->base);
+	release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
+
+	platform_set_drvdata(pdev, NULL);
+
+	kfree(davinci_rtc);
+
+	return 0;
+}
+
+static struct platform_driver davinci_rtc_driver = {
+	.probe		= davinci_rtc_probe,
+	.remove		= __devexit_p(davinci_rtc_remove),
+	.driver		= {
+		.name = "rtc_davinci",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init rtc_init(void)
+{
+	return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe);
+}
+module_init(rtc_init);
+
+static void __exit rtc_exit(void)
+{
+	platform_driver_unregister(&davinci_rtc_driver);
+}
+module_exit(rtc_exit);
+
+MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar at ridgerun.com>");
+MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
+MODULE_LICENSE("GPL");
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:23:58 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:23:58 -0700
Subject: [PATCH 07/34] rtc: omap: let device wakeup capability be configured
	from chip init logic
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-8-git-send-email-khilman@deeprootsystems.com>

From: Sekhar Nori <nsekhar at ti.com>

The rtc-omap driver currently hardcodes the RTC wakeup capability
to be "not capable". While this seems to be true for existing OMAP1
boards which are not wired for this, the DA850/OMAP-L138 SoC, the
RTC can always be wake up source from its "deep sleep" mode.

This patch lets the wakeup capability to be set from platform data and
does not override the setting from the driver. For DA850/OMAP-L138, this
is done from arch/arm/mach-davinci/devices-da8xx.c:da8xx_register_rtc()

Note that this patch does not change the behavior on any existing OMAP1
board since the platform device registration sets the wakeup capability
to 0 by default.

Signed-off-by: Sekhar Nori <nsekhar at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 drivers/rtc/rtc-omap.c |   12 +++++++-----
 1 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index 64d9727..73377b0 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -34,7 +34,8 @@
  * Board-specific wiring options include using split power mode with
  * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
  * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
- * low power modes).  See the BOARD-SPECIFIC CUSTOMIZATION comment.
+ * low power modes) for OMAP1 boards (OMAP-L138 has this built into
+ * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
  */
 
 #define OMAP_RTC_BASE			0xfffb4800
@@ -401,16 +402,17 @@ static int __init omap_rtc_probe(struct platform_device *pdev)
 
 	/* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
 	 *
-	 *  - Boards wired so that RTC_WAKE_INT does something, and muxed
-	 *    right (W13_1610_RTC_WAKE_INT is the default after chip reset),
-	 *    should initialize the device wakeup flag appropriately.
+	 *  - Device wake-up capability setting should come through chip
+	 *    init logic. OMAP1 boards should initialize the "wakeup capable"
+	 *    flag in the platform device if the board is wired right for
+	 *    being woken up by RTC alarm. For OMAP-L138, this capability
+	 *    is built into the SoC by the "Deep Sleep" capability.
 	 *
 	 *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
 	 *    rather than nPWRON_RESET, should forcibly enable split
 	 *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
 	 *    is write-only, and always reads as zero...)
 	 */
-	device_init_wakeup(&pdev->dev, 0);
 
 	if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT)
 		pr_info("%s: split power mode\n", pdev->name);
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:23:59 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:23:59 -0700
Subject: [PATCH 08/34] Davinci: allow SOCs based on other ARM CPUs
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-9-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

Preliminary modification prior to adding support for TNETV107X based on
ARM1176.  This change allows for CPUs other than ARM926T to be used for Davinci
derivative SoCs.  Existing devices (DA8x and DMx) operate unchanged.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/Kconfig              |    1 -
 arch/arm/mach-davinci/Kconfig |    2 ++
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 92622eb..1151d1a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -776,7 +776,6 @@ config ARCH_NOMADIK
 
 config ARCH_DAVINCI
 	bool "TI DaVinci"
-	select CPU_ARM926T
 	select GENERIC_TIME
 	select GENERIC_CLOCKEVENTS
 	select GENERIC_GPIO
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0ebe185..0316e20 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -7,6 +7,7 @@ config CP_INTC
 	bool
 
 config ARCH_DAVINCI_DMx
+	select CPU_ARM926T
 	bool
 
 menu "TI DaVinci Implementations"
@@ -41,6 +42,7 @@ config ARCH_DAVINCI_DA850
 	select ARCH_HAS_CPUFREQ
 
 config ARCH_DAVINCI_DA8XX
+	select CPU_ARM926T
 	bool
 
 config ARCH_DAVINCI_DM365
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:00 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:00 -0700
Subject: [PATCH 09/34] Davinci: enable timer clock before use
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-10-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

timer_init() programs timer64 hardware.  The module should ideally be brought
out of reset before this happens.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/time.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 9e0b106..b21f763 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -361,13 +361,13 @@ static void __init davinci_timer_init(void)
 		}
 	}
 
-	/* init timer hw */
-	timer_init();
-
 	timer_clk = clk_get(NULL, "timer0");
 	BUG_ON(IS_ERR(timer_clk));
 	clk_enable(timer_clk);
 
+	/* init timer hw */
+	timer_init();
+
 	davinci_clock_tick_rate = clk_get_rate(timer_clk);
 
 	/* setup clocksource */
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:01 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:01 -0700
Subject: [PATCH 10/34] Davinci: cpintc host map configuration
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-11-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

Host map configuration instructs the interrupt controller to route interrupt
channels to FIQ or IRQ lines.  Currently, DA8xx family of devices leave these
registers at their reset-default values.

TNETV107X however does not have sane reset defaults, and therefore this
architecture needs to reconfigure the host-map such that channels 0 and 1
go to FIQ, and the remaining channels raise IRQs.

This patch adds an optional host map argument to cp_intc_init() for this.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/board-da830-evm.c      |    2 +-
 arch/arm/mach-davinci/board-da850-evm.c      |    2 +-
 arch/arm/mach-davinci/cp_intc.c              |    6 +++++-
 arch/arm/mach-davinci/include/mach/cp_intc.h |    2 +-
 4 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index ea293b8..db5ac0f 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -569,7 +569,7 @@ static __init void da830_evm_irq_init(void)
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 
 	cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ,
-			soc_info->intc_irq_prios);
+			soc_info->intc_irq_prios, NULL);
 }
 
 static void __init da830_evm_map_io(void)
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 411284d..ef691ae 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -741,7 +741,7 @@ static __init void da850_evm_irq_init(void)
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 
 	cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ,
-			soc_info->intc_irq_prios);
+			soc_info->intc_irq_prios, NULL);
 }
 
 static void __init da850_evm_map_io(void)
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 37311d1..2a8d26e 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -101,7 +101,7 @@ static struct irq_chip cp_intc_irq_chip = {
 };
 
 void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
-			 u8 *irq_prio)
+			 u8 *irq_prio, u32 *host_map)
 {
 	unsigned num_reg	= BITS_TO_LONGS(num_irq);
 	int i;
@@ -157,6 +157,10 @@ void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
 			cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
 	}
 
+	if (host_map)
+		for (i = 0; host_map[i] != -1; i++)
+			cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
+
 	/* Set up genirq dispatching for cp_intc */
 	for (i = 0; i < num_irq; i++) {
 		set_irq_chip(i, &cp_intc_irq_chip);
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index c4d27ee..121b114 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -52,6 +52,6 @@
 #define CP_INTC_VECTOR_ADDR(n)		(0x2000 + (n << 2))
 
 void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
-			 u8 *irq_prio);
+			 u8 *irq_prio, u32 *host_map);
 
 #endif	/* __ASM_HARDWARE_CP_INTC_H */
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:02 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:02 -0700
Subject: [PATCH 11/34] Davinci: support LPSC SwRstDisable state
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-12-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

The current clock control code always gates the clock (PSC state Disable = 2)
on clk_disable().  Some on-chip peripherals (e.g. LCD controller on TNETV107X)
need to be put into SwRstDisable = 0 on clock disable, to maintain
hardware sanity.

This patch extends the davinci_psc_config() arguments to pass in the desired
module state instead of a boolean enable/disable.  Further, clk_disable() now
checks for the PSC_SWRSTDISABLE clk flag before selecting the target state.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/clock.c            |   12 +++++++++---
 arch/arm/mach-davinci/clock.h            |    7 ++++---
 arch/arm/mach-davinci/include/mach/psc.h |    8 +++++++-
 arch/arm/mach-davinci/psc.c              |    3 +--
 4 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 058c77f..5de60ae 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -43,7 +43,8 @@ static void __clk_enable(struct clk *clk)
 	if (clk->parent)
 		__clk_enable(clk->parent);
 	if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
-		davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 1);
+		davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+				PSC_STATE_ENABLE);
 }
 
 static void __clk_disable(struct clk *clk)
@@ -52,7 +53,9 @@ static void __clk_disable(struct clk *clk)
 		return;
 	if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
 	    (clk->flags & CLK_PSC))
-		davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0);
+		davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+				(clk->flags & PSC_SWRSTDISABLE) ?
+				PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
 	if (clk->parent)
 		__clk_disable(clk->parent);
 }
@@ -234,7 +237,10 @@ static int __init clk_disable_unused(void)
 			continue;
 
 		pr_info("Clocks: disable unused %s\n", ck->name);
-		davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 0);
+
+		davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
+				(ck->flags & PSC_SWRSTDISABLE) ?
+				PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
 	}
 	spin_unlock_irq(&clockfw_lock);
 
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index aa0a611..53a0f7b 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -101,10 +101,11 @@ struct clk {
 
 /* Clock flags: SoC-specific flags start at BIT(16) */
 #define ALWAYS_ENABLED		BIT(1)
-#define CLK_PSC                 BIT(2)
-#define PSC_DSP                 BIT(3) /* PSC uses DSP domain, not ARM */
+#define CLK_PSC			BIT(2)
+#define PSC_DSP			BIT(3) /* PSC uses DSP domain, not ARM */
 #define CLK_PLL			BIT(4) /* PLL-derived clock */
-#define PRE_PLL                 BIT(5) /* source is before PLL mult/div */
+#define PRE_PLL			BIT(5) /* source is before PLL mult/div */
+#define PSC_SWRSTDISABLE	BIT(6) /* Disable state is SwRstDisable */
 
 #define CLK(dev, con, ck) 	\
 	{			\
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 651f6d8..7dd2962 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -189,13 +189,19 @@
 #define MDSTAT		0x800
 #define MDCTL		0xA00
 
+/* PSC module states */
+#define PSC_STATE_SWRSTDISABLE	0
+#define PSC_STATE_SYNCRST	1
+#define PSC_STATE_DISABLE	2
+#define PSC_STATE_ENABLE	3
+
 #define MDSTAT_STATE_MASK 0x1f
 
 #ifndef __ASSEMBLER__
 
 extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
 extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
-		unsigned int id, char enable);
+		unsigned int id, u32 next_state);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index adf6b5c..d7cb438 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -47,12 +47,11 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
 
 /* Enable or disable a PSC domain */
 void davinci_psc_config(unsigned int domain, unsigned int ctlr,
-		unsigned int id, char enable)
+		unsigned int id, u32 next_state)
 {
 	u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
 	void __iomem *psc_base;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
 
 	if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
 		pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:03 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:03 -0700
Subject: [PATCH 12/34] Davinci: promote da8xx_pinmux_setup()
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-13-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

Rename da8xx_pinmux_setup() to davinci_cfg_reg_list() and promote it for use in
other SOCs that may need the ability to configure multiple pins in one shot.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/board-da830-evm.c    |   14 +++++++-------
 arch/arm/mach-davinci/board-da850-evm.c    |   18 +++++++++---------
 arch/arm/mach-davinci/include/mach/da8xx.h |    6 ------
 arch/arm/mach-davinci/include/mach/mux.h   |    5 +++++
 arch/arm/mach-davinci/mux.c                |    3 +--
 5 files changed, 22 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index db5ac0f..9257056 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -157,7 +157,7 @@ static __init void da830_evm_usb_init(void)
 				   __func__, ret);
 	}
 
-	ret = da8xx_pinmux_setup(da830_evm_usb11_pins);
+	ret = davinci_cfg_reg_list(da830_evm_usb11_pins);
 	if (ret) {
 		pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
 			   __func__, ret);
@@ -254,7 +254,7 @@ static inline void da830_evm_init_mmc(void)
 {
 	int ret;
 
-	ret = da8xx_pinmux_setup(da830_evm_mmc_sd_pins);
+	ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins);
 	if (ret) {
 		pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n",
 				ret);
@@ -407,7 +407,7 @@ static inline void da830_evm_init_nand(int mux_mode)
 		return;
 	}
 
-	ret = da8xx_pinmux_setup(da830_evm_emif25_pins);
+	ret = davinci_cfg_reg_list(da830_evm_emif25_pins);
 	if (ret)
 		pr_warning("da830_evm_init: emif25 mux setup failed: %d\n",
 				ret);
@@ -427,7 +427,7 @@ static inline void da830_evm_init_lcdc(int mux_mode)
 {
 	int ret;
 
-	ret = da8xx_pinmux_setup(da830_lcdcntl_pins);
+	ret = davinci_cfg_reg_list(da830_lcdcntl_pins);
 	if (ret)
 		pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n",
 				ret);
@@ -507,7 +507,7 @@ static __init void da830_evm_init(void)
 		pr_warning("da830_evm_init: edma registration failed: %d\n",
 				ret);
 
-	ret = da8xx_pinmux_setup(da830_i2c0_pins);
+	ret = davinci_cfg_reg_list(da830_i2c0_pins);
 	if (ret)
 		pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n",
 				ret);
@@ -523,7 +523,7 @@ static __init void da830_evm_init(void)
 	soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
 	soc_info->emac_pdata->rmii_en = 1;
 
-	ret = da8xx_pinmux_setup(da830_cpgmac_pins);
+	ret = davinci_cfg_reg_list(da830_cpgmac_pins);
 	if (ret)
 		pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n",
 				ret);
@@ -542,7 +542,7 @@ static __init void da830_evm_init(void)
 	i2c_register_board_info(1, da830_evm_i2c_devices,
 			ARRAY_SIZE(da830_evm_i2c_devices));
 
-	ret = da8xx_pinmux_setup(da830_evm_mcasp1_pins);
+	ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins);
 	if (ret)
 		pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n",
 				ret);
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index ef691ae..6c137e0 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -206,12 +206,12 @@ static __init void da850_evm_setup_nor_nand(void)
 	int ret = 0;
 
 	if (ui_card_detected & !HAS_MMC) {
-		ret = da8xx_pinmux_setup(da850_nand_pins);
+		ret = davinci_cfg_reg_list(da850_nand_pins);
 		if (ret)
 			pr_warning("da850_evm_init: nand mux setup failed: "
 					"%d\n", ret);
 
-		ret = da8xx_pinmux_setup(da850_nor_pins);
+		ret = davinci_cfg_reg_list(da850_nor_pins);
 		if (ret)
 			pr_warning("da850_evm_init: nor mux setup failed: %d\n",
 				ret);
@@ -568,12 +568,12 @@ static int __init da850_evm_config_emac(void)
 
 	if (rmii_en) {
 		val |= BIT(8);
-		ret = da8xx_pinmux_setup(da850_rmii_pins);
+		ret = davinci_cfg_reg_list(da850_rmii_pins);
 		pr_info("EMAC: RMII PHY configured, MII PHY will not be"
 							" functional\n");
 	} else {
 		val &= ~BIT(8);
-		ret = da8xx_pinmux_setup(da850_cpgmac_pins);
+		ret = davinci_cfg_reg_list(da850_cpgmac_pins);
 		pr_info("EMAC: MII PHY configured, RMII PHY will not be"
 							" functional\n");
 	}
@@ -626,7 +626,7 @@ static __init void da850_evm_init(void)
 		pr_warning("da850_evm_init: edma registration failed: %d\n",
 				ret);
 
-	ret = da8xx_pinmux_setup(da850_i2c0_pins);
+	ret = davinci_cfg_reg_list(da850_i2c0_pins);
 	if (ret)
 		pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n",
 				ret);
@@ -643,7 +643,7 @@ static __init void da850_evm_init(void)
 				ret);
 
 	if (HAS_MMC) {
-		ret = da8xx_pinmux_setup(da850_mmcsd0_pins);
+		ret = davinci_cfg_reg_list(da850_mmcsd0_pins);
 		if (ret)
 			pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
 					" %d\n", ret);
@@ -679,20 +679,20 @@ static __init void da850_evm_init(void)
 	__raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
 	__raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
 
-	ret = da8xx_pinmux_setup(da850_mcasp_pins);
+	ret = davinci_cfg_reg_list(da850_mcasp_pins);
 	if (ret)
 		pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
 				ret);
 
 	da8xx_register_mcasp(0, &da850_evm_snd_data);
 
-	ret = da8xx_pinmux_setup(da850_lcdcntl_pins);
+	ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
 	if (ret)
 		pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
 				ret);
 
 	/* Handle board specific muxing for LCD here */
-	ret = da8xx_pinmux_setup(da850_evm_lcdc_pins);
+	ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
 	if (ret)
 		pr_warning("da850_evm_init: evm specific lcd mux setup "
 				"failed: %d\n",	ret);
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 03acfd3..33471c9 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -146,10 +146,4 @@ extern const short da850_mmcsd0_pins[];
 extern const short da850_nand_pins[];
 extern const short da850_nor_pins[];
 
-#ifdef CONFIG_DAVINCI_MUX
-int da8xx_pinmux_setup(const short pins[]);
-#else
-static inline int da8xx_pinmux_setup(const short pins[]) { return 0; }
-#endif
-
 #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 2a68c1d..48888db 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -907,9 +907,14 @@ enum davinci_da850_index {
 #ifdef CONFIG_DAVINCI_MUX
 /* setup pin muxing */
 extern int davinci_cfg_reg(unsigned long reg_cfg);
+extern int davinci_cfg_reg_list(const short pins[]);
 #else
 /* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
 static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
+static inline int davinci_cfg_reg_list(const short pins[])
+{
+	return 0;
+}
 #endif
 
 #endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index c942c89..e9d530a 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -21,7 +21,6 @@
 
 #include <mach/mux.h>
 #include <mach/common.h>
-#include <mach/da8xx.h>
 
 /*
  * Sets the DAVINCI MUX register based on the table
@@ -92,7 +91,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
 }
 EXPORT_SYMBOL(davinci_cfg_reg);
 
-int da8xx_pinmux_setup(const short pins[])
+int __init_or_module davinci_cfg_reg_list(const short pins[])
 {
 	int i, error = -EINVAL;
 
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:04 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:04 -0700
Subject: [PATCH 13/34] Davinci: tnetv107x pin list
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-14-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

Added list of muxed pins on the tnetv107x SOC.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/include/mach/mux.h |  269 ++++++++++++++++++++++++++++++
 1 files changed, 269 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 48888db..8638903 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -904,6 +904,275 @@ enum davinci_da850_index {
 	DA850_RTC_ALARM,
 };
 
+enum davinci_tnetv107x_index {
+	TNETV107X_ASR_A00,
+	TNETV107X_GPIO32,
+	TNETV107X_ASR_A01,
+	TNETV107X_GPIO33,
+	TNETV107X_ASR_A02,
+	TNETV107X_GPIO34,
+	TNETV107X_ASR_A03,
+	TNETV107X_GPIO35,
+	TNETV107X_ASR_A04,
+	TNETV107X_GPIO36,
+	TNETV107X_ASR_A05,
+	TNETV107X_GPIO37,
+	TNETV107X_ASR_A06,
+	TNETV107X_GPIO38,
+	TNETV107X_ASR_A07,
+	TNETV107X_GPIO39,
+	TNETV107X_ASR_A08,
+	TNETV107X_GPIO40,
+	TNETV107X_ASR_A09,
+	TNETV107X_GPIO41,
+	TNETV107X_ASR_A10,
+	TNETV107X_GPIO42,
+	TNETV107X_ASR_A11,
+	TNETV107X_BOOT_STRP_0,
+	TNETV107X_ASR_A12,
+	TNETV107X_BOOT_STRP_1,
+	TNETV107X_ASR_A13,
+	TNETV107X_GPIO43,
+	TNETV107X_ASR_A14,
+	TNETV107X_GPIO44,
+	TNETV107X_ASR_A15,
+	TNETV107X_GPIO45,
+	TNETV107X_ASR_A16,
+	TNETV107X_GPIO46,
+	TNETV107X_ASR_A17,
+	TNETV107X_GPIO47,
+	TNETV107X_ASR_A18,
+	TNETV107X_GPIO48,
+	TNETV107X_SDIO1_DATA3_0,
+	TNETV107X_ASR_A19,
+	TNETV107X_GPIO49,
+	TNETV107X_SDIO1_DATA2_0,
+	TNETV107X_ASR_A20,
+	TNETV107X_GPIO50,
+	TNETV107X_SDIO1_DATA1_0,
+	TNETV107X_ASR_A21,
+	TNETV107X_GPIO51,
+	TNETV107X_SDIO1_DATA0_0,
+	TNETV107X_ASR_A22,
+	TNETV107X_GPIO52,
+	TNETV107X_SDIO1_CMD_0,
+	TNETV107X_ASR_A23,
+	TNETV107X_GPIO53,
+	TNETV107X_SDIO1_CLK_0,
+	TNETV107X_ASR_BA_1,
+	TNETV107X_GPIO54,
+	TNETV107X_SYS_PLL_CLK,
+	TNETV107X_ASR_CS0,
+	TNETV107X_ASR_CS1,
+	TNETV107X_ASR_CS2,
+	TNETV107X_TDM_PLL_CLK,
+	TNETV107X_ASR_CS3,
+	TNETV107X_ETH_PHY_CLK,
+	TNETV107X_ASR_D00,
+	TNETV107X_GPIO55,
+	TNETV107X_ASR_D01,
+	TNETV107X_GPIO56,
+	TNETV107X_ASR_D02,
+	TNETV107X_GPIO57,
+	TNETV107X_ASR_D03,
+	TNETV107X_GPIO58,
+	TNETV107X_ASR_D04,
+	TNETV107X_GPIO59_0,
+	TNETV107X_ASR_D05,
+	TNETV107X_GPIO60_0,
+	TNETV107X_ASR_D06,
+	TNETV107X_GPIO61_0,
+	TNETV107X_ASR_D07,
+	TNETV107X_GPIO62_0,
+	TNETV107X_ASR_D08,
+	TNETV107X_GPIO63_0,
+	TNETV107X_ASR_D09,
+	TNETV107X_GPIO64_0,
+	TNETV107X_ASR_D10,
+	TNETV107X_SDIO1_DATA3_1,
+	TNETV107X_ASR_D11,
+	TNETV107X_SDIO1_DATA2_1,
+	TNETV107X_ASR_D12,
+	TNETV107X_SDIO1_DATA1_1,
+	TNETV107X_ASR_D13,
+	TNETV107X_SDIO1_DATA0_1,
+	TNETV107X_ASR_D14,
+	TNETV107X_SDIO1_CMD_1,
+	TNETV107X_ASR_D15,
+	TNETV107X_SDIO1_CLK_1,
+	TNETV107X_ASR_OE,
+	TNETV107X_BOOT_STRP_2,
+	TNETV107X_ASR_RNW,
+	TNETV107X_GPIO29_0,
+	TNETV107X_ASR_WAIT,
+	TNETV107X_GPIO30_0,
+	TNETV107X_ASR_WE,
+	TNETV107X_BOOT_STRP_3,
+	TNETV107X_ASR_WE_DQM0,
+	TNETV107X_GPIO31,
+	TNETV107X_LCD_PD17_0,
+	TNETV107X_ASR_WE_DQM1,
+	TNETV107X_ASR_BA0_0,
+	TNETV107X_VLYNQ_CLK,
+	TNETV107X_GPIO14,
+	TNETV107X_LCD_PD19_0,
+	TNETV107X_VLYNQ_RXD0,
+	TNETV107X_GPIO15,
+	TNETV107X_LCD_PD20_0,
+	TNETV107X_VLYNQ_RXD1,
+	TNETV107X_GPIO16,
+	TNETV107X_LCD_PD21_0,
+	TNETV107X_VLYNQ_TXD0,
+	TNETV107X_GPIO17,
+	TNETV107X_LCD_PD22_0,
+	TNETV107X_VLYNQ_TXD1,
+	TNETV107X_GPIO18,
+	TNETV107X_LCD_PD23_0,
+	TNETV107X_SDIO0_CLK,
+	TNETV107X_GPIO19,
+	TNETV107X_SDIO0_CMD,
+	TNETV107X_GPIO20,
+	TNETV107X_SDIO0_DATA0,
+	TNETV107X_GPIO21,
+	TNETV107X_SDIO0_DATA1,
+	TNETV107X_GPIO22,
+	TNETV107X_SDIO0_DATA2,
+	TNETV107X_GPIO23,
+	TNETV107X_SDIO0_DATA3,
+	TNETV107X_GPIO24,
+	TNETV107X_EMU0,
+	TNETV107X_EMU1,
+	TNETV107X_RTCK,
+	TNETV107X_TRST_N,
+	TNETV107X_TCK,
+	TNETV107X_TDI,
+	TNETV107X_TDO,
+	TNETV107X_TMS,
+	TNETV107X_TDM1_CLK,
+	TNETV107X_TDM1_RX,
+	TNETV107X_TDM1_TX,
+	TNETV107X_TDM1_FS,
+	TNETV107X_KEYPAD_R0,
+	TNETV107X_KEYPAD_R1,
+	TNETV107X_KEYPAD_R2,
+	TNETV107X_KEYPAD_R3,
+	TNETV107X_KEYPAD_R4,
+	TNETV107X_KEYPAD_R5,
+	TNETV107X_KEYPAD_R6,
+	TNETV107X_GPIO12,
+	TNETV107X_KEYPAD_R7,
+	TNETV107X_GPIO10,
+	TNETV107X_KEYPAD_C0,
+	TNETV107X_KEYPAD_C1,
+	TNETV107X_KEYPAD_C2,
+	TNETV107X_KEYPAD_C3,
+	TNETV107X_KEYPAD_C4,
+	TNETV107X_KEYPAD_C5,
+	TNETV107X_KEYPAD_C6,
+	TNETV107X_GPIO13,
+	TNETV107X_TEST_CLK_IN,
+	TNETV107X_KEYPAD_C7,
+	TNETV107X_GPIO11,
+	TNETV107X_SSP0_0,
+	TNETV107X_SCC_DCLK,
+	TNETV107X_LCD_PD20_1,
+	TNETV107X_SSP0_1,
+	TNETV107X_SCC_CS_N,
+	TNETV107X_LCD_PD21_1,
+	TNETV107X_SSP0_2,
+	TNETV107X_SCC_D,
+	TNETV107X_LCD_PD22_1,
+	TNETV107X_SSP0_3,
+	TNETV107X_SCC_RESETN,
+	TNETV107X_LCD_PD23_1,
+	TNETV107X_SSP1_0,
+	TNETV107X_GPIO25,
+	TNETV107X_UART2_CTS,
+	TNETV107X_SSP1_1,
+	TNETV107X_GPIO26,
+	TNETV107X_UART2_RD,
+	TNETV107X_SSP1_2,
+	TNETV107X_GPIO27,
+	TNETV107X_UART2_RTS,
+	TNETV107X_SSP1_3,
+	TNETV107X_GPIO28,
+	TNETV107X_UART2_TD,
+	TNETV107X_UART0_CTS,
+	TNETV107X_UART0_RD,
+	TNETV107X_UART0_RTS,
+	TNETV107X_UART0_TD,
+	TNETV107X_UART1_RD,
+	TNETV107X_UART1_TD,
+	TNETV107X_LCD_AC_NCS,
+	TNETV107X_LCD_HSYNC_RNW,
+	TNETV107X_LCD_VSYNC_A0,
+	TNETV107X_LCD_MCLK,
+	TNETV107X_LCD_PD16_0,
+	TNETV107X_LCD_PCLK_E,
+	TNETV107X_LCD_PD00,
+	TNETV107X_LCD_PD01,
+	TNETV107X_LCD_PD02,
+	TNETV107X_LCD_PD03,
+	TNETV107X_LCD_PD04,
+	TNETV107X_LCD_PD05,
+	TNETV107X_LCD_PD06,
+	TNETV107X_LCD_PD07,
+	TNETV107X_LCD_PD08,
+	TNETV107X_GPIO59_1,
+	TNETV107X_LCD_PD09,
+	TNETV107X_GPIO60_1,
+	TNETV107X_LCD_PD10,
+	TNETV107X_ASR_BA0_1,
+	TNETV107X_GPIO61_1,
+	TNETV107X_LCD_PD11,
+	TNETV107X_GPIO62_1,
+	TNETV107X_LCD_PD12,
+	TNETV107X_GPIO63_1,
+	TNETV107X_LCD_PD13,
+	TNETV107X_GPIO64_1,
+	TNETV107X_LCD_PD14,
+	TNETV107X_GPIO29_1,
+	TNETV107X_LCD_PD15,
+	TNETV107X_GPIO30_1,
+	TNETV107X_EINT0,
+	TNETV107X_GPIO08,
+	TNETV107X_EINT1,
+	TNETV107X_GPIO09,
+	TNETV107X_GPIO00,
+	TNETV107X_LCD_PD20_2,
+	TNETV107X_TDM_CLK_IN_2,
+	TNETV107X_GPIO01,
+	TNETV107X_LCD_PD21_2,
+	TNETV107X_24M_CLK_OUT_1,
+	TNETV107X_GPIO02,
+	TNETV107X_LCD_PD22_2,
+	TNETV107X_GPIO03,
+	TNETV107X_LCD_PD23_2,
+	TNETV107X_GPIO04,
+	TNETV107X_LCD_PD16_1,
+	TNETV107X_USB0_RXERR,
+	TNETV107X_GPIO05,
+	TNETV107X_LCD_PD17_1,
+	TNETV107X_TDM_CLK_IN_1,
+	TNETV107X_GPIO06,
+	TNETV107X_LCD_PD18,
+	TNETV107X_24M_CLK_OUT_2,
+	TNETV107X_GPIO07,
+	TNETV107X_LCD_PD19_1,
+	TNETV107X_USB1_RXERR,
+	TNETV107X_ETH_PLL_CLK,
+	TNETV107X_MDIO,
+	TNETV107X_MDC,
+	TNETV107X_AIC_MUTE_STAT_N,
+	TNETV107X_TDM0_CLK,
+	TNETV107X_AIC_HNS_EN_N,
+	TNETV107X_TDM0_FS,
+	TNETV107X_AIC_HDS_EN_STAT_N,
+	TNETV107X_TDM0_TX,
+	TNETV107X_AIC_HNF_EN_STAT_N,
+	TNETV107X_TDM0_RX,
+};
+
 #ifdef CONFIG_DAVINCI_MUX
 /* setup pin muxing */
 extern int davinci_cfg_reg(unsigned long reg_cfg);
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:05 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:05 -0700
Subject: [PATCH 14/34] Davinci: tnetv107x LPSC modules
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-15-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

Added definitions for LPSC modules in the tnetv107x SOC

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/include/mach/psc.h |   47 ++++++++++++++++++++++++++++++
 1 files changed, 47 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 7dd2962..983da6e 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -180,6 +180,53 @@
 #define DA8XX_LPSC1_CR_P3_SS		26
 #define DA8XX_LPSC1_L3_CBA_RAM		31
 
+/* TNETV107X LPSC Assignments */
+#define TNETV107X_LPSC_ARM			0
+#define TNETV107X_LPSC_GEM			1
+#define TNETV107X_LPSC_DDR2_PHY			2
+#define TNETV107X_LPSC_TPCC			3
+#define TNETV107X_LPSC_TPTC0			4
+#define TNETV107X_LPSC_TPTC1			5
+#define TNETV107X_LPSC_RAM			6
+#define TNETV107X_LPSC_MBX_LITE			7
+#define TNETV107X_LPSC_LCD			8
+#define TNETV107X_LPSC_ETHSS			9
+#define TNETV107X_LPSC_AEMIF			10
+#define TNETV107X_LPSC_CHIP_CFG			11
+#define TNETV107X_LPSC_TSC			12
+#define TNETV107X_LPSC_ROM			13
+#define TNETV107X_LPSC_UART2			14
+#define TNETV107X_LPSC_PKTSEC			15
+#define TNETV107X_LPSC_SECCTL			16
+#define TNETV107X_LPSC_KEYMGR			17
+#define TNETV107X_LPSC_KEYPAD			18
+#define TNETV107X_LPSC_GPIO			19
+#define TNETV107X_LPSC_MDIO			20
+#define TNETV107X_LPSC_SDIO0			21
+#define TNETV107X_LPSC_UART0			22
+#define TNETV107X_LPSC_UART1			23
+#define TNETV107X_LPSC_TIMER0			24
+#define TNETV107X_LPSC_TIMER1			25
+#define TNETV107X_LPSC_WDT_ARM			26
+#define TNETV107X_LPSC_WDT_DSP			27
+#define TNETV107X_LPSC_SSP			28
+#define TNETV107X_LPSC_TDM0			29
+#define TNETV107X_LPSC_VLYNQ			30
+#define TNETV107X_LPSC_MCDMA			31
+#define TNETV107X_LPSC_USB0			32
+#define TNETV107X_LPSC_TDM1			33
+#define TNETV107X_LPSC_DEBUGSS			34
+#define TNETV107X_LPSC_ETHSS_RGMII		35
+#define TNETV107X_LPSC_SYSTEM			36
+#define TNETV107X_LPSC_IMCOP			37
+#define TNETV107X_LPSC_SPARE			38
+#define TNETV107X_LPSC_SDIO1			39
+#define TNETV107X_LPSC_USB1			40
+#define TNETV107X_LPSC_USBSS			41
+#define TNETV107X_LPSC_DDR2_EMIF1_VRST		42
+#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST	43
+#define TNETV107X_LPSC_MAX			44
+
 /* PSC register offsets */
 #define EPCPR		0x070
 #define PTCMD		0x120
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:06 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:06 -0700
Subject: [PATCH 15/34] Davinci: tnetv107x IRQ definitions
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-16-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

IRQ numbers as defined for tnetv107x cp_intc.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/include/mach/irqs.h |   97 +++++++++++++++++++++++++++++
 1 files changed, 97 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 354af71..ec76c77 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -401,6 +401,103 @@
 
 #define DA850_N_CP_INTC_IRQ		101
 
+
+/* TNETV107X specific interrupts */
+#define IRQ_TNETV107X_TDM1_TXDMA		0
+#define IRQ_TNETV107X_EXT_INT_0			1
+#define IRQ_TNETV107X_EXT_INT_1			2
+#define IRQ_TNETV107X_GPIO_INT12		3
+#define IRQ_TNETV107X_GPIO_INT13		4
+#define IRQ_TNETV107X_TIMER_0_TINT12		5
+#define IRQ_TNETV107X_TIMER_1_TINT12		6
+#define IRQ_TNETV107X_UART0			7
+#define IRQ_TNETV107X_TDM1_RXDMA		8
+#define IRQ_TNETV107X_MCDMA_INT0		9
+#define IRQ_TNETV107X_MCDMA_INT1		10
+#define IRQ_TNETV107X_TPCC			11
+#define IRQ_TNETV107X_TPCC_INT0			12
+#define IRQ_TNETV107X_TPCC_INT1			13
+#define IRQ_TNETV107X_TPCC_INT2			14
+#define IRQ_TNETV107X_TPCC_INT3			15
+#define IRQ_TNETV107X_TPTC0			16
+#define IRQ_TNETV107X_TPTC1			17
+#define IRQ_TNETV107X_TIMER_0_TINT34		18
+#define IRQ_TNETV107X_ETHSS			19
+#define IRQ_TNETV107X_TIMER_1_TINT34		20
+#define IRQ_TNETV107X_DSP2ARM_INT0		21
+#define IRQ_TNETV107X_DSP2ARM_INT1		22
+#define IRQ_TNETV107X_ARM_NPMUIRQ		23
+#define IRQ_TNETV107X_USB1			24
+#define IRQ_TNETV107X_VLYNQ			25
+#define IRQ_TNETV107X_UART0_DMATX		26
+#define IRQ_TNETV107X_UART0_DMARX		27
+#define IRQ_TNETV107X_TDM1_TXMCSP		28
+#define IRQ_TNETV107X_SSP			29
+#define IRQ_TNETV107X_MCDMA_INT2		30
+#define IRQ_TNETV107X_MCDMA_INT3		31
+#define IRQ_TNETV107X_TDM_CODECIF_EOT		32
+#define IRQ_TNETV107X_IMCOP_SQR_ARM		33
+#define IRQ_TNETV107X_USB0			34
+#define IRQ_TNETV107X_USB_CDMA			35
+#define IRQ_TNETV107X_LCD			36
+#define IRQ_TNETV107X_KEYPAD			37
+#define IRQ_TNETV107X_KEYPAD_FREE		38
+#define IRQ_TNETV107X_RNG			39
+#define IRQ_TNETV107X_PKA			40
+#define IRQ_TNETV107X_TDM0_TXDMA		41
+#define IRQ_TNETV107X_TDM0_RXDMA		42
+#define IRQ_TNETV107X_TDM0_TXMCSP		43
+#define IRQ_TNETV107X_TDM0_RXMCSP		44
+#define IRQ_TNETV107X_TDM1_RXMCSP		45
+#define IRQ_TNETV107X_SDIO1			46
+#define IRQ_TNETV107X_SDIO0			47
+#define IRQ_TNETV107X_TSC			48
+#define IRQ_TNETV107X_TS			49
+#define IRQ_TNETV107X_UART1			50
+#define IRQ_TNETV107X_MBX_LITE			51
+#define IRQ_TNETV107X_GPIO_INT00		52
+#define IRQ_TNETV107X_GPIO_INT01		53
+#define IRQ_TNETV107X_GPIO_INT02		54
+#define IRQ_TNETV107X_GPIO_INT03		55
+#define IRQ_TNETV107X_UART2			56
+#define IRQ_TNETV107X_UART2_DMATX		57
+#define IRQ_TNETV107X_UART2_DMARX		58
+#define IRQ_TNETV107X_IMCOP_IMX			59
+#define IRQ_TNETV107X_IMCOP_VLCD		60
+#define IRQ_TNETV107X_AES			61
+#define IRQ_TNETV107X_DES			62
+#define IRQ_TNETV107X_SHAMD5			63
+#define IRQ_TNETV107X_TPCC_ERR			68
+#define IRQ_TNETV107X_TPCC_PROT			69
+#define IRQ_TNETV107X_TPTC0_ERR			70
+#define IRQ_TNETV107X_TPTC1_ERR			71
+#define IRQ_TNETV107X_UART0_ERR			72
+#define IRQ_TNETV107X_UART1_ERR			73
+#define IRQ_TNETV107X_AEMIF_ERR			74
+#define IRQ_TNETV107X_DDR_ERR			75
+#define IRQ_TNETV107X_WDTARM_INT0		76
+#define IRQ_TNETV107X_MCDMA_ERR			77
+#define IRQ_TNETV107X_GPIO_ERR			78
+#define IRQ_TNETV107X_MPU_ADDR			79
+#define IRQ_TNETV107X_MPU_PROT			80
+#define IRQ_TNETV107X_IOPU_ADDR			81
+#define IRQ_TNETV107X_IOPU_PROT			82
+#define IRQ_TNETV107X_KEYPAD_ADDR_ERR		83
+#define IRQ_TNETV107X_WDT0_ADDR_ERR		84
+#define IRQ_TNETV107X_WDT1_ADDR_ERR		85
+#define IRQ_TNETV107X_CLKCTL_ADDR_ERR		86
+#define IRQ_TNETV107X_PLL_UNLOCK		87
+#define IRQ_TNETV107X_WDTDSP_INT0		88
+#define IRQ_TNETV107X_SEC_CTRL_VIOLATION	89
+#define IRQ_TNETV107X_KEY_MNG_VIOLATION		90
+#define IRQ_TNETV107X_PBIST_CPU			91
+#define IRQ_TNETV107X_WDTARM			92
+#define IRQ_TNETV107X_PSC			93
+#define IRQ_TNETV107X_MMC0			94
+#define IRQ_TNETV107X_MMC1			95
+
+#define TNETV107X_N_CP_INTC_IRQ			96
+
 /* da850 currently has the most gpio pins (144) */
 #define DAVINCI_N_GPIO			144
 /* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:07 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:07 -0700
Subject: [PATCH 16/34] Davinci: tnetv107x cpu types
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-17-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

Added tnetv107x cpu type definitions and cpu identification macros.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/include/mach/cputype.h |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 189b1ff..cea6b89 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -33,6 +33,7 @@ struct davinci_id {
 #define	DAVINCI_CPU_ID_DM365		0x03650000
 #define	DAVINCI_CPU_ID_DA830		0x08300000
 #define	DAVINCI_CPU_ID_DA850		0x08500000
+#define	DAVINCI_CPU_ID_TNETV107X	0x0b8a0000
 
 #define IS_DAVINCI_CPU(type, id)					\
 static inline int is_davinci_ ##type(void)				\
@@ -46,6 +47,7 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
 IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
 IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
 IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
+IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
 
 #ifdef CONFIG_ARCH_DAVINCI_DM644x
 #define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -83,4 +85,10 @@ IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
 #define cpu_is_davinci_da850() 0
 #endif
 
+#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
+#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
+#else
+#define cpu_is_davinci_tnetv107x() 0
+#endif
+
 #endif
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:08 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:08 -0700
Subject: [PATCH 17/34] DaVinci: move AEMIF #define's to the proper headers
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-18-git-send-email-khilman@deeprootsystems.com>

From: Sergei Shtylyov <sshtylyov at ru.mvista.com>

Currently each DaVinci board file #define's its own version of the EMIFA base
addresses (all named DAVINCI_ASYNC_EMIF_*_BASE), which leads to duplication.
Move these #define's to the SoC specific headers, changing their prefixes from
'DAVINCI' to the 'DM355', 'DM644X', and 'DM646X' since all these base addresses
are SoC specific...

And while at it, rename DM646X_ASYNC_EMIF_DATA_CE0_BASE to
DM646X_ASYNC_EMIF_CS2_SPACE_BASE in order to match the DM646x datasheet.

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/board-dm355-evm.c     |   11 ++++-------
 arch/arm/mach-davinci/board-dm355-leopard.c |   11 ++++-------
 arch/arm/mach-davinci/board-dm365-evm.c     |    5 -----
 arch/arm/mach-davinci/board-dm644x-evm.c    |   18 ++++++------------
 arch/arm/mach-davinci/board-dm646x-evm.c    |   11 ++++-------
 arch/arm/mach-davinci/board-neuros-osd2.c   |   11 ++++-------
 arch/arm/mach-davinci/board-sffsdr.c        |   11 ++++-------
 arch/arm/mach-davinci/include/mach/dm355.h  |    3 +++
 arch/arm/mach-davinci/include/mach/dm365.h  |    4 ++++
 arch/arm/mach-davinci/include/mach/dm644x.h |    6 ++++++
 arch/arm/mach-davinci/include/mach/dm646x.h |    3 +++
 11 files changed, 42 insertions(+), 52 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index aa48e3f..a0ad7d9 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -33,9 +33,6 @@
 #include <mach/mmc.h>
 #include <mach/usb.h>
 
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE		0x01e10000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x02000000
-
 /* NOTE:  this is geared for the standard config, with a socketed
  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
  * swap chips, maybe with a different block size, partitioning may
@@ -86,12 +83,12 @@ static struct davinci_nand_pdata davinci_nand_data = {
 
 static struct resource davinci_nand_resources[] = {
 	{
-		.start		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
-		.end		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
+		.start		= DM355_ASYNC_EMIF_DATA_CE0_BASE,
+		.end		= DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
 		.flags		= IORESOURCE_MEM,
 	}, {
-		.start		= DAVINCI_ASYNC_EMIF_CONTROL_BASE,
-		.end		= DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+		.start		= DM355_ASYNC_EMIF_CONTROL_BASE,
+		.end		= DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 };
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 21f32eb..c3d5a70 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -30,9 +30,6 @@
 #include <mach/mmc.h>
 #include <mach/usb.h>
 
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE		0x01e10000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x02000000
-
 /* NOTE:  this is geared for the standard config, with a socketed
  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
  * swap chips, maybe with a different block size, partitioning may
@@ -82,12 +79,12 @@ static struct davinci_nand_pdata davinci_nand_data = {
 
 static struct resource davinci_nand_resources[] = {
 	{
-		.start		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
-		.end		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
+		.start		= DM355_ASYNC_EMIF_DATA_CE0_BASE,
+		.end		= DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
 		.flags		= IORESOURCE_MEM,
 	}, {
-		.start		= DAVINCI_ASYNC_EMIF_CONTROL_BASE,
-		.end		= DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+		.start		= DM355_ASYNC_EMIF_CONTROL_BASE,
+		.end		= DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 };
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index df4ab21..b98b35c 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -54,11 +54,6 @@ static inline int have_tvp7002(void)
 	return 0;
 }
 
-
-#define DM365_ASYNC_EMIF_CONTROL_BASE	0x01d10000
-#define DM365_ASYNC_EMIF_DATA_CE0_BASE	0x02000000
-#define DM365_ASYNC_EMIF_DATA_CE1_BASE	0x04000000
-
 #define DM365_EVM_PHY_MASK		(0x2)
 #define DM365_EVM_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */
 
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 95cef1f..d028bab 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -43,12 +43,6 @@
 
 #define DAVINCI_CFC_ATA_BASE		  0x01C66000
 
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE   0x01e00000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE  0x06000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE  0x08000000
-
 #define LXT971_PHY_ID	(0x001378e2)
 #define LXT971_PHY_MASK	(0xfffffff0)
 
@@ -92,8 +86,8 @@ static struct physmap_flash_data davinci_evm_norflash_data = {
 /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
  * limits addresses to 16M, so using addresses past 16M will wrap */
 static struct resource davinci_evm_norflash_resource = {
-	.start		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
-	.end		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
+	.start		= DM644X_ASYNC_EMIF_DATA_CE0_BASE,
+	.end		= DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
 	.flags		= IORESOURCE_MEM,
 };
 
@@ -154,12 +148,12 @@ static struct davinci_nand_pdata davinci_evm_nandflash_data = {
 
 static struct resource davinci_evm_nandflash_resource[] = {
 	{
-		.start		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
-		.end		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
+		.start		= DM644X_ASYNC_EMIF_DATA_CE0_BASE,
+		.end		= DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
 		.flags		= IORESOURCE_MEM,
 	}, {
-		.start		= DAVINCI_ASYNC_EMIF_CONTROL_BASE,
-		.end		= DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+		.start		= DM644X_ASYNC_EMIF_CONTROL_BASE,
+		.end		= DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 };
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 5ba3cb2..b22e22c 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -80,17 +80,14 @@ static struct davinci_nand_pdata davinci_nand_data = {
 	.options		= 0,
 };
 
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE		0x20008000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x42000000
-
 static struct resource davinci_nand_resources[] = {
 	{
-		.start		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
-		.end		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
+		.start		= DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
+		.end		= DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
 		.flags		= IORESOURCE_MEM,
 	}, {
-		.start		= DAVINCI_ASYNC_EMIF_CONTROL_BASE,
-		.end		= DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+		.start		= DM646X_ASYNC_EMIF_CONTROL_BASE,
+		.end		= DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 };
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 1fadc68..5afe37e 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -43,9 +43,6 @@
 
 #define DAVINCI_CFC_ATA_BASE		 0x01C66000
 
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE	 0x01e00000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-
 #define LXT971_PHY_ID			0x001378e2
 #define LXT971_PHY_MASK			0xfffffff0
 
@@ -98,12 +95,12 @@ static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
 
 static struct resource davinci_ntosd2_nandflash_resource[] = {
 	{
-		.start		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
-		.end		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
+		.start		= DM644X_ASYNC_EMIF_DATA_CE0_BASE,
+		.end		= DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
 		.flags		= IORESOURCE_MEM,
 	}, {
-		.start		= DAVINCI_ASYNC_EMIF_CONTROL_BASE,
-		.end		= DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+		.start		= DM644X_ASYNC_EMIF_CONTROL_BASE,
+		.end		= DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 };
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index a7cf810..1ed0662 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -45,9 +45,6 @@
 #define SFFSDR_PHY_MASK		(0x2)
 #define SFFSDR_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */
 
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE   0x01e00000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
-
 static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
 	/* U-Boot Environment: Block 0
 	 * UBL:                Block 1
@@ -76,12 +73,12 @@ static struct flash_platform_data davinci_sffsdr_nandflash_data = {
 
 static struct resource davinci_sffsdr_nandflash_resource[] = {
 	{
-		.start		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
-		.end		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
+		.start		= DM644X_ASYNC_EMIF_DATA_CE0_BASE,
+		.end		= DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
 		.flags		= IORESOURCE_MEM,
 	}, {
-		.start		= DAVINCI_ASYNC_EMIF_CONTROL_BASE,
-		.end		= DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+		.start		= DM644X_ASYNC_EMIF_CONTROL_BASE,
+		.end		= DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 };
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
index 85536d8..36dff4a 100644
--- a/arch/arm/mach-davinci/include/mach/dm355.h
+++ b/arch/arm/mach-davinci/include/mach/dm355.h
@@ -15,6 +15,9 @@
 #include <mach/asp.h>
 #include <media/davinci/vpfe_capture.h>
 
+#define DM355_ASYNC_EMIF_CONTROL_BASE	0x01E10000
+#define DM355_ASYNC_EMIF_DATA_CE0_BASE	0x02000000
+
 #define ASP1_TX_EVT_EN	1
 #define ASP1_RX_EVT_EN	2
 
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 3a37b5a..ea5df3b 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -36,6 +36,10 @@
 #define DAVINCI_DMA_VC_TX		2
 #define DAVINCI_DMA_VC_RX		3
 
+#define DM365_ASYNC_EMIF_CONTROL_BASE	0x01D10000
+#define DM365_ASYNC_EMIF_DATA_CE0_BASE	0x02000000
+#define DM365_ASYNC_EMIF_DATA_CE1_BASE	0x04000000
+
 void __init dm365_init(void);
 void __init dm365_init_asp(struct snd_platform_data *pdata);
 void __init dm365_init_vc(struct snd_platform_data *pdata);
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 1a8b09c..6fca568 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -34,6 +34,12 @@
 #define DM644X_EMAC_MDIO_OFFSET		(0x4000)
 #define DM644X_EMAC_CNTRL_RAM_SIZE	(0x2000)
 
+#define DM644X_ASYNC_EMIF_CONTROL_BASE	0x01E00000
+#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
+#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
+#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
+#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
+
 void __init dm644x_init(void);
 void __init dm644x_init_asp(struct snd_platform_data *pdata);
 void dm644x_set_vpfe_config(struct vpfe_config *cfg);
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 846da98..4d62db7 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -27,6 +27,9 @@
 
 #define DM646X_ATA_REG_BASE		(0x01C66000)
 
+#define DM646X_ASYNC_EMIF_CONTROL_BASE	0x20008000
+#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
+
 void __init dm646x_init(void);
 void __init dm646x_init_ide(void);
 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:09 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:09 -0700
Subject: [PATCH 18/34] DA830 EVM: use DA8XX_AEMIF_*_BASE #define's
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-19-git-send-email-khilman@deeprootsystems.com>

From: Sergei Shtylyov <sshtylyov at ru.mvista.com>

The board file #define's its own version of EMIFA base addresses, while there
are DA8XX_AEMIF_*_BASE macros #define'd in <mach/da8xx.h>.  Start using them
instead.

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/board-da830-evm.c |   11 ++++-------
 1 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 9257056..8f079d2 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -33,9 +33,6 @@
 #define DA830_EVM_PHY_MASK		0x0
 #define DA830_EVM_MDIO_FREQUENCY	2200000	/* PHY bus frequency */
 
-#define DA830_EMIF25_ASYNC_DATA_CE3_BASE	0x62000000
-#define DA830_EMIF25_CONTROL_BASE		0x68000000
-
 /*
  * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
  */
@@ -375,13 +372,13 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = {
 
 static struct resource da830_evm_nand_resources[] = {
 	[0] = {		/* First memory resource is NAND I/O window */
-		.start	= DA830_EMIF25_ASYNC_DATA_CE3_BASE,
-		.end	= DA830_EMIF25_ASYNC_DATA_CE3_BASE + PAGE_SIZE - 1,
+		.start	= DA8XX_AEMIF_CS3_BASE,
+		.end	= DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {		/* Second memory resource is AEMIF control registers */
-		.start	= DA830_EMIF25_CONTROL_BASE,
-		.end	= DA830_EMIF25_CONTROL_BASE + SZ_32K - 1,
+		.start	= DA8XX_AEMIF_CTL_BASE,
+		.end	= DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:10 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:10 -0700
Subject: [PATCH 19/34] davinci: DM365: Allow use of GPIO64_57
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-20-git-send-email-khilman@deeprootsystems.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

Extended the MUX configuration to allow use of GPIO
terminals 64..57.

Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/dm365.c            |    1 +
 arch/arm/mach-davinci/include/mach/mux.h |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 871be5a..1ee3fc8 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -576,6 +576,7 @@ MUX_CFG(DM365,	SPI4_SDENA1,	4,   16,    3,    2,	 false)
 MUX_CFG(DM365,	GPIO20,		3,   21,    3,    0,	 false)
 MUX_CFG(DM365,	GPIO33,		4,   12,    3,	  0,	 false)
 MUX_CFG(DM365,	GPIO40,		4,   26,    3,	  0,	 false)
+MUX_CFG(DM365,	GPIO64_57,	2,   6,     1,	  0,	 false)
 
 MUX_CFG(DM365,	VOUT_FIELD,	1,   18,    3,	  1,	 false)
 MUX_CFG(DM365,	VOUT_FIELD_G81,	1,   18,    3,	  0,	 false)
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 8638903..923debe 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -291,6 +291,7 @@ enum davinci_dm365_index {
 	DM365_GPIO20,
 	DM365_GPIO33,
 	DM365_GPIO40,
+	DM365_GPIO64_57,
 
 	/* Video */
 	DM365_VOUT_FIELD,
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:11 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:11 -0700
Subject: [PATCH 20/34] Davinci: configurable pll divider mask
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-21-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

This patch allows socs to override the divider ratio mask by setting an
optional field (div_ratio_mask) in the pll_data structure.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/clock.c |    9 ++++++---
 arch/arm/mach-davinci/clock.h |    1 +
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 5de60ae..868cb76 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -279,7 +279,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
 
 	v = __raw_readl(pll->base + clk->div_reg);
 	if (v & PLLDIV_EN) {
-		plldiv = (v & PLLDIV_RATIO_MASK) + 1;
+		plldiv = (v & pll->div_ratio_mask) + 1;
 		if (plldiv)
 			rate /= plldiv;
 	}
@@ -319,7 +319,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
 	if (pll->flags & PLL_HAS_PREDIV) {
 		prediv = __raw_readl(pll->base + PREDIV);
 		if (prediv & PLLDIV_EN)
-			prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
+			prediv = (prediv & pll->div_ratio_mask) + 1;
 		else
 			prediv = 1;
 	}
@@ -331,7 +331,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
 	if (pll->flags & PLL_HAS_POSTDIV) {
 		postdiv = __raw_readl(pll->base + POSTDIV);
 		if (postdiv & PLLDIV_EN)
-			postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
+			postdiv = (postdiv & pll->div_ratio_mask) + 1;
 		else
 			postdiv = 1;
 	}
@@ -458,6 +458,9 @@ int __init davinci_clk_init(struct clk_lookup *clocks)
 				clk->recalc = clk_leafclk_recalc;
 		}
 
+		if (clk->pll_data && !clk->pll_data->div_ratio_mask)
+			clk->pll_data->div_ratio_mask = PLLDIV_RATIO_MASK;
+
 		if (clk->recalc)
 			clk->rate = clk->recalc(clk);
 
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 53a0f7b..ce26015 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -76,6 +76,7 @@ struct pll_data {
 	u32 num;
 	u32 flags;
 	u32 input_rate;
+	u32 div_ratio_mask;
 };
 #define PLL_HAS_PREDIV          0x01
 #define PLL_HAS_POSTDIV         0x02
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:12 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:12 -0700
Subject: [PATCH 21/34] davinci: mach/common.h: add missing includes
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-22-git-send-email-khilman@deeprootsystems.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

linux/compiler.h is required for __iomem
linux/types.h is required u32

Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/include/mach/common.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 50a955f..d88104e 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -12,6 +12,9 @@
 #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
 #define __ARCH_ARM_MACH_DAVINCI_COMMON_H
 
+#include <linux/compiler.h>
+#include <linux/types.h>
+
 struct sys_timer;
 
 extern struct sys_timer davinci_timer;
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:13 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:13 -0700
Subject: [PATCH 22/34] DaVinci: move IDE platform device to its proper place
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-23-git-send-email-khilman@deeprootsystems.com>

From: Sergei Shtylyov <sshtylyov at ru.mvista.com>

The IDE platform device is registered in three different places (2 board files
for DM644x and in dm646x.c for DM646x) while both the IDE base address and the
IDE IRQ are the same for both SoCs -- therefore,  the proper place for the IDE
platform seems to be in devices.c. Merge the IDE platform data and registration
code and create davinci_init_ide() in place of dm646x_init_ide()...

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/board-dm644x-evm.c    |   33 +-------------------
 arch/arm/mach-davinci/board-dm646x-evm.c    |    2 +-
 arch/arm/mach-davinci/board-neuros-osd2.c   |   34 +-------------------
 arch/arm/mach-davinci/devices.c             |   44 +++++++++++++++++++++++++++
 arch/arm/mach-davinci/dm646x.c              |   32 -------------------
 arch/arm/mach-davinci/include/mach/common.h |    1 +
 arch/arm/mach-davinci/include/mach/dm646x.h |    3 --
 7 files changed, 49 insertions(+), 100 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index d028bab..73c0b04 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -41,8 +41,6 @@
 #define DM644X_EVM_PHY_MASK		(0x2)
 #define DM644X_EVM_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */
 
-#define DAVINCI_CFC_ATA_BASE		  0x01C66000
-
 #define LXT971_PHY_ID	(0x001378e2)
 #define LXT971_PHY_MASK	(0xfffffff0)
 
@@ -252,32 +250,6 @@ static struct platform_device rtc_dev = {
 	.id             = -1,
 };
 
-static struct resource ide_resources[] = {
-	{
-		.start          = DAVINCI_CFC_ATA_BASE,
-		.end            = DAVINCI_CFC_ATA_BASE + 0x7ff,
-		.flags          = IORESOURCE_MEM,
-	},
-	{
-		.start          = IRQ_IDE,
-		.end            = IRQ_IDE,
-		.flags          = IORESOURCE_IRQ,
-	},
-};
-
-static u64 ide_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device ide_dev = {
-	.name           = "palm_bk3710",
-	.id             = -1,
-	.resource       = ide_resources,
-	.num_resources  = ARRAY_SIZE(ide_resources),
-	.dev = {
-		.dma_mask		= &ide_dma_mask,
-		.coherent_dma_mask      = DMA_BIT_MASK(32),
-	},
-};
-
 static struct snd_platform_data dm644x_evm_snd_data;
 
 /*----------------------------------------------------------------------*/
@@ -698,10 +670,7 @@ static __init void davinci_evm_init(void)
 			pr_warning("WARNING: both IDE and Flash are "
 				"enabled, but they share AEMIF pins.\n"
 				"\tDisable IDE for NAND/NOR support.\n");
-		davinci_cfg_reg(DM644X_HPIEN_DISABLE);
-		davinci_cfg_reg(DM644X_ATAEN);
-		davinci_cfg_reg(DM644X_HDIREN);
-		platform_device_register(&ide_dev);
+		davinci_init_ide();
 	} else if (HAS_NAND || HAS_NOR) {
 		davinci_cfg_reg(DM644X_HPIEN_DISABLE);
 		davinci_cfg_reg(DM644X_ATAEN_DISABLE);
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index b22e22c..e2ac06f 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -733,7 +733,7 @@ static __init void evm_init(void)
 	platform_device_register(&davinci_nand_device);
 
 	if (HAS_ATA)
-		dm646x_init_ide();
+		davinci_init_ide();
 
 	soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
 	soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 5afe37e..875770c 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -31,6 +31,7 @@
 #include <asm/mach/arch.h>
 
 #include <mach/dm644x.h>
+#include <mach/common.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
 #include <mach/mux.h>
@@ -41,8 +42,6 @@
 #define NEUROS_OSD2_PHY_MASK		0x2
 #define NEUROS_OSD2_MDIO_FREQUENCY	2200000 /* PHY bus frequency */
 
-#define DAVINCI_CFC_ATA_BASE		 0x01C66000
-
 #define LXT971_PHY_ID			0x001378e2
 #define LXT971_PHY_MASK			0xfffffff0
 
@@ -127,32 +126,6 @@ static struct platform_device davinci_fb_device = {
 	.num_resources = 0,
 };
 
-static struct resource ide_resources[] = {
-	{
-		.start		= DAVINCI_CFC_ATA_BASE,
-		.end		= DAVINCI_CFC_ATA_BASE + 0x7ff,
-		.flags		= IORESOURCE_MEM,
-	},
-	{
-		.start		= IRQ_IDE,
-		.end		= IRQ_IDE,
-		.flags		= IORESOURCE_IRQ,
-	},
-};
-
-static u64 ide_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device ide_dev = {
-	.name		= "palm_bk3710",
-	.id		= -1,
-	.resource	= ide_resources,
-	.num_resources	= ARRAY_SIZE(ide_resources),
-	.dev = {
-		.dma_mask		= &ide_dma_mask,
-		.coherent_dma_mask	= DMA_BIT_MASK(32),
-	},
-};
-
 static struct snd_platform_data dm644x_ntosd2_snd_data;
 
 static struct gpio_led ntosd2_leds[] = {
@@ -256,10 +229,7 @@ static __init void davinci_ntosd2_init(void)
 			pr_warning("WARNING: both IDE and Flash are "
 				"enabled, but they share AEMIF pins.\n"
 				"\tDisable IDE for NAND/NOR support.\n");
-		davinci_cfg_reg(DM644X_HPIEN_DISABLE);
-		davinci_cfg_reg(DM644X_ATAEN);
-		davinci_cfg_reg(DM644X_HDIREN);
-		platform_device_register(&ide_dev);
+		davinci_init_ide();
 	} else if (HAS_NAND) {
 		davinci_cfg_reg(DM644X_HPIEN_DISABLE);
 		davinci_cfg_reg(DM644X_ATAEN_DISABLE);
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index ef28080..d9c82ee 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -26,6 +26,7 @@
 #include "clock.h"
 
 #define DAVINCI_I2C_BASE	     0x01C21000
+#define DAVINCI_ATA_BASE	     0x01C66000
 #define DAVINCI_MMCSD0_BASE	     0x01E10000
 #define DM355_MMCSD0_BASE	     0x01E11000
 #define DM355_MMCSD1_BASE	     0x01E00000
@@ -60,6 +61,49 @@ void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
 	(void) platform_device_register(&davinci_i2c_device);
 }
 
+static struct resource ide_resources[] = {
+	{
+		.start		= DAVINCI_ATA_BASE,
+		.end		= DAVINCI_ATA_BASE + 0x7ff,
+		.flags		= IORESOURCE_MEM,
+	},
+	{
+		.start		= IRQ_IDE,
+		.end		= IRQ_IDE,
+		.flags		= IORESOURCE_IRQ,
+	},
+};
+
+static u64 ide_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device ide_device = {
+	.name           = "palm_bk3710",
+	.id             = -1,
+	.resource       = ide_resources,
+	.num_resources  = ARRAY_SIZE(ide_resources),
+	.dev = {
+		.dma_mask		= &ide_dma_mask,
+		.coherent_dma_mask      = DMA_BIT_MASK(32),
+	},
+};
+
+void __init davinci_init_ide(void)
+{
+	if (cpu_is_davinci_dm644x()) {
+		davinci_cfg_reg(DM644X_HPIEN_DISABLE);
+		davinci_cfg_reg(DM644X_ATAEN);
+		davinci_cfg_reg(DM644X_HDIREN);
+	} else if (cpu_is_davinci_dm646x()) {
+		/* IRQ_DM646X_IDE is the same as IRQ_IDE */
+		davinci_cfg_reg(DM646X_ATAEN);
+	} else {
+		WARN_ON(1);
+		return;
+	}
+
+	platform_device_register(&ide_device);
+}
+
 #if	defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
 
 static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index b67b997..a0b3739 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -596,32 +596,6 @@ static struct platform_device dm646x_edma_device = {
 	.resource		= edma_resources,
 };
 
-static struct resource ide_resources[] = {
-	{
-		.start          = DM646X_ATA_REG_BASE,
-		.end            = DM646X_ATA_REG_BASE + 0x7ff,
-		.flags          = IORESOURCE_MEM,
-	},
-	{
-		.start          = IRQ_DM646X_IDE,
-		.end            = IRQ_DM646X_IDE,
-		.flags          = IORESOURCE_IRQ,
-	},
-};
-
-static u64 ide_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device ide_dev = {
-	.name           = "palm_bk3710",
-	.id             = -1,
-	.resource       = ide_resources,
-	.num_resources  = ARRAY_SIZE(ide_resources),
-	.dev = {
-		.dma_mask		= &ide_dma_mask,
-		.coherent_dma_mask      = DMA_BIT_MASK(32),
-	},
-};
-
 static struct resource dm646x_mcasp0_resources[] = {
 	{
 		.name	= "mcasp0",
@@ -867,12 +841,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.sram_len		= SZ_32K,
 };
 
-void __init dm646x_init_ide(void)
-{
-	davinci_cfg_reg(DM646X_ATAEN);
-	platform_device_register(&ide_dev);
-}
-
 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
 {
 	dm646x_mcasp0_device.dev.platform_data = pdata;
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index d88104e..884dc72 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -70,6 +70,7 @@ struct davinci_soc_info {
 extern struct davinci_soc_info davinci_soc_info;
 
 extern void davinci_common_init(struct davinci_soc_info *soc_info);
+extern void davinci_init_ide(void);
 
 /* standard place to map on-chip SRAMs; they *may* support DMA */
 #define SRAM_VIRT	0xfffe0000
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 4d62db7..add6f79 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -25,13 +25,10 @@
 #define DM646X_EMAC_MDIO_OFFSET		(0x4000)
 #define DM646X_EMAC_CNTRL_RAM_SIZE	(0x2000)
 
-#define DM646X_ATA_REG_BASE		(0x01C66000)
-
 #define DM646X_ASYNC_EMIF_CONTROL_BASE	0x20008000
 #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
 
 void __init dm646x_init(void);
-void __init dm646x_init_ide(void);
 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
 void __init dm646x_board_setup_refclk(struct clk *clk);
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:15 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:15 -0700
Subject: [PATCH 24/34] Davinci: gpio - structs and functions renamed
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-25-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

Renamed gpio types to something more sensible:
	struct gpio_controller	--> struct davinci_gpio_regs
	struct davinci_gpio	--> struct davinci_gpio_controller
	gpio2controller()	--> gpio2regs()
	irq2controller()	--> irq2regs()

This change also moves davinci_gpio_controller definition to gpio.h.
Eventually, the gpio registers structure will be moved to gpio.c and no longer
a common cross-soc definition.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/gpio.c              |   50 +++++++++++++----------------
 arch/arm/mach-davinci/include/mach/gpio.h |   14 ++++++--
 2 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 93f7c68..c77683c 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -22,28 +22,22 @@
 
 static DEFINE_SPINLOCK(gpio_lock);
 
-struct davinci_gpio {
-	struct gpio_chip	chip;
-	struct gpio_controller	__iomem *regs;
-	int			irq_base;
-};
-
 #define chip2controller(chip)	\
-	container_of(chip, struct davinci_gpio, chip)
+	container_of(chip, struct davinci_gpio_controller, chip)
 
-static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
+static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 
 /* create a non-inlined version */
-static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
+static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
 {
 	return __gpio_to_controller(gpio);
 }
 
-static inline struct gpio_controller __iomem *irq2controller(int irq)
+static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
 {
-	struct gpio_controller __iomem *g;
+	struct davinci_gpio_regs __iomem *g;
 
-	g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq);
+	g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
 
 	return g;
 }
@@ -60,8 +54,8 @@ static int __init davinci_gpio_irq_setup(void);
 static inline int __davinci_direction(struct gpio_chip *chip,
 			unsigned offset, bool out, int value)
 {
-	struct davinci_gpio *d = chip2controller(chip);
-	struct gpio_controller __iomem *g = d->regs;
+	struct davinci_gpio_controller *d = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *g = d->regs;
 	u32 temp;
 	u32 mask = 1 << offset;
 
@@ -99,8 +93,8 @@ davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
  */
 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-	struct davinci_gpio *d = chip2controller(chip);
-	struct gpio_controller __iomem *g = d->regs;
+	struct davinci_gpio_controller *d = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *g = d->regs;
 
 	return (1 << offset) & __raw_readl(&g->in_data);
 }
@@ -111,8 +105,8 @@ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 static void
 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
-	struct davinci_gpio *d = chip2controller(chip);
-	struct gpio_controller __iomem *g = d->regs;
+	struct davinci_gpio_controller *d = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *g = d->regs;
 
 	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
 }
@@ -150,7 +144,7 @@ static int __init davinci_gpio_setup(void)
 		if (chips[i].chip.ngpio > 32)
 			chips[i].chip.ngpio = 32;
 
-		chips[i].regs = gpio2controller(base);
+		chips[i].regs = gpio2regs(base);
 
 		gpiochip_add(&chips[i].chip);
 	}
@@ -174,7 +168,7 @@ pure_initcall(davinci_gpio_setup);
 
 static void gpio_irq_disable(unsigned irq)
 {
-	struct gpio_controller __iomem *g = irq2controller(irq);
+	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	__raw_writel(mask, &g->clr_falling);
@@ -183,7 +177,7 @@ static void gpio_irq_disable(unsigned irq)
 
 static void gpio_irq_enable(unsigned irq)
 {
-	struct gpio_controller __iomem *g = irq2controller(irq);
+	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 	u32 mask = (u32) get_irq_data(irq);
 	unsigned status = irq_desc[irq].status;
 
@@ -199,7 +193,7 @@ static void gpio_irq_enable(unsigned irq)
 
 static int gpio_irq_type(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller __iomem *g = irq2controller(irq);
+	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -228,7 +222,7 @@ static struct irq_chip gpio_irqchip = {
 static void
 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-	struct gpio_controller __iomem *g = irq2controller(irq);
+	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 	u32 mask = 0xffff;
 
 	/* we only care about one bank */
@@ -266,7 +260,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 
 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 {
-	struct davinci_gpio *d = chip2controller(chip);
+	struct davinci_gpio_controller *d = chip2controller(chip);
 
 	if (d->irq_base >= 0)
 		return d->irq_base + offset;
@@ -289,7 +283,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 
 static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller __iomem *g = irq2controller(irq);
+	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -318,7 +312,7 @@ static int __init davinci_gpio_irq_setup(void)
 	u32		binten = 0;
 	unsigned	ngpio, bank_irq;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	struct gpio_controller	__iomem *g;
+	struct davinci_gpio_regs	__iomem *g;
 
 	ngpio = soc_info->gpio_num;
 
@@ -367,7 +361,7 @@ static int __init davinci_gpio_irq_setup(void)
 		gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
 
 		/* default trigger: both edges */
-		g = gpio2controller(0);
+		g = gpio2regs(0);
 		__raw_writel(~0, &g->set_falling);
 		__raw_writel(~0, &g->set_rising);
 
@@ -392,7 +386,7 @@ static int __init davinci_gpio_irq_setup(void)
 		unsigned		i;
 
 		/* disabled by default, enabled only as needed */
-		g = gpio2controller(gpio);
+		g = gpio2regs(gpio);
 		__raw_writel(~0, &g->clr_falling);
 		__raw_writel(~0, &g->clr_rising);
 
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 0099e6e..bdab001 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -45,7 +45,7 @@
 /* Convert GPIO signal to GPIO pin number */
 #define GPIO_TO_PIN(bank, gpio)	(16 * (bank) + (gpio))
 
-struct gpio_controller {
+struct davinci_gpio_regs {
 	u32	dir;
 	u32	out_data;
 	u32	set_data;
@@ -58,6 +58,12 @@ struct gpio_controller {
 	u32	intstat;
 };
 
+struct davinci_gpio_controller {
+	struct davinci_gpio_regs __iomem *regs;
+	struct gpio_chip	chip;
+	int			irq_base;
+};
+
 /* The __gpio_to_controller() and __gpio_mask() functions inline to constants
  * with constant parameters; or in outlined code they execute at runtime.
  *
@@ -67,7 +73,7 @@ struct gpio_controller {
  *
  * These are NOT part of the cross-platform GPIO interface
  */
-static inline struct gpio_controller __iomem *
+static inline struct davinci_gpio_regs __iomem *
 __gpio_to_controller(unsigned gpio)
 {
 	void __iomem *ptr;
@@ -102,7 +108,7 @@ static inline u32 __gpio_mask(unsigned gpio)
 static inline void gpio_set_value(unsigned gpio, int value)
 {
 	if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
-		struct gpio_controller	__iomem *g;
+		struct davinci_gpio_regs	__iomem *g;
 		u32			mask;
 
 		g = __gpio_to_controller(gpio);
@@ -128,7 +134,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
  */
 static inline int gpio_get_value(unsigned gpio)
 {
-	struct gpio_controller	__iomem *g;
+	struct davinci_gpio_regs	__iomem *g;
 
 	if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
 		return __gpio_get_value(gpio);
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:14 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:14 -0700
Subject: [PATCH 23/34] Davinci: gpio - minor cleanup
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-24-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

macroized repeated container_of()s to improve readability.
unified direction in/out functions.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/gpio.c |   50 ++++++++++++++++++++++-------------------
 1 files changed, 27 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 5476ad1..93f7c68 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -28,6 +28,9 @@ struct davinci_gpio {
 	int			irq_base;
 };
 
+#define chip2controller(chip)	\
+	container_of(chip, struct davinci_gpio, chip)
+
 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 
 /* create a non-inlined version */
@@ -54,21 +57,39 @@ static int __init davinci_gpio_irq_setup(void);
  * needed, and enable the GPIO clock.
  */
 
-static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
+static inline int __davinci_direction(struct gpio_chip *chip,
+			unsigned offset, bool out, int value)
 {
-	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+	struct davinci_gpio *d = chip2controller(chip);
 	struct gpio_controller __iomem *g = d->regs;
 	u32 temp;
+	u32 mask = 1 << offset;
 
 	spin_lock(&gpio_lock);
 	temp = __raw_readl(&g->dir);
-	temp |= (1 << offset);
+	if (out) {
+		temp &= ~mask;
+		__raw_writel(mask, value ? &g->set_data : &g->clr_data);
+	} else {
+		temp |= mask;
+	}
 	__raw_writel(temp, &g->dir);
 	spin_unlock(&gpio_lock);
 
 	return 0;
 }
 
+static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
+{
+	return __davinci_direction(chip, offset, false, 0);
+}
+
+static int
+davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
+{
+	return __davinci_direction(chip, offset, true, value);
+}
+
 /*
  * Read the pin's value (works even if it's set up as output);
  * returns zero/nonzero.
@@ -78,36 +99,19 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
  */
 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+	struct davinci_gpio *d = chip2controller(chip);
 	struct gpio_controller __iomem *g = d->regs;
 
 	return (1 << offset) & __raw_readl(&g->in_data);
 }
 
-static int
-davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
-{
-	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller __iomem *g = d->regs;
-	u32 temp;
-	u32 mask = 1 << offset;
-
-	spin_lock(&gpio_lock);
-	temp = __raw_readl(&g->dir);
-	temp &= ~mask;
-	__raw_writel(mask, value ? &g->set_data : &g->clr_data);
-	__raw_writel(temp, &g->dir);
-	spin_unlock(&gpio_lock);
-	return 0;
-}
-
 /*
  * Assuming the pin is muxed as a gpio output, set its output value.
  */
 static void
 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
-	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+	struct davinci_gpio *d = chip2controller(chip);
 	struct gpio_controller __iomem *g = d->regs;
 
 	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
@@ -262,7 +266,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 
 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 {
-	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+	struct davinci_gpio *d = chip2controller(chip);
 
 	if (d->irq_base >= 0)
 		return d->irq_base + offset;
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:16 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:16 -0700
Subject: [PATCH 25/34] Davinci: gpio - register layout invariant inlines
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-26-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

This patch renders the inlined gpio accessors in gpio.h independent of the
underlying controller's register layout.  This is done by including three new
fields in davinci_gpio_controller to hold the addresses of the set, clear, and
in data registers.

Other changes:

1. davinci_gpio_regs structure definition moved to gpio.c.  This structure is
no longer common across all davinci socs (davinci_gpio_controller is).

2. controller base address calculation code (gpio2controller()) moved to
gpio.c as this was no longer necessary for the inline implementation.

3. modified inline range checks to use davinci_soc_info.gpio_num instead of
DAVINCI_N_GPIO.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/gpio.c                |   41 ++++++++++++++++-
 arch/arm/mach-davinci/include/mach/common.h |    4 ++
 arch/arm/mach-davinci/include/mach/gpio.h   |   65 +++++++++-----------------
 3 files changed, 65 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index c77683c..d241b4f 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -20,6 +20,19 @@
 
 #include <asm/mach/irq.h>
 
+struct davinci_gpio_regs {
+	u32	dir;
+	u32	out_data;
+	u32	set_data;
+	u32	clr_data;
+	u32	in_data;
+	u32	set_rising;
+	u32	clr_rising;
+	u32	set_falling;
+	u32	clr_falling;
+	u32	intstat;
+};
+
 static DEFINE_SPINLOCK(gpio_lock);
 
 #define chip2controller(chip)	\
@@ -27,10 +40,24 @@ static DEFINE_SPINLOCK(gpio_lock);
 
 static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 
-/* create a non-inlined version */
 static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
 {
-	return __gpio_to_controller(gpio);
+	void __iomem *ptr;
+	void __iomem *base = davinci_soc_info.gpio_base;
+
+	if (gpio < 32 * 1)
+		ptr = base + 0x10;
+	else if (gpio < 32 * 2)
+		ptr = base + 0x38;
+	else if (gpio < 32 * 3)
+		ptr = base + 0x60;
+	else if (gpio < 32 * 4)
+		ptr = base + 0x88;
+	else if (gpio < 32 * 5)
+		ptr = base + 0xb0;
+	else
+		ptr = NULL;
+	return ptr;
 }
 
 static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
@@ -116,6 +143,7 @@ static int __init davinci_gpio_setup(void)
 	int i, base;
 	unsigned ngpio;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
+	struct davinci_gpio_regs *regs;
 
 	/*
 	 * The gpio banks conceptually expose a segmented bitmap,
@@ -144,11 +172,18 @@ static int __init davinci_gpio_setup(void)
 		if (chips[i].chip.ngpio > 32)
 			chips[i].chip.ngpio = 32;
 
-		chips[i].regs = gpio2regs(base);
+		regs = gpio2regs(base);
+		chips[i].regs = regs;
+		chips[i].set_data = &regs->set_data;
+		chips[i].clr_data = &regs->clr_data;
+		chips[i].in_data = &regs->in_data;
 
 		gpiochip_add(&chips[i].chip);
 	}
 
+	soc_info->gpio_ctlrs = chips;
+	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
+
 	davinci_gpio_irq_setup();
 	return 0;
 }
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 884dc72..1d72883 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -37,6 +37,8 @@ struct davinci_timer_info {
 	unsigned int			clocksource_id;
 };
 
+struct davinci_gpio_controller;
+
 /* SoC specific init support */
 struct davinci_soc_info {
 	struct map_desc			*io_desc;
@@ -61,6 +63,8 @@ struct davinci_soc_info {
 	unsigned			gpio_num;
 	unsigned			gpio_irq;
 	unsigned			gpio_unbanked;
+	struct davinci_gpio_controller	*gpio_ctlrs;
+	int				gpio_ctlrs_num;
 	struct platform_device		*serial_dev;
 	struct emac_platform_data	*emac_pdata;
 	dma_addr_t			sram_dma;
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index bdab001..82591d0 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -45,23 +45,13 @@
 /* Convert GPIO signal to GPIO pin number */
 #define GPIO_TO_PIN(bank, gpio)	(16 * (bank) + (gpio))
 
-struct davinci_gpio_regs {
-	u32	dir;
-	u32	out_data;
-	u32	set_data;
-	u32	clr_data;
-	u32	in_data;
-	u32	set_rising;
-	u32	clr_rising;
-	u32	set_falling;
-	u32	clr_falling;
-	u32	intstat;
-};
-
 struct davinci_gpio_controller {
-	struct davinci_gpio_regs __iomem *regs;
 	struct gpio_chip	chip;
 	int			irq_base;
+	void __iomem		*regs;
+	void __iomem		*set_data;
+	void __iomem		*clr_data;
+	void __iomem		*in_data;
 };
 
 /* The __gpio_to_controller() and __gpio_mask() functions inline to constants
@@ -73,25 +63,16 @@ struct davinci_gpio_controller {
  *
  * These are NOT part of the cross-platform GPIO interface
  */
-static inline struct davinci_gpio_regs __iomem *
+static inline struct davinci_gpio_controller *
 __gpio_to_controller(unsigned gpio)
 {
-	void __iomem *ptr;
-	void __iomem *base = davinci_soc_info.gpio_base;
-
-	if (gpio < 32 * 1)
-		ptr = base + 0x10;
-	else if (gpio < 32 * 2)
-		ptr = base + 0x38;
-	else if (gpio < 32 * 3)
-		ptr = base + 0x60;
-	else if (gpio < 32 * 4)
-		ptr = base + 0x88;
-	else if (gpio < 32 * 5)
-		ptr = base + 0xb0;
-	else
-		ptr = NULL;
-	return ptr;
+	struct davinci_gpio_controller *ctlrs = davinci_soc_info.gpio_ctlrs;
+	int index = gpio / 32;
+
+	if (!ctlrs || index >= davinci_soc_info.gpio_ctlrs_num)
+		return NULL;
+
+	return ctlrs + index;
 }
 
 static inline u32 __gpio_mask(unsigned gpio)
@@ -107,16 +88,16 @@ static inline u32 __gpio_mask(unsigned gpio)
  */
 static inline void gpio_set_value(unsigned gpio, int value)
 {
-	if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
-		struct davinci_gpio_regs	__iomem *g;
-		u32			mask;
+	if (__builtin_constant_p(value) && gpio < davinci_soc_info.gpio_num) {
+		struct davinci_gpio_controller *ctlr;
+		u32				mask;
 
-		g = __gpio_to_controller(gpio);
+		ctlr = __gpio_to_controller(gpio);
 		mask = __gpio_mask(gpio);
 		if (value)
-			__raw_writel(mask, &g->set_data);
+			__raw_writel(mask, ctlr->set_data);
 		else
-			__raw_writel(mask, &g->clr_data);
+			__raw_writel(mask, ctlr->clr_data);
 		return;
 	}
 
@@ -134,18 +115,18 @@ static inline void gpio_set_value(unsigned gpio, int value)
  */
 static inline int gpio_get_value(unsigned gpio)
 {
-	struct davinci_gpio_regs	__iomem *g;
+	struct davinci_gpio_controller *ctlr;
 
-	if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
+	if (!__builtin_constant_p(gpio) || gpio >= davinci_soc_info.gpio_num)
 		return __gpio_get_value(gpio);
 
-	g = __gpio_to_controller(gpio);
-	return __gpio_mask(gpio) & __raw_readl(&g->in_data);
+	ctlr = __gpio_to_controller(gpio);
+	return __gpio_mask(gpio) & __raw_readl(ctlr->in_data);
 }
 
 static inline int gpio_cansleep(unsigned gpio)
 {
-	if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO)
+	if (__builtin_constant_p(gpio) && gpio < davinci_soc_info.gpio_num)
 		return 0;
 	else
 		return __gpio_cansleep(gpio);
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:17 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:17 -0700
Subject: [PATCH 26/34] Davinci: gpio - controller type support
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-27-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

This patch allows for gpio controllers that deviate from those found on
traditional davinci socs.  davinci_soc_info has an added field to indicate the
soc-specific gpio controller type.  The gpio initialization code then bails
out if necessary.

More elements (tnetv107x) to be added later into enum davinci_gpio_type.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/da830.c               |    2 ++
 arch/arm/mach-davinci/da850.c               |    2 ++
 arch/arm/mach-davinci/dm355.c               |    1 +
 arch/arm/mach-davinci/dm365.c               |    1 +
 arch/arm/mach-davinci/dm644x.c              |    1 +
 arch/arm/mach-davinci/dm646x.c              |    1 +
 arch/arm/mach-davinci/gpio.c                |    3 +++
 arch/arm/mach-davinci/include/mach/common.h |    1 +
 arch/arm/mach-davinci/include/mach/gpio.h   |    4 ++++
 9 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 122e61a..68e5233 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -19,6 +19,7 @@
 #include <mach/common.h>
 #include <mach/time.h>
 #include <mach/da8xx.h>
+#include <mach/gpio.h>
 
 #include "clock.h"
 #include "mux.h"
@@ -1199,6 +1200,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.intc_irq_prios		= da830_default_priorities,
 	.intc_irq_num		= DA830_N_CP_INTC_IRQ,
 	.timer_info		= &da830_timer_info,
+	.gpio_type		= GPIO_TYPE_DAVINCI,
 	.gpio_base		= IO_ADDRESS(DA8XX_GPIO_BASE),
 	.gpio_num		= 128,
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index d0fd756..8aefcff 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -27,6 +27,7 @@
 #include <mach/da8xx.h>
 #include <mach/cpufreq.h>
 #include <mach/pm.h>
+#include <mach/gpio.h>
 
 #include "clock.h"
 #include "mux.h"
@@ -1084,6 +1085,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.intc_irq_prios		= da850_default_priorities,
 	.intc_irq_num		= DA850_N_CP_INTC_IRQ,
 	.timer_info		= &da850_timer_info,
+	.gpio_type		= GPIO_TYPE_DAVINCI,
 	.gpio_base		= IO_ADDRESS(DA8XX_GPIO_BASE),
 	.gpio_num		= 144,
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 5efce70..f9a54ff 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -859,6 +859,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.intc_irq_prios		= dm355_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm355_timer_info,
+	.gpio_type		= GPIO_TYPE_DAVINCI,
 	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
 	.gpio_num		= 104,
 	.gpio_irq		= IRQ_DM355_GPIOBNK0,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 1ee3fc8..0566675 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1064,6 +1064,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.intc_irq_prios		= dm365_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm365_timer_info,
+	.gpio_type		= GPIO_TYPE_DAVINCI,
 	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
 	.gpio_num		= 104,
 	.gpio_irq		= IRQ_DM365_GPIO0,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 23cbe9d..4af349e 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -748,6 +748,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.intc_irq_prios 	= dm644x_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm644x_timer_info,
+	.gpio_type		= GPIO_TYPE_DAVINCI,
 	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
 	.gpio_num		= 71,
 	.gpio_irq		= IRQ_GPIOBNK0,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index a0b3739..bdb1ace 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -832,6 +832,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.intc_irq_prios		= dm646x_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm646x_timer_info,
+	.gpio_type		= GPIO_TYPE_DAVINCI,
 	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
 	.gpio_num		= 43, /* Only 33 usable */
 	.gpio_irq		= IRQ_DM646X_GPIOBNK0,
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index d241b4f..e422cd3 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -145,6 +145,9 @@ static int __init davinci_gpio_setup(void)
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	struct davinci_gpio_regs *regs;
 
+	if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
+		return 0;
+
 	/*
 	 * The gpio banks conceptually expose a segmented bitmap,
 	 * and "ngpio" is one more than the largest zero-based
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 1d72883..8ffef5b 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -59,6 +59,7 @@ struct davinci_soc_info {
 	u8				*intc_irq_prios;
 	unsigned long			intc_irq_num;
 	struct davinci_timer_info	*timer_info;
+	int				gpio_type;
 	void __iomem			*gpio_base;
 	unsigned			gpio_num;
 	unsigned			gpio_irq;
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 82591d0..9a71a26 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -21,6 +21,10 @@
 
 #define DAVINCI_GPIO_BASE 0x01C67000
 
+enum davinci_gpio_type {
+	GPIO_TYPE_DAVINCI = 0,
+};
+
 /*
  * basic gpio routines
  *
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:18 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:18 -0700
Subject: [PATCH 27/34] Davinci: gpio - fine grained locking
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-28-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

This patch eliminates the global gpio_lock, and implements a per-controller
lock instead.  This also switches to irqsave/irqrestore locks in case gpios
are manipulated in isr.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/gpio.c              |    9 +++++----
 arch/arm/mach-davinci/include/mach/gpio.h |    3 +++
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index e422cd3..b62d5e2 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -33,8 +33,6 @@ struct davinci_gpio_regs {
 	u32	intstat;
 };
 
-static DEFINE_SPINLOCK(gpio_lock);
-
 #define chip2controller(chip)	\
 	container_of(chip, struct davinci_gpio_controller, chip)
 
@@ -83,10 +81,11 @@ static inline int __davinci_direction(struct gpio_chip *chip,
 {
 	struct davinci_gpio_controller *d = chip2controller(chip);
 	struct davinci_gpio_regs __iomem *g = d->regs;
+	unsigned long flags;
 	u32 temp;
 	u32 mask = 1 << offset;
 
-	spin_lock(&gpio_lock);
+	spin_lock_irqsave(&d->lock, flags);
 	temp = __raw_readl(&g->dir);
 	if (out) {
 		temp &= ~mask;
@@ -95,7 +94,7 @@ static inline int __davinci_direction(struct gpio_chip *chip,
 		temp |= mask;
 	}
 	__raw_writel(temp, &g->dir);
-	spin_unlock(&gpio_lock);
+	spin_unlock_irqrestore(&d->lock, flags);
 
 	return 0;
 }
@@ -175,6 +174,8 @@ static int __init davinci_gpio_setup(void)
 		if (chips[i].chip.ngpio > 32)
 			chips[i].chip.ngpio = 32;
 
+		spin_lock_init(&chips[i].lock);
+
 		regs = gpio2regs(base);
 		chips[i].regs = regs;
 		chips[i].set_data = &regs->set_data;
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 9a71a26..504cc18 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -14,6 +14,8 @@
 #define	__DAVINCI_GPIO_H
 
 #include <linux/io.h>
+#include <linux/spinlock.h>
+
 #include <asm-generic/gpio.h>
 
 #include <mach/irqs.h>
@@ -52,6 +54,7 @@ enum davinci_gpio_type {
 struct davinci_gpio_controller {
 	struct gpio_chip	chip;
 	int			irq_base;
+	spinlock_t		lock;
 	void __iomem		*regs;
 	void __iomem		*set_data;
 	void __iomem		*clr_data;
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:19 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:19 -0700
Subject: [PATCH 28/34] Davinci: eliminate pinmux offset verbosity
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-29-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

Pinmux registers are sequential, and do not need to be enumerated out as they
currently are.  This reduces code volume and keeps things simple.

If some future SoC comes up with a discontiguous register map, PINMUX() can
then be expanded with local token pasting.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/dm355.c              |    5 -----
 arch/arm/mach-davinci/dm365.c              |    5 -----
 arch/arm/mach-davinci/dm644x.c             |    3 ---
 arch/arm/mach-davinci/dm646x.c             |    3 ---
 arch/arm/mach-davinci/gpio.c               |    6 +-----
 arch/arm/mach-davinci/include/mach/da8xx.h |   21 ---------------------
 arch/arm/mach-davinci/include/mach/mux.h   |    2 ++
 arch/arm/mach-davinci/mux.h                |    2 +-
 8 files changed, 4 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index f9a54ff..f91e9a1 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -450,11 +450,6 @@ void __init dm355_init_spi0(unsigned chipselect_mask,
 
 /*----------------------------------------------------------------------*/
 
-#define PINMUX0		0x00
-#define PINMUX1		0x04
-#define PINMUX2		0x08
-#define PINMUX3		0x0c
-#define PINMUX4		0x10
 #define INTMUX		0x18
 #define EVTMUX		0x1c
 
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0566675..f2b1d93 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -467,11 +467,6 @@ static struct clk_lookup dm365_clks[] = {
 
 /*----------------------------------------------------------------------*/
 
-#define PINMUX0		0x00
-#define PINMUX1		0x04
-#define PINMUX2		0x08
-#define PINMUX3		0x0c
-#define PINMUX4		0x10
 #define INTMUX		0x18
 #define EVTMUX		0x1c
 
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 4af349e..85c88ec 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -350,9 +350,6 @@ static struct platform_device dm644x_emac_device = {
        .resource	= dm644x_emac_resources,
 };
 
-#define PINMUX0		0x00
-#define PINMUX1		0x04
-
 /*
  * Device specific mux setup
  *
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index bdb1ace..a8189c9 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -401,9 +401,6 @@ static struct platform_device dm646x_emac_device = {
 	.resource	= dm646x_emac_resources,
 };
 
-#define PINMUX0		0x00
-#define PINMUX1		0x04
-
 /*
  * Device specific mux setup
  *
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index b62d5e2..2efb446 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -71,11 +71,7 @@ static int __init davinci_gpio_irq_setup(void);
 
 /*--------------------------------------------------------------------------*/
 
-/*
- * board setup code *MUST* set PINMUX0 and PINMUX1 as
- * needed, and enable the GPIO clock.
- */
-
+/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
 static inline int __davinci_direction(struct gpio_chip *chip,
 			unsigned offset, bool out, int value)
 {
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 33471c9..dbb4ebe 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -64,27 +64,6 @@ extern void __iomem *da8xx_syscfg1_base;
 #define DA8XX_DDR2_CTL_BASE	0xb0000000
 #define DA8XX_ARM_RAM_BASE	0xffff0000
 
-#define PINMUX0			0x00
-#define PINMUX1			0x04
-#define PINMUX2			0x08
-#define PINMUX3			0x0c
-#define PINMUX4			0x10
-#define PINMUX5			0x14
-#define PINMUX6			0x18
-#define PINMUX7			0x1c
-#define PINMUX8			0x20
-#define PINMUX9			0x24
-#define PINMUX10		0x28
-#define PINMUX11		0x2c
-#define PINMUX12		0x30
-#define PINMUX13		0x34
-#define PINMUX14		0x38
-#define PINMUX15		0x3c
-#define PINMUX16		0x40
-#define PINMUX17		0x44
-#define PINMUX18		0x48
-#define PINMUX19		0x4c
-
 void __init da830_init(void);
 void __init da850_init(void);
 
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 923debe..743dbd2 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -1174,6 +1174,8 @@ enum davinci_tnetv107x_index {
 	TNETV107X_TDM0_RX,
 };
 
+#define PINMUX(x)		(4 * (x))
+
 #ifdef CONFIG_DAVINCI_MUX
 /* setup pin muxing */
 extern int davinci_cfg_reg(unsigned long reg_cfg);
diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h
index adc8694..5aad1e7 100644
--- a/arch/arm/mach-davinci/mux.h
+++ b/arch/arm/mach-davinci/mux.h
@@ -20,7 +20,7 @@
 			.name =  #desc,					\
 			.debug = dbg,					\
 			.mux_reg_name = "PINMUX"#muxreg,		\
-			.mux_reg = PINMUX##muxreg,			\
+			.mux_reg = PINMUX(muxreg),			\
 			.mask_offset = mode_offset,			\
 			.mask = mode_mask,				\
 			.mode = mux_mode,				\
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:20 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:20 -0700
Subject: [PATCH 29/34] Davinci: watchdog reset separation across socs
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-30-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

The earlier watchdog reset mechanism had a couple of limitations.  First, it
embedded a reference to "davinci_wdt_device" inside common code.  This
forced all derived platforms (da8xx and tnetv107x) to define such a device.
This also would have caused problems in including multiple socs in a single
build due to symbol redefinition.

With this patch, davinci_watchdog_reset() now takes the platform device as an
argument.  The davinci_soc_info struct has been extended to include a reset
function and a watchdog platform_device.  arch_reset() then uses these
elements to reset the system in a SoC specific fashion.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Tested-by: Sandeep Paulraj <s-paulraj at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/clock.h               |    1 +
 arch/arm/mach-davinci/common.c              |    3 +++
 arch/arm/mach-davinci/da830.c               |    1 +
 arch/arm/mach-davinci/da850.c               |    1 +
 arch/arm/mach-davinci/devices-da8xx.c       |    4 ++--
 arch/arm/mach-davinci/dm355.c               |    1 +
 arch/arm/mach-davinci/dm365.c               |    1 +
 arch/arm/mach-davinci/dm644x.c              |    1 +
 arch/arm/mach-davinci/dm646x.c              |    1 +
 arch/arm/mach-davinci/include/mach/common.h |    2 ++
 arch/arm/mach-davinci/include/mach/da8xx.h  |    2 ++
 arch/arm/mach-davinci/include/mach/system.h |    5 +++--
 arch/arm/mach-davinci/time.c                |    9 ++++++---
 13 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index ce26015..01e3648 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -120,6 +120,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
 				unsigned int mult, unsigned int postdiv);
 
 extern struct platform_device davinci_wdt_device;
+extern void davinci_watchdog_reset(struct platform_device *);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 94f27cb..f8221c5 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -77,6 +77,9 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
 	local_flush_tlb_all();
 	flush_cache_all();
 
+	if (!davinci_soc_info.reset)
+		davinci_soc_info.reset = davinci_watchdog_reset;
+
 	/*
 	 * We want to check CPU revision early for cpu_is_xxxx() macros.
 	 * IO space mapping must be initialized before we can do that.
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 68e5233..83879f8 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1206,6 +1206,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
 	.serial_dev		= &da8xx_serial_device,
 	.emac_pdata		= &da8xx_emac_pdata,
+	.reset_device		= &da8xx_wdt_device,
 };
 
 void __init da830_init(void)
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 8aefcff..2b6dd59 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1093,6 +1093,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.emac_pdata		= &da8xx_emac_pdata,
 	.sram_dma		= DA8XX_ARM_RAM_BASE,
 	.sram_len		= SZ_8K,
+	.reset_device		= &da8xx_wdt_device,
 };
 
 void __init da850_init(void)
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 0a96791..67a6fbc 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -326,7 +326,7 @@ static struct resource da8xx_watchdog_resources[] = {
 	},
 };
 
-struct platform_device davinci_wdt_device = {
+struct platform_device da8xx_wdt_device = {
 	.name		= "watchdog",
 	.id		= -1,
 	.num_resources	= ARRAY_SIZE(da8xx_watchdog_resources),
@@ -335,7 +335,7 @@ struct platform_device davinci_wdt_device = {
 
 int __init da8xx_register_watchdog(void)
 {
-	return platform_device_register(&davinci_wdt_device);
+	return platform_device_register(&da8xx_wdt_device);
 }
 
 static struct resource da8xx_emac_resources[] = {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index f91e9a1..0c62a68 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -861,6 +861,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.serial_dev		= &dm355_serial_device,
 	.sram_dma		= 0x00010000,
 	.sram_len		= SZ_32K,
+	.reset_device		= &davinci_wdt_device,
 };
 
 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index f2b1d93..ed76450 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1068,6 +1068,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.emac_pdata		= &dm365_emac_pdata,
 	.sram_dma		= 0x00010000,
 	.sram_len		= SZ_32K,
+	.reset_device		= &davinci_wdt_device,
 };
 
 void __init dm365_init_asp(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 85c88ec..7f36c22 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -753,6 +753,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.emac_pdata		= &dm644x_emac_pdata,
 	.sram_dma		= 0x00008000,
 	.sram_len		= SZ_16K,
+	.reset_device		= &davinci_wdt_device,
 };
 
 void __init dm644x_init_asp(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index a8189c9..8dd0afe 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -837,6 +837,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.emac_pdata		= &dm646x_emac_pdata,
 	.sram_dma		= 0x10010000,
 	.sram_len		= SZ_32K,
+	.reset_device		= &davinci_wdt_device,
 };
 
 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 8ffef5b..a58bd88 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -70,6 +70,8 @@ struct davinci_soc_info {
 	struct emac_platform_data	*emac_pdata;
 	dma_addr_t			sram_dma;
 	unsigned			sram_len;
+	struct platform_device		*reset_device;
+	void				(*reset)(struct platform_device *);
 };
 
 extern struct davinci_soc_info davinci_soc_info;
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index dbb4ebe..1b31a9a 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -87,6 +87,8 @@ extern struct emac_platform_data da8xx_emac_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
 
+extern struct platform_device da8xx_wdt_device;
+
 extern const short da830_emif25_pins[];
 extern const short da830_spi0_pins[];
 extern const short da830_spi1_pins[];
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
index 5a7d758..e65629c 100644
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -11,7 +11,7 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-extern void davinci_watchdog_reset(void);
+#include <mach/common.h>
 
 static inline void arch_idle(void)
 {
@@ -20,7 +20,8 @@ static inline void arch_idle(void)
 
 static inline void arch_reset(char mode, const char *cmd)
 {
-	davinci_watchdog_reset();
+	if (davinci_soc_info.reset)
+		davinci_soc_info.reset(davinci_soc_info.reset_device);
 }
 
 #endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index b21f763..e5c598a 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -399,13 +399,16 @@ struct sys_timer davinci_timer = {
 
 
 /* reset board using watchdog timer */
-void davinci_watchdog_reset(void)
+void davinci_watchdog_reset(struct platform_device *pdev)
 {
 	u32 tgcr, wdtcr;
-	struct platform_device *pdev = &davinci_wdt_device;
-	void __iomem *base = IO_ADDRESS(pdev->resource[0].start);
+	void __iomem *base;
 	struct clk *wd_clk;
 
+	base = ioremap(pdev->resource[0].start, SZ_4K);
+	if (WARN_ON(!base))
+		return;
+
 	wd_clk = clk_get(&pdev->dev, NULL);
 	if (WARN_ON(IS_ERR(wd_clk)))
 		return;
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:21 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:21 -0700
Subject: [PATCH 30/34] Davinci: serial - remove unnecessary define
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-31-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

The uart pdata array is already terminated by a zero flag field.

This patch reuses this terminator and eliminates DAVINCI_MAX_NR_UARTS
definition.  This way, future platforms can have different number of uarts
initialized via davinci_serial_init().

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/include/mach/serial.h |    1 -
 arch/arm/mach-davinci/serial.c              |    2 +-
 2 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index a584697..f6c4f34 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -13,7 +13,6 @@
 
 #include <mach/hardware.h>
 
-#define DAVINCI_MAX_NR_UARTS	3
 #define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 7ce5ba0..709e1a9 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -77,7 +77,7 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
 	 * Make sure the serial ports are muxed on at this point.
 	 * You have to mux them off in device drivers later on if not needed.
 	 */
-	for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++, p++) {
+	for (i = 0; p->flags; i++, p++) {
 		if (!(info->enabled_uarts & (1 << i)))
 			continue;
 
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:22 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:22 -0700
Subject: [PATCH 31/34] Davinci: serial - use ioremap()
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-32-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

This patch implements davinci serial cleanups towards having this code
reusable on tnetv107x.

The change reuses the platform data membase field to hold the remapped space.
By disabling the UPF_IOREMAP flag in the platform data, we prevent
the 8250 driver from repeating the ioremap.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/serial.c |   32 +++++++++++++++++++++++++-------
 1 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 709e1a9..81af42c 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -35,14 +35,20 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
 					   int offset)
 {
 	offset <<= up->regshift;
-	return (unsigned int)__raw_readl(IO_ADDRESS(up->mapbase) + offset);
+
+	WARN_ONCE(!up->membase, "unmapped read: uart[%d]\n", offset);
+
+	return (unsigned int)__raw_readl(up->membase + offset);
 }
 
 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
 				    int value)
 {
 	offset <<= p->regshift;
-	__raw_writel(value, IO_ADDRESS(p->mapbase) + offset);
+
+	WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset);
+
+	__raw_writel(value, p->membase + offset);
 }
 
 static void __init davinci_serial_reset(struct plat_serial8250_port *p)
@@ -83,14 +89,26 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
 
 		sprintf(name, "uart%d", i);
 		uart_clk = clk_get(dev, name);
-		if (IS_ERR(uart_clk))
+		if (IS_ERR(uart_clk)) {
 			printk(KERN_ERR "%s:%d: failed to get UART%d clock\n",
 					__func__, __LINE__, i);
-		else {
-			clk_enable(uart_clk);
-			p->uartclk = clk_get_rate(uart_clk);
-			davinci_serial_reset(p);
+			continue;
 		}
+
+		clk_enable(uart_clk);
+		p->uartclk = clk_get_rate(uart_clk);
+
+		if (!p->membase && p->mapbase) {
+			p->membase = ioremap(p->mapbase, SZ_4K);
+
+			if (p->membase)
+				p->flags &= ~UPF_IOREMAP;
+			else
+				pr_err("uart regs ioremap failed\n");
+		}
+
+		if (p->membase)
+			davinci_serial_reset(p);
 	}
 
 	return platform_device_register(soc_info->serial_dev);
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:23 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:23 -0700
Subject: [PATCH 32/34] Davinci: serial - conditional reset via pwremu
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-33-git-send-email-khilman@deeprootsystems.com>

From: Cyril Chemparathy <cyril at ti.com>

With this patch, AR7 type uart ports are not reset via pwremu registers.  This
allows davinci_serial_init() reuse on tnetv107x soc.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/serial.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 81af42c..1875740 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -107,7 +107,7 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
 				pr_err("uart regs ioremap failed\n");
 		}
 
-		if (p->membase)
+		if (p->membase && p->type != PORT_AR7)
 			davinci_serial_reset(p);
 	}
 
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:24 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:24 -0700
Subject: [PATCH 33/34] davinci: edma: use a more intuitive name for edma_info
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-34-git-send-email-khilman@deeprootsystems.com>

From: Sekhar Nori <nsekhar at ti.com>

'edma_info' structure inside the edma driver represents
a single instance of edma channel controller. Call it
'edma_cc' instead. This also avoids readers confusing
it with an instance of edma_soc_info structre which
carries the platform data for a single channel controller
instance.

Signed-off-by: Sekhar Nori <nsekhar at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/dma.c |  158 +++++++++++++++++++++----------------------
 1 files changed, 77 insertions(+), 81 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 0bf290b..b705089 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -243,7 +243,7 @@ struct edma {
 	} intr_data[EDMA_MAX_DMACH];
 };
 
-static struct edma *edma_info[EDMA_MAX_CC];
+static struct edma *edma_cc[EDMA_MAX_CC];
 static int arch_num_cc;
 
 /* dummy param set used to (re)initialize parameter RAM slots */
@@ -261,7 +261,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
 
 	/* default to low priority queue */
 	if (queue_no == EVENTQ_DEFAULT)
-		queue_no = edma_info[ctlr]->default_queue;
+		queue_no = edma_cc[ctlr]->default_queue;
 
 	queue_no &= 7;
 	edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
@@ -315,8 +315,8 @@ setup_dma_interrupt(unsigned lch,
 				(1 << (lch & 0x1f)));
 	}
 
-	edma_info[ctlr]->intr_data[lch].callback = callback;
-	edma_info[ctlr]->intr_data[lch].data = data;
+	edma_cc[ctlr]->intr_data[lch].callback = callback;
+	edma_cc[ctlr]->intr_data[lch].data = data;
 
 	if (callback) {
 		edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
@@ -328,11 +328,10 @@ setup_dma_interrupt(unsigned lch,
 
 static int irq2ctlr(int irq)
 {
-	if (irq >= edma_info[0]->irq_res_start &&
-		irq <= edma_info[0]->irq_res_end)
+	if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
 		return 0;
-	else if (irq >= edma_info[1]->irq_res_start &&
-		irq <= edma_info[1]->irq_res_end)
+	else if (irq >= edma_cc[1]->irq_res_start &&
+		irq <= edma_cc[1]->irq_res_end)
 		return 1;
 
 	return -1;
@@ -377,10 +376,10 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 				/* Clear the corresponding IPR bits */
 				edma_shadow0_write_array(ctlr, SH_ICR, j,
 							(1 << i));
-				if (edma_info[ctlr]->intr_data[k].callback) {
-					edma_info[ctlr]->intr_data[k].callback(
+				if (edma_cc[ctlr]->intr_data[k].callback) {
+					edma_cc[ctlr]->intr_data[k].callback(
 						k, DMA_COMPLETE,
-						edma_info[ctlr]->intr_data[k].
+						edma_cc[ctlr]->intr_data[k].
 						data);
 				}
 			}
@@ -433,12 +432,12 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 					/* Clear any SER */
 					edma_shadow0_write_array(ctlr, SH_SECR,
 								j, (1 << i));
-					if (edma_info[ctlr]->intr_data[k].
+					if (edma_cc[ctlr]->intr_data[k].
 								callback) {
-						edma_info[ctlr]->intr_data[k].
+						edma_cc[ctlr]->intr_data[k].
 						callback(k,
 						DMA_CC_ERROR,
-						edma_info[ctlr]->intr_data
+						edma_cc[ctlr]->intr_data
 						[k].data);
 					}
 				}
@@ -514,9 +513,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
 	int stop_slot = start_slot;
 	DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
 
-	for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) {
+	for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
 		j = EDMA_CHAN_SLOT(i);
-		if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) {
+		if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
 			/* Record our current beginning slot */
 			if (count == num_slots)
 				stop_slot = i;
@@ -543,12 +542,12 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
 	 * of contiguous parameter RAM slots but do not find the exact number
 	 * requested as we may reach the total number of parameter RAM slots
 	 */
-	if (i == edma_info[ctlr]->num_slots)
+	if (i == edma_cc[ctlr]->num_slots)
 		stop_slot = i;
 
 	for (j = start_slot; j < stop_slot; j++)
 		if (test_bit(j, tmp_inuse))
-			clear_bit(j, edma_info[ctlr]->edma_inuse);
+			clear_bit(j, edma_cc[ctlr]->edma_inuse);
 
 	if (count)
 		return -EBUSY;
@@ -570,7 +569,7 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
 				(int)pdev->resource[i].start >= 0) {
 			ctlr = EDMA_CTLR(pdev->resource[i].start);
 			clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
-					edma_info[ctlr]->edma_unused);
+					edma_cc[ctlr]->edma_unused);
 		}
 	}
 
@@ -644,14 +643,13 @@ int edma_alloc_channel(int channel,
 		for (i = 0; i < arch_num_cc; i++) {
 			channel = 0;
 			for (;;) {
-				channel = find_next_bit(edma_info[i]->
-						edma_unused,
-						edma_info[i]->num_channels,
+				channel = find_next_bit(edma_cc[i]->edma_unused,
+						edma_cc[i]->num_channels,
 						channel);
-				if (channel == edma_info[i]->num_channels)
+				if (channel == edma_cc[i]->num_channels)
 					break;
 				if (!test_and_set_bit(channel,
-						edma_info[i]->edma_inuse)) {
+						edma_cc[i]->edma_inuse)) {
 					done = 1;
 					ctlr = i;
 					break;
@@ -663,9 +661,9 @@ int edma_alloc_channel(int channel,
 		}
 		if (!done)
 			return -ENOMEM;
-	} else if (channel >= edma_info[ctlr]->num_channels) {
+	} else if (channel >= edma_cc[ctlr]->num_channels) {
 		return -EINVAL;
-	} else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) {
+	} else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
 		return -EBUSY;
 	}
 
@@ -706,7 +704,7 @@ void edma_free_channel(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel >= edma_info[ctlr]->num_channels)
+	if (channel >= edma_cc[ctlr]->num_channels)
 		return;
 
 	setup_dma_interrupt(channel, NULL, NULL);
@@ -714,7 +712,7 @@ void edma_free_channel(unsigned channel)
 
 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
 			&dummy_paramset, PARM_SIZE);
-	clear_bit(channel, edma_info[ctlr]->edma_inuse);
+	clear_bit(channel, edma_cc[ctlr]->edma_inuse);
 }
 EXPORT_SYMBOL(edma_free_channel);
 
@@ -738,20 +736,19 @@ int edma_alloc_slot(unsigned ctlr, int slot)
 		slot = EDMA_CHAN_SLOT(slot);
 
 	if (slot < 0) {
-		slot = edma_info[ctlr]->num_channels;
+		slot = edma_cc[ctlr]->num_channels;
 		for (;;) {
-			slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse,
-					edma_info[ctlr]->num_slots, slot);
-			if (slot == edma_info[ctlr]->num_slots)
+			slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
+					edma_cc[ctlr]->num_slots, slot);
+			if (slot == edma_cc[ctlr]->num_slots)
 				return -ENOMEM;
-			if (!test_and_set_bit(slot,
-						edma_info[ctlr]->edma_inuse))
+			if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
 				break;
 		}
-	} else if (slot < edma_info[ctlr]->num_channels ||
-			slot >= edma_info[ctlr]->num_slots) {
+	} else if (slot < edma_cc[ctlr]->num_channels ||
+			slot >= edma_cc[ctlr]->num_slots) {
 		return -EINVAL;
-	} else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) {
+	} else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
 		return -EBUSY;
 	}
 
@@ -777,13 +774,13 @@ void edma_free_slot(unsigned slot)
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_channels ||
-		slot >= edma_info[ctlr]->num_slots)
+	if (slot < edma_cc[ctlr]->num_channels ||
+		slot >= edma_cc[ctlr]->num_slots)
 		return;
 
 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
 			&dummy_paramset, PARM_SIZE);
-	clear_bit(slot, edma_info[ctlr]->edma_inuse);
+	clear_bit(slot, edma_cc[ctlr]->edma_inuse);
 }
 EXPORT_SYMBOL(edma_free_slot);
 
@@ -821,8 +818,8 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
 	 * of slots
 	 */
 	if ((id != EDMA_CONT_PARAMS_ANY) &&
-		(slot < edma_info[ctlr]->num_channels ||
-		slot >= edma_info[ctlr]->num_slots))
+		(slot < edma_cc[ctlr]->num_channels ||
+		slot >= edma_cc[ctlr]->num_slots))
 		return -EINVAL;
 
 	/*
@@ -831,13 +828,13 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
 	 * channels
 	 */
 	if (count < 1 || count >
-		(edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels))
+		(edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
 		return -EINVAL;
 
 	switch (id) {
 	case EDMA_CONT_PARAMS_ANY:
 		return reserve_contiguous_slots(ctlr, id, count,
-						 edma_info[ctlr]->num_channels);
+						 edma_cc[ctlr]->num_channels);
 	case EDMA_CONT_PARAMS_FIXED_EXACT:
 	case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
 		return reserve_contiguous_slots(ctlr, id, count, slot);
@@ -869,8 +866,8 @@ int edma_free_cont_slots(unsigned slot, int count)
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_channels ||
-		slot >= edma_info[ctlr]->num_slots ||
+	if (slot < edma_cc[ctlr]->num_channels ||
+		slot >= edma_cc[ctlr]->num_slots ||
 		count < 1)
 		return -EINVAL;
 
@@ -880,7 +877,7 @@ int edma_free_cont_slots(unsigned slot, int count)
 
 		memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
 			&dummy_paramset, PARM_SIZE);
-		clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse);
+		clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
 	}
 
 	return 0;
@@ -910,7 +907,7 @@ void edma_set_src(unsigned slot, dma_addr_t src_port,
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_slots) {
+	if (slot < edma_cc[ctlr]->num_slots) {
 		unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
 
 		if (mode) {
@@ -948,7 +945,7 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port,
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_slots) {
+	if (slot < edma_cc[ctlr]->num_slots) {
 		unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
 
 		if (mode) {
@@ -1008,7 +1005,7 @@ void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_slots) {
+	if (slot < edma_cc[ctlr]->num_slots) {
 		edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
 				0xffff0000, src_bidx);
 		edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
@@ -1034,7 +1031,7 @@ void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_slots) {
+	if (slot < edma_cc[ctlr]->num_slots) {
 		edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
 				0x0000ffff, dest_bidx << 16);
 		edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
@@ -1081,7 +1078,7 @@ void edma_set_transfer_params(unsigned slot,
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_info[ctlr]->num_slots) {
+	if (slot < edma_cc[ctlr]->num_slots) {
 		edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
 				0x0000ffff, bcnt_rld << 16);
 		if (sync_mode == ASYNC)
@@ -1111,9 +1108,9 @@ void edma_link(unsigned from, unsigned to)
 	ctlr_to = EDMA_CTLR(to);
 	to = EDMA_CHAN_SLOT(to);
 
-	if (from >= edma_info[ctlr_from]->num_slots)
+	if (from >= edma_cc[ctlr_from]->num_slots)
 		return;
-	if (to >= edma_info[ctlr_to]->num_slots)
+	if (to >= edma_cc[ctlr_to]->num_slots)
 		return;
 	edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
 				PARM_OFFSET(to));
@@ -1134,7 +1131,7 @@ void edma_unlink(unsigned from)
 	ctlr = EDMA_CTLR(from);
 	from = EDMA_CHAN_SLOT(from);
 
-	if (from >= edma_info[ctlr]->num_slots)
+	if (from >= edma_cc[ctlr]->num_slots)
 		return;
 	edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
 }
@@ -1161,7 +1158,7 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param)
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot >= edma_info[ctlr]->num_slots)
+	if (slot >= edma_cc[ctlr]->num_slots)
 		return;
 	memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
 			PARM_SIZE);
@@ -1183,7 +1180,7 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param)
 	ctlr = EDMA_CTLR(slot);
 	slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot >= edma_info[ctlr]->num_slots)
+	if (slot >= edma_cc[ctlr]->num_slots)
 		return;
 	memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
 			PARM_SIZE);
@@ -1208,7 +1205,7 @@ void edma_pause(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_info[ctlr]->num_channels) {
+	if (channel < edma_cc[ctlr]->num_channels) {
 		unsigned int mask = (1 << (channel & 0x1f));
 
 		edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
@@ -1229,7 +1226,7 @@ void edma_resume(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_info[ctlr]->num_channels) {
+	if (channel < edma_cc[ctlr]->num_channels) {
 		unsigned int mask = (1 << (channel & 0x1f));
 
 		edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
@@ -1255,12 +1252,12 @@ int edma_start(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_info[ctlr]->num_channels) {
+	if (channel < edma_cc[ctlr]->num_channels) {
 		int j = channel >> 5;
 		unsigned int mask = (1 << (channel & 0x1f));
 
 		/* EDMA channels without event association */
-		if (test_bit(channel, edma_info[ctlr]->edma_unused)) {
+		if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
 			pr_debug("EDMA: ESR%d %08x\n", j,
 				edma_shadow0_read_array(ctlr, SH_ESR, j));
 			edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
@@ -1301,7 +1298,7 @@ void edma_stop(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_info[ctlr]->num_channels) {
+	if (channel < edma_cc[ctlr]->num_channels) {
 		int j = channel >> 5;
 		unsigned int mask = (1 << (channel & 0x1f));
 
@@ -1340,7 +1337,7 @@ void edma_clean_channel(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_info[ctlr]->num_channels) {
+	if (channel < edma_cc[ctlr]->num_channels) {
 		int j = (channel >> 5);
 		unsigned int mask = 1 << (channel & 0x1f);
 
@@ -1368,7 +1365,7 @@ void edma_clear_event(unsigned channel)
 	ctlr = EDMA_CTLR(channel);
 	channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel >= edma_info[ctlr]->num_channels)
+	if (channel >= edma_cc[ctlr]->num_channels)
 		return;
 	if (channel < 32)
 		edma_write(ctlr, EDMA_ECR, 1 << channel);
@@ -1423,38 +1420,37 @@ static int __init edma_probe(struct platform_device *pdev)
 			goto fail1;
 		}
 
-		edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
-		if (!edma_info[j]) {
+		edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
+		if (!edma_cc[j]) {
 			status = -ENOMEM;
 			goto fail1;
 		}
-		memset(edma_info[j], 0, sizeof(struct edma));
+		memset(edma_cc[j], 0, sizeof(struct edma));
 
-		edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel,
+		edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel,
 							EDMA_MAX_DMACH);
-		edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot,
+		edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot,
 							EDMA_MAX_PARAMENTRY);
-		edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc,
-							EDMA_MAX_CC);
+		edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC);
 
-		edma_info[j]->default_queue = info[j].default_queue;
-		if (!edma_info[j]->default_queue)
-			edma_info[j]->default_queue = EVENTQ_1;
+		edma_cc[j]->default_queue = info[j].default_queue;
+		if (!edma_cc[j]->default_queue)
+			edma_cc[j]->default_queue = EVENTQ_1;
 
 		dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
 			edmacc_regs_base[j]);
 
-		for (i = 0; i < edma_info[j]->num_slots; i++)
+		for (i = 0; i < edma_cc[j]->num_slots; i++)
 			memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
 					&dummy_paramset, PARM_SIZE);
 
 		/* Mark all channels as unused */
-		memset(edma_info[j]->edma_unused, 0xff,
-			sizeof(edma_info[j]->edma_unused));
+		memset(edma_cc[j]->edma_unused, 0xff,
+			sizeof(edma_cc[j]->edma_unused));
 
 		sprintf(irq_name, "edma%d", j);
 		irq[j] = platform_get_irq_byname(pdev, irq_name);
-		edma_info[j]->irq_res_start = irq[j];
+		edma_cc[j]->irq_res_start = irq[j];
 		status = request_irq(irq[j], dma_irq_handler, 0, "edma",
 					&pdev->dev);
 		if (status < 0) {
@@ -1465,7 +1461,7 @@ static int __init edma_probe(struct platform_device *pdev)
 
 		sprintf(irq_name, "edma%d_err", j);
 		err_irq[j] = platform_get_irq_byname(pdev, irq_name);
-		edma_info[j]->irq_res_end = err_irq[j];
+		edma_cc[j]->irq_res_end = err_irq[j];
 		status = request_irq(err_irq[j], dma_ccerr_handler, 0,
 					"edma_error", &pdev->dev);
 		if (status < 0) {
@@ -1478,7 +1474,7 @@ static int __init edma_probe(struct platform_device *pdev)
 		 * specified. This way, long transfers on the low priority queue
 		 * started by the codec engine will not cause audio defects.
 		 */
-		for (i = 0; i < edma_info[j]->num_channels; i++)
+		for (i = 0; i < edma_cc[j]->num_channels; i++)
 			map_dmach_queue(j, i, EVENTQ_1);
 
 		queue_tc_mapping = info[j].queue_tc_mapping;
@@ -1541,7 +1537,7 @@ fail1:
 			release_mem_region(r[i]->start, len[i]);
 		if (edmacc_regs_base[i])
 			iounmap(edmacc_regs_base[i]);
-		kfree(edma_info[i]);
+		kfree(edma_cc[i]);
 	}
 	return status;
 }
-- 
1.7.0.2


From khilman at deeprootsystems.com  Thu May  6 18:24:25 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu,  6 May 2010 16:24:25 -0700
Subject: [PATCH 34/34] davinci: edma: fix coding style issue related to usage
	of braces
In-Reply-To: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1273188265-12782-35-git-send-email-khilman@deeprootsystems.com>

From: Sekhar Nori <nsekhar at ti.com>

In the edma driver, there are couple of instances where braces
are used for a single statement 'if' construct.

There are other instances where 'else' part of the if-else construct
does not use braces even if the 'if' part is a multi-line statement.

This patch fixes both.

Signed-off-by: Sekhar Nori <nsekhar at ti.com>
Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-davinci/dma.c |   15 +++++++--------
 1 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index b705089..cc5fcda 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -310,10 +310,9 @@ setup_dma_interrupt(unsigned lch,
 	ctlr = EDMA_CTLR(lch);
 	lch = EDMA_CHAN_SLOT(lch);
 
-	if (!callback) {
+	if (!callback)
 		edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
 				(1 << (lch & 0x1f)));
-	}
 
 	edma_cc[ctlr]->intr_data[lch].callback = callback;
 	edma_cc[ctlr]->intr_data[lch].data = data;
@@ -376,12 +375,11 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 				/* Clear the corresponding IPR bits */
 				edma_shadow0_write_array(ctlr, SH_ICR, j,
 							(1 << i));
-				if (edma_cc[ctlr]->intr_data[k].callback) {
+				if (edma_cc[ctlr]->intr_data[k].callback)
 					edma_cc[ctlr]->intr_data[k].callback(
 						k, DMA_COMPLETE,
 						edma_cc[ctlr]->intr_data[k].
 						data);
-				}
 			}
 		}
 		cnt++;
@@ -473,9 +471,8 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 		if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
 		    && (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
 		    && (edma_read(ctlr, EDMA_QEMR) == 0)
-		    && (edma_read(ctlr, EDMA_CCERR) == 0)) {
+		    && (edma_read(ctlr, EDMA_CCERR) == 0))
 			break;
-		}
 		cnt++;
 		if (cnt > 10)
 			break;
@@ -531,8 +528,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
 			if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
 				stop_slot = i;
 				break;
-			} else
+			} else {
 				count = num_slots;
+			}
 		}
 	}
 
@@ -1402,8 +1400,9 @@ static int __init edma_probe(struct platform_device *pdev)
 				break;
 			else
 				return -ENODEV;
-		} else
+		} else {
 			found = 1;
+		}
 
 		len[j] = resource_size(r[j]);
 
-- 
1.7.0.2


From nsekhar at ti.com  Fri May  7 00:34:05 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Fri, 7 May 2010 11:04:05 +0530
Subject: [PATCH 3/5] davinci: edma: fix coding style issues related to
	indentation
In-Reply-To: <877hngoefz.fsf@deeprootsystems.com>
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
	<1272962499-18932-3-git-send-email-nsekhar@ti.com>
	<1272962499-18932-4-git-send-email-nsekhar@ti.com>
	<877hngoefz.fsf@deeprootsystems.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6DB7BE9@dbde02.ent.ti.com>

On Fri, May 07, 2010 at 03:55:36, Kevin Hilman wrote:
> Sekhar Nori <nsekhar at ti.com> writes:
>
> > In the edma driver some if statememnts are broken up such that
> > the condition code is at the same indentation level as the
> > statement block. This makes reading it particularly difficult.
> >
> > This patch fixes that issue.
> >
> > Signed-off-by: Sekhar Nori <nsekhar at ti.com>
>
> Hmm, I'm with Sergei on this one...
>
> > ---
> >  arch/arm/mach-davinci/dma.c |   26 +++++++++++++-------------
> >  1 files changed, 13 insertions(+), 13 deletions(-)
> >
> > diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
> > index cc5fcda..2734de9 100644
> > --- a/arch/arm/mach-davinci/dma.c
> > +++ b/arch/arm/mach-davinci/dma.c
> > @@ -330,7 +330,7 @@ static int irq2ctlr(int irq)
> >     if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
> >             return 0;
> >     else if (irq >= edma_cc[1]->irq_res_start &&
> > -           irq <= edma_cc[1]->irq_res_end)
> > +                           irq <= edma_cc[1]->irq_res_end)
>
> I much prefer the former style.  IMO, all that's needed here is adding
> one space on the 2nd line so both 'irq's align.
>
> In Emacs with (c-set-style "linux"), just hitting TAB to get
> indentation will get you this style, without having to worry about
> tabs/spaces etc.

Hmm, I thought using spaces for indentation was expressly disallowed
in Documentation/CodingStyle. From Chapter 1:

"
Outside of comments, documentation and except in Kconfig, spaces are never
used for indentation, and the above example is deliberately broken.
"

Am I misinterpreting something?

Thanks,
Sekhar


From nsekhar at ti.com  Fri May  7 00:36:11 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Fri, 7 May 2010 11:06:11 +0530
Subject: [PATCH 4/5] davinci: edma: fix coding style issues related to
	long lines
In-Reply-To: <87zl0cmzs2.fsf@deeprootsystems.com>
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
	<1272962499-18932-3-git-send-email-nsekhar@ti.com>
	<1272962499-18932-4-git-send-email-nsekhar@ti.com>
	<1272962499-18932-5-git-send-email-nsekhar@ti.com>
	<87zl0cmzs2.fsf@deeprootsystems.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6DB7BF2@dbde02.ent.ti.com>

On Fri, May 07, 2010 at 03:57:41, Kevin Hilman wrote:
> Sekhar Nori <nsekhar at ti.com> writes:
>
> > In the edma driver, some lines are broken up at really
> > odd places to meet the 80 chars per line rule. This make
> > reading those parts particularly difficult.
> >
> > This patch fixes that by creating a few lines over 80
> > characters, but I feel it still improves readability over
> > what is existing currently.
>
> This version is more readable (barring similar alignmen comments from
> previous patch) but...  this code really needs some subroutines
> (inlines?) to make it so that there aren't lines > 80 characters.
>
> That would solve all the problems, although requiring a little more
> work on your part.

True, and I had half-seen this comment coming :) Will rework.

Thanks,
Sekhar


From Jon.Povey at racelogic.co.uk  Fri May  7 03:24:19 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Fri, 7 May 2010 09:24:19 +0100
Subject: [PATCH] USB: musb: silence warning about unused flags
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08DE6D1408@Cloud.RL.local>

My first attempt at a kernel patch. Mostly I am interested in feedback about if my patch posting style is right, if this is the right way to deal with this kind of warning, and if this kind of tiny patch is welcomed.

---
 drivers/usb/musb/cppi_dma.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
index 59dc3d3..428ca1b 100644
--- a/drivers/usb/musb/cppi_dma.c
+++ b/drivers/usb/musb/cppi_dma.c
@@ -1155,7 +1155,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
        struct musb_hw_ep       *hw_ep = NULL;
        u32                     rx, tx;
        int                     i, index;
-       unsigned long           flags;
+       unsigned long           flags = 0;

        cppi = container_of(musb->dma_controller, struct cppi, controller);
        if (cppi->irq)
--
1.6.3.3

Thanks,

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network



From nick.thompson at ge.com  Fri May  7 03:25:49 2010
From: nick.thompson at ge.com (Nick Thompson)
Date: Fri, 07 May 2010 09:25:49 +0100
Subject: Linux patch for CHIPINT Errata in davinci SoC's?
Message-ID: <4BE3CE8D.3030202@ge.com>

I'm developing on the da830 and am just about to try an figure out
a way to deal with Advisory 1.1.13 on that device:

"A Single CHIPINTn Interrupt Event Will Register Multiple Times in
the DSP Event Combiner Module (ECM)"

Although that description implies a problem on the DSP side, I
think this also causes a problem on the ARM AINTC as well. da850
errata does mention this more explicitly in Advisory 2.0.12:

"A Single CHIPINTn Interrupt Event Can Register Multiple Times in
the AINTC"

That advisory gives a couple of workarounds which I think could
work on da830 as well.

So, my query: Is there a proposed Linux patch for these issues for
all the effected platforms? Is this the real reason I'm getting
two-for-one interrupts from the CHIPSIG[0] DSP->ARM signal on da830?

Thanks,
Nick.

From nsekhar at ti.com  Fri May  7 03:44:34 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Fri, 7 May 2010 14:14:34 +0530
Subject: [PATCH] USB: musb: silence warning about unused flags
In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE08DE6D1408@Cloud.RL.local>
References: <70E876B0EA86DD4BAF101844BC814DFE08DE6D1408@Cloud.RL.local>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6DB7DE6@dbde02.ent.ti.com>

Hello,

On Fri, May 07, 2010 at 13:54:19, Jon Povey wrote:
> My first attempt at a kernel patch.

Welcome! But, this text will make it to git log which isn't
interesting to someone who looks at it two years later. In
next version this should be replaced with some actual patch
description.

Any text that should not go into the git log should be placed
below the ---

> Mostly I am interested in feedback about if my patch posting style is right,

I noticed that your description text has more than 80 character lines.
That makes for an ugly looking git log and is difficult to read on
many e-mail clients.

> if this is the right way to deal with this kind of warning, and if this kind of tiny
> patch is welcomed.

Sure, warnings are potential bugs.

A log of the exact warning would be good. Also the patch
will eventually need to be sent to linux-usb mailing list
although sending such patches to this list for a pre-review
shouldn't be harmful.

>
> ---
>  drivers/usb/musb/cppi_dma.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
> index 59dc3d3..428ca1b 100644
> --- a/drivers/usb/musb/cppi_dma.c
> +++ b/drivers/usb/musb/cppi_dma.c
> @@ -1155,7 +1155,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
>         struct musb_hw_ep       *hw_ep = NULL;
>         u32                     rx, tx;
>         int                     i, index;
> -       unsigned long           flags;
> +       unsigned long           flags = 0;

In case this is not really a bug you can also use
uninitialized_var() to suppress the warning.

Thanks,
Sekhar


From Jon.Povey at racelogic.co.uk  Fri May  7 04:09:08 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Fri, 7 May 2010 10:09:08 +0100
Subject: [PATCH v2] USB: musb: suppress warning about unused flags
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08DE6D1432@Cloud.RL.local>


Wrap flags with uninitialized_var() to suppress unhelpful warning.
---

Patch take 2.. Fixes this warning:

  CC      drivers/usb/musb/cppi_dma.o
drivers/usb/musb/cppi_dma.c: In function 'cppi_interrupt':
drivers/usb/musb/cppi_dma.c:1158: warning: 'flags' may be used uninitialized in this function

Feedback welcome again.. Also I'm not subscribed to linux-usb, is it appropriate to cross-post there without being subscribed?

And is it OK to ramble away in this part of the patch mail?

Thanks..

 drivers/usb/musb/cppi_dma.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
index 59dc3d3..e3753ba 100644
--- a/drivers/usb/musb/cppi_dma.c
+++ b/drivers/usb/musb/cppi_dma.c
@@ -1155,7 +1155,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
        struct musb_hw_ep       *hw_ep = NULL;
        u32                     rx, tx;
        int                     i, index;
-       unsigned long           flags;
+       unsigned long           uninitialized_var(flags);

        cppi = container_of(musb->dma_controller, struct cppi, controller);
        if (cppi->irq)
--
1.6.3.3


--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network



From sshtylyov at mvista.com  Fri May  7 04:27:46 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 07 May 2010 13:27:46 +0400
Subject: [PATCH v2] USB: musb: suppress warning about unused flags
In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE08DE6D1432@Cloud.RL.local>
References: <70E876B0EA86DD4BAF101844BC814DFE08DE6D1432@Cloud.RL.local>
Message-ID: <4BE3DD12.5000501@mvista.com>

Hello.

Jon Povey wrote:

> Wrap flags with uninitialized_var() to suppress unhelpful warning.
> ---
>
> Patch take 2.. Fixes this warning:
>
>   CC      drivers/usb/musb/cppi_dma.o
> drivers/usb/musb/cppi_dma.c: In function 'cppi_interrupt':
> drivers/usb/musb/cppi_dma.c:1158: warning: 'flags' may be used uninitialized in this function
>   

   The warning should probably have been cited before the --- tearline.

> Feedback welcome again..

   The patch looks OK

>  Also I'm not subscribed to linux-usb, is it appropriate to cross-post there without being subscribed?
>   

   AFAIK, yes.

> And is it OK to ramble away in this part of the patch mail?
>   

   Yes.

> Thanks..
>
>  drivers/usb/musb/cppi_dma.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
> index 59dc3d3..e3753ba 100644
> --- a/drivers/usb/musb/cppi_dma.c
> +++ b/drivers/usb/musb/cppi_dma.c
> @@ -1155,7 +1155,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
>         struct musb_hw_ep       *hw_ep = NULL;
>         u32                     rx, tx;
>         int                     i, index;
> -       unsigned long           flags;
> +       unsigned long           uninitialized_var(flags);
>
>         cppi = container_of(musb->dma_controller, struct cppi, controller);
>         if (cppi->irq)
> --
> 1.6.3.3
>
>
> --
> Jon Povey
> jon.povey at racelogic.co.uk
>
> Racelogic is a limited company registered in England. Registered number 2743719 .
> Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .
>
> The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network
>   

   What's not OK is this text. However, you probably don't have control 
over its appearance in your mails?

WBR, Sergei


From Jon.Povey at racelogic.co.uk  Fri May  7 04:32:49 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Fri, 7 May 2010 10:32:49 +0100
Subject: [PATCH v2] USB: musb: suppress warning about unused flags
In-Reply-To: <4BE3DD12.5000501@mvista.com>
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08DE6D144B@Cloud.RL.local>

Sergei Shtylyov wrote:
>    The warning should probably have been cited before the ---
> tearline.

OK.

[disclaimer]
>    What's not OK is this text. However, you probably don't have
> control over its appearance in your mails?

Nope :(

Thanks for the feedback. I suppose I'll wait a while for any more comments then repost to both lists.

Lots of drama for a one-line patch, but.. Have to learn somehow. :)

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network



From nsekhar at ti.com  Fri May  7 05:23:54 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Fri, 7 May 2010 15:53:54 +0530
Subject: DM365 audio -- bad PLL setting in tlv320aic3x driver
In-Reply-To: <4BE0E012.1030406@roadrunner.com>
References: <4BE0E012.1030406@roadrunner.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6DB7EEB@dbde02.ent.ti.com>


Hello Jimmy,

On Wed, May 05, 2010 at 08:33:46, Jimmy Blair wrote:
> 44100 Hz audio plays slightly fast on the DM365.
> This is because the tlv320aic3x driver is calculating
> invalid PLL parameters for the WCLK.  The parameters
> it calculates are:
>
> pll_p = 1, pll_r = 1, pll_j = 3, pll_d = 3450
>
> According to the codec datasheet, the value of J
> should be greater than 3.  The datasheet is correct.
> The WCLK signal is unstable, bouncing between 44200 and 44500 Hz.

Are you seeing this on latest kernel? I haven't tested
this, but looking at the code, it looks like this has
been taken care of in the latest kernel:

...
        for (r = 1; r <= 16; r++)
                for (p = 1; p <= 8; p++) {
                        for (j = 4; j <= 55; j++) {

...

                if (j < 4 || j > 11)
                        continue;
...

Thanks,
Sekhar


From cyril at ti.com  Fri May  7 08:28:20 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 07 May 2010 09:28:20 -0400
Subject: [PATCH v2 3/8] Davinci: jtag_id - use ioremap()
In-Reply-To: <87fx24pusu.fsf@deeprootsystems.com>
References: <1272753528-22981-1-git-send-email-cyril@ti.com>	<1272753528-22981-4-git-send-email-cyril@ti.com>
	<87fx24pusu.fsf@deeprootsystems.com>
Message-ID: <4BE41574.20203@ti.com>

Hi Kevin,

[...]
>> This patch replaces the jtag id base info in davinci_soc_info with a physical
>> address which is then ioremap()ed within common code.

[...]
> This one was failing on da8xx...

[...]
>> +	base = ioremap(davinci_soc_info.jtag_id_reg, SZ_4K);
> 
> ...because here you're assuming this value is an absolute physical address...

[...]
> -	.jtag_id_reg		= DA8XX_JTAG_ID_REG,
> +	.jtag_id_reg		= DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,

Ouch, that was pretty dumb. Thanks.

Regards
Cyril.

From khilman at deeprootsystems.com  Fri May  7 09:55:39 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Fri, 07 May 2010 07:55:39 -0700
Subject: [PATCH 3/5] davinci: edma: fix coding style issues related to
	indentation
In-Reply-To: <B85A65D85D7EB246BE421B3FB0FBB59301E6DB7BE9@dbde02.ent.ti.com>
	(Sekhar Nori's message of "Fri\, 7 May 2010 11\:04\:05 +0530")
References: <1272962499-18932-1-git-send-email-nsekhar@ti.com>
	<1272962499-18932-2-git-send-email-nsekhar@ti.com>
	<1272962499-18932-3-git-send-email-nsekhar@ti.com>
	<1272962499-18932-4-git-send-email-nsekhar@ti.com>
	<877hngoefz.fsf@deeprootsystems.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E6DB7BE9@dbde02.ent.ti.com>
Message-ID: <8739y3lq1g.fsf@deeprootsystems.com>

"Nori, Sekhar" <nsekhar at ti.com> writes:

> On Fri, May 07, 2010 at 03:55:36, Kevin Hilman wrote:
>> Sekhar Nori <nsekhar at ti.com> writes:
>>
>> > In the edma driver some if statememnts are broken up such that
>> > the condition code is at the same indentation level as the
>> > statement block. This makes reading it particularly difficult.
>> >
>> > This patch fixes that issue.
>> >
>> > Signed-off-by: Sekhar Nori <nsekhar at ti.com>
>>
>> Hmm, I'm with Sergei on this one...
>>
>> > ---
>> >  arch/arm/mach-davinci/dma.c |   26 +++++++++++++-------------
>> >  1 files changed, 13 insertions(+), 13 deletions(-)
>> >
>> > diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
>> > index cc5fcda..2734de9 100644
>> > --- a/arch/arm/mach-davinci/dma.c
>> > +++ b/arch/arm/mach-davinci/dma.c
>> > @@ -330,7 +330,7 @@ static int irq2ctlr(int irq)
>> >     if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
>> >             return 0;
>> >     else if (irq >= edma_cc[1]->irq_res_start &&
>> > -           irq <= edma_cc[1]->irq_res_end)
>> > +                           irq <= edma_cc[1]->irq_res_end)
>>
>> I much prefer the former style.  IMO, all that's needed here is adding
>> one space on the 2nd line so both 'irq's align.
>>
>> In Emacs with (c-set-style "linux"), just hitting TAB to get
>> indentation will get you this style, without having to worry about
>> tabs/spaces etc.
>
> Hmm, I thought using spaces for indentation was expressly disallowed
> in Documentation/CodingStyle. From Chapter 1:
>
> "
> Outside of comments, documentation and except in Kconfig, spaces are never
> used for indentation, and the above example is deliberately broken.
> "
>
> Am I misinterpreting something?

I've never seen any hard rule on this, but what seems to be the
standard is that TABs are always used for the main indent levels, but
it is common practice to use TABS and optionally some spaces to fine
tune the kinds of vertical alignment we've been discussing in this patch.

I'm a blind user of Emacs' (c-set-style "linux") and so I haven't
thought about this for awhile.  I imagine there is a vim equivalent as
well.

Below is an excerpt from my .emacs that turns on this mode everytime I
open a C file.

Kevin


;; Editing C code
(defun linux-c-mode ()
  "C mode with adjusted defaults for use with the Linux kernel."
  (c-set-style "linux")
  )

(add-hook 'c-mode-hook 'linux-c-mode)

From khilman at deeprootsystems.com  Fri May  7 10:15:33 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Fri, 07 May 2010 08:15:33 -0700
Subject: [PATCH v2] USB: musb: suppress warning about unused flags
In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE08DE6D1432@Cloud.RL.local> (Jon
	Povey's message of "Fri\, 7 May 2010 10\:09\:08 +0100")
References: <70E876B0EA86DD4BAF101844BC814DFE08DE6D1432@Cloud.RL.local>
Message-ID: <878w7vkaju.fsf@deeprootsystems.com>

Jon Povey <Jon.Povey at racelogic.co.uk> writes:

> Wrap flags with uninitialized_var() to suppress unhelpful warning.

missing signoff

> ---
>
> Patch take 2.. Fixes this warning:

After the '---' , it's common to summarize what changed since the
previous version as well, although for one-liners like this, it's not
entirely necessary.

>   CC      drivers/usb/musb/cppi_dma.o
> drivers/usb/musb/cppi_dma.c: In function 'cppi_interrupt':
> drivers/usb/musb/cppi_dma.c:1158: warning: 'flags' may be used uninitialized in this function
>
> Feedback welcome again.. Also I'm not subscribed to linux-usb, is it appropriate to cross-post there without being subscribed?
>
> And is it OK to ramble away in this part of the patch mail?

Yes, this is the ramble-away zone of the patch. :)

Here's a simple 5-step working model for submitting patches in the
future using git each step of the way:

1) create/checkout a branch in your local git, based at davinci git master

  $ git checkout -b my_fix master

2) make your changes and commit your fix to your branch

  $ git add <files/that/changed.c>
  $ git commit --signoff

  Here, in the commit log, create a descriptive changelog of what is
  being done.  Typically a summary of what is changing, but should
  also answer the question "why?"

  The '--signoff' option will add a Signed-off-by line with 
  your name/email.  To tune the values it uses for name and
  email, create a ~/.gitconfig file (see mine below[1])

3) export/format your changes for sending to the mailing list

  $ git format-patch -o tmp master..my_fix

4) visually inspect the patches created in the 'tmp' dir 
   and add some additional comments as needed after the '---' line.

5) send the patches

  $ git-send-email --dry-run --to davinci-linux-open-source at linux.davincidsp.com tmp

  Using '--dry-run' won't actually send the mails, but will give a
  test run so you see what it would do.  When you're ready to send them,
  just remove the --dry-run.
 
For more details on all of the git commands, start with the Git User's
Manual:

   http://www.kernel.org/pub/software/scm/git/docs/user-manual.html

And, thanks for contributing!

Kevin


[1] name/email excerpt from ~/.gitconfig

[user]
	name = Kevin Hilman
	email = khilman at deeprootsystems.com


  




> Thanks..
>
>  drivers/usb/musb/cppi_dma.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
> index 59dc3d3..e3753ba 100644
> --- a/drivers/usb/musb/cppi_dma.c
> +++ b/drivers/usb/musb/cppi_dma.c
> @@ -1155,7 +1155,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
>         struct musb_hw_ep       *hw_ep = NULL;
>         u32                     rx, tx;
>         int                     i, index;
> -       unsigned long           flags;
> +       unsigned long           uninitialized_var(flags);
>
>         cppi = container_of(musb->dma_controller, struct cppi, controller);
>         if (cppi->irq)
> --
> 1.6.3.3
>
>
> --
> Jon Povey
> jon.povey at racelogic.co.uk
>
> Racelogic is a limited company registered in England. Registered number 2743719 .
> Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .
>
> The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network
>
>
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source

From lamiaposta71 at gmail.com  Fri May  7 10:34:09 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Fri, 7 May 2010 17:34:09 +0200
Subject: spi chip select using a gpio
Message-ID: <v2hade1bdc1005070834n5901df50x8b26b9e680b8b3f0@mail.gmail.com>

The patch applies to v2.6.34-rc1, but can be useful also for the actual
HEAD.


diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index cc62b2c..3183568 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -702,12 +702,14 @@ void __init dm365_init_spi0(unsigned chipselect_mask,
        davinci_cfg_reg(DM365_SPI0_SDI);
        davinci_cfg_reg(DM365_SPI0_SDO);

-       /* not all slaves will be wired up */
-       if (chipselect_mask & BIT(0))
-               davinci_cfg_reg(DM365_SPI0_SDENA0);
-       if (chipselect_mask & BIT(1))
-               davinci_cfg_reg(DM365_SPI0_SDENA1);
-
+       if  (!((unsigned long) info->controller_data)) {
+               /* not all slaves will be wired up */
+               if (chipselect_mask & BIT(0))
+                       davinci_cfg_reg(DM365_SPI0_SDENA0);
+               if (chipselect_mask & BIT(1))
+                       davinci_cfg_reg(DM365_SPI0_SDENA1);
+       }
+
        spi_register_board_info(info, len);

        platform_device_register(&dm365_spi0_device);



diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 225ab60..8fef47b 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -28,6 +28,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_bitbang.h>

+#include <mach/gpio.h>
 #include <mach/spi.h>
 #include <mach/edma.h>

@@ -269,19 +270,29 @@ static void davinci_spi_chipselect(struct spi_device
*spi, int value)
        pdata = davinci_spi->pdata;

        /*
-        * Board specific chip select logic decides the polarity and cs
-        * line for the controller
-        */
+       * Board specific chip select logic decides the polarity and cs
+       * line for the controller
+       */
        if (value == BITBANG_CS_INACTIVE) {
-               set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);

-               data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
-               iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
+               if  ((unsigned long) spi->controller_data) {
+                       gpio_set_value(spi->controller_data, !(spi->mode &
SPI_CS_HIGH));
+               } else {
+                       set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);

+                       data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
+                       iowrite32(data1_reg_val, davinci_spi->base +
SPIDAT1);
+               }
+
                while ((ioread32(davinci_spi->base + SPIBUF)
-                                       & SPIBUF_RXEMPTY_MASK) == 0)
+                               & SPIBUF_RXEMPTY_MASK) == 0)
                        cpu_relax();
+       } else {
+               if  ((unsigned long) spi->controller_data) {
+                       gpio_set_value(spi->controller_data, (spi->mode &
SPI_CS_HIGH));
+               }
        }
+
 }

 /**

@@ -439,6 +450,8 @@ static int davinci_spi_setup(struct spi_device *spi)
        davinci_spi = spi_master_get_devdata(spi->master);
        sdev = davinci_spi->bitbang.master->dev.parent;

+
+
        /* if bits per word length is zero then set it default 8 */
        if (!spi->bits_per_word)
                spi->bits_per_word = 8;
-------------- next part --------------
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From cyril at ti.com  Fri May  7 16:06:32 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 17:06:32 -0400
Subject: [PATCH v3 1/8] Davinci: gpio - use ioremap()
In-Reply-To: <1273266399-17164-1-git-send-email-cyril@ti.com>
References: <1273266399-17164-1-git-send-email-cyril@ti.com>
Message-ID: <1273266399-17164-2-git-send-email-cyril@ti.com>

This patch modifies the gpio_base definition in davinci_soc_info to be a
physical address, which is then ioremap()ed by the gpio initialization
function.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v3: return ENOMEM on ioremap failure
v2: fixed raw_write to soc_info->gpio_base 

 arch/arm/mach-davinci/da830.c               |    2 +-
 arch/arm/mach-davinci/da850.c               |    2 +-
 arch/arm/mach-davinci/dm355.c               |    2 +-
 arch/arm/mach-davinci/dm365.c               |    2 +-
 arch/arm/mach-davinci/dm644x.c              |    2 +-
 arch/arm/mach-davinci/dm646x.c              |    2 +-
 arch/arm/mach-davinci/gpio.c                |   18 +++++++++++-------
 arch/arm/mach-davinci/include/mach/common.h |    2 +-
 8 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 83879f8..4f5727f 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1201,7 +1201,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.intc_irq_num		= DA830_N_CP_INTC_IRQ,
 	.timer_info		= &da830_timer_info,
 	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= IO_ADDRESS(DA8XX_GPIO_BASE),
+	.gpio_base		= DA8XX_GPIO_BASE,
 	.gpio_num		= 128,
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
 	.serial_dev		= &da8xx_serial_device,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 2b6dd59..cb7f663 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1086,7 +1086,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.intc_irq_num		= DA850_N_CP_INTC_IRQ,
 	.timer_info		= &da850_timer_info,
 	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= IO_ADDRESS(DA8XX_GPIO_BASE),
+	.gpio_base		= DA8XX_GPIO_BASE,
 	.gpio_num		= 144,
 	.gpio_irq		= IRQ_DA8XX_GPIO0,
 	.serial_dev		= &da8xx_serial_device,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 0c62a68..277041d 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -855,7 +855,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm355_timer_info,
 	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
+	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 104,
 	.gpio_irq		= IRQ_DM355_GPIOBNK0,
 	.serial_dev		= &dm355_serial_device,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index ed76450..ecdbc67 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1060,7 +1060,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm365_timer_info,
 	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
+	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 104,
 	.gpio_irq		= IRQ_DM365_GPIO0,
 	.gpio_unbanked		= 8,	/* really 16 ... skip muxed GPIOs */
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 7f36c22..beb315c 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -746,7 +746,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm644x_timer_info,
 	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
+	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 71,
 	.gpio_irq		= IRQ_GPIOBNK0,
 	.serial_dev		= &dm644x_serial_device,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 8dd0afe..95fc981 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -830,7 +830,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
 	.timer_info		= &dm646x_timer_info,
 	.gpio_type		= GPIO_TYPE_DAVINCI,
-	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
+	.gpio_base		= DAVINCI_GPIO_BASE,
 	.gpio_num		= 43, /* Only 33 usable */
 	.gpio_irq		= IRQ_DM646X_GPIOBNK0,
 	.serial_dev		= &dm646x_serial_device,
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 2efb446..bf0ff58 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -37,22 +37,22 @@ struct davinci_gpio_regs {
 	container_of(chip, struct davinci_gpio_controller, chip)
 
 static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
+static void __iomem *gpio_base;
 
 static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
 {
 	void __iomem *ptr;
-	void __iomem *base = davinci_soc_info.gpio_base;
 
 	if (gpio < 32 * 1)
-		ptr = base + 0x10;
+		ptr = gpio_base + 0x10;
 	else if (gpio < 32 * 2)
-		ptr = base + 0x38;
+		ptr = gpio_base + 0x38;
 	else if (gpio < 32 * 3)
-		ptr = base + 0x60;
+		ptr = gpio_base + 0x60;
 	else if (gpio < 32 * 4)
-		ptr = base + 0x88;
+		ptr = gpio_base + 0x88;
 	else if (gpio < 32 * 5)
-		ptr = base + 0xb0;
+		ptr = gpio_base + 0xb0;
 	else
 		ptr = NULL;
 	return ptr;
@@ -157,6 +157,10 @@ static int __init davinci_gpio_setup(void)
 	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
 		ngpio = DAVINCI_N_GPIO;
 
+	gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
+	if (WARN_ON(!gpio_base))
+		return -ENOMEM;
+
 	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
 		chips[i].chip.label = "DaVinci";
 
@@ -445,7 +449,7 @@ done:
 	/* BINTEN -- per-bank interrupt enable. genirq would also let these
 	 * bits be set/cleared dynamically.
 	 */
-	__raw_writel(binten, soc_info->gpio_base + 0x08);
+	__raw_writel(binten, gpio_base + 0x08);
 
 	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
 
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index a58bd88..2dd2226 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -60,7 +60,7 @@ struct davinci_soc_info {
 	unsigned long			intc_irq_num;
 	struct davinci_timer_info	*timer_info;
 	int				gpio_type;
-	void __iomem			*gpio_base;
+	u32				gpio_base;
 	unsigned			gpio_num;
 	unsigned			gpio_irq;
 	unsigned			gpio_unbanked;
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 16:06:33 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 17:06:33 -0400
Subject: [PATCH v3 2/8] Davinci: da8xx: rtc - use ioremap
In-Reply-To: <1273266399-17164-1-git-send-email-cyril@ti.com>
References: <1273266399-17164-1-git-send-email-cyril@ti.com>
Message-ID: <1273266399-17164-3-git-send-email-cyril@ti.com>

This patch modifies the RTC unlock code to use ioremap() maps instead of
IO_ADDRESS() translation.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v3: return ENOMEM on ioremap failure
v2: unchanged from v1

 arch/arm/mach-davinci/devices-da8xx.c |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 67a6fbc..8cda729 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -584,10 +584,17 @@ static struct platform_device da8xx_rtc_device = {
 int da8xx_register_rtc(void)
 {
 	int ret;
+	void __iomem *base;
+
+	base = ioremap(DA8XX_RTC_BASE, SZ_4K);
+	if (WARN_ON(!base))
+		return -ENOMEM;
 
 	/* Unlock the rtc's registers */
-	__raw_writel(0x83e70b13, IO_ADDRESS(DA8XX_RTC_BASE + 0x6c));
-	__raw_writel(0x95a4f1e0, IO_ADDRESS(DA8XX_RTC_BASE + 0x70));
+	__raw_writel(0x83e70b13, base + 0x6c);
+	__raw_writel(0x95a4f1e0, base + 0x70);
+
+	iounmap(base);
 
 	ret = platform_device_register(&da8xx_rtc_device);
 	if (!ret)
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 16:06:31 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 17:06:31 -0400
Subject: [PATCH v3 0/8] pre-tnetv107x ioremap series
Message-ID: <1273266399-17164-1-git-send-email-cyril@ti.com>

With this patch, various davinci modules (gpio, timer, psc, etc.) now use
ioremap() instead of having virtual addresses passed in via davinci_soc_info.
Based on this cleanup, davinci_ioremap() has been modified to search through
the iotable instead of mapping based on IO_PHYS and IO_VIRT.

Cyril Chemparathy (8):
  Davinci: gpio - use ioremap()
  Davinci: da8xx: rtc - use ioremap
  Davinci: jtag_id - use ioremap()
  Davinci: timer - use ioremap()
  Davinci: psc - use ioremap()
  Davinci: aintc/cpintc - use ioremap()
  Davinci: pinmux - use ioremap()
  Davinci: iotable based ioremap() interception

 arch/arm/mach-davinci/board-da830-evm.c      |   10 +----
 arch/arm/mach-davinci/board-da850-evm.c      |   10 +----
 arch/arm/mach-davinci/board-dm355-evm.c      |    7 +---
 arch/arm/mach-davinci/board-dm355-leopard.c  |    7 +---
 arch/arm/mach-davinci/board-dm365-evm.c      |    7 +---
 arch/arm/mach-davinci/board-dm644x-evm.c     |    7 +---
 arch/arm/mach-davinci/board-dm646x-evm.c     |    9 +---
 arch/arm/mach-davinci/board-neuros-osd2.c    |    7 +---
 arch/arm/mach-davinci/board-sffsdr.c         |    7 +---
 arch/arm/mach-davinci/clock.c                |   14 +++++-
 arch/arm/mach-davinci/common.c               |   54 ++++++++++++++-----------
 arch/arm/mach-davinci/cp_intc.c              |   18 +++++---
 arch/arm/mach-davinci/da830.c                |   26 +++++--------
 arch/arm/mach-davinci/da850.c                |   27 +++++--------
 arch/arm/mach-davinci/devices-da8xx.c        |   11 ++++-
 arch/arm/mach-davinci/devices.c              |    4 +-
 arch/arm/mach-davinci/dm355.c                |   12 ++---
 arch/arm/mach-davinci/dm365.c                |   12 ++---
 arch/arm/mach-davinci/dm644x.c               |   12 ++---
 arch/arm/mach-davinci/dm646x.c               |   12 ++---
 arch/arm/mach-davinci/gpio.c                 |   18 +++++---
 arch/arm/mach-davinci/include/mach/common.h  |   21 +++++++---
 arch/arm/mach-davinci/include/mach/cp_intc.h |    3 +-
 arch/arm/mach-davinci/io.c                   |   20 +++++++--
 arch/arm/mach-davinci/irq.c                  |    7 +++-
 arch/arm/mach-davinci/mux.c                  |   17 ++++++--
 arch/arm/mach-davinci/psc.c                  |    7 ++-
 arch/arm/mach-davinci/time.c                 |   22 +++++++----
 28 files changed, 192 insertions(+), 196 deletions(-)


From cyril at ti.com  Fri May  7 16:06:36 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 17:06:36 -0400
Subject: [PATCH v3 5/8] Davinci: psc - use ioremap()
In-Reply-To: <1273266399-17164-1-git-send-email-cyril@ti.com>
References: <1273266399-17164-1-git-send-email-cyril@ti.com>
Message-ID: <1273266399-17164-6-git-send-email-cyril@ti.com>

This patch modifies the psc and clock control code to use ioremap()ed
registers.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v3: checkpatch fix - white space
v2: bug --> warn

 arch/arm/mach-davinci/clock.c               |   14 +++++++++++---
 arch/arm/mach-davinci/da830.c               |    5 +----
 arch/arm/mach-davinci/da850.c               |    5 +----
 arch/arm/mach-davinci/dm355.c               |    4 +---
 arch/arm/mach-davinci/dm365.c               |    4 +---
 arch/arm/mach-davinci/dm644x.c              |    4 +---
 arch/arm/mach-davinci/dm646x.c              |    4 +---
 arch/arm/mach-davinci/include/mach/common.h |    2 +-
 arch/arm/mach-davinci/psc.c                 |    7 +++++--
 9 files changed, 23 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 868cb76..054c303 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -302,7 +302,6 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
 	struct pll_data *pll = clk->pll_data;
 	unsigned long rate = clk->rate;
 
-	pll->base = IO_ADDRESS(pll->phys_base);
 	ctrl = __raw_readl(pll->base + PLLCTL);
 	rate = pll->input_rate = clk->parent->rate;
 
@@ -458,8 +457,17 @@ int __init davinci_clk_init(struct clk_lookup *clocks)
 				clk->recalc = clk_leafclk_recalc;
 		}
 
-		if (clk->pll_data && !clk->pll_data->div_ratio_mask)
-			clk->pll_data->div_ratio_mask = PLLDIV_RATIO_MASK;
+		if (clk->pll_data) {
+			struct pll_data *pll = clk->pll_data;
+
+			if (!pll->div_ratio_mask)
+				pll->div_ratio_mask = PLLDIV_RATIO_MASK;
+
+			if (pll->phys_base && !pll->base) {
+				pll->base = ioremap(pll->phys_base, SZ_4K);
+				WARN_ON(!pll->base);
+			}
+		}
 
 		if (clk->recalc)
 			clk->rate = clk->recalc(clk);
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 8a2510c..47a7f49 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1127,10 +1127,7 @@ static struct map_desc da830_io_desc[] = {
 	},
 };
 
-static void __iomem *da830_psc_bases[] = {
-	IO_ADDRESS(DA8XX_PSC0_BASE),
-	IO_ADDRESS(DA8XX_PSC1_BASE),
-};
+static u32 da830_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
 
 /* Contents of JTAG ID register used to identify exact cpu type */
 static struct davinci_id da830_ids[] = {
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index ebfa5ca..2a430bb 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -782,10 +782,7 @@ static struct map_desc da850_io_desc[] = {
 	},
 };
 
-static void __iomem *da850_psc_bases[] = {
-	IO_ADDRESS(DA8XX_PSC0_BASE),
-	IO_ADDRESS(DA8XX_PSC1_BASE),
-};
+static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
 
 /* Contents of JTAG ID register used to identify exact cpu type */
 static struct davinci_id da850_ids[] = {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 228b6d1..70a1827 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -783,9 +783,7 @@ static struct davinci_id dm355_ids[] = {
 	},
 };
 
-static void __iomem *dm355_psc_bases[] = {
-	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
-};
+static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 
 /*
  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index b396d58..451a4ef 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1002,9 +1002,7 @@ static struct davinci_id dm365_ids[] = {
 	},
 };
 
-static void __iomem *dm365_psc_bases[] = {
-	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
-};
+static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 
 static struct davinci_timer_info dm365_timer_info = {
 	.timers		= davinci_timer_instance,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 9859567..ee654de 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -674,9 +674,7 @@ static struct davinci_id dm644x_ids[] = {
 	},
 };
 
-static void __iomem *dm644x_psc_bases[] = {
-	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
-};
+static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 
 /*
  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index f9a8cc4..4c98ef0 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -758,9 +758,7 @@ static struct davinci_id dm646x_ids[] = {
 	},
 };
 
-static void __iomem *dm646x_psc_bases[] = {
-	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
-};
+static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 
 /*
  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 2e15464..4c8dfcb 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -49,7 +49,7 @@ struct davinci_soc_info {
 	struct davinci_id		*ids;
 	unsigned long			ids_num;
 	struct clk_lookup		*cpu_clks;
-	void __iomem			**psc_bases;
+	u32				*psc_bases;
 	unsigned long			psc_bases_num;
 	void __iomem			*pinmux_base;
 	const struct mux_config		*pinmux_pins;
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index d7cb438..1b15dbd 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -38,8 +38,9 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
 		return 0;
 	}
 
-	psc_base = soc_info->psc_bases[ctlr];
+	psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
 	mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
+	iounmap(psc_base);
 
 	/* if clocked, state can be "Enable" or "SyncReset" */
 	return mdstat & BIT(12);
@@ -59,7 +60,7 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
 		return;
 	}
 
-	psc_base = soc_info->psc_bases[ctlr];
+	psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
 
 	mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
 	mdctl &= ~MDSTAT_STATE_MASK;
@@ -99,4 +100,6 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
 	do {
 		mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
 	} while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
+
+	iounmap(psc_base);
 }
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 16:06:37 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 17:06:37 -0400
Subject: [PATCH v3 6/8] Davinci: aintc/cpintc - use ioremap()
In-Reply-To: <1273266399-17164-1-git-send-email-cyril@ti.com>
References: <1273266399-17164-1-git-send-email-cyril@ti.com>
Message-ID: <1273266399-17164-7-git-send-email-cyril@ti.com>

This patch implements the following:

 - interrupt initialization uses ioremap() instead of passing a virtual address
   via davinci_soc_info.

 - machine definitions directly point to cp_intc_init() or davinci_irq_init()

 - davinci_intc_type and davinci_intc_base now get initialized in controller
   specific init functions instead of davinci_common_init()

 - minor fix in davinci_irq_init() to use intc_irq_num instead of
   DAVINCI_N_AINTC_IRQ

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v3: map in 8k instead of 4k register space
v2: unchanged from v1

 arch/arm/mach-davinci/board-da830-evm.c      |   10 +---------
 arch/arm/mach-davinci/board-da850-evm.c      |   10 +---------
 arch/arm/mach-davinci/board-dm355-evm.c      |    7 +------
 arch/arm/mach-davinci/board-dm355-leopard.c  |    7 +------
 arch/arm/mach-davinci/board-dm365-evm.c      |    7 +------
 arch/arm/mach-davinci/board-dm644x-evm.c     |    7 +------
 arch/arm/mach-davinci/board-dm646x-evm.c     |    9 ++-------
 arch/arm/mach-davinci/board-neuros-osd2.c    |    7 +------
 arch/arm/mach-davinci/board-sffsdr.c         |    7 +------
 arch/arm/mach-davinci/common.c               |    2 --
 arch/arm/mach-davinci/cp_intc.c              |   18 +++++++++++-------
 arch/arm/mach-davinci/da830.c                |    2 +-
 arch/arm/mach-davinci/da850.c                |    2 +-
 arch/arm/mach-davinci/dm355.c                |    2 +-
 arch/arm/mach-davinci/dm365.c                |    2 +-
 arch/arm/mach-davinci/dm644x.c               |    2 +-
 arch/arm/mach-davinci/dm646x.c               |    2 +-
 arch/arm/mach-davinci/include/mach/common.h  |    3 ++-
 arch/arm/mach-davinci/include/mach/cp_intc.h |    3 +--
 arch/arm/mach-davinci/irq.c                  |    7 ++++++-
 20 files changed, 36 insertions(+), 80 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 8f079d2..212d970 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -561,14 +561,6 @@ static int __init da830_evm_console_init(void)
 console_initcall(da830_evm_console_init);
 #endif
 
-static __init void da830_evm_irq_init(void)
-{
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
-
-	cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ,
-			soc_info->intc_irq_prios, NULL);
-}
-
 static void __init da830_evm_map_io(void)
 {
 	da830_init();
@@ -579,7 +571,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM")
 	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params	= (DA8XX_DDR_BASE + 0x100),
 	.map_io		= da830_evm_map_io,
-	.init_irq	= da830_evm_irq_init,
+	.init_irq	= cp_intc_init,
 	.timer		= &davinci_timer,
 	.init_machine	= da830_evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 6c137e0..abd0493 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -736,14 +736,6 @@ static int __init da850_evm_console_init(void)
 console_initcall(da850_evm_console_init);
 #endif
 
-static __init void da850_evm_irq_init(void)
-{
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
-
-	cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ,
-			soc_info->intc_irq_prios, NULL);
-}
-
 static void __init da850_evm_map_io(void)
 {
 	da850_init();
@@ -754,7 +746,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM")
 	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params	= (DA8XX_DDR_BASE + 0x100),
 	.map_io		= da850_evm_map_io,
-	.init_irq	= da850_evm_irq_init,
+	.init_irq	= cp_intc_init,
 	.timer		= &davinci_timer,
 	.init_machine	= da850_evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index a0ad7d9..a319101 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -350,17 +350,12 @@ static __init void dm355_evm_init(void)
 	dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data);
 }
 
-static __init void dm355_evm_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (0x80000100),
 	.map_io	      = dm355_evm_map_io,
-	.init_irq     = dm355_evm_irq_init,
+	.init_irq     = davinci_irq_init,
 	.timer	      = &davinci_timer,
 	.init_machine = dm355_evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index c3d5a70..f1d8132 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -269,17 +269,12 @@ static __init void dm355_leopard_init(void)
 			ARRAY_SIZE(dm355_leopard_spi_info));
 }
 
-static __init void dm355_leopard_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (0x80000100),
 	.map_io	      = dm355_leopard_map_io,
-	.init_irq     = dm355_leopard_irq_init,
+	.init_irq     = davinci_irq_init,
 	.timer	      = &davinci_timer,
 	.init_machine = dm355_leopard_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index b98b35c..98814e6 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -608,17 +608,12 @@ static __init void dm365_evm_init(void)
 			ARRAY_SIZE(dm365_evm_spi_info));
 }
 
-static __init void dm365_evm_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
 	.phys_io	= IO_PHYS,
 	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params	= (0x80000100),
 	.map_io		= dm365_evm_map_io,
-	.init_irq	= dm365_evm_irq_init,
+	.init_irq	= davinci_irq_init,
 	.timer		= &davinci_timer,
 	.init_machine	= dm365_evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 73c0b04..34c8b41 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -704,18 +704,13 @@ static __init void davinci_evm_init(void)
 
 }
 
-static __init void davinci_evm_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
 	/* Maintainer: MontaVista Software <source at mvista.com> */
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (DAVINCI_DDR_BASE + 0x100),
 	.map_io	      = davinci_evm_map_io,
-	.init_irq     = davinci_evm_irq_init,
+	.init_irq     = davinci_irq_init,
 	.timer	      = &davinci_timer,
 	.init_machine = davinci_evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index e2ac06f..6d88893 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -739,11 +739,6 @@ static __init void evm_init(void)
 	soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
 }
 
-static __init void davinci_dm646x_evm_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 #define DM646X_EVM_REF_FREQ		27000000
 #define DM6467T_EVM_REF_FREQ		33000000
 
@@ -760,7 +755,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (0x80000100),
 	.map_io       = davinci_map_io,
-	.init_irq     = davinci_dm646x_evm_irq_init,
+	.init_irq     = davinci_irq_init,
 	.timer        = &davinci_timer,
 	.init_machine = evm_init,
 MACHINE_END
@@ -770,7 +765,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (0x80000100),
 	.map_io       = davinci_map_io,
-	.init_irq     = davinci_dm646x_evm_irq_init,
+	.init_irq     = davinci_irq_init,
 	.timer        = &davinci_timer,
 	.init_machine = evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 875770c..4c30e92 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -273,18 +273,13 @@ static __init void davinci_ntosd2_init(void)
 	davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
 }
 
-static __init void davinci_ntosd2_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
 	/* Maintainer: Neuros Technologies <neuros at groups.google.com> */
 	.phys_io	= IO_PHYS,
 	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params	= (DAVINCI_DDR_BASE + 0x100),
 	.map_io		 = davinci_ntosd2_map_io,
-	.init_irq	= davinci_ntosd2_irq_init,
+	.init_irq	= davinci_irq_init,
 	.timer		= &davinci_timer,
 	.init_machine = davinci_ntosd2_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 1ed0662..23e664a 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -152,18 +152,13 @@ static __init void davinci_sffsdr_init(void)
 	davinci_cfg_reg(DM644X_VLYNQWD);
 }
 
-static __init void davinci_sffsdr_irq_init(void)
-{
-	davinci_irq_init();
-}
-
 MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
 	/* Maintainer: Hugo Villeneuve hugo.villeneuve at lyrtech.com */
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (DAVINCI_DDR_BASE + 0x100),
 	.map_io	      = davinci_sffsdr_map_io,
-	.init_irq     = davinci_sffsdr_irq_init,
+	.init_irq     = davinci_irq_init,
 	.timer	      = &davinci_timer,
 	.init_machine = davinci_sffsdr_init,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 65e073d..1d25573 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -112,8 +112,6 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
 			goto err;
 	}
 
-	davinci_intc_base = davinci_soc_info.intc_base;
-	davinci_intc_type = davinci_soc_info.intc_type;
 	return;
 
 err:
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 2a8d26e..bb4c40e 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -13,18 +13,17 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 
+#include <mach/common.h>
 #include <mach/cp_intc.h>
 
-static void __iomem *cp_intc_base;
-
 static inline unsigned int cp_intc_read(unsigned offset)
 {
-	return __raw_readl(cp_intc_base + offset);
+	return __raw_readl(davinci_intc_base + offset);
 }
 
 static inline void cp_intc_write(unsigned long value, unsigned offset)
 {
-	__raw_writel(value, cp_intc_base + offset);
+	__raw_writel(value, davinci_intc_base + offset);
 }
 
 static void cp_intc_ack_irq(unsigned int irq)
@@ -100,13 +99,18 @@ static struct irq_chip cp_intc_irq_chip = {
 	.set_wake	= cp_intc_set_wake,
 };
 
-void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
-			 u8 *irq_prio, u32 *host_map)
+void __init cp_intc_init(void)
 {
+	unsigned long num_irq	= davinci_soc_info.intc_irq_num;
+	u8 *irq_prio		= davinci_soc_info.intc_irq_prios;
+	u32 *host_map		= davinci_soc_info.intc_host_map;
 	unsigned num_reg	= BITS_TO_LONGS(num_irq);
 	int i;
 
-	cp_intc_base = base;
+	davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
+	davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
+	if (WARN_ON(!davinci_intc_base))
+		return;
 
 	cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
 
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 47a7f49..2c84f07 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1193,7 +1193,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.psc_bases_num		= ARRAY_SIZE(da830_psc_bases),
 	.pinmux_pins		= da830_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(da830_pins),
-	.intc_base		= (void __iomem *)DA8XX_CP_INTC_VIRT,
+	.intc_base		= DA8XX_CP_INTC_BASE,
 	.intc_type		= DAVINCI_INTC_TYPE_CP_INTC,
 	.intc_irq_prios		= da830_default_priorities,
 	.intc_irq_num		= DA830_N_CP_INTC_IRQ,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 2a430bb..6f5ea2a 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1078,7 +1078,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.psc_bases_num		= ARRAY_SIZE(da850_psc_bases),
 	.pinmux_pins		= da850_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(da850_pins),
-	.intc_base		= (void __iomem *)DA8XX_CP_INTC_VIRT,
+	.intc_base		= DA8XX_CP_INTC_BASE,
 	.intc_type		= DAVINCI_INTC_TYPE_CP_INTC,
 	.intc_irq_prios		= da850_default_priorities,
 	.intc_irq_num		= DA850_N_CP_INTC_IRQ,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 70a1827..5ab39f6 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -847,7 +847,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 	.pinmux_pins		= dm355_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm355_pins),
-	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+	.intc_base		= DAVINCI_ARM_INTC_BASE,
 	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
 	.intc_irq_prios		= dm355_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 451a4ef..be340ed 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1052,7 +1052,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 	.pinmux_pins		= dm365_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm365_pins),
-	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+	.intc_base		= DAVINCI_ARM_INTC_BASE,
 	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
 	.intc_irq_prios		= dm365_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index ee654de..d3aa1f7 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -738,7 +738,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 	.pinmux_pins		= dm644x_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm644x_pins),
-	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+	.intc_base		= DAVINCI_ARM_INTC_BASE,
 	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
 	.intc_irq_prios 	= dm644x_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 4c98ef0..e0153b3 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -822,7 +822,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 	.pinmux_pins		= dm646x_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm646x_pins),
-	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+	.intc_base		= DAVINCI_ARM_INTC_BASE,
 	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
 	.intc_irq_prios		= dm646x_default_priorities,
 	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 4c8dfcb..005f624 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -54,10 +54,11 @@ struct davinci_soc_info {
 	void __iomem			*pinmux_base;
 	const struct mux_config		*pinmux_pins;
 	unsigned long			pinmux_pins_num;
-	void __iomem			*intc_base;
+	u32				intc_base;
 	int				intc_type;
 	u8				*intc_irq_prios;
 	unsigned long			intc_irq_num;
+	u32				*intc_host_map;
 	struct davinci_timer_info	*timer_info;
 	int				gpio_type;
 	u32				gpio_base;
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index 121b114..4e8190e 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -51,7 +51,6 @@
 #define CP_INTC_HOST_PRIO_VECTOR(n)	(0x1600 + (n << 2))
 #define CP_INTC_VECTOR_ADDR(n)		(0x2000 + (n << 2))
 
-void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
-			 u8 *irq_prio, u32 *host_map);
+void __init cp_intc_init(void);
 
 #endif	/* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index af92ffe..784ddf3 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -116,6 +116,11 @@ void __init davinci_irq_init(void)
 	unsigned i;
 	const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
 
+	davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
+	davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
+	if (WARN_ON(!davinci_intc_base))
+		return;
+
 	/* Clear all interrupt requests */
 	davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
 	davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
@@ -148,7 +153,7 @@ void __init davinci_irq_init(void)
 	}
 
 	/* set up genirq dispatch for ARM INTC */
-	for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) {
+	for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
 		set_irq_chip(i, &davinci_irq_chip_0);
 		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 		if (i != IRQ_TINT1_TINT34)
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 16:06:39 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 17:06:39 -0400
Subject: [PATCH v3 8/8] Davinci: iotable based ioremap() interception
In-Reply-To: <1273266399-17164-1-git-send-email-cyril@ti.com>
References: <1273266399-17164-1-git-send-email-cyril@ti.com>
Message-ID: <1273266399-17164-9-git-send-email-cyril@ti.com>

This patch allows for a more flexible ioremap() interception based on iotable
contents.

With this patch, the ioremap() interception code can properly translate
addresses only after davinci_soc_info has been initialized.  Consequently,
in soc-specific init functions, davinci_common_init() has to happen before any
ioremap() attempts. The da8xx init sequence has been suitably modified to meet
this restriction.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v3: unchanged from v2
v2: commit description changed
v2: davinci_soc_info comment added

 arch/arm/mach-davinci/da830.c               |    7 +++----
 arch/arm/mach-davinci/da850.c               |    4 ++--
 arch/arm/mach-davinci/include/mach/common.h |    8 +++++++-
 arch/arm/mach-davinci/io.c                  |   20 +++++++++++++++-----
 4 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 94fe971..3a7a96f 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1210,9 +1210,8 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 
 void __init da830_init(void)
 {
-	da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
-	if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
-		return;
-
 	davinci_common_init(&davinci_soc_info_da830);
+
+	da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
+	WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
 }
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 74d4e49..6b8331b 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1099,6 +1099,8 @@ void __init da850_init(void)
 {
 	unsigned int v;
 
+	davinci_common_init(&davinci_soc_info_da850);
+
 	da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
 	if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
 		return;
@@ -1107,8 +1109,6 @@ void __init da850_init(void)
 	if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
 		return;
 
-	davinci_common_init(&davinci_soc_info_da850);
-
 	/*
 	 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
 	 * This helps keeping the peripherals on this domain insulated
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 2e07248..a57cba2 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -39,7 +39,13 @@ struct davinci_timer_info {
 
 struct davinci_gpio_controller;
 
-/* SoC specific init support */
+/*
+ * SoC info passed into common davinci modules.
+ *
+ * Base addresses in this structure should be physical and not virtual.
+ * Modules that take such base addresses, should internally ioremap() them to
+ * use.
+ */
 struct davinci_soc_info {
 	struct map_desc			*io_desc;
 	unsigned long			io_desc_num;
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index a1c0b6b..8ea60a8 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -12,19 +12,29 @@
 #include <linux/io.h>
 
 #include <asm/tlb.h>
+#include <asm/mach/map.h>
 
-#define BETWEEN(p, st, sz)	((p) >= (st) && (p) < ((st) + (sz)))
-#define XLATE(p, pst, vst)	((void __iomem *)((p) - (pst) + (vst)))
+#include <mach/common.h>
 
 /*
  * Intercept ioremap() requests for addresses in our fixed mapping regions.
  */
 void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
 {
-	if (BETWEEN(p, IO_PHYS, IO_SIZE))
-		return XLATE(p, IO_PHYS, IO_VIRT);
+	struct map_desc *desc = davinci_soc_info.io_desc;
+	int desc_num = davinci_soc_info.io_desc_num;
+	int i;
 
-	return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
+	for (i = 0; i < desc_num; i++, desc++) {
+		unsigned long iophys = __pfn_to_phys(desc->pfn);
+		unsigned long iosize = desc->length;
+
+		if (p >= iophys && (p + size) <= (iophys + iosize))
+			return __io(desc->virtual + p - iophys);
+	}
+
+	return __arm_ioremap_caller(p, size, type,
+					__builtin_return_address(0));
 }
 EXPORT_SYMBOL(davinci_ioremap);
 
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 16:06:35 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 17:06:35 -0400
Subject: [PATCH v3 4/8] Davinci: timer - use ioremap()
In-Reply-To: <1273266399-17164-1-git-send-email-cyril@ti.com>
References: <1273266399-17164-1-git-send-email-cyril@ti.com>
Message-ID: <1273266399-17164-5-git-send-email-cyril@ti.com>

This patch eliminates IO_ADDRESS() usage for Davinci timer definitions.  The
timer code has correspondingly been modified to ioremap() MMRs instead.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v3: unchanged from v2
v2: unchanged from v1

 arch/arm/mach-davinci/da830.c               |    4 ++--
 arch/arm/mach-davinci/da850.c               |    8 ++++----
 arch/arm/mach-davinci/devices.c             |    4 ++--
 arch/arm/mach-davinci/include/mach/common.h |    2 +-
 arch/arm/mach-davinci/time.c                |   22 ++++++++++++++--------
 5 files changed, 23 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index c5600b8..8a2510c 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1159,14 +1159,14 @@ static struct davinci_id da830_ids[] = {
 
 static struct davinci_timer_instance da830_timer_instance[2] = {
 	{
-		.base		= IO_ADDRESS(DA8XX_TIMER64P0_BASE),
+		.base		= DA8XX_TIMER64P0_BASE,
 		.bottom_irq	= IRQ_DA8XX_TINT12_0,
 		.top_irq	= IRQ_DA8XX_TINT34_0,
 		.cmp_off	= DA830_CMP12_0,
 		.cmp_irq	= IRQ_DA830_T12CMPINT0_0,
 	},
 	{
-		.base		= IO_ADDRESS(DA8XX_TIMER64P1_BASE),
+		.base		= DA8XX_TIMER64P1_BASE,
 		.bottom_irq	= IRQ_DA8XX_TINT12_1,
 		.top_irq	= IRQ_DA8XX_TINT34_1,
 		.cmp_off	= DA830_CMP12_0,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index fcf7016..ebfa5ca 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -800,22 +800,22 @@ static struct davinci_id da850_ids[] = {
 
 static struct davinci_timer_instance da850_timer_instance[4] = {
 	{
-		.base		= IO_ADDRESS(DA8XX_TIMER64P0_BASE),
+		.base		= DA8XX_TIMER64P0_BASE,
 		.bottom_irq	= IRQ_DA8XX_TINT12_0,
 		.top_irq	= IRQ_DA8XX_TINT34_0,
 	},
 	{
-		.base		= IO_ADDRESS(DA8XX_TIMER64P1_BASE),
+		.base		= DA8XX_TIMER64P1_BASE,
 		.bottom_irq	= IRQ_DA8XX_TINT12_1,
 		.top_irq	= IRQ_DA8XX_TINT34_1,
 	},
 	{
-		.base		= IO_ADDRESS(DA850_TIMER64P2_BASE),
+		.base		= DA850_TIMER64P2_BASE,
 		.bottom_irq	= IRQ_DA850_TINT12_2,
 		.top_irq	= IRQ_DA850_TINT34_2,
 	},
 	{
-		.base		= IO_ADDRESS(DA850_TIMER64P3_BASE),
+		.base		= DA850_TIMER64P3_BASE,
 		.bottom_irq	= IRQ_DA850_TINT12_3,
 		.top_irq	= IRQ_DA850_TINT34_3,
 	},
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index d9c82ee..8b7201e 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -297,12 +297,12 @@ static void davinci_init_wdt(void)
 
 struct davinci_timer_instance davinci_timer_instance[2] = {
 	{
-		.base		= IO_ADDRESS(DAVINCI_TIMER0_BASE),
+		.base		= DAVINCI_TIMER0_BASE,
 		.bottom_irq	= IRQ_TINT0_TINT12,
 		.top_irq	= IRQ_TINT0_TINT34,
 	},
 	{
-		.base		= IO_ADDRESS(DAVINCI_TIMER1_BASE),
+		.base		= DAVINCI_TIMER1_BASE,
 		.bottom_irq	= IRQ_TINT1_TINT12,
 		.top_irq	= IRQ_TINT1_TINT34,
 	},
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 1078458..2e15464 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -24,7 +24,7 @@ extern void __iomem *davinci_intc_base;
 extern int davinci_intc_type;
 
 struct davinci_timer_instance {
-	void __iomem	*base;
+	u32		base;
 	u32		bottom_irq;
 	u32		top_irq;
 	unsigned long	cmp_off;
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index e5c598a..0f21c36 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -197,32 +197,36 @@ static void __init timer_init(void)
 {
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
+	void __iomem *base[2];
 	int i;
 
 	/* Global init of each 64-bit timer as a whole */
 	for(i=0; i<2; i++) {
 		u32 tgcr;
-		void __iomem *base = dtip[i].base;
+
+		base[i] = ioremap(dtip[i].base, SZ_4K);
+		if (WARN_ON(!base[i]))
+			continue;
 
 		/* Disabled, Internal clock source */
-		__raw_writel(0, base + TCR);
+		__raw_writel(0, base[i] + TCR);
 
 		/* reset both timers, no pre-scaler for timer34 */
 		tgcr = 0;
-		__raw_writel(tgcr, base + TGCR);
+		__raw_writel(tgcr, base[i] + TGCR);
 
 		/* Set both timers to unchained 32-bit */
 		tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
-		__raw_writel(tgcr, base + TGCR);
+		__raw_writel(tgcr, base[i] + TGCR);
 
 		/* Unreset timers */
 		tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
 			(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
-		__raw_writel(tgcr, base + TGCR);
+		__raw_writel(tgcr, base[i] + TGCR);
 
 		/* Init both counters to zero */
-		__raw_writel(0, base + TIM12);
-		__raw_writel(0, base + TIM34);
+		__raw_writel(0, base[i] + TIM12);
+		__raw_writel(0, base[i] + TIM34);
 	}
 
 	/* Init of each timer as a 32-bit timer */
@@ -231,7 +235,9 @@ static void __init timer_init(void)
 		int timer = ID_TO_TIMER(t->id);
 		u32 irq;
 
-		t->base = dtip[timer].base;
+		t->base = base[timer];
+		if (!t->base)
+			continue;
 
 		if (IS_TIMER_BOT(t->id)) {
 			t->enamode_shift = 6;
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 16:06:38 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 17:06:38 -0400
Subject: [PATCH v3 7/8] Davinci: pinmux - use ioremap()
In-Reply-To: <1273266399-17164-1-git-send-email-cyril@ti.com>
References: <1273266399-17164-1-git-send-email-cyril@ti.com>
Message-ID: <1273266399-17164-8-git-send-email-cyril@ti.com>

This patch modifies the pinmux implementation so as to ioremap() the pinmux
register area on first use.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v3: fail gracefully on soc_info pinmux_pins being null
v3: return ENOMEM on ioremap failure
v2: bug --> warn

 arch/arm/mach-davinci/da830.c               |    3 +--
 arch/arm/mach-davinci/da850.c               |    3 +--
 arch/arm/mach-davinci/dm355.c               |    2 +-
 arch/arm/mach-davinci/dm365.c               |    2 +-
 arch/arm/mach-davinci/dm644x.c              |    2 +-
 arch/arm/mach-davinci/dm646x.c              |    2 +-
 arch/arm/mach-davinci/include/mach/common.h |    2 +-
 arch/arm/mach-davinci/mux.c                 |   17 ++++++++++++-----
 8 files changed, 19 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 2c84f07..94fe971 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1191,6 +1191,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 	.cpu_clks		= da830_clks,
 	.psc_bases		= da830_psc_bases,
 	.psc_bases_num		= ARRAY_SIZE(da830_psc_bases),
+	.pinmux_base		= DA8XX_SYSCFG0_BASE + 0x120,
 	.pinmux_pins		= da830_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(da830_pins),
 	.intc_base		= DA8XX_CP_INTC_BASE,
@@ -1213,7 +1214,5 @@ void __init da830_init(void)
 	if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
 		return;
 
-	davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
-
 	davinci_common_init(&davinci_soc_info_da830);
 }
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 6f5ea2a..74d4e49 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1076,6 +1076,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
 	.cpu_clks		= da850_clks,
 	.psc_bases		= da850_psc_bases,
 	.psc_bases_num		= ARRAY_SIZE(da850_psc_bases),
+	.pinmux_base		= DA8XX_SYSCFG0_BASE + 0x120,
 	.pinmux_pins		= da850_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(da850_pins),
 	.intc_base		= DA8XX_CP_INTC_BASE,
@@ -1106,8 +1107,6 @@ void __init da850_init(void)
 	if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
 		return;
 
-	davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
-
 	davinci_common_init(&davinci_soc_info_da850);
 
 	/*
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 5ab39f6..3834781 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -844,7 +844,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.cpu_clks		= dm355_clks,
 	.psc_bases		= dm355_psc_bases,
 	.psc_bases_num		= ARRAY_SIZE(dm355_psc_bases),
-	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
+	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
 	.pinmux_pins		= dm355_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm355_pins),
 	.intc_base		= DAVINCI_ARM_INTC_BASE,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index be340ed..e5e3dce 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1049,7 +1049,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.cpu_clks		= dm365_clks,
 	.psc_bases		= dm365_psc_bases,
 	.psc_bases_num		= ARRAY_SIZE(dm365_psc_bases),
-	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
+	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
 	.pinmux_pins		= dm365_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm365_pins),
 	.intc_base		= DAVINCI_ARM_INTC_BASE,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index d3aa1f7..7ad1520 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -735,7 +735,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.cpu_clks		= dm644x_clks,
 	.psc_bases		= dm644x_psc_bases,
 	.psc_bases_num		= ARRAY_SIZE(dm644x_psc_bases),
-	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
+	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
 	.pinmux_pins		= dm644x_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm644x_pins),
 	.intc_base		= DAVINCI_ARM_INTC_BASE,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index e0153b3..9404565 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -819,7 +819,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.cpu_clks		= dm646x_clks,
 	.psc_bases		= dm646x_psc_bases,
 	.psc_bases_num		= ARRAY_SIZE(dm646x_psc_bases),
-	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
+	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
 	.pinmux_pins		= dm646x_pins,
 	.pinmux_pins_num	= ARRAY_SIZE(dm646x_pins),
 	.intc_base		= DAVINCI_ARM_INTC_BASE,
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 005f624..2e07248 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -51,7 +51,7 @@ struct davinci_soc_info {
 	struct clk_lookup		*cpu_clks;
 	u32				*psc_bases;
 	unsigned long			psc_bases_num;
-	void __iomem			*pinmux_base;
+	u32				pinmux_base;
 	const struct mux_config		*pinmux_pins;
 	unsigned long			pinmux_pins_num;
 	u32				intc_base;
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index e9d530a..f34a8dc 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -22,6 +22,8 @@
 #include <mach/mux.h>
 #include <mach/common.h>
 
+static void __iomem *pinmux_base;
+
 /*
  * Sets the DAVINCI MUX register based on the table
  */
@@ -29,14 +31,19 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
 {
 	static DEFINE_SPINLOCK(mux_spin_lock);
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	void __iomem *base = soc_info->pinmux_base;
 	unsigned long flags;
 	const struct mux_config *cfg;
 	unsigned int reg_orig = 0, reg = 0;
 	unsigned int mask, warn = 0;
 
-	if (!soc_info->pinmux_pins)
-		BUG();
+	if (WARN_ON(!soc_info->pinmux_pins))
+		return -ENODEV;
+
+	if (!pinmux_base) {
+		pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
+		if (WARN_ON(!pinmux_base))
+			return -ENOMEM;
+	}
 
 	if (index >= soc_info->pinmux_pins_num) {
 		printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
@@ -57,7 +64,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
 		unsigned	tmp1, tmp2;
 
 		spin_lock_irqsave(&mux_spin_lock, flags);
-		reg_orig = __raw_readl(base + cfg->mux_reg);
+		reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
 
 		mask = (cfg->mask << cfg->mask_offset);
 		tmp1 = reg_orig & mask;
@@ -69,7 +76,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
 		if (tmp1 != tmp2)
 			warn = 1;
 
-		__raw_writel(reg, base + cfg->mux_reg);
+		__raw_writel(reg, pinmux_base + cfg->mux_reg);
 		spin_unlock_irqrestore(&mux_spin_lock, flags);
 	}
 
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 16:06:34 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 17:06:34 -0400
Subject: [PATCH v3 3/8] Davinci: jtag_id - use ioremap()
In-Reply-To: <1273266399-17164-1-git-send-email-cyril@ti.com>
References: <1273266399-17164-1-git-send-email-cyril@ti.com>
Message-ID: <1273266399-17164-4-git-send-email-cyril@ti.com>

This patch replaces the jtag id base info in davinci_soc_info with a physical
address which is then ioremap()ed within common code.

This patch (in combination with a similar change for PSC) will allow us to
eliminate the SYSCFG nastiness in DA8xx code.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v3: use soc_info arg instead of global davinci_soc_info in davinci_init_id()
v3: fix jtag id register address on da8xx
v2: fixed return value on ioremap failure

 arch/arm/mach-davinci/common.c              |   52 +++++++++++++++-----------
 arch/arm/mach-davinci/da830.c               |    3 +-
 arch/arm/mach-davinci/da850.c               |    3 +-
 arch/arm/mach-davinci/dm355.c               |    2 +-
 arch/arm/mach-davinci/dm365.c               |    2 +-
 arch/arm/mach-davinci/dm644x.c              |    2 +-
 arch/arm/mach-davinci/dm646x.c              |    2 +-
 arch/arm/mach-davinci/include/mach/common.h |    2 +-
 8 files changed, 37 insertions(+), 31 deletions(-)

diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index f8221c5..65e073d 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -37,26 +37,43 @@ void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context)
 		pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
 }
 
-static struct davinci_id * __init davinci_get_id(u32 jtag_id)
+static int __init davinci_init_id(struct davinci_soc_info *soc_info)
 {
-	int i;
-	struct davinci_id *dip;
-	u8 variant = (jtag_id & 0xf0000000) >> 28;
-	u16 part_no = (jtag_id & 0x0ffff000) >> 12;
+	int			i;
+	struct davinci_id	*dip;
+	u8			variant;
+	u16			part_no;
+	void __iomem		*base;
+
+	base = ioremap(soc_info->jtag_id_reg, SZ_4K);
+	if (!base) {
+		pr_err("Unable to map JTAG ID register\n");
+		return -ENOMEM;
+	}
+
+	soc_info->jtag_id = __raw_readl(base);
+	iounmap(base);
 
-	for (i = 0, dip = davinci_soc_info.ids; i < davinci_soc_info.ids_num;
+	variant = (soc_info->jtag_id & 0xf0000000) >> 28;
+	part_no = (soc_info->jtag_id & 0x0ffff000) >> 12;
+
+	for (i = 0, dip = soc_info->ids; i < soc_info->ids_num;
 			i++, dip++)
 		/* Don't care about the manufacturer right now */
-		if ((dip->part_no == part_no) && (dip->variant == variant))
-			return dip;
-
-	return NULL;
+		if ((dip->part_no == part_no) && (dip->variant == variant)) {
+			soc_info->cpu_id = dip->cpu_id;
+			pr_info("DaVinci %s variant 0x%x\n", dip->name,
+					dip->variant);
+			return 0;
+		}
+
+	pr_err("Unknown DaVinci JTAG ID 0x%x\n", soc_info->jtag_id);
+	return -EINVAL;
 }
 
 void __init davinci_common_init(struct davinci_soc_info *soc_info)
 {
 	int ret;
-	struct davinci_id *dip;
 
 	if (!soc_info) {
 		ret = -EINVAL;
@@ -84,18 +101,9 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
 	 * We want to check CPU revision early for cpu_is_xxxx() macros.
 	 * IO space mapping must be initialized before we can do that.
 	 */
-	davinci_soc_info.jtag_id = __raw_readl(davinci_soc_info.jtag_id_base);
-
-	dip = davinci_get_id(davinci_soc_info.jtag_id);
-	if (!dip) {
-		ret = -EINVAL;
-		pr_err("Unknown DaVinci JTAG ID 0x%x\n",
-						davinci_soc_info.jtag_id);
+	ret = davinci_init_id(&davinci_soc_info);
+	if (ret < 0)
 		goto err;
-	}
-
-	davinci_soc_info.cpu_id = dip->cpu_id;
-	pr_info("DaVinci %s variant 0x%x\n", dip->name, dip->variant);
 
 	if (davinci_soc_info.cpu_clks) {
 		ret = davinci_clk_init(davinci_soc_info.cpu_clks);
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 4f5727f..c5600b8 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1188,6 +1188,7 @@ static struct davinci_timer_info da830_timer_info = {
 static struct davinci_soc_info davinci_soc_info_da830 = {
 	.io_desc		= da830_io_desc,
 	.io_desc_num		= ARRAY_SIZE(da830_io_desc),
+	.jtag_id_reg		= DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
 	.ids			= da830_ids,
 	.ids_num		= ARRAY_SIZE(da830_ids),
 	.cpu_clks		= da830_clks,
@@ -1215,8 +1216,6 @@ void __init da830_init(void)
 	if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
 		return;
 
-	davinci_soc_info_da830.jtag_id_base =
-					DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
 	davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
 
 	davinci_common_init(&davinci_soc_info_da830);
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index cb7f663..fcf7016 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1073,6 +1073,7 @@ no_ddrpll_mem:
 static struct davinci_soc_info davinci_soc_info_da850 = {
 	.io_desc		= da850_io_desc,
 	.io_desc_num		= ARRAY_SIZE(da850_io_desc),
+	.jtag_id_reg		= DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
 	.ids			= da850_ids,
 	.ids_num		= ARRAY_SIZE(da850_ids),
 	.cpu_clks		= da850_clks,
@@ -1108,8 +1109,6 @@ void __init da850_init(void)
 	if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
 		return;
 
-	davinci_soc_info_da850.jtag_id_base =
-					DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
 	davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
 
 	davinci_common_init(&davinci_soc_info_da850);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 277041d..228b6d1 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -840,7 +840,7 @@ static struct platform_device dm355_serial_device = {
 static struct davinci_soc_info davinci_soc_info_dm355 = {
 	.io_desc		= dm355_io_desc,
 	.io_desc_num		= ARRAY_SIZE(dm355_io_desc),
-	.jtag_id_base		= IO_ADDRESS(0x01c40028),
+	.jtag_id_reg		= 0x01c40028,
 	.ids			= dm355_ids,
 	.ids_num		= ARRAY_SIZE(dm355_ids),
 	.cpu_clks		= dm355_clks,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index ecdbc67..b396d58 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1045,7 +1045,7 @@ static struct platform_device dm365_serial_device = {
 static struct davinci_soc_info davinci_soc_info_dm365 = {
 	.io_desc		= dm365_io_desc,
 	.io_desc_num		= ARRAY_SIZE(dm365_io_desc),
-	.jtag_id_base		= IO_ADDRESS(0x01c40028),
+	.jtag_id_reg		= 0x01c40028,
 	.ids			= dm365_ids,
 	.ids_num		= ARRAY_SIZE(dm365_ids),
 	.cpu_clks		= dm365_clks,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index beb315c..9859567 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -731,7 +731,7 @@ static struct platform_device dm644x_serial_device = {
 static struct davinci_soc_info davinci_soc_info_dm644x = {
 	.io_desc		= dm644x_io_desc,
 	.io_desc_num		= ARRAY_SIZE(dm644x_io_desc),
-	.jtag_id_base		= IO_ADDRESS(0x01c40028),
+	.jtag_id_reg		= 0x01c40028,
 	.ids			= dm644x_ids,
 	.ids_num		= ARRAY_SIZE(dm644x_ids),
 	.cpu_clks		= dm644x_clks,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 95fc981..f9a8cc4 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -815,7 +815,7 @@ static struct platform_device dm646x_serial_device = {
 static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.io_desc		= dm646x_io_desc,
 	.io_desc_num		= ARRAY_SIZE(dm646x_io_desc),
-	.jtag_id_base		= IO_ADDRESS(0x01c40028),
+	.jtag_id_reg		= 0x01c40028,
 	.ids			= dm646x_ids,
 	.ids_num		= ARRAY_SIZE(dm646x_ids),
 	.cpu_clks		= dm646x_clks,
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 2dd2226..1078458 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -45,7 +45,7 @@ struct davinci_soc_info {
 	unsigned long			io_desc_num;
 	u32				cpu_id;
 	u32				jtag_id;
-	void __iomem			*jtag_id_base;
+	u32				jtag_id_reg;
 	struct davinci_id		*ids;
 	unsigned long			ids_num;
 	struct clk_lookup		*cpu_clks;
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 17:38:00 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 18:38:00 -0400
Subject: [PATCH v6 0/6] Davinci: initial tnetv107x patch series
Message-ID: <1273271886-15190-1-git-send-email-cyril@ti.com>

This patch series adds support for TNETV107X - a Texas Instruments SOC that
shares a number of common features with the Davinci architecture.

This version includes minor fixes over the v5 series posted earlier

Cyril Chemparathy (6):
  Davinci: generalized debug macros
  Davinci: tnetv107x decompresser uart definitions
  Davinci: tnetv107x soc support
  Davinci: tnetv107x initial gpio support
  Davinci: tnetv107x evm board initial support
  Davinci: tnetv107x default configuration

 arch/arm/configs/tnetv107x_defconfig             | 1741 ++++++++++++++++++++++
 arch/arm/mach-davinci/Kconfig                    |   12 +
 arch/arm/mach-davinci/Makefile                   |    3 +
 arch/arm/mach-davinci/board-tnetv107x-evm.c      |  174 +++
 arch/arm/mach-davinci/devices-tnetv107x.c        |  318 ++++
 arch/arm/mach-davinci/gpio-tnetv107x.c           |  205 +++
 arch/arm/mach-davinci/include/mach/debug-macro.S |   50 +-
 arch/arm/mach-davinci/include/mach/gpio.h        |   27 +-
 arch/arm/mach-davinci/include/mach/serial.h      |   21 +
 arch/arm/mach-davinci/include/mach/tnetv107x.h   |   56 +
 arch/arm/mach-davinci/include/mach/uncompress.h  |   87 +-
 arch/arm/mach-davinci/tnetv107x.c                |  753 ++++++++++
 12 files changed, 3410 insertions(+), 37 deletions(-)
 create mode 100644 arch/arm/configs/tnetv107x_defconfig
 create mode 100644 arch/arm/mach-davinci/board-tnetv107x-evm.c
 create mode 100644 arch/arm/mach-davinci/devices-tnetv107x.c
 create mode 100644 arch/arm/mach-davinci/gpio-tnetv107x.c
 create mode 100644 arch/arm/mach-davinci/include/mach/tnetv107x.h
 create mode 100644 arch/arm/mach-davinci/tnetv107x.c


From cyril at ti.com  Fri May  7 17:38:02 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 18:38:02 -0400
Subject: [PATCH v6 2/6] Davinci: tnetv107x decompresser uart definitions
In-Reply-To: <1273271886-15190-1-git-send-email-cyril@ti.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
Message-ID: <1273271886-15190-3-git-send-email-cyril@ti.com>

Added definitions for tnetv107x uart base addresses, and modified base address
selection for kernel decompressor to check for tnetv107x machine type.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v6: unchanged from v5
v5: unchanged from v4
v4: unchanged from v3
v3: migrated to uncompress.h based implementation added earlier in this series

 arch/arm/mach-davinci/include/mach/serial.h     |    8 ++++++++
 arch/arm/mach-davinci/include/mach/uncompress.h |    7 +++++++
 2 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index b21ec22..56cc338 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -32,6 +32,14 @@
 #define DA8XX_UART1_BASE	(IO_PHYS + 0x10c000)
 #define DA8XX_UART2_BASE	(IO_PHYS + 0x10d000)
 
+#define TNETV107X_UART0_BASE	(0x08108100)
+#define TNETV107X_UART1_BASE	(0x08088400)
+#define TNETV107X_UART2_BASE	(0x08108300)
+
+#define TNETV107X_UART0_VIRT	IOMEM(0xfee08100)
+#define TNETV107X_UART1_VIRT	IOMEM(0xfed88400)
+#define TNETV107X_UART2_VIRT	IOMEM(0xfee08300)
+
 /* DaVinci UART register offsets */
 #define UART_DAVINCI_PWREMU		0x0c
 #define UART_DM646X_SCR			0x10
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 20c23a3..15a6192 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -63,6 +63,10 @@ static inline void set_uart_info(u32 phys, void * __iomem virt)
 	_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE,	\
 			IO_ADDRESS(DA8XX_UART##port##_BASE))
 
+#define DEBUG_LL_TNETV107X(machine, port)			\
+	_DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE,	\
+			TNETV107X_UART##port##_VIRT)
+
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
 	/*
@@ -84,6 +88,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 		/* DA8xx boards */
 		DEBUG_LL_DA8XX(davinci_da830_evm,	2);
 		DEBUG_LL_DA8XX(davinci_da850_evm,	2);
+
+		/* TNETV107x boards */
+		DEBUG_LL_TNETV107X(tnetv107x,		1);
 	} while (0);
 }
 
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 17:38:01 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 18:38:01 -0400
Subject: [PATCH v6 1/6] Davinci: generalized debug macros
In-Reply-To: <1273271886-15190-1-git-send-email-cyril@ti.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
Message-ID: <1273271886-15190-2-git-send-email-cyril@ti.com>

This patch adopts a debug uart selection similar to the OMAP model.  During
the boot process, the uncompress code determines the physical and virtual base
addresses of the board-specific debug uart.  These addresses are then passed
on to the in-kernel debug macros through a small chunk of memory placed just
below the page tables (@0x80003ff8).

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v6: unchanged from v5
v5: removed redundant mmu enable check
v4: unchanged from v3

 arch/arm/mach-davinci/include/mach/debug-macro.S |   50 +++++++++++---
 arch/arm/mach-davinci/include/mach/serial.h      |   13 ++++
 arch/arm/mach-davinci/include/mach/uncompress.h  |   80 ++++++++++++++++------
 3 files changed, 111 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index 3cd93a8..f761dfd 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -17,22 +17,50 @@
  */
 
 #include <linux/serial_reg.h>
+
+#include <asm/memory.h>
+
+#include <mach/serial.h>
+
 #define UART_SHIFT	2
 
+		.pushsection .data
+davinci_uart_phys:	.word	0
+davinci_uart_virt:	.word	0
+		.popsection
+
 		.macro addruart, rx, tmp
+
+		/* Use davinci_uart_phys/virt if already configured */
+10:		mrc	p15, 0, \rx, c1, c0
+		tst	\rx, #1			@ MMU enabled?
+		ldreq	\rx, =__virt_to_phys(davinci_uart_phys)
+		ldrne	\rx, =davinci_uart_virt
+		ldr	\rx, [\rx]
+		cmp	\rx, #0			@ is port configured?
+		bne	99f			@ already configured
+
 		mrc	p15, 0, \rx, c1, c0
 		tst	\rx, #1			@ MMU enabled?
-		moveq	\rx, #0x01000000	@ physical base address
-		movne	\rx, #0xfe000000	@ virtual base
-#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
-#error Cannot enable DaVinci and DA8XX platforms concurrently
-#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \
-	defined(CONFIG_MACH_DAVINCI_DA850_EVM)
-		orr	\rx, \rx, #0x00d00000	@ physical base address
-		orr	\rx, \rx, #0x0000d000	@ of UART 2
-#else
-		orr	\rx, \rx, #0x00c20000   @ UART 0
-#endif
+
+		/* Copy uart phys address from decompressor uart info */
+		ldreq	\tmp, =__virt_to_phys(davinci_uart_phys)
+		ldrne	\tmp, =davinci_uart_phys
+		ldreq	\rx, =DAVINCI_UART_INFO
+		ldrne	\rx, =__phys_to_virt(DAVINCI_UART_INFO)
+		ldr	\rx, [\rx, #0]
+		str	\rx, [\tmp]
+
+		/* Copy uart virt address from decompressor uart info */
+		ldreq	\tmp, =__virt_to_phys(davinci_uart_virt)
+		ldrne	\tmp, =davinci_uart_virt
+		ldreq	\rx, =DAVINCI_UART_INFO
+		ldrne	\rx, =__phys_to_virt(DAVINCI_UART_INFO)
+		ldr	\rx, [\rx, #4]
+		str	\rx, [\tmp]
+
+		b	10b
+99:
 		.endm
 
 		.macro	senduart,rd,rx
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index f6c4f34..b21ec22 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -11,8 +11,19 @@
 #ifndef __ASM_ARCH_SERIAL_H
 #define __ASM_ARCH_SERIAL_H
 
+#include <asm/memory.h>
+
 #include <mach/hardware.h>
 
+/*
+ * Stolen area that contains debug uart physical and virtual addresses.  These
+ * addresses are filled in by the uncompress.h code, and are used by the debug
+ * macros in debug-macro.S.
+ *
+ * This area sits just below the page tables (see arch/arm/kernel/head.S).
+ */
+#define DAVINCI_UART_INFO	(PHYS_OFFSET + 0x3ff8)
+
 #define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
@@ -26,11 +37,13 @@
 #define UART_DM646X_SCR			0x10
 #define UART_DM646X_SCR_TX_WATERMARK	0x08
 
+#ifndef __ASSEMBLY__
 struct davinci_uart_config {
 	/* Bit field of UARTs present; bit 0 --> UART1 */
 	unsigned int enabled_uarts;
 };
 
 extern int davinci_serial_init(struct davinci_uart_config *);
+#endif
 
 #endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 33796b4..20c23a3 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -1,8 +1,17 @@
 /*
  * Serial port stubs for kernel decompress status messages
  *
- *  Author:     Anant Gole
- * (C) Copyright (C) 2006, Texas Instruments, Inc
+ * Initially based on:
+ * arch/arm/plat-omap/include/mach/uncompress.h
+ *
+ * Original copyrights follow.
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon at ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source at mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2. This program is licensed "as is" without any warranty of any
@@ -11,30 +20,17 @@
 
 #include <linux/types.h>
 #include <linux/serial_reg.h>
-#include <mach/serial.h>
 
 #include <asm/mach-types.h>
 
-extern unsigned int __machine_arch_type;
+#include <mach/serial.h>
 
 static u32 *uart;
-
-static u32 *get_uart_base(void)
-{
-	if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM ||
-		__machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM)
-		return (u32 *)DA8XX_UART2_BASE;
-	else
-		return (u32 *)DAVINCI_UART0_BASE;
-}
+static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
 
 /* PORT_16C550A, in polled non-fifo mode */
-
 static void putc(char c)
 {
-	if (!uart)
-		uart = get_uart_base();
-
 	while (!(uart[UART_LSR] & UART_LSR_THRE))
 		barrier();
 	uart[UART_TX] = c;
@@ -42,12 +38,54 @@ static void putc(char c)
 
 static inline void flush(void)
 {
-	if (!uart)
-		uart = get_uart_base();
-
 	while (!(uart[UART_LSR] & UART_LSR_THRE))
 		barrier();
 }
 
-#define arch_decomp_setup()
+static inline void set_uart_info(u32 phys, void * __iomem virt)
+{
+	uart = (u32 *)phys;
+	uart_info[0] = phys;
+	uart_info[1] = (u32)virt;
+}
+
+#define _DEBUG_LL_ENTRY(machine, phys, virt)			\
+	if (machine_is_##machine()) {				\
+		set_uart_info(phys, virt);			\
+		break;						\
+	}
+
+#define DEBUG_LL_DAVINCI(machine, port)				\
+	_DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE,	\
+			IO_ADDRESS(DAVINCI_UART##port##_BASE))
+
+#define DEBUG_LL_DA8XX(machine, port)				\
+	_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE,	\
+			IO_ADDRESS(DA8XX_UART##port##_BASE))
+
+static inline void __arch_decomp_setup(unsigned long arch_id)
+{
+	/*
+	 * Initialize the port based on the machine ID from the bootloader.
+	 * Note that we're using macros here instead of switch statement
+	 * as machine_is functions are optimized out for the boards that
+	 * are not selected.
+	 */
+	do {
+		/* Davinci boards */
+		DEBUG_LL_DAVINCI(davinci_evm,		0);
+		DEBUG_LL_DAVINCI(sffsdr,		0);
+		DEBUG_LL_DAVINCI(neuros_osd2,		0);
+		DEBUG_LL_DAVINCI(davinci_dm355_evm,	0);
+		DEBUG_LL_DAVINCI(dm355_leopard,		0);
+		DEBUG_LL_DAVINCI(davinci_dm6467_evm,	0);
+		DEBUG_LL_DAVINCI(davinci_dm365_evm,	0);
+
+		/* DA8xx boards */
+		DEBUG_LL_DA8XX(davinci_da830_evm,	2);
+		DEBUG_LL_DA8XX(davinci_da850_evm,	2);
+	} while (0);
+}
+
+#define arch_decomp_setup()	__arch_decomp_setup(arch_id)
 #define arch_decomp_wdog()
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 17:38:05 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 18:38:05 -0400
Subject: [PATCH v6 5/6] Davinci: tnetv107x evm board initial support
In-Reply-To: <1273271886-15190-1-git-send-email-cyril@ti.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
Message-ID: <1273271886-15190-6-git-send-email-cyril@ti.com>

Added support for tnetv107x evaluation module.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v6: unchanged from v5
v5: modifications as per ioremap patch series for cpintc
v5: add comments to clarify nand chipselect and mmc controller instance
v5: enable nand bad block table
v4: updated copyrights
v4: squashed relevant gpio pins into sdio1 pin list
v4: eliminated platform device definitions, moved to tnetv107x_devices_init()
    implementation instead
v4: platform devices moved out to devices-tnetv107x.c
v3: moved some base address and edma channel definitions here
v3: minor formatting changes

 arch/arm/mach-davinci/Kconfig               |    7 +
 arch/arm/mach-davinci/Makefile              |    1 +
 arch/arm/mach-davinci/board-tnetv107x-evm.c |  174 +++++++++++++++++++++++++++
 3 files changed, 182 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-davinci/board-tnetv107x-evm.c

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a67b47b..71f90f8 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -178,6 +178,13 @@ config DA850_UI_RMII
 
 endchoice
 
+config MACH_TNETV107X
+	bool "TI TNETV107X Reference Platform"
+	default ARCH_DAVINCI_TNETV107X
+	depends on ARCH_DAVINCI_TNETV107X
+	help
+	  Say Y here to select the TI TNETV107X Evaluation Module.
+
 config DAVINCI_MUX
 	bool "DAVINCI multiplexing support"
 	depends on ARCH_DAVINCI
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 62c5116..eab4c0f 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)	+= board-dm646x-evm.o cdce949.o
 obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)	+= board-dm365-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)	+= board-da830-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= board-da850-evm.o
+obj-$(CONFIG_MACH_TNETV107X)		+= board-tnetv107x-evm.o
 
 # Power Management
 obj-$(CONFIG_CPU_FREQ)			+= cpufreq.o
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
new file mode 100644
index 0000000..fe2a9d9
--- /dev/null
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -0,0 +1,174 @@
+/*
+ * Texas Instruments TNETV107X EVM Board Support
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/ratelimit.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/irqs.h>
+#include <mach/edma.h>
+#include <mach/mux.h>
+#include <mach/cp_intc.h>
+#include <mach/tnetv107x.h>
+
+#define EVM_MMC_WP_GPIO		21
+#define EVM_MMC_CD_GPIO		24
+
+static int initialize_gpio(int gpio, char *desc)
+{
+	int ret;
+
+	ret = gpio_request(gpio, desc);
+	if (ret < 0) {
+		pr_err_ratelimited("cannot open %s gpio\n", desc);
+		return -ENOSYS;
+	}
+	gpio_direction_input(gpio);
+	return gpio;
+}
+
+static int mmc_get_cd(int index)
+{
+	static int gpio;
+
+	if (!gpio)
+		gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect");
+
+	if (gpio < 0)
+		return gpio;
+
+	return gpio_get_value(gpio) ? 0 : 1;
+}
+
+static int mmc_get_ro(int index)
+{
+	static int gpio;
+
+	if (!gpio)
+		gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect");
+
+	if (gpio < 0)
+		return gpio;
+
+	return gpio_get_value(gpio) ? 1 : 0;
+}
+
+static struct davinci_mmc_config mmc_config = {
+	.get_cd		= mmc_get_cd,
+	.get_ro		= mmc_get_ro,
+	.wires		= 4,
+	.max_freq	= 50000000,
+	.caps		= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+	.version	= MMC_CTLR_VERSION_1,
+};
+
+static const short sdio1_pins[] __initdata = {
+	TNETV107X_SDIO1_CLK_1,		TNETV107X_SDIO1_CMD_1,
+	TNETV107X_SDIO1_DATA0_1,	TNETV107X_SDIO1_DATA1_1,
+	TNETV107X_SDIO1_DATA2_1,	TNETV107X_SDIO1_DATA3_1,
+	TNETV107X_GPIO21,		TNETV107X_GPIO24,
+	-1
+};
+
+static const short uart1_pins[] __initdata = {
+	TNETV107X_UART1_RD,		TNETV107X_UART1_TD,
+	-1
+};
+
+static struct mtd_partition nand_partitions[] = {
+	/* bootloader (U-Boot, etc) in first 12 sectors */
+	{
+		.name		= "bootloader",
+		.offset		= 0,
+		.size		= (12*SZ_128K),
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	/* bootloader params in the next sector */
+	{
+		.name		= "params",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	/* kernel */
+	{
+		.name		= "kernel",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= SZ_4M,
+		.mask_flags	= 0,
+	},
+	/* file system */
+	{
+		.name		= "filesystem",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= MTDPART_SIZ_FULL,
+		.mask_flags	= 0,
+	}
+};
+
+static struct davinci_nand_pdata nand_config = {
+	.mask_cle	= 0x4000,
+	.mask_ale	= 0x2000,
+	.parts		= nand_partitions,
+	.nr_parts	= ARRAY_SIZE(nand_partitions),
+	.ecc_mode	= NAND_ECC_HW,
+	.options	= NAND_USE_FLASH_BBT,
+	.ecc_bits	= 1,
+};
+
+static struct davinci_uart_config serial_config __initconst = {
+	.enabled_uarts	= BIT(1),
+};
+
+static struct tnetv107x_device_info evm_device_info __initconst = {
+	.serial_config		= &serial_config,
+	.mmc_config[1]		= &mmc_config,	/* controller 1 */
+	.nand_config[0]		= &nand_config,	/* chip select 0 */
+};
+
+static __init void tnetv107x_evm_board_init(void)
+{
+	davinci_cfg_reg_list(sdio1_pins);
+	davinci_cfg_reg_list(uart1_pins);
+
+	tnetv107x_devices_init(&evm_device_info);
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+static int __init tnetv107x_evm_console_init(void)
+{
+	return add_preferred_console("ttyS", 0, "115200");
+}
+console_initcall(tnetv107x_evm_console_init);
+#endif
+
+MACHINE_START(TNETV107X, "TNETV107X EVM")
+	.phys_io	= TNETV107X_IO_BASE,
+	.io_pg_offst	= (TNETV107X_IO_VIRT >> 18) & 0xfffc,
+	.boot_params	= (TNETV107X_DDR_BASE + 0x100),
+	.map_io		= tnetv107x_init,
+	.init_irq	= cp_intc_init,
+	.timer		= &davinci_timer,
+	.init_machine	= tnetv107x_evm_board_init,
+MACHINE_END
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 17:38:03 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 18:38:03 -0400
Subject: [PATCH v6 3/6] Davinci: tnetv107x soc support
In-Reply-To: <1273271886-15190-1-git-send-email-cyril@ti.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
Message-ID: <1273271886-15190-4-git-send-email-cyril@ti.com>

TNETV107X is a Texas Instruments SOC that shares a number of common features
with the Davinci architecture.  Some of the key differences between
traditional Davincis and this new SOC are as follow:

1. The SOCs clock architecture includes a new spread-spectrum PLL.  Some
elements of the clock architecture are reused from Davinci (e.g. LPSC), but
the PLL related code is overridden using existing interfaces in "struct clk".

2. The MMR layout on this SOC is substantially different from Davinci.
Consequently, the fixed I/O map is a whole lot more convoluted (more so than
DA8xx).  The net impact here is that IO_ADDRESS() will not work on this SoC,
and therefore all mappings have to be through ioremap().

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v6: unchanged from v5
v5: simplified watchdog reset code
v5: removed edma iotable entry
v5: updated soc_info interface according to ioremap patch series
v5: reuse davinci serial init code, now that it is generalized enough
v5: allow boards to use nand device on any emif chip select
v5: sorted base address definitions
v4: macroized clock definitions to reduce code volume
v4: moved to new davinci_io_init() mechanism (earlier in this series)
v4: squashed tnetv107x.h header and watchdog reset patches into this
v4: moved all platform_device definitions into soc code, accessible to board
    specific code via tnetv107x_devices_init()
v3: eliminated recalc routines for pll and leaf clocks
v3: stripped "clk_" prefix from clock names
v3: use newly added div_ratio_mask functionality (earlier in this series)
v3: move from fixed_ioremap to __davinci_ioremap() implementation (earlier in
    this series

 arch/arm/mach-davinci/Kconfig                  |    5 +
 arch/arm/mach-davinci/Makefile                 |    1 +
 arch/arm/mach-davinci/devices-tnetv107x.c      |  318 ++++++++++
 arch/arm/mach-davinci/include/mach/tnetv107x.h |   56 ++
 arch/arm/mach-davinci/tnetv107x.c              |  753 ++++++++++++++++++++++++
 5 files changed, 1133 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-davinci/devices-tnetv107x.c
 create mode 100644 arch/arm/mach-davinci/include/mach/tnetv107x.h
 create mode 100644 arch/arm/mach-davinci/tnetv107x.c

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0316e20..a67b47b 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -50,6 +50,11 @@ config ARCH_DAVINCI_DM365
 	select AINTC
 	select ARCH_DAVINCI_DMx
 
+config ARCH_DAVINCI_TNETV107X
+	select CPU_V6
+	select CP_INTC
+	bool "TNETV107X based system"
+
 comment "DaVinci Board Type"
 
 config MACH_DAVINCI_EVM
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 6aac880..1c7bcfe 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= dm365.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o
+obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += tnetv107x.o devices-tnetv107x.o
 
 obj-$(CONFIG_AINTC)			+= irq.o
 obj-$(CONFIG_CP_INTC)			+= cp_intc.o
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
new file mode 100644
index 0000000..4eef6cc
--- /dev/null
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -0,0 +1,318 @@
+/*
+ * Texas Instruments TNETV107X SoC devices
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/edma.h>
+#include <mach/tnetv107x.h>
+
+#include "clock.h"
+
+/* Base addresses for on-chip devices */
+#define TNETV107X_TPCC_BASE			0x01c00000
+#define TNETV107X_TPTC0_BASE			0x01c10000
+#define TNETV107X_TPTC1_BASE			0x01c10400
+#define TNETV107X_WDOG_BASE			0x08086700
+#define TNETV107X_SDIO0_BASE			0x08088700
+#define TNETV107X_SDIO1_BASE			0x08088800
+#define TNETV107X_ASYNC_EMIF_CNTRL_BASE		0x08200000
+#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE	0x30000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE	0x40000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE	0x44000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
+
+/* TNETV107X specific EDMA3 information */
+#define EDMA_TNETV107X_NUM_DMACH	64
+#define EDMA_TNETV107X_NUM_TCC		64
+#define EDMA_TNETV107X_NUM_PARAMENTRY	128
+#define EDMA_TNETV107X_NUM_EVQUE	2
+#define EDMA_TNETV107X_NUM_TC		2
+#define EDMA_TNETV107X_CHMAP_EXIST	0
+#define EDMA_TNETV107X_NUM_REGIONS	4
+#define TNETV107X_DMACH2EVENT_MAP0	0x3C0CE000u
+#define TNETV107X_DMACH2EVENT_MAP1	0x000FFFFFu
+
+#define TNETV107X_DMACH_SDIO0_RX		26
+#define TNETV107X_DMACH_SDIO0_TX		27
+#define TNETV107X_DMACH_SDIO1_RX		28
+#define TNETV107X_DMACH_SDIO1_TX		29
+
+static const s8 edma_tc_mapping[][2] = {
+	/* event queue no	TC no	*/
+	{	 0,		 0	},
+	{	 1,		 1	},
+	{	-1,		-1	}
+};
+
+static const s8 edma_priority_mapping[][2] = {
+	/* event queue no	Prio	*/
+	{	 0,		 3	},
+	{	 1,		 7	},
+	{	-1,		-1	}
+};
+
+static struct edma_soc_info edma_info[] = {
+	{
+		.n_channel		= EDMA_TNETV107X_NUM_DMACH,
+		.n_region		= EDMA_TNETV107X_NUM_REGIONS,
+		.n_slot			= EDMA_TNETV107X_NUM_PARAMENTRY,
+		.n_tc			= EDMA_TNETV107X_NUM_TC,
+		.n_cc			= 1,
+		.queue_tc_mapping	= edma_tc_mapping,
+		.queue_priority_mapping	= edma_priority_mapping,
+	},
+};
+
+static struct resource edma_resources[] = {
+	{
+		.name	= "edma_cc0",
+		.start	= TNETV107X_TPCC_BASE,
+		.end	= TNETV107X_TPCC_BASE + SZ_32K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma_tc0",
+		.start	= TNETV107X_TPTC0_BASE,
+		.end	= TNETV107X_TPTC0_BASE + SZ_1K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma_tc1",
+		.start	= TNETV107X_TPTC1_BASE,
+		.end	= TNETV107X_TPTC1_BASE + SZ_1K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma0",
+		.start	= IRQ_TNETV107X_TPCC,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "edma0_err",
+		.start	= IRQ_TNETV107X_TPCC_ERR,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device edma_device = {
+	.name		= "edma",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(edma_resources),
+	.resource	= edma_resources,
+	.dev.platform_data = edma_info,
+};
+
+static struct plat_serial8250_port serial_data[] = {
+	{
+		.mapbase	= TNETV107X_UART0_BASE,
+		.irq		= IRQ_TNETV107X_UART0,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.mapbase	= TNETV107X_UART1_BASE,
+		.irq		= IRQ_TNETV107X_UART1,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.mapbase	= TNETV107X_UART2_BASE,
+		.irq		= IRQ_TNETV107X_UART2,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.flags	= 0,
+	},
+};
+
+struct platform_device tnetv107x_serial_device = {
+	.name			= "serial8250",
+	.id			= PLAT8250_DEV_PLATFORM,
+	.dev.platform_data	= serial_data,
+};
+
+static struct resource mmc0_resources[] = {
+	{ /* Memory mapped registers */
+		.start	= TNETV107X_SDIO0_BASE,
+		.end	= TNETV107X_SDIO0_BASE + 0x0ff,
+		.flags	= IORESOURCE_MEM
+	},
+	{ /* MMC interrupt */
+		.start	= IRQ_TNETV107X_MMC0,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* SDIO interrupt */
+		.start	= IRQ_TNETV107X_SDIO0,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* DMA RX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX),
+		.flags	= IORESOURCE_DMA
+	},
+	{ /* DMA TX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX),
+		.flags	= IORESOURCE_DMA
+	},
+};
+
+static struct resource mmc1_resources[] = {
+	{ /* Memory mapped registers */
+		.start	= TNETV107X_SDIO1_BASE,
+		.end	= TNETV107X_SDIO1_BASE + 0x0ff,
+		.flags	= IORESOURCE_MEM
+	},
+	{ /* MMC interrupt */
+		.start	= IRQ_TNETV107X_MMC1,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* SDIO interrupt */
+		.start	= IRQ_TNETV107X_SDIO1,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* DMA RX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX),
+		.flags	= IORESOURCE_DMA
+	},
+	{ /* DMA TX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX),
+		.flags	= IORESOURCE_DMA
+	},
+};
+
+static u64 mmc0_dma_mask = DMA_BIT_MASK(32);
+static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device mmc_devices[2] = {
+	{
+		.name		= "davinci_mmc",
+		.id		= 0,
+		.dev		= {
+			.dma_mask		= &mmc0_dma_mask,
+			.coherent_dma_mask	= DMA_BIT_MASK(32),
+		},
+		.num_resources	= ARRAY_SIZE(mmc0_resources),
+		.resource	= mmc0_resources
+	},
+	{
+		.name		= "davinci_mmc",
+		.id		= 1,
+		.dev		= {
+			.dma_mask		= &mmc1_dma_mask,
+			.coherent_dma_mask	= DMA_BIT_MASK(32),
+		},
+		.num_resources	= ARRAY_SIZE(mmc1_resources),
+		.resource	= mmc1_resources
+	},
+};
+
+static const u32 emif_windows[] = {
+	TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE,
+	TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE,
+};
+
+static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M };
+
+static struct resource wdt_resources[] = {
+	{
+		.start	= TNETV107X_WDOG_BASE,
+		.end	= TNETV107X_WDOG_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device tnetv107x_wdt_device = {
+	.name		= "tnetv107x_wdt",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(wdt_resources),
+	.resource	= wdt_resources,
+};
+
+static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
+{
+	struct resource res[2];
+	struct platform_device *pdev;
+	u32	range;
+	int	ret;
+
+	/* Figure out the resource range from the ale/cle masks */
+	range = max(data->mask_cle, data->mask_ale);
+	range = PAGE_ALIGN(range + 4) - 1;
+
+	if (range >= emif_window_sizes[chipsel])
+		return -EINVAL;
+
+	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+	if (!pdev)
+		return -ENOMEM;
+
+	pdev->name		= "davinci_nand";
+	pdev->id		= chipsel;
+	pdev->dev.platform_data	= data;
+
+	memset(res, 0, sizeof(res));
+
+	res[0].start	= emif_windows[chipsel];
+	res[0].end	= res[0].start + range;
+	res[0].flags	= IORESOURCE_MEM;
+
+	res[1].start	= TNETV107X_ASYNC_EMIF_CNTRL_BASE;
+	res[1].end	= res[1].start + SZ_4K - 1;
+	res[1].flags	= IORESOURCE_MEM;
+
+	ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
+	if (ret < 0) {
+		kfree(pdev);
+		return ret;
+	}
+
+	return platform_device_register(pdev);
+}
+
+void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
+{
+	int i;
+
+	platform_device_register(&edma_device);
+	platform_device_register(&tnetv107x_wdt_device);
+
+	if (info->serial_config)
+		davinci_serial_init(info->serial_config);
+
+	for (i = 0; i < 2; i++)
+		if (info->mmc_config[i]) {
+			mmc_devices[i].dev.platform_data = info->mmc_config[i];
+			platform_device_register(&mmc_devices[i]);
+		}
+
+	for (i = 0; i < 4; i++)
+		if (info->nand_config[i])
+			nand_init(i, info->nand_config[i]);
+}
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
new file mode 100644
index 0000000..cc44678
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -0,0 +1,56 @@
+/*
+ * Texas Instruments TNETV107X SoC Specific Defines
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
+#define __ASM_ARCH_DAVINCI_TNETV107X_H
+
+#include <asm/sizes.h>
+
+#define TNETV107X_DDR_BASE	0x80000000
+
+/*
+ * Fixed mapping for early init starts here. If low-level debug is enabled,
+ * this area also gets mapped via io_pg_offset and io_phys by the boot code.
+ * To fit in with the io_pg_offset calculation, the io base address selected
+ * here _must_ be a multiple of 2^20.
+ */
+#define TNETV107X_IO_BASE	0x08000000
+#define TNETV107X_IO_VIRT	(IO_VIRT + SZ_1M)
+
+#define PINMUX(x)		(4 * (x))
+#define TNETV107X_N_GPIO	65
+
+#ifndef __ASSEMBLY__
+
+#include <linux/serial_8250.h>
+#include <mach/mmc.h>
+#include <mach/nand.h>
+#include <mach/serial.h>
+
+struct tnetv107x_device_info {
+	struct davinci_uart_config	*serial_config;
+	struct davinci_mmc_config	*mmc_config[2];  /* 2 controllers */
+	struct davinci_nand_pdata	*nand_config[4]; /* 4 chipsels */
+};
+
+extern struct platform_device tnetv107x_wdt_device;
+extern struct platform_device tnetv107x_serial_device;
+
+extern void __init tnetv107x_init(void);
+extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
+extern void __init tnetv107x_irq_init(void);
+
+#endif
+
+#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
new file mode 100644
index 0000000..864e604
--- /dev/null
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -0,0 +1,753 @@
+/*
+ * Texas Instruments TNETV107X SoC Support
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/common.h>
+#include <mach/time.h>
+#include <mach/cputype.h>
+#include <mach/psc.h>
+#include <mach/cp_intc.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#include <mach/hardware.h>
+#include <mach/tnetv107x.h>
+
+#include "clock.h"
+#include "mux.h"
+
+/* Base addresses for on-chip devices */
+#define TNETV107X_INTC_BASE			0x03000000
+#define TNETV107X_TIMER0_BASE			0x08086500
+#define TNETV107X_TIMER1_BASE			0x08086600
+#define TNETV107X_CHIP_CFG_BASE			0x08087000
+#define TNETV107X_GPIO_BASE			0x08088000
+#define TNETV107X_CLOCK_CONTROL_BASE		0x0808a000
+#define TNETV107X_PSC_BASE			0x0808b000
+
+/* Reference clock frequencies */
+#define OSC_FREQ_ONCHIP		(24000 * 1000)
+#define OSC_FREQ_OFFCHIP_SYS	(25000 * 1000)
+#define OSC_FREQ_OFFCHIP_ETH	(25000 * 1000)
+#define OSC_FREQ_OFFCHIP_TDM	(19200 * 1000)
+
+#define N_PLLS	3
+
+/* Clock Control Registers */
+struct clk_ctrl_regs {
+	u32	pll_bypass;
+	u32	_reserved0;
+	u32	gem_lrst;
+	u32	_reserved1;
+	u32	pll_unlock_stat;
+	u32	sys_unlock;
+	u32	eth_unlock;
+	u32	tdm_unlock;
+};
+
+/* SSPLL Registers */
+struct sspll_regs {
+	u32	modes;
+	u32	post_div;
+	u32	pre_div;
+	u32	mult_factor;
+	u32	divider_range;
+	u32	bw_divider;
+	u32	spr_amount;
+	u32	spr_rate_div;
+	u32	diag;
+};
+
+/* Watchdog Timer Registers */
+struct wdt_regs {
+	u32	kick_lock;
+	u32	kick;
+	u32	change_lock;
+	u32	change ;
+	u32	disable_lock;
+	u32	disable;
+	u32	prescale_lock;
+	u32	prescale;
+};
+
+static struct clk_ctrl_regs __iomem *clk_ctrl_regs;
+
+static struct sspll_regs __iomem *sspll_regs[N_PLLS];
+static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 };
+
+/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */
+static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) };
+
+/* offchip (external) reference clock frequencies */
+static u32 pll_ext_freq[] = {
+	OSC_FREQ_OFFCHIP_SYS,
+	OSC_FREQ_OFFCHIP_TDM,
+	OSC_FREQ_OFFCHIP_ETH
+};
+
+/* PSC control registers */
+static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE };
+
+/* Host map for interrupt controller */
+static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 };
+
+static unsigned long clk_sspll_recalc(struct clk *clk);
+
+/* Level 1 - the PLLs */
+#define define_pll_clk(cname, pll, divmask, base)	\
+	static struct pll_data pll_##cname##_data = {	\
+		.num		= pll,			\
+		.div_ratio_mask	= divmask,		\
+		.phys_base	= base +		\
+			TNETV107X_CLOCK_CONTROL_BASE,	\
+	};						\
+	static struct clk pll_##cname##_clk = {		\
+		.name		= "pll_" #cname "_clk",	\
+		.pll_data	= &pll_##cname##_data,	\
+		.flags		= CLK_PLL,		\
+		.recalc		= clk_sspll_recalc,	\
+	}
+
+define_pll_clk(sys, 0, 0x1ff, 0x600);
+define_pll_clk(tdm, 1, 0x0ff, 0x200);
+define_pll_clk(eth, 2, 0x0ff, 0x400);
+
+/* Level 2 - divided outputs from the PLLs */
+#define define_pll_div_clk(pll, cname, div)		\
+	static struct clk pll##_##cname##_clk = {	\
+		.name		= #pll "_" #cname "_clk",\
+		.parent		= &pll_##pll##_clk,	\
+		.flags		= CLK_PLL,		\
+		.div_reg	= PLLDIV##div,		\
+	}
+
+define_pll_div_clk(sys, arm1176,	1);
+define_pll_div_clk(sys, dsp,		2);
+define_pll_div_clk(sys, ddr,		3);
+define_pll_div_clk(sys, full,		4);
+define_pll_div_clk(sys, lcd,		5);
+define_pll_div_clk(sys, vlynq_ref,	6);
+define_pll_div_clk(sys, tsc,		7);
+define_pll_div_clk(sys, half,		8);
+
+define_pll_div_clk(eth, 5mhz,		1);
+define_pll_div_clk(eth, 50mhz,		2);
+define_pll_div_clk(eth, 125mhz,		3);
+define_pll_div_clk(eth, 250mhz,		4);
+define_pll_div_clk(eth, 25mhz,		5);
+
+define_pll_div_clk(tdm, 0,		1);
+define_pll_div_clk(tdm, extra,		2);
+define_pll_div_clk(tdm, 1,		3);
+
+
+/* Level 3 - LPSC gated clocks */
+#define __lpsc_clk(cname, _parent, mod, flg)		\
+	static struct clk clk_##cname = {		\
+		.name		= #cname,		\
+		.parent		= &_parent,		\
+		.lpsc		= TNETV107X_LPSC_##mod,\
+		.flags		= flg,			\
+	}
+
+#define lpsc_clk_enabled(cname, parent, mod)		\
+	__lpsc_clk(cname, parent, mod, ALWAYS_ENABLED)
+
+#define lpsc_clk(cname, parent, mod)			\
+	__lpsc_clk(cname, parent, mod, 0)
+
+lpsc_clk_enabled(arm,		sys_arm1176_clk, ARM);
+lpsc_clk_enabled(gem,		sys_dsp_clk,	GEM);
+lpsc_clk_enabled(ddr2_phy,	sys_ddr_clk,	DDR2_PHY);
+lpsc_clk_enabled(tpcc,		sys_full_clk,	TPCC);
+lpsc_clk_enabled(tptc0,		sys_full_clk,	TPTC0);
+lpsc_clk_enabled(tptc1,		sys_full_clk,	TPTC1);
+lpsc_clk_enabled(ram,		sys_full_clk,	RAM);
+lpsc_clk_enabled(aemif,		sys_full_clk,	AEMIF);
+lpsc_clk_enabled(chipcfg,	sys_half_clk,	CHIP_CFG);
+lpsc_clk_enabled(rom,		sys_half_clk,	ROM);
+lpsc_clk_enabled(secctl,	sys_half_clk,	SECCTL);
+lpsc_clk_enabled(keymgr,	sys_half_clk,	KEYMGR);
+lpsc_clk_enabled(gpio,		sys_half_clk,	GPIO);
+lpsc_clk_enabled(debugss,	sys_half_clk,	DEBUGSS);
+lpsc_clk_enabled(system,	sys_half_clk,	SYSTEM);
+lpsc_clk_enabled(ddr2_vrst,	sys_ddr_clk,	DDR2_EMIF1_VRST);
+lpsc_clk_enabled(ddr2_vctl_rst,	sys_ddr_clk,	DDR2_EMIF2_VCTL_RST);
+lpsc_clk_enabled(wdt_arm,	sys_half_clk,	WDT_ARM);
+
+lpsc_clk(mbx_lite,	sys_arm1176_clk,	MBX_LITE);
+lpsc_clk(ethss,		eth_125mhz_clk,		ETHSS);
+lpsc_clk(tsc,		sys_tsc_clk,		TSC);
+lpsc_clk(uart0,		sys_half_clk,		UART0);
+lpsc_clk(uart1,		sys_half_clk,		UART1);
+lpsc_clk(uart2,		sys_half_clk,		UART2);
+lpsc_clk(pktsec,	sys_half_clk,		PKTSEC);
+lpsc_clk(keypad,	sys_half_clk,		KEYPAD);
+lpsc_clk(mdio,		sys_half_clk,		MDIO);
+lpsc_clk(sdio0,		sys_half_clk,		SDIO0);
+lpsc_clk(sdio1,		sys_half_clk,		SDIO1);
+lpsc_clk(timer0,	sys_half_clk,		TIMER0);
+lpsc_clk(timer1,	sys_half_clk,		TIMER1);
+lpsc_clk(wdt_dsp,	sys_half_clk,		WDT_DSP);
+lpsc_clk(ssp,		sys_half_clk,		SSP);
+lpsc_clk(tdm0,		tdm_0_clk,		TDM0);
+lpsc_clk(tdm1,		tdm_1_clk,		TDM1);
+lpsc_clk(vlynq,		sys_vlynq_ref_clk,	VLYNQ);
+lpsc_clk(mcdma,		sys_half_clk,		MCDMA);
+lpsc_clk(usb0,		sys_half_clk,		USB0);
+lpsc_clk(usb1,		sys_half_clk,		USB1);
+lpsc_clk(usbss,		sys_half_clk,		USBSS);
+lpsc_clk(ethss_rgmii,	eth_250mhz_clk,		ETHSS_RGMII);
+lpsc_clk(imcop,		sys_dsp_clk,		IMCOP);
+lpsc_clk(spare,		sys_half_clk,		SPARE);
+
+/* LCD needs a full power down to clear controller state */
+__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE);
+
+
+/* Level 4 - leaf clocks for LPSC modules shared across drivers */
+static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec };
+static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec };
+
+static struct clk_lookup clks[] = {
+	CLK(NULL,		"pll_sys_clk",		&pll_sys_clk),
+	CLK(NULL,		"pll_eth_clk",		&pll_eth_clk),
+	CLK(NULL,		"pll_tdm_clk",		&pll_tdm_clk),
+	CLK(NULL,		"sys_arm1176_clk",	&sys_arm1176_clk),
+	CLK(NULL,		"sys_dsp_clk",		&sys_dsp_clk),
+	CLK(NULL,		"sys_ddr_clk",		&sys_ddr_clk),
+	CLK(NULL,		"sys_full_clk",		&sys_full_clk),
+	CLK(NULL,		"sys_lcd_clk",		&sys_lcd_clk),
+	CLK(NULL,		"sys_vlynq_ref_clk",	&sys_vlynq_ref_clk),
+	CLK(NULL,		"sys_tsc_clk",		&sys_tsc_clk),
+	CLK(NULL,		"sys_half_clk",		&sys_half_clk),
+	CLK(NULL,		"eth_5mhz_clk",		&eth_5mhz_clk),
+	CLK(NULL,		"eth_50mhz_clk",	&eth_50mhz_clk),
+	CLK(NULL,		"eth_125mhz_clk",	&eth_125mhz_clk),
+	CLK(NULL,		"eth_250mhz_clk",	&eth_250mhz_clk),
+	CLK(NULL,		"eth_25mhz_clk",	&eth_25mhz_clk),
+	CLK(NULL,		"tdm_0_clk",		&tdm_0_clk),
+	CLK(NULL,		"tdm_extra_clk",	&tdm_extra_clk),
+	CLK(NULL,		"tdm_1_clk",		&tdm_1_clk),
+	CLK(NULL,		"clk_arm",		&clk_arm),
+	CLK(NULL,		"clk_gem",		&clk_gem),
+	CLK(NULL,		"clk_ddr2_phy",		&clk_ddr2_phy),
+	CLK(NULL,		"clk_tpcc",		&clk_tpcc),
+	CLK(NULL,		"clk_tptc0",		&clk_tptc0),
+	CLK(NULL,		"clk_tptc1",		&clk_tptc1),
+	CLK(NULL,		"clk_ram",		&clk_ram),
+	CLK(NULL,		"clk_mbx_lite",		&clk_mbx_lite),
+	CLK("tnetv107x-fb.0",	NULL,			&clk_lcd),
+	CLK(NULL,		"clk_ethss",		&clk_ethss),
+	CLK(NULL,		"aemif",		&clk_aemif),
+	CLK(NULL,		"clk_chipcfg",		&clk_chipcfg),
+	CLK("tnetv107x-ts.0",	NULL,			&clk_tsc),
+	CLK(NULL,		"clk_rom",		&clk_rom),
+	CLK(NULL,		"uart2",		&clk_uart2),
+	CLK(NULL,		"clk_pktsec",		&clk_pktsec),
+	CLK("tnetv107x-rng.0",	NULL,			&clk_rng),
+	CLK("tnetv107x-pka.0",	NULL,			&clk_pka),
+	CLK(NULL,		"clk_secctl",		&clk_secctl),
+	CLK(NULL,		"clk_keymgr",		&clk_keymgr),
+	CLK("tnetv107x-keypad.0", NULL,			&clk_keypad),
+	CLK(NULL,		"clk_gpio",		&clk_gpio),
+	CLK(NULL,		"clk_mdio",		&clk_mdio),
+	CLK("davinci_mmc.0",	NULL,			&clk_sdio0),
+	CLK(NULL,		"uart0",		&clk_uart0),
+	CLK(NULL,		"uart1",		&clk_uart1),
+	CLK(NULL,		"timer0",		&clk_timer0),
+	CLK(NULL,		"timer1",		&clk_timer1),
+	CLK("tnetv107x_wdt.0",	NULL,			&clk_wdt_arm),
+	CLK(NULL,		"clk_wdt_dsp",		&clk_wdt_dsp),
+	CLK("ti-ssp.0",		NULL,			&clk_ssp),
+	CLK(NULL,		"clk_tdm0",		&clk_tdm0),
+	CLK(NULL,		"clk_vlynq",		&clk_vlynq),
+	CLK(NULL,		"clk_mcdma",		&clk_mcdma),
+	CLK(NULL,		"clk_usb0",		&clk_usb0),
+	CLK(NULL,		"clk_tdm1",		&clk_tdm1),
+	CLK(NULL,		"clk_debugss",		&clk_debugss),
+	CLK(NULL,		"clk_ethss_rgmii",	&clk_ethss_rgmii),
+	CLK(NULL,		"clk_system",		&clk_system),
+	CLK(NULL,		"clk_imcop",		&clk_imcop),
+	CLK(NULL,		"clk_spare",		&clk_spare),
+	CLK("davinci_mmc.1",	NULL,			&clk_sdio1),
+	CLK(NULL,		"clk_usb1",		&clk_usb1),
+	CLK(NULL,		"clk_usbss",		&clk_usbss),
+	CLK(NULL,		"clk_ddr2_vrst",	&clk_ddr2_vrst),
+	CLK(NULL,		"clk_ddr2_vctl_rst",	&clk_ddr2_vctl_rst),
+	CLK(NULL,		NULL,			NULL),
+};
+
+static const struct mux_config pins[] = {
+#ifdef CONFIG_DAVINCI_MUX
+	MUX_CFG(TNETV107X, ASR_A00,		0, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO32,		0, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A01,		0, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO33,		0, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A02,		0, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO34,		0, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A03,		0, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO35,		0, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A04,		0, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO36,		0, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A05,		0, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO37,		0, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A06,		1, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO38,		1, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A07,		1, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO39,		1, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A08,		1, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO40,		1, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A09,		1, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO41,		1, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A10,		1, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO42,		1, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A11,		1, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_0,		1, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A12,		2, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_1,		2, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A13,		2, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO43,		2, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A14,		2, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO44,		2, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A15,		2, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO45,		2, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A16,		2, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO46,		2, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A17,		2, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO47,		2, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A18,		3, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO48,		3, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA3_0,	3, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A19,		3, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO49,		3, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA2_0,	3, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A20,		3, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO50,		3, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA1_0,	3, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A21,		3, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO51,		3, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA0_0,	3, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A22,		3, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO52,		3, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_CMD_0,		3, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A23,		3, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO53,		3, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_CLK_0,		3, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_BA_1,		4, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO54,		4, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SYS_PLL_CLK,		4, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_CS0,		4, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_CS1,		4, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_CS2,		4, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM_PLL_CLK,		4, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_CS3,		4, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ETH_PHY_CLK,		4, 20, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, ASR_D00,		4, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO55,		4, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D01,		5, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO56,		5, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D02,		5, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO57,		5, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D03,		5, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO58,		5, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D04,		5, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO59_0,		5, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D05,		5, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO60_0,		5, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D06,		5, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO61_0,		5, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D07,		6, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO62_0,		6, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D08,		6, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO63_0,		6, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D09,		6, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO64_0,		6, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D10,		6, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA3_1,	6, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D11,		6, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA2_1,	6, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D12,		6, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA1_1,	6, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D13,		7, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA0_1,	7, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D14,		7, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_CMD_1,		7, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D15,		7, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_CLK_1,		7, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_OE,		7, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_2,		7, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_RNW,		7, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO29_0,		7, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_WAIT,		7, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO30_0,		7, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_WE,		8, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_3,		8, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_WE_DQM0,		8, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO31,		8, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD17_0,		8, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_WE_DQM1,		8, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_BA0_0,		8, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, VLYNQ_CLK,		9, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO14,		9, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD19_0,		9, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_RXD0,		9, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO15,		9, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD20_0,		9, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_RXD1,		9, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO16,		9, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD21_0,		9, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_TXD0,		9, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO17,		9, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD22_0,		9, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_TXD1,		9, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO18,		9, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD23_0,		9, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, SDIO0_CLK,		10, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO19,		10, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_CMD,		10, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO20,		10, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA0,		10, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO21,		10, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA1,		10, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO22,		10, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA2,		10, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO23,		10, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA3,		10, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO24,		10, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, EMU0,		11, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, EMU1,		11, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, RTCK,		12, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TRST_N,		12, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TCK,			12, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDI,			12, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDO,			12, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TMS,			12, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_CLK,		13, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_RX,		13, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_TX,		13, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_FS,		13, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R0,		14, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R1,		14, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R2,		14, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R3,		14, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R4,		14, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R5,		14, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R6,		15, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO12,		15, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, KEYPAD_R7,		15, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO10,		15, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, KEYPAD_C0,		15, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C1,		15, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C2,		15, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C3,		15, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C4,		16, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C5,		16, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C6,		16, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO13,		16, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, TEST_CLK_IN,		16, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, KEYPAD_C7,		16, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO11,		16, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SSP0_0,		17, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_DCLK,		17, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD20_1,		17, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP0_1,		17, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_CS_N,		17, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD21_1,		17, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP0_2,		17, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_D,		17, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD22_1,		17, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP0_3,		17, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_RESETN,		17, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD23_1,		17, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_0,		18, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO25,		18, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_CTS,		18, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_1,		18, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO26,		18, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_RD,		18, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_2,		18, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO27,		18, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_RTS,		18, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_3,		18, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO28,		18, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_TD,		18, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, UART0_CTS,		19, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART0_RD,		19, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART0_RTS,		19, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART0_TD,		19, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART1_RD,		19, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART1_TD,		19, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_AC_NCS,		20, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_HSYNC_RNW,	20, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_VSYNC_A0,	20, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_MCLK,		20, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD16_0,		20, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PCLK_E,		20, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD00,		20, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD01,		21, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD02,		21, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD03,		21, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD04,		21, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD05,		21, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD06,		21, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD07,		22, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD08,		22, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO59_1,		22, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD09,		22, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO60_1,		22, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD10,		22, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_BA0_1,		22, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO61_1,		22, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD11,		22, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO62_1,		22, 20, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD12,		22, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO63_1,		22, 25, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD13,		23, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO64_1,		23, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD14,		23, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO29_1,		23, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD15,		23, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO30_1,		23, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, EINT0,		24, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO08,		24, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, EINT1,		24, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO09,		24, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO00,		24, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD20_2,		24, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, TDM_CLK_IN_2,	24, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO01,		24, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD21_2,		24, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, 24M_CLK_OUT_1,	24, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO02,		24, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD22_2,		24, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO03,		24, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD23_2,		24, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO04,		25, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD16_1,		25, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, USB0_RXERR,		25, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO05,		25, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD17_1,		25, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, TDM_CLK_IN_1,	25, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO06,		25, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD18,		25, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, 24M_CLK_OUT_2,	25, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO07,		25, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD19_1,		25, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, USB1_RXERR,		25, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, ETH_PLL_CLK,		25, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, MDIO,		26, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, MDC,			26, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, AIC_MUTE_STAT_N,	26, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_CLK,		26, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, AIC_HNS_EN_N,	26, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_FS,		26, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N,	26, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_TX,		26, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N,	26, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_RX,		26, 25, 0x1f, 0x04, false)
+#endif
+};
+
+/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
+static u8 irq_prios[TNETV107X_N_CP_INTC_IRQ] = {
+	/* fill in default priority 7 */
+	[0 ... (TNETV107X_N_CP_INTC_IRQ - 1)]	= 7,
+	/* now override as needed, e.g. [xxx] = 5 */
+};
+
+/* Contents of JTAG ID register used to identify exact cpu type */
+static struct davinci_id ids[] = {
+	{
+		.variant	= 0x0,
+		.part_no	= 0xb8a1,
+		.manufacturer	= 0x017,
+		.cpu_id		= DAVINCI_CPU_ID_TNETV107X,
+		.name		= "tnetv107x rev1.0",
+	},
+};
+
+static struct davinci_timer_instance timer_instance[2] = {
+	{
+		.base		= TNETV107X_TIMER0_BASE,
+		.bottom_irq	= IRQ_TNETV107X_TIMER_0_TINT12,
+		.top_irq	= IRQ_TNETV107X_TIMER_0_TINT34,
+	},
+	{
+		.base		= TNETV107X_TIMER1_BASE,
+		.bottom_irq	= IRQ_TNETV107X_TIMER_1_TINT12,
+		.top_irq	= IRQ_TNETV107X_TIMER_1_TINT34,
+	},
+};
+
+static struct davinci_timer_info timer_info = {
+	.timers		= timer_instance,
+	.clockevent_id	= T0_BOT,
+	.clocksource_id	= T0_TOP,
+};
+
+/*
+ * TNETV107X platforms do not use the static mappings from Davinci
+ * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses,
+ * and changing IO_PHYS would break away from existing Davinci SOCs.
+ *
+ * The primary impact of the current model is that IO_ADDRESS() is not to be
+ * used to map registers on TNETV107X.
+ *
+ * 1.	The first chunk is for INTC:  This needs to be mapped in via iotable
+ *	because ioremap() does not seem to be operational at the time when
+ *	irqs are initialized.  Without this, consistent dma init bombs.
+ *
+ * 2.	The second chunk maps in register areas that need to be populated into
+ *	davinci_soc_info.  Note that alignment restrictions come into play if
+ *	low-level debug is enabled (see note in <mach/tnetv107x.h>).
+ */
+static struct map_desc io_desc[] = {
+	{	/* INTC */
+		.virtual	= IO_VIRT,
+		.pfn		= __phys_to_pfn(TNETV107X_INTC_BASE),
+		.length		= SZ_16K,
+		.type		= MT_DEVICE
+	},
+	{	/* Most of the rest */
+		.virtual	= TNETV107X_IO_VIRT,
+		.pfn		= __phys_to_pfn(TNETV107X_IO_BASE),
+		.length		= IO_SIZE - SZ_1M,
+		.type		= MT_DEVICE
+	},
+};
+
+static unsigned long clk_sspll_recalc(struct clk *clk)
+{
+	int		pll;
+	unsigned long	mult = 0, prediv = 1, postdiv = 1;
+	unsigned long	ref = OSC_FREQ_ONCHIP, ret;
+	u32		tmp;
+
+	if (WARN_ON(!clk->pll_data))
+		return clk->rate;
+
+	if (!clk_ctrl_regs) {
+		void __iomem *tmp;
+
+		tmp = ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K);
+
+		if (WARN(!tmp, "failed ioremap for clock control regs\n"))
+			return clk->parent ? clk->parent->rate : 0;
+
+		for (pll = 0; pll < N_PLLS; pll++)
+			sspll_regs[pll] = tmp + sspll_regs_base[pll];
+
+		clk_ctrl_regs = tmp;
+	}
+
+	pll = clk->pll_data->num;
+
+	tmp = __raw_readl(&clk_ctrl_regs->pll_bypass);
+	if (!(tmp & bypass_mask[pll])) {
+		mult	= __raw_readl(&sspll_regs[pll]->mult_factor);
+		prediv	= __raw_readl(&sspll_regs[pll]->pre_div) + 1;
+		postdiv	= __raw_readl(&sspll_regs[pll]->post_div) + 1;
+	}
+
+	tmp = __raw_readl(clk->pll_data->base + PLLCTL);
+	if (tmp & PLLCTL_CLKMODE)
+		ref = pll_ext_freq[pll];
+
+	clk->pll_data->input_rate = ref;
+
+	tmp = __raw_readl(clk->pll_data->base + PLLCTL);
+	if (!(tmp & PLLCTL_PLLEN))
+		return ref;
+
+	ret = ref;
+	if (mult)
+		ret += ((unsigned long long)ref * mult) / 256;
+
+	ret /= (prediv * postdiv);
+
+	return ret;
+}
+
+static void tnetv107x_watchdog_reset(struct platform_device *pdev)
+{
+	struct wdt_regs __iomem *regs;
+
+	regs = ioremap(pdev->resource[0].start, SZ_4K);
+
+	/* disable watchdog */
+	__raw_writel(0x7777, &regs->disable_lock);
+	__raw_writel(0xcccc, &regs->disable_lock);
+	__raw_writel(0xdddd, &regs->disable_lock);
+	__raw_writel(0, &regs->disable);
+
+	/* program prescale */
+	__raw_writel(0x5a5a, &regs->prescale_lock);
+	__raw_writel(0xa5a5, &regs->prescale_lock);
+	__raw_writel(0, &regs->prescale);
+
+	/* program countdown */
+	__raw_writel(0x6666, &regs->change_lock);
+	__raw_writel(0xbbbb, &regs->change_lock);
+	__raw_writel(1, &regs->change);
+
+	/* enable watchdog */
+	__raw_writel(0x7777, &regs->disable_lock);
+	__raw_writel(0xcccc, &regs->disable_lock);
+	__raw_writel(0xdddd, &regs->disable_lock);
+	__raw_writel(1, &regs->disable);
+
+	/* kick */
+	__raw_writel(0x5555, &regs->kick_lock);
+	__raw_writel(0xaaaa, &regs->kick_lock);
+	__raw_writel(1, &regs->kick);
+}
+
+static struct davinci_soc_info tnetv107x_soc_info = {
+	.io_desc		= io_desc,
+	.io_desc_num		= ARRAY_SIZE(io_desc),
+	.ids			= ids,
+	.ids_num		= ARRAY_SIZE(ids),
+	.jtag_id_reg		= TNETV107X_CHIP_CFG_BASE + 0x018,
+	.cpu_clks		= clks,
+	.psc_bases		= psc_regs,
+	.psc_bases_num		= ARRAY_SIZE(psc_regs),
+	.pinmux_base		= TNETV107X_CHIP_CFG_BASE + 0x150,
+	.pinmux_pins		= pins,
+	.pinmux_pins_num	= ARRAY_SIZE(pins),
+	.intc_type		= DAVINCI_INTC_TYPE_CP_INTC,
+	.intc_base		= TNETV107X_INTC_BASE,
+	.intc_irq_prios		= irq_prios,
+	.intc_irq_num		= TNETV107X_N_CP_INTC_IRQ,
+	.intc_host_map		= intc_host_map,
+	.gpio_base		= TNETV107X_GPIO_BASE,
+	.gpio_type		= GPIO_TYPE_TNETV107X,
+	.gpio_num		= TNETV107X_N_GPIO,
+	.timer_info		= &timer_info,
+	.serial_dev		= &tnetv107x_serial_device,
+	.reset			= tnetv107x_watchdog_reset,
+	.reset_device		= &tnetv107x_wdt_device,
+};
+
+void __init tnetv107x_init(void)
+{
+	davinci_common_init(&tnetv107x_soc_info);
+}
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 17:38:04 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 18:38:04 -0400
Subject: [PATCH v6 4/6] Davinci: tnetv107x initial gpio support
In-Reply-To: <1273271886-15190-1-git-send-email-cyril@ti.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
Message-ID: <1273271886-15190-5-git-send-email-cyril@ti.com>

This patch adds support for the tnetv107x gpio controller.

Key differences between davinci and tnetv107x controllers:
 - register map - davinci's controller is organized into banks of 32 gpios,
   tnetv107x has a single space with arrays of registers for in, out,
   direction, etc.
 - davinci's controller has separate set/clear registers for output, tnetv107x
   has a single direct mapped register.

This patch does not yet add gpio irq support on this controller.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v6: allow tnetv107x style out registers
v5: changes as per ioremap patch series, gpio base is no longer virt
v4: range check against number of tnetv107x gpios
v3: switched to spin_lock_irq from local_irq_save/restore
v3: migrated to restructured gpio framework from earlier patches in this
    series

 arch/arm/mach-davinci/Makefile            |    1 +
 arch/arm/mach-davinci/gpio-tnetv107x.c    |  205 +++++++++++++++++++++++++++++
 arch/arm/mach-davinci/include/mach/gpio.h |   27 +++-
 3 files changed, 228 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-davinci/gpio-tnetv107x.c

diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 1c7bcfe..62c5116 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= dm365.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += tnetv107x.o devices-tnetv107x.o
+obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += gpio-tnetv107x.o
 
 obj-$(CONFIG_AINTC)			+= irq.o
 obj-$(CONFIG_CP_INTC)			+= cp_intc.o
diff --git a/arch/arm/mach-davinci/gpio-tnetv107x.c b/arch/arm/mach-davinci/gpio-tnetv107x.c
new file mode 100644
index 0000000..d102986
--- /dev/null
+++ b/arch/arm/mach-davinci/gpio-tnetv107x.c
@@ -0,0 +1,205 @@
+/*
+ * Texas Instruments TNETV107X GPIO Controller
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <mach/common.h>
+#include <mach/tnetv107x.h>
+
+struct tnetv107x_gpio_regs {
+	u32	idver;
+	u32	data_in[3];
+	u32	data_out[3];
+	u32	direction[3];
+	u32	enable[3];
+};
+
+#define gpio_reg_index(gpio)	((gpio) >> 5)
+#define gpio_reg_bit(gpio)	BIT((gpio) & 0x1f)
+
+#define gpio_reg_rmw(reg, mask, val)	\
+	__raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg))
+
+#define gpio_reg_set_bit(reg, gpio)	\
+	gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio))
+
+#define gpio_reg_clear_bit(reg, gpio)	\
+	gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0)
+
+#define gpio_reg_get_bit(reg, gpio)	\
+	(__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio))
+
+#define chip2controller(chip)		\
+	container_of(chip, struct davinci_gpio_controller, chip)
+
+#define TNETV107X_GPIO_CTLRS	DIV_ROUND_UP(TNETV107X_N_GPIO, 32)
+
+static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS];
+
+static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	gpio_reg_set_bit(&regs->enable, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+
+	return 0;
+}
+
+static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	gpio_reg_clear_bit(&regs->enable, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+}
+
+static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	gpio_reg_set_bit(&regs->direction, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+
+	return 0;
+}
+
+static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
+		unsigned offset, int value)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	if (value)
+		gpio_reg_set_bit(&regs->data_out, gpio);
+	else
+		gpio_reg_clear_bit(&regs->data_out, gpio);
+
+	gpio_reg_clear_bit(&regs->direction, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+
+	return 0;
+}
+
+static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	int ret;
+
+	ret = gpio_reg_get_bit(&regs->data_in, gpio);
+
+	return ret ? 1 : 0;
+}
+
+static void tnetv107x_gpio_set(struct gpio_chip *chip,
+		unsigned offset, int value)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	if (value)
+		gpio_reg_set_bit(&regs->data_out, gpio);
+	else
+		gpio_reg_clear_bit(&regs->data_out, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+}
+
+static int __init tnetv107x_gpio_setup(void)
+{
+	int i, base;
+	unsigned ngpio;
+	struct davinci_soc_info *soc_info = &davinci_soc_info;
+	struct tnetv107x_gpio_regs *regs;
+	struct davinci_gpio_controller *ctlr;
+
+	if (soc_info->gpio_type != GPIO_TYPE_TNETV107X)
+		return 0;
+
+	ngpio = soc_info->gpio_num;
+	if (ngpio == 0) {
+		pr_err("GPIO setup:  how many GPIOs?\n");
+		return -EINVAL;
+	}
+
+	if (WARN_ON(TNETV107X_N_GPIO < ngpio))
+		ngpio = TNETV107X_N_GPIO;
+
+	regs = ioremap(soc_info->gpio_base, SZ_4K);
+	if (WARN_ON(!regs))
+		return -EINVAL;
+
+	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
+		ctlr = &chips[i];
+
+		ctlr->chip.label	= "tnetv107x";
+		ctlr->chip.can_sleep	= 0;
+		ctlr->chip.base		= base;
+		ctlr->chip.ngpio	= ngpio - base;
+		if (ctlr->chip.ngpio > 32)
+			ctlr->chip.ngpio = 32;
+
+		ctlr->chip.request		= tnetv107x_gpio_request;
+		ctlr->chip.free			= tnetv107x_gpio_free;
+		ctlr->chip.direction_input	= tnetv107x_gpio_dir_in;
+		ctlr->chip.get			= tnetv107x_gpio_get;
+		ctlr->chip.direction_output	= tnetv107x_gpio_dir_out;
+		ctlr->chip.set			= tnetv107x_gpio_set;
+
+		spin_lock_init(&ctlr->lock);
+
+		ctlr->regs	= regs;
+		ctlr->set_data	= &regs->data_out[i];
+		ctlr->clr_data	= &regs->data_out[i];
+		ctlr->in_data	= &regs->data_in[i];
+
+		gpiochip_add(&ctlr->chip);
+	}
+
+	soc_info->gpio_ctlrs = chips;
+	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
+	return 0;
+}
+pure_initcall(tnetv107x_gpio_setup);
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 504cc18..7475138 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -25,6 +25,7 @@
 
 enum davinci_gpio_type {
 	GPIO_TYPE_DAVINCI = 0,
+	GPIO_TYPE_TNETV107X,
 };
 
 /*
@@ -97,14 +98,30 @@ static inline void gpio_set_value(unsigned gpio, int value)
 {
 	if (__builtin_constant_p(value) && gpio < davinci_soc_info.gpio_num) {
 		struct davinci_gpio_controller *ctlr;
-		u32				mask;
+		u32				mask, data;
+		unsigned long			flags;
 
 		ctlr = __gpio_to_controller(gpio);
 		mask = __gpio_mask(gpio);
-		if (value)
-			__raw_writel(mask, ctlr->set_data);
-		else
-			__raw_writel(mask, ctlr->clr_data);
+
+		if (ctlr->set_data != ctlr->clr_data) {
+			/* traditional set/clear registers */
+			if (value)
+				__raw_writel(mask, ctlr->set_data);
+			else
+				__raw_writel(mask, ctlr->clr_data);
+		} else {
+			/* tnetv107x style single out register */
+			spin_lock_irqsave(&ctlr->lock, flags);
+			data = __raw_readl(ctlr->set_data);
+			if (value)
+				data |= mask;
+			else
+				data &= ~mask;
+			__raw_writel(data, ctlr->set_data);
+			spin_unlock_irqrestore(&ctlr->lock, flags);
+		}
+
 		return;
 	}
 
-- 
1.7.0.4


From cyril at ti.com  Fri May  7 17:38:06 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri,  7 May 2010 18:38:06 -0400
Subject: [PATCH v6 6/6] Davinci: tnetv107x default configuration
In-Reply-To: <1273271886-15190-1-git-send-email-cyril@ti.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
Message-ID: <1273271886-15190-7-git-send-email-cyril@ti.com>

Added default configuration for tnetv107x platforms.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v6: unchanged from v5

 arch/arm/configs/tnetv107x_defconfig | 1741 ++++++++++++++++++++++++++++++++++
 1 files changed, 1741 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/configs/tnetv107x_defconfig

diff --git a/arch/arm/configs/tnetv107x_defconfig b/arch/arm/configs/tnetv107x_defconfig
new file mode 100644
index 0000000..efc101f
--- /dev/null
+++ b/arch/arm/configs/tnetv107x_defconfig
@@ -0,0 +1,1741 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.34-rc5
+# Sun May  2 15:05:52 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+CONFIG_ARCH_DAVINCI=y
+# CONFIG_ARCH_OMAP is not set
+CONFIG_CP_INTC=y
+
+#
+# TI DaVinci Implementations
+#
+
+#
+# DaVinci Core Type
+#
+# CONFIG_ARCH_DAVINCI_DM644x is not set
+# CONFIG_ARCH_DAVINCI_DM355 is not set
+# CONFIG_ARCH_DAVINCI_DM646x is not set
+# CONFIG_ARCH_DAVINCI_DA830 is not set
+# CONFIG_ARCH_DAVINCI_DA850 is not set
+# CONFIG_ARCH_DAVINCI_DM365 is not set
+CONFIG_ARCH_DAVINCI_TNETV107X=y
+
+#
+# DaVinci Board Type
+#
+CONFIG_MACH_TNETV107X=y
+CONFIG_DAVINCI_MUX=y
+CONFIG_DAVINCI_MUX_DEBUG=y
+CONFIG_DAVINCI_MUX_WARNINGS=y
+CONFIG_DAVINCI_RESET_CLOCKS=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_V6=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_ARM_ERRATA_411920 is not set
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_LEDS=y
+# CONFIG_LEDS_CPU is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=m
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=m
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI_AMDSTD=m
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=m
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=m
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_DAVINCI=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IWMC3200TOP is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=m
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_TI_DAVINCI_EMAC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+CONFIG_INPUT_SPARSEKMAP=m
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVBUG=m
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=m
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+CONFIG_KEYBOARD_XTKBD=m
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+# CONFIG_VT_CONSOLE is not set
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_DAVINCI_WATCHDOG=m
+# CONFIG_MAX63XX_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=m
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_DAVINCI_SOC=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_3M_PCT is not set
+CONFIG_HID_A4TECH=m
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+# CONFIG_HID_DRAGONRISE is not set
+CONFIG_HID_EZKEY=m
+# CONFIG_HID_KYE is not set
+CONFIG_HID_GYRATION=m
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+CONFIG_HID_LOGITECH=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGIG940_FF is not set
+CONFIG_HID_MICROSOFT=m
+# CONFIG_HID_MOSART is not set
+CONFIG_HID_MONTEREY=m
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+CONFIG_HID_PANTHERLORD=m
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=m
+# CONFIG_HID_QUANTA is not set
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+# CONFIG_HID_STANTUM is not set
+CONFIG_HID_SUNPLUS=m
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=m
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_SOC=y
+
+#
+# DaVinci 35x and 644x USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+CONFIG_USB_MUSB_PERIPHERAL=y
+# CONFIG_USB_MUSB_OTG is not set
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_MUSB_PIO_ONLY=y
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_MASS_STORAGE is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+# CONFIG_USB_G_NOKIA is not set
+# CONFIG_USB_G_MULTI is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+CONFIG_NOP_USB_XCEIV=m
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_DAVINCI=y
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=m
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=m
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=m
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
-- 
1.7.0.4


From seek_for at 163.com  Thu May 13 00:58:04 2010
From: seek_for at 163.com (seek_for)
Date: Thu, 13 May 2010 13:58:04 +0800
Subject: did anybody has the TVP5158 driver(MCVIP for dm365)?
Message-ID: <201005131358033595344@163.com>

hello all,
I want get the tvp5158 driver for dm365,but i can not download it.
I found "mcvip_tvp5158_xxxx.zip" for dm6467,but it can not build under dm365.
can you help me?
TKS!

2010-05-13 



seek_for 
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From sshtylyov at mvista.com  Sat May  8 05:48:01 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Sat, 08 May 2010 14:48:01 +0400
Subject: [PATCH v6 4/6] Davinci: tnetv107x initial gpio support
In-Reply-To: <1273271886-15190-5-git-send-email-cyril@ti.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
	<1273271886-15190-5-git-send-email-cyril@ti.com>
Message-ID: <4BE54161.4090900@mvista.com>

Hello.

Cyril Chemparathy wrote:

> This patch adds support for the tnetv107x gpio controller.
>
> Key differences between davinci and tnetv107x controllers:
>  - register map - davinci's controller is organized into banks of 32 gpios,
>    tnetv107x has a single space with arrays of registers for in, out,
>    direction, etc.
>  - davinci's controller has separate set/clear registers for output, tnetv107x
>    has a single direct mapped register.
>
> This patch does not yet add gpio irq support on this controller.
>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>   
[...]
> diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
> index 504cc18..7475138 100644
> --- a/arch/arm/mach-davinci/include/mach/gpio.h
> +++ b/arch/arm/mach-davinci/include/mach/gpio.h
>   
[...]
> @@ -97,14 +98,30 @@ static inline void gpio_set_value(unsigned gpio, int value)
>  {
>  	if (__builtin_constant_p(value) && gpio < davinci_soc_info.gpio_num) {
>  		struct davinci_gpio_controller *ctlr;
> -		u32				mask;
> +		u32				mask, data;
> +		unsigned long			flags;
>  
>  		ctlr = __gpio_to_controller(gpio);
>  		mask = __gpio_mask(gpio);
> -		if (value)
> -			__raw_writel(mask, ctlr->set_data);
> -		else
> -			__raw_writel(mask, ctlr->clr_data);
> +
> +		if (ctlr->set_data != ctlr->clr_data) {
> +			/* traditional set/clear registers */
> +			if (value)
> +				__raw_writel(mask, ctlr->set_data);
> +			else
> +				__raw_writel(mask, ctlr->clr_data);
> +		} else {
> +			/* tnetv107x style single out register */
> +			spin_lock_irqsave(&ctlr->lock, flags);
> +			data = __raw_readl(ctlr->set_data);
> +			if (value)
> +				data |= mask;
> +			else
> +				data &= ~mask;
> +			__raw_writel(data, ctlr->set_data);
> +			spin_unlock_irqrestore(&ctlr->lock, flags);
> +		}
>   

  Sigh, now this has become too bulky for an inline function...

WBR, Sergei



From blueskyjb at roadrunner.com  Sat May  8 12:52:40 2010
From: blueskyjb at roadrunner.com (Jimmy Blair)
Date: Sat, 08 May 2010 10:52:40 -0700
Subject: DM365 audio -- bad PLL setting in tlv320aic3x driver
In-Reply-To: <B85A65D85D7EB246BE421B3FB0FBB59301E6DB7EEB@dbde02.ent.ti.com>
References: <4BE0E012.1030406@roadrunner.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E6DB7EEB@dbde02.ent.ti.com>
Message-ID: <4BE5A4E8.4070007@roadrunner.com>


Looks like it has been fixed.  I was working from a snapshot
of 2.6.32-rc2. Thanks!

> Hello Jimmy,
> 
> On Wed, May 05, 2010 at 08:33:46, Jimmy Blair wrote:
>> 44100 Hz audio plays slightly fast on the DM365.
>> This is because the tlv320aic3x driver is calculating
>> invalid PLL parameters for the WCLK.  The parameters
>> it calculates are:
>>
>> pll_p = 1, pll_r = 1, pll_j = 3, pll_d = 3450
>>
>> According to the codec datasheet, the value of J
>> should be greater than 3.  The datasheet is correct.
>> The WCLK signal is unstable, bouncing between 44200 and 44500 Hz.
> 
> Are you seeing this on latest kernel? I haven't tested
> this, but looking at the code, it looks like this has
> been taken care of in the latest kernel:
> 
> ...
>         for (r = 1; r <= 16; r++)
>                 for (p = 1; p <= 8; p++) {
>                         for (j = 4; j <= 55; j++) {
> 
> ...
> 
>                 if (j < 4 || j > 11)
>                         continue;
> ...
> 
> 

From cyril at ti.com  Sat May  8 13:24:41 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat, 08 May 2010 14:24:41 -0400
Subject: [PATCH v6 4/6] Davinci: tnetv107x initial gpio support
In-Reply-To: <4BE54161.4090900@mvista.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
	<1273271886-15190-5-git-send-email-cyril@ti.com>
	<4BE54161.4090900@mvista.com>
Message-ID: <4BE5AC69.7030605@ti.com>

Sergei,

>   Sigh, now this has become too bulky for an inline function...

I added the following to measure increase in bulk:
> void test_fn(void) {
>         extern void marker(void);
>         marker();
>         gpio_set_value(0, 0);
>         marker();
> }

Disassembly (before):
> 000003d8 <test_fn>:
[...]
>  3e4:	ebfffffe 	bl	0 <marker>
[...]
>  428:	ebfffffe 	bl	0 <marker>

Disassembly (after):
> 000003d8 <test_fn>:
[...]
>  3e4:	ebfffffe 	bl	0 <marker>
[...]
>  480:	ebfffffe 	bl	0 <marker>

Per call site, this change increases code by 88 bytes (from 68 to 156).

For an overall perspective, when built with davinci_all_defconfig and
da8xx_omapl_defconfig, compressed image sizes are:

> (before)
> [...] 1525080 May  8 13:55 davinci-test-before.uimg
> [...] 1370725 May  8 13:55 modules-davinci-test-before.tgz
> [...] 1560728 May  8 13:55 da8xx-test-before.uimg
> [...]  770842 May  8 14:55 modules-da8xx-test-before.tgz

> (after)
> [...] 1525080 May  8 13:56 davinci-test-after.uimg
> [...] 1370782 May  8 13:56 modules-davinci-test-after.tgz
> [...] 1560876 May  8 13:57 da8xx-test-after.uimg
> [...]  770866 May  8 13:57 modules-da8xx-test-after.tgz
> 


Total Growth (compressed):
	davinci	uimage	  0 bytes
	davinci	modules	 57 bytes
	da8xx	uimage	148 bytes
	da8xx	modules	 24 bytes

In this light, could you please comment on acceptable limits for inline
growth?

Regards
Cyril.

From sameo at linux.intel.com  Sun May  9 16:09:41 2010
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Sun, 9 May 2010 23:09:41 +0200
Subject: [PATCH 4/4]-V3 Add MFD driver for TPS6507x family of
	multi-function chips and move TPS6507x regulator driver from being
	stand-alone to using the MFD driver.
In-Reply-To: <87633kacmq.fsf@deeprootsystems.com>
References: <1270520639-20516-1-git-send-email-todd.fischer@ridgerun.com>
	<1270520639-20516-2-git-send-email-todd.fischer@ridgerun.com>
	<1270520639-20516-3-git-send-email-todd.fischer@ridgerun.com>
	<1270520639-20516-4-git-send-email-todd.fischer@ridgerun.com>
	<1270520639-20516-5-git-send-email-todd.fischer@ridgerun.com>
	<87633kacmq.fsf@deeprootsystems.com>
Message-ID: <20100509210940.GA3269@sortiz.org>

Hi Kevin,

On Wed, Apr 21, 2010 at 11:23:09AM -0700, Kevin Hilman wrote:
> Todd Fischer <todd.fischer at ridgerun.com> writes:
> 
> > Add MFD driver for TPS6507x family of multi-function chips.  Move TPS6507x 
> > regulator driver from being stand-alone driver to using the MFD TPS6507x driver.
> >
> > Signed-off-by: Todd Fischer <todd.fischer at ridgerun.com>
> 
> [...]
> 
> Not sure whose tree this is queued in currently, but testing with
> current davinci git, I had a compile problem...
This is fixed in the MFD tree.

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/

From anshuman at ti.com  Mon May 10 00:56:41 2010
From: anshuman at ti.com (Saxena, Anshuman)
Date: Mon, 10 May 2010 11:26:41 +0530
Subject: did anybody has the TVP5158 driver(MCVIP for dm365)?
In-Reply-To: <201005131358033595344@163.com>
References: <201005131358033595344@163.com>
Message-ID: <2A3DCF3DA181AD40BDE86A3150B27B6B030D7DF98A@dbde02.ent.ti.com>

Hi,
Can you please look at http://e2e.ti.com<http://e2e.ti.com/> ? We have MCVIP source code for TVP5158 working with DM365 on the forum. If you don't find it, you can post the same question again on forum and I can respond to it there. Sorry for redirecting you to E2E forum, but I am just trying to make it more usable for others if the source code sit on the forum and others can also access it.

Regards,
Anshuman

________________________________
From: davinci-linux-open-source-bounces+anshuman=ti.com at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces+anshuman=ti.com at linux.davincidsp.com] On Behalf Of seek_for
Sent: Thursday, May 13, 2010 11:28 AM
To: davinci-linux-open-source
Subject: did anybody has the TVP5158 driver(MCVIP for dm365)?

hello all,
I want get the tvp5158 driver for dm365,but i can not download it.
I found "mcvip_tvp5158_xxxx.zip" for dm6467,but it can not build under dm365.
can you help me?
TKS!

2010-05-13
________________________________
seek_for
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From nsekhar at ti.com  Mon May 10 02:11:18 2010
From: nsekhar at ti.com (Sekhar Nori)
Date: Mon, 10 May 2010 12:41:18 +0530
Subject: [PATCH v2 1/2] davinci: edma: use BIT() wherever possible
Message-ID: <1273475479-15573-1-git-send-email-nsekhar@ti.com>

This patch replaces occurences of (1 << x) with
BIT(x) as it makes for much better reading.

Signed-off-by: Sekhar Nori <nsekhar at ti.com>
---
v2: no functional changes from v1, just rebased to latest master

 arch/arm/mach-davinci/dma.c |   42 +++++++++++++++++++++---------------------
 1 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index cc5fcda..1922d46 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -312,16 +312,16 @@ setup_dma_interrupt(unsigned lch,
 
 	if (!callback)
 		edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
-				(1 << (lch & 0x1f)));
+				BIT(lch & 0x1f));
 
 	edma_cc[ctlr]->intr_data[lch].callback = callback;
 	edma_cc[ctlr]->intr_data[lch].data = data;
 
 	if (callback) {
 		edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
-				(1 << (lch & 0x1f)));
+				BIT(lch & 0x1f));
 		edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
-				(1 << (lch & 0x1f)));
+				BIT(lch & 0x1f));
 	}
 }
 
@@ -374,7 +374,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 							SH_IER, j) & BIT(i))) {
 				/* Clear the corresponding IPR bits */
 				edma_shadow0_write_array(ctlr, SH_ICR, j,
-							(1 << i));
+							BIT(i));
 				if (edma_cc[ctlr]->intr_data[k].callback)
 					edma_cc[ctlr]->intr_data[k].callback(
 						k, DMA_COMPLETE,
@@ -423,13 +423,13 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 			for (i = 0; i < 32; i++) {
 				int k = (j << 5) + i;
 				if (edma_read_array(ctlr, EDMA_EMR, j) &
-							(1 << i)) {
+							BIT(i)) {
 					/* Clear the corresponding EMR bits */
 					edma_write_array(ctlr, EDMA_EMCR, j,
-							1 << i);
+							BIT(i));
 					/* Clear any SER */
 					edma_shadow0_write_array(ctlr, SH_SECR,
-								j, (1 << i));
+								j, BIT(i));
 					if (edma_cc[ctlr]->intr_data[k].
 								callback) {
 						edma_cc[ctlr]->intr_data[k].
@@ -444,11 +444,11 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 			dev_dbg(data, "QEMR %02x\n",
 				edma_read(ctlr, EDMA_QEMR));
 			for (i = 0; i < 8; i++) {
-				if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) {
+				if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
 					/* Clear the corresponding IPR bits */
-					edma_write(ctlr, EDMA_QEMCR, 1 << i);
+					edma_write(ctlr, EDMA_QEMCR, BIT(i));
 					edma_shadow0_write(ctlr, SH_QSECR,
-								(1 << i));
+								BIT(i));
 
 					/* NOTE:  not reported!! */
 				}
@@ -460,9 +460,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 			 * to just write CCERRCLR with CCERR value...
 			 */
 			for (i = 0; i < 8; i++) {
-				if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) {
+				if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
 					/* Clear the corresponding IPR bits */
-					edma_write(ctlr, EDMA_CCERRCLR, 1 << i);
+					edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
 
 					/* NOTE:  not reported!! */
 				}
@@ -666,7 +666,7 @@ int edma_alloc_channel(int channel,
 	}
 
 	/* ensure access through shadow region 0 */
-	edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
+	edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
 
 	/* ensure no events are pending */
 	edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
@@ -1204,7 +1204,7 @@ void edma_pause(unsigned channel)
 	channel = EDMA_CHAN_SLOT(channel);
 
 	if (channel < edma_cc[ctlr]->num_channels) {
-		unsigned int mask = (1 << (channel & 0x1f));
+		unsigned int mask = BIT(channel & 0x1f);
 
 		edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
 	}
@@ -1225,7 +1225,7 @@ void edma_resume(unsigned channel)
 	channel = EDMA_CHAN_SLOT(channel);
 
 	if (channel < edma_cc[ctlr]->num_channels) {
-		unsigned int mask = (1 << (channel & 0x1f));
+		unsigned int mask = BIT(channel & 0x1f);
 
 		edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
 	}
@@ -1252,7 +1252,7 @@ int edma_start(unsigned channel)
 
 	if (channel < edma_cc[ctlr]->num_channels) {
 		int j = channel >> 5;
-		unsigned int mask = (1 << (channel & 0x1f));
+		unsigned int mask = BIT(channel & 0x1f);
 
 		/* EDMA channels without event association */
 		if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
@@ -1298,7 +1298,7 @@ void edma_stop(unsigned channel)
 
 	if (channel < edma_cc[ctlr]->num_channels) {
 		int j = channel >> 5;
-		unsigned int mask = (1 << (channel & 0x1f));
+		unsigned int mask = BIT(channel & 0x1f);
 
 		edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
 		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
@@ -1337,7 +1337,7 @@ void edma_clean_channel(unsigned channel)
 
 	if (channel < edma_cc[ctlr]->num_channels) {
 		int j = (channel >> 5);
-		unsigned int mask = 1 << (channel & 0x1f);
+		unsigned int mask = BIT(channel & 0x1f);
 
 		pr_debug("EDMA: EMR%d %08x\n", j,
 				edma_read_array(ctlr, EDMA_EMR, j));
@@ -1346,7 +1346,7 @@ void edma_clean_channel(unsigned channel)
 		edma_write_array(ctlr, EDMA_EMCR, j, mask);
 		/* Clear any SER */
 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
-		edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3);
+		edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
 	}
 }
 EXPORT_SYMBOL(edma_clean_channel);
@@ -1366,9 +1366,9 @@ void edma_clear_event(unsigned channel)
 	if (channel >= edma_cc[ctlr]->num_channels)
 		return;
 	if (channel < 32)
-		edma_write(ctlr, EDMA_ECR, 1 << channel);
+		edma_write(ctlr, EDMA_ECR, BIT(channel));
 	else
-		edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32));
+		edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
 }
 EXPORT_SYMBOL(edma_clear_event);
 
-- 
1.6.2.4


From nsekhar at ti.com  Mon May 10 02:11:19 2010
From: nsekhar at ti.com (Sekhar Nori)
Date: Mon, 10 May 2010 12:41:19 +0530
Subject: [PATCH 2/2] davinci: edma: fix coding style issue related to breaking
	lines
In-Reply-To: <1273475479-15573-1-git-send-email-nsekhar@ti.com>
References: <1273475479-15573-1-git-send-email-nsekhar@ti.com>
Message-ID: <1273475479-15573-2-git-send-email-nsekhar@ti.com>

In the edma driver, most of the long lines in 'if condition' are
broken after the logical operator '&&' except two instances.

This patch fixes that to bring consistency across the file.

Signed-off-by: Sekhar Nori <nsekhar at ti.com>
---
 arch/arm/mach-davinci/dma.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 1922d46..d33827a 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -351,8 +351,8 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 
 	dev_dbg(data, "dma_irq_handler\n");
 
-	if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
-	    && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
+	if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) &&
+	    (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
 		return IRQ_NONE;
 
 	while (1) {
@@ -468,10 +468,10 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 				}
 			}
 		}
-		if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
-		    && (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
-		    && (edma_read(ctlr, EDMA_QEMR) == 0)
-		    && (edma_read(ctlr, EDMA_CCERR) == 0))
+		if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
+		    (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
+		    (edma_read(ctlr, EDMA_QEMR) == 0) &&
+		    (edma_read(ctlr, EDMA_CCERR) == 0))
 			break;
 		cnt++;
 		if (cnt > 10)
-- 
1.6.2.4


From jaya.krishnan at samsung.com  Mon May 10 04:17:43 2010
From: jaya.krishnan at samsung.com (Jaya krishnan)
Date: Mon, 10 May 2010 09:17:43 +0000 (GMT)
Subject: DM6467 McASP : unable to set  GBLCTL   for  port1
Message-ID: <454193.50561273483062950.JavaMail.weblogic@epml18>


I want  to  use  AHCLKX1   (from port 1)  to be used as  master clk  for  another  device in the  system. 
But  I am  not  able  to  set GBLCTL.  for port 1
bit= 1<<9;
 bit &= 0x1f00;
  mcasp_port[port].mcasp_vregs->gblctlx |= bit;
    while ((mcasp_port[port].mcasp_vregs->gblctlx & bit) != bit);
It  does come out  from the  while  loop. But  for port 0  no  such problem. Pls  help


    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  

From kieranbingham at gmail.com  Mon May 10 06:31:11 2010
From: kieranbingham at gmail.com (Kieran Bingham)
Date: Mon, 10 May 2010 12:31:11 +0100
Subject: WARNING: at drivers/gpio/gpiolib.c:1288 __gpio_get_value
Message-ID: <4BE7EE7F.3040402@gmail.com>

Hi Guys,

I'm getting this Warning littered everywhere in my Kernel Bootlog... 
(arago-2.6.32-rc2 dm365)

Does anyone understand why the GPIO lib thinks it needs to WARN_ON?

   WARN_ON(extra_checks && chip->can_sleep);

Is this just overkill warnings ? or are they legitimate?

--
Kieran


[    1.290000] ------------[ cut here 
]------------                                                                                                                               
 
[    1.300000] WARNING: at drivers/gpio/gpiolib.c:1288 
__gpio_get_value+0x5c/0x6c()                                                                                               
 
[    1.310000] Modules linked 
in:                                                                                                                                                 
 
[    1.310000] 
Backtrace:                                                                                                                                                         
 
[    1.310000] [<c0030938>] (dump_backtrace+0x0/0x10c) from [<c036b208>] 
(dump_stack+0x18/0x1c)                                                                                   
 
[    1.320000]  r7:00000000 r6:c01bff4c r5:c0423de8 
r4:00000508                                                                                                                   
 
[    1.330000] [<c036b1f0>] (dump_stack+0x0/0x1c) from [<c004227c>] 
(warn_slowpath_common+0x50/0x80)                                                                              
 
[    1.340000] [<c004222c>] (warn_slowpath_common+0x0/0x80) from 
[<c00422c4>] 
(warn_slowpath_null+0x18/0x1c)                                                                      
 
[    1.350000]  r7:c3011000 r6:c0479878 r5:00000072 
r4:c309cf10                                                                                                                   
 
[    1.350000] [<c00422ac>] (warn_slowpath_null+0x0/0x1c) from 
[<c01bff4c>] 
(__gpio_get_value+0x5c/0x6c)                                                                          
 
[    1.360000] [<c01bfef0>] (__gpio_get_value+0x0/0x6c) from 
[<c036a1d8>] 
(button_board_probe+0x108/0x298)                                                                        
 
[    1.370000]  r5:00000000 
r4:00000001                                                                                                                                           
 
[    1.370000] [<c036a0d0>] (button_board_probe+0x0/0x298) from 
[<c0205fac>] 
(platform_drv_probe+0x20/0x24)                                                                       
 
[    1.380000] [<c0205f8c>] (platform_drv_probe+0x0/0x24) from 
[<c0204e7c>] 
(driver_probe_device+0x88/0x19c)                                                                      
 
[    1.390000] [<c0204df4>] (driver_probe_device+0x0/0x19c) from 
[<c0205024>] 
(__driver_attach+0x94/0x98)                                                                         
 
[    1.400000] [<c0204f90>] (__driver_attach+0x0/0x98) from [<c0204654>] 
(bus_for_each_dev+0x68/0x94)                                                                             
 
[    1.410000]  r7:c0204f90 r6:c0498720 r5:c3029ee0 
r4:00000000                                                                                                                   
 
[    1.420000] [<c02045ec>] (bus_for_each_dev+0x0/0x94) from 
[<c0204d00>] 
(driver_attach+0x20/0x28)                                                                               
 
[    1.430000]  r7:c0498720 r6:c3028000 r5:c0498720 
r4:c0024b0c                                                                                                                   
 
[    1.430000] [<c0204ce0>] (driver_attach+0x0/0x28) from [<c0203e78>] 
(bus_add_driver+0xa4/0x244)                                                                                
 
[    1.440000] [<c0203dd4>] (bus_add_driver+0x0/0x244) from [<c02052e8>] 
(driver_register+0x74/0x15c)                                                                             
 
[    1.450000] [<c0205274>] (driver_register+0x0/0x15c) from 
[<c0206298>] 
(platform_driver_register+0x4c/0x60)                                                                    
 
[    1.460000]  r7:c04a34a0 r6:c3028000 r5:c0024bc4 
r4:c0024b0c                                                                                                                   
 
[    1.470000] [<c020624c>] (platform_driver_register+0x0/0x60) from 
[<c001c7c4>] 
(button_board_init+0x14/0x1c)                                                                   
 
[    1.480000] [<c001c7b0>] (button_board_init+0x0/0x1c) from 
[<c002c350>] 
(do_one_initcall+0x38/0x1c8)                                                                           
 
[    1.490000] [<c002c318>] (do_one_initcall+0x0/0x1c8) from 
[<c0008480>] 
(kernel_init+0xb0/0x128)                                                                                
 
[    1.500000] [<c00083d0>] (kernel_init+0x0/0x128) from [<c0045a38>] 
(do_exit+0x0/0x6e4)                                                                                         
 
[    1.500000]  r7:00000000 r6:00000000 r5:00000000 
r4:00000000                                                                                                                   
 
[    1.510000] ---[ end trace 81d16ffaeddeb109 
]---                                                                                                                               
 
[    1.520000] ------------[ cut here 
]------------                                                                                                                               
 
[    1.520000] WARNING: at drivers/gpio/gpiolib.c:1288 
__gpio_get_value+0x5c/0x6c()                                                                                               
 
[    1.530000] Modules linked 
in:                                                                                                                                                 
 
[    1.530000] 
Backtrace:                                                                                                                                                         
 
[    1.530000] [<c0030938>] (dump_backtrace+0x0/0x10c) from [<c036b208>] 
(dump_stack+0x18/0x1c)                                                                                   
 
[    1.540000]  r7:00000000 r6:c01bff4c r5:c0423de8 
r4:00000508                                                                                                                   
 
[    1.550000] [<c036b1f0>] (dump_stack+0x0/0x1c) from [<c004227c>] 
(warn_slowpath_common+0x50/0x80)                                                                              
 
[    1.560000] [<c004222c>] (warn_slowpath_common+0x0/0x80) from 
[<c00422c4>] 
(warn_slowpath_null+0x18/0x1c)                                                                      
 
[    1.570000]  r7:c3011000 r6:c0479878 r5:00000073 
r4:c309cf10                                                                                                                   
 
[    1.570000] [<c00422ac>] (warn_slowpath_null+0x0/0x1c) from 
[<c01bff4c>] 
(__gpio_get_value+0x5c/0x6c)                                                                          
 
[    1.580000] [<c01bfef0>] (__gpio_get_value+0x0/0x6c) from 
[<c036a1d8>] 
(button_board_probe+0x108/0x298)                                                                        
 
[    1.590000]  r5:00000000 
r4:00000002                                                                                                                                           
 
[    1.600000] [<c036a0d0>] (button_board_probe+0x0/0x298) from 
[<c0205fac>] 
(platform_drv_probe+0x20/0x24)                                                                       
 
[    1.610000] [<c0205f8c>] (platform_drv_probe+0x0/0x24) from 
[<c0204e7c>] 
(driver_probe_device+0x88/0x19c)                                                                      
 
[    1.620000] [<c0204df4>] (driver_probe_device+0x0/0x19c) from 
[<c0205024>] 
(__driver_attach+0x94/0x98)                                                                         
 
[    1.630000] [<c0204f90>] (__driver_attach+0x0/0x98) from [<c0204654>] 
(bus_for_each_dev+0x68/0x94)                                                                             
 
[    1.630000]  r7:c0204f90 r6:c0498720 r5:c3029ee0 
r4:00000000                                                                                                                   
 
[    1.640000] [<c02045ec>] (bus_for_each_dev+0x0/0x94) from 
[<c0204d00>] 
(driver_attach+0x20/0x28)                                                                               
 
[    1.650000]  r7:c0498720 r6:c3028000 r5:c0498720 
r4:c0024b0c                                                                                                                   
 
[    1.650000] [<c0204ce0>] (driver_attach+0x0/0x28) from [<c0203e78>] 
(bus_add_driver+0xa4/0x244)                                                                                
 
[    1.660000] [<c0203dd4>] (bus_add_driver+0x0/0x244) from [<c02052e8>] 
(driver_register+0x74/0x15c)                                                                             
 
[    1.670000] [<c0205274>] (driver_register+0x0/0x15c) from 
[<c0206298>] 
(platform_driver_register+0x4c/0x60)                                                                    
 
[    1.680000]  r7:c04a34a0 r6:c3028000 r5:c0024bc4 
r4:c0024b0c                                                                                                                   
 
[    1.690000] [<c020624c>] (platform_driver_register+0x0/0x60) from 
[<c001c7c4>] 
(button_board_init+0x14/0x1c)                                                                   
 
[    1.700000] [<c001c7b0>] (button_board_init+0x0/0x1c) from 
[<c002c350>] 
(do_one_initcall+0x38/0x1c8)                                                                           
 
[    1.710000] [<c002c318>] (do_one_initcall+0x0/0x1c8) from 
[<c0008480>] 
(kernel_init+0xb0/0x128)                                                                                
 
[    1.720000] [<c00083d0>] (kernel_init+0x0/0x128) from [<c0045a38>] 
(do_exit+0x0/0x6e4)                                                                                         
 
[    1.730000]  r7:00000000 r6:00000000 r5:00000000 
r4:00000000                                                                                                                   
 
[    1.730000] ---[ end trace 81d16ffaeddeb10a 
]---                                                                                                                               
 
[    1.740000] usb 1-1: new high speed USB device using musb_hdrc and 
address 
2                                                                                                   
 
[    1.740000] ------------[ cut here 
]------------                                                                                                                               
 
[    1.750000] WARNING: at drivers/gpio/gpiolib.c:1288 
__gpio_get_value+0x5c/0x6c()                                                                                               
 
[    1.760000] Modules linked 
in:                                                                                                                                                 
 
[    1.760000] 
Backtrace:                                                                                                                                                         
 
[    1.760000] [<c0030938>] (dump_backtrace+0x0/0x10c) from [<c036b208>] 
(dump_stack+0x18/0x1c)                                                                                   
 
[    1.770000]  r7:00000000 r6:c01bff4c r5:c0423de8 
r4:00000508                                                                                                                   
 
[    1.780000] [<c036b1f0>] (dump_stack+0x0/0x1c) from [<c004227c>] 
(warn_slowpath_common+0x50/0x80)                                                                              
 
[    1.790000] [<c004222c>] (warn_slowpath_common+0x0/0x80) from 
[<c00422c4>] 
(warn_slowpath_null+0x18/0x1c)                                                                      
 
[    1.800000]  r7:c3011000 r6:c0479878 r5:00000074 
r4:c309cf10                                                                                                                   
 
[    1.800000] [<c00422ac>] (warn_slowpath_null+0x0/0x1c) from 
[<c01bff4c>] 
(__gpio_get_value+0x5c/0x6c)                                                                          
 
[    1.810000] [<c01bfef0>] (__gpio_get_value+0x0/0x6c) from 
[<c036a1d8>] 
(button_board_probe+0x108/0x298)                                                                        
 
[    1.820000]  r5:00000000 
r4:00000003                                                                                                                                           
 
[    1.820000] [<c036a0d0>] (button_board_probe+0x0/0x298) from 
[<c0205fac>] 
(platform_drv_probe+0x20/0x24)                                                                       
 
[    1.830000] [<c0205f8c>] (platform_drv_probe+0x0/0x24) from 
[<c0204e7c>] 
(driver_probe_device+0x88/0x19c)                                                                      
 
[    1.840000] [<c0204df4>] (driver_probe_device+0x0/0x19c) from 
[<c0205024>] 
(__driver_attach+0x94/0x98)                                                                         
 
[    1.850000] [<c0204f90>] (__driver_attach+0x0/0x98) from [<c0204654>] 
(bus_for_each_dev+0x68/0x94)                                                                             
 
[    1.860000]  r7:c0204f90 r6:c0498720 r5:c3029ee0 
r4:00000000                                                                                                                   
 
[    1.870000] [<c02045ec>] (bus_for_each_dev+0x0/0x94) from 
[<c0204d00>] 
(driver_attach+0x20/0x28)                                                                               
 
[    1.880000]  r7:c0498720 r6:c3028000 r5:c0498720 
r4:c0024b0c                                                                                                                   
 
[    1.880000] [<c0204ce0>] (driver_attach+0x0/0x28) from [<c0203e78>] 
(bus_add_driver+0xa4/0x244)                                                                                
 
[    1.890000] [<c0203dd4>] (bus_add_driver+0x0/0x244) from [<c02052e8>] 
(driver_register+0x74/0x15c)                                                                             
 
[    1.900000] [<c0205274>] (driver_register+0x0/0x15c) from 
[<c0206298>] 
(platform_driver_register+0x4c/0x60)                                                                    
 
[    1.910000]  r7:c04a34a0 r6:c3028000 r5:c0024bc4 
r4:c0024b0c                                                                                                                   
 
[    1.920000] [<c020624c>] (platform_driver_register+0x0/0x60) from 
[<c001c7c4>] 
(button_board_init+0x14/0x1c)                                                                   
 
[    1.930000] [<c001c7b0>] (button_board_init+0x0/0x1c) from 
[<c002c350>] 
(do_one_initcall+0x38/0x1c8)                                                                           
 
[    1.940000] [<c002c318>] (do_one_initcall+0x0/0x1c8) from 
[<c0008480>] 
(kernel_init+0xb0/0x128)                                                                                
 
[    1.950000] [<c00083d0>] (kernel_init+0x0/0x128) from [<c0045a38>] 
(do_exit+0x0/0x6e4)                                                                                         
 
[    1.950000]  r7:00000000 r6:00000000 r5:00000000 
r4:00000000                                                                                                                   
 
[    1.960000] ---[ end trace 81d16ffaeddeb10b 
]---                                                                                                                               
 
[    1.970000] ------------[ cut here ]------------ 

From ipcevm at gmail.com  Mon May 10 06:49:02 2010
From: ipcevm at gmail.com (shaofeng zhang)
Date: Mon, 10 May 2010 19:49:02 +0800
Subject: Problems About thttpd 2.25b
Message-ID: <AANLkTilBcshULnzfxT66yJAo0EqbG_rrMX1PulhdCIyo@mail.gmail.com>

Hi,All,

I am using the webserver thttpd 2.25b on my DM6446 board, and I found that a
problem abouth it:
When I use the configuration file like this:
*/thttpd -c /opt/dvevm/thttpd.conf *
but the webserver could not
use the config file thttpd.conf and the web page dir could not be set
in the config file
my config file is :
*# This section overrides defaults*
*dir=/opt/Network_Demo/web*
*chroot*
*user=root*
*logfile=/opt/Network_Demo/web/thttpd.log*
*pidfile=/opt/Network_Demo/web/thttpd.pid*
*# This section _documents_ defaults in effect*
*# port=80*
*# nosymlink# default = !chroot*
*# novhost*
*# nocgipat*
*# nothrottles*
*# host=0.0.0.0*
*# charset=iso-8859-1*
When I use the command :
*/thttpd -d /opt/Network_Demo/web*
It seems like the webdir could not be set correctly!

Could anyone tell me how to set the webdir for thttpd 2.25b?
what use of  the scrips file thttpd_wrapper?
*#!/bin/sh*
*DVEVMDIR=/opt/dvevm*
*while true ; do*
*    cd $DVEVMDIR/web*
*    ./thttpd -c "/cgi-bin/*" -l /dev/null*
*    sleep 10*
*done*

-- 
Best Regards!                   zhangshaofeng
       @Xi'an JiaoTong University
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From vaibhav.bedia at ti.com  Mon May 10 07:42:23 2010
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Mon, 10 May 2010 18:12:23 +0530
Subject: DM6467 McASP : unable to set  GBLCTL   for  port1
In-Reply-To: <454193.50561273483062950.JavaMail.weblogic@epml18>
References: <454193.50561273483062950.JavaMail.weblogic@epml18>
Message-ID: <FCCFB4CDC6E5564B9182F639FC356087030500DA87@dbde02.ent.ti.com>


Jayakrishnan,

The bit field in GBLCTL register that you are trying to set is synchronized and latched by the corresponding clock(ACLKX in your case).

Since you want to use AHCLKX1 as master clk for another device I suspect the ACLKX is not already running. If you don't have ACLKX externally generated you need to select the internal clk source in ACLKXCTL (and possibly even in AHCLKXCTL - depends on the use case) before GBLCTL is programmed.

Regards,
Vaibhav


-----Original Message-----
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com] 
Sent: Monday, May 10, 2010 2:48 PM
To: davinci-linux-open-source at linux.davincidsp.com; Bedia, Vaibhav
Subject: DM6467 McASP : unable to set GBLCTL for port1


I want  to  use  AHCLKX1   (from port 1)  to be used as  master clk  for  another  device in the  system. 
But  I am  not  able  to  set GBLCTL.  for port 1
bit= 1<<9;
 bit &= 0x1f00;
  mcasp_port[port].mcasp_vregs->gblctlx |= bit;
    while ((mcasp_port[port].mcasp_vregs->gblctlx & bit) != bit);
It  does come out  from the  while  loop. But  for port 0  no  such problem. Pls  help


    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  

From khilman at deeprootsystems.com  Mon May 10 09:18:45 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 10 May 2010 07:18:45 -0700
Subject: [PATCH 4/4]-V3 Add MFD driver for TPS6507x family of
	multi-function chips and move TPS6507x regulator driver from
	being stand-alone to using the MFD driver.
In-Reply-To: <20100509210940.GA3269@sortiz.org> (Samuel Ortiz's message of
	"Sun\, 9 May 2010 23\:09\:41 +0200")
References: <1270520639-20516-1-git-send-email-todd.fischer@ridgerun.com>
	<1270520639-20516-2-git-send-email-todd.fischer@ridgerun.com>
	<1270520639-20516-3-git-send-email-todd.fischer@ridgerun.com>
	<1270520639-20516-4-git-send-email-todd.fischer@ridgerun.com>
	<1270520639-20516-5-git-send-email-todd.fischer@ridgerun.com>
	<87633kacmq.fsf@deeprootsystems.com>
	<20100509210940.GA3269@sortiz.org>
Message-ID: <87tyqfq1q2.fsf@deeprootsystems.com>

Samuel Ortiz <sameo at linux.intel.com> writes:

> Hi Kevin,
>
> On Wed, Apr 21, 2010 at 11:23:09AM -0700, Kevin Hilman wrote:
>> Todd Fischer <todd.fischer at ridgerun.com> writes:
>> 
>> > Add MFD driver for TPS6507x family of multi-function chips.  Move TPS6507x 
>> > regulator driver from being stand-alone driver to using the MFD TPS6507x driver.
>> >
>> > Signed-off-by: Todd Fischer <todd.fischer at ridgerun.com>
>> 
>> [...]
>> 
>> Not sure whose tree this is queued in currently, but testing with
>> current davinci git, I had a compile problem...
>
> This is fixed in the MFD tree.
>

Thanks!

Kevin

From surfinbum at mac.com  Mon May 10 14:49:41 2010
From: surfinbum at mac.com (Chris Jackson)
Date: Mon, 10 May 2010 15:49:41 -0400
Subject: Using IMGLIB with the DVSDK
Message-ID: <1273520981.7863.13.camel@JaxTechIPL>

Hello, 

I want to use the IMGLIB library to implement a basic edge detection
algorithm.  The problem is I am not using CCS, and I'm not sure how to
build, or where to include the .lib files for the linker to pick them
up.  

So far I have downloaded the library, unzipped and have the imglib_v201
directory structure recreated on my host linux machine.

I see there are two .lib files, one for the host (imglib2_host.lib), and
the other for the target (imglib2_host.lib).  I am rebuilding the encode
demo app that came with the DVSDK installation on the host machine, and
running the executable over an NFS server, so I'm thinking I'll need the
imglib2_host.lib file, but i can't find the linker command file where to
include this deceleration. 

Am I going down the wrong path?  I will eventually migrate to the CCS
environment for heavy DSP algorithm development, but my client just
wants to see a few benchmarks with an edge detection filter in
real-time, so I am thinking I'll just start with the sobel 3x3 in IMGLIB
and stick it in a processing thread in the encode demo.  I'm open to any
other ideas somebody might have.

thanks for any help.

Chris Jackson
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From surfinbum at mac.com  Mon May 10 18:43:45 2010
From: surfinbum at mac.com (Chris Jackson)
Date: Mon, 10 May 2010 19:43:45 -0400
Subject: copy files to EVM6446 Hard Drive
Message-ID: <1273535025.14416.4.camel@JaxTechIPL>

Hello All, 


I have a EVM6446 board set-up and configured according to the Getting
Started Users Guide. 

I am booted from the NAND and mounted to my shared NFS directory on
Linux Host.  My question is:  how can I copy files from my host to the
EVM hard drive?  I want to run an updated Encode demo application hard
drive of the EVM, and not over the NFS shared directory.

I know I must be missing something basic here, but I cannot figure out
how to copy files from host to target.  Any help is greatly appreciated.

Thank You, 

Chris Jackson

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From jaya.krishnan at samsung.com  Mon May 10 23:54:45 2010
From: jaya.krishnan at samsung.com (Jaya krishnan)
Date: Tue, 11 May 2010 04:54:45 +0000 (GMT)
Subject: DM6467 McASP : unable to set  GBLCTL   for  port1
Message-ID: <24109121.88521273553685097.JavaMail.weblogic@epml18>



 
 Vaibhav, 
Thanks  for the  reply.
I have  selected intenal  clk  sources  for both ACLKXCTL  and AHCLKXCTL
ACLKXCTL=0x00000061
AHCLKXCTL=0x00008033
PDIR=0x0A000000
ACLKX1 is  not  produced. The  above  settings  should  produce ACLKX1, so that GBLCTLX  can be  set. Am I correct?
What  are  the  other  checks  to be  done, so that ACLKX1  is  produced?  Pls  reply

Regards
JK
------- Original Message-------
Sender: Bedia, Vaibhav<vaibhav.bedia at ti.com>
Date: May 10, 2010 21:42 (GMT+09:00)
Title: RE: DM6467 McASP : unable to set GBLCTL for port1


Jayakrishnan, 

The bit field in GBLCTL register that you are trying to set is synchronized and latched by the corresponding clock(ACLKX in your case). 

Since you want to use AHCLKX1 as master clk for another device I suspect the ACLKX is not already running. If you don't have ACLKX externally generated you need to select the internal clk source in ACLKXCTL (and possibly even in AHCLKXCTL - depends on the use case) before GBLCTL is programmed. 

Regards, 
Vaibhav 


-----Original Message----- 
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com]  
Sent: Monday, May 10, 2010 2:48 PM 
To: davinci-linux-open-source at linux.davincidsp.com; Bedia, Vaibhav 
Subject: DM6467 McASP : unable to set GBLCTL for port1 


I want  to  use  AHCLKX1   (from port 1)  to be used as  master clk  for  another  device in the  system.  
But  I am  not  able  to  set GBLCTL.  for port 1 
bit= 1<<9; 
 bit &= 0x1f00; 
  mcasp_port[port].mcasp_vregs->gblctlx |= bit; 
    while ((mcasp_port[port].mcasp_vregs->gblctlx & bit) != bit); 
It  does come out  from the  while  loop. But  for port 0  no  such problem. Pls  help 


     
Jayakrishnan M M 
Research Engineer 
R&D Team-2 , Group-5 
Security Solutions  Division 
SAMSUNG TECHWIN CO.,LTD 

TEL +82-70-7147-8482 
FAX +82-31-8018-3712 
Mobile +82-10-6409-3619 
E-mail:jaya.krishnan at samsung.com 
  
   

 
    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  
 
 

From vaibhav.bedia at ti.com  Tue May 11 04:26:25 2010
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Tue, 11 May 2010 14:56:25 +0530
Subject: DM6467 McASP : unable to set  GBLCTL   for  port1
In-Reply-To: <24109121.88521273553685097.JavaMail.weblogic@epml18>
References: <24109121.88521273553685097.JavaMail.weblogic@epml18>
Message-ID: <FCCFB4CDC6E5564B9182F639FC35608703050DE23B@dbde02.ent.ti.com>

With the register config as you mentioned, what do you observe when you try to write to XHCLKRST bit followed by a write to XCLKRST bit in GBLCTL?

Also, please verify that AUXCLK is coming in to McASP1. If not, you need to check whether there in any additional PLL setting required for this.

Regards,
Vaibhav

-----Original Message-----
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com] 
Sent: Tuesday, May 11, 2010 10:25 AM
To: Bedia, Vaibhav; davinci-linux-open-source at linux.davincidsp.com
Cc: Pasupathy, Visuvanadan
Subject: RE: DM6467 McASP : unable to set GBLCTL for port1



 
 Vaibhav, 
Thanks  for the  reply.
I have  selected intenal  clk  sources  for both ACLKXCTL  and AHCLKXCTL
ACLKXCTL=0x00000061
AHCLKXCTL=0x00008033
PDIR=0x0A000000
ACLKX1 is  not  produced. The  above  settings  should  produce ACLKX1, so that GBLCTLX  can be  set. Am I correct?
What  are  the  other  checks  to be  done, so that ACLKX1  is  produced?  Pls  reply

Regards
JK
------- Original Message-------
Sender: Bedia, Vaibhav<vaibhav.bedia at ti.com>
Date: May 10, 2010 21:42 (GMT+09:00)
Title: RE: DM6467 McASP : unable to set GBLCTL for port1


Jayakrishnan, 

The bit field in GBLCTL register that you are trying to set is synchronized and latched by the corresponding clock(ACLKX in your case). 

Since you want to use AHCLKX1 as master clk for another device I suspect the ACLKX is not already running. If you don't have ACLKX externally generated you need to select the internal clk source in ACLKXCTL (and possibly even in AHCLKXCTL - depends on the use case) before GBLCTL is programmed. 

Regards, 
Vaibhav 


-----Original Message----- 
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com]  
Sent: Monday, May 10, 2010 2:48 PM 
To: davinci-linux-open-source at linux.davincidsp.com; Bedia, Vaibhav 
Subject: DM6467 McASP : unable to set GBLCTL for port1 


I want  to  use  AHCLKX1   (from port 1)  to be used as  master clk  for  another  device in the  system.  
But  I am  not  able  to  set GBLCTL.  for port 1 
bit= 1<<9; 
 bit &= 0x1f00; 
  mcasp_port[port].mcasp_vregs->gblctlx |= bit; 
    while ((mcasp_port[port].mcasp_vregs->gblctlx & bit) != bit); 
It  does come out  from the  while  loop. But  for port 0  no  such problem. Pls  help 


     
Jayakrishnan M M 
Research Engineer 
R&D Team-2 , Group-5 
Security Solutions  Division 
SAMSUNG TECHWIN CO.,LTD 

TEL +82-70-7147-8482 
FAX +82-31-8018-3712 
Mobile +82-10-6409-3619 
E-mail:jaya.krishnan at samsung.com 
  
   

 
    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  
 
 

From jaya.krishnan at samsung.com  Tue May 11 04:43:36 2010
From: jaya.krishnan at samsung.com (Jaya krishnan)
Date: Tue, 11 May 2010 09:43:36 +0000 (GMT)
Subject: DM6467 McASP : unable to set  GBLCTL   for  port1
Message-ID: <424514.107491273571016859.JavaMail.weblogic@epml20>


Thanks Vaibhav.
With  the  settings I  mentioned, the execution goes into infinite while loop, as  the  XHCLKRST write  operation was  not successful.
How  to  check the AUXCLK input  to McASP1?
Regards
JK


 
 
 

------- Original Message-------
Sender: Bedia, Vaibhav<vaibhav.bedia at ti.com>
Date: May 11, 2010 18:26 (GMT+09:00)
Title: RE: DM6467 McASP : unable to set GBLCTL for port1

With the register config as you mentioned, what do you observe when you try to write to XHCLKRST bit followed by a write to XCLKRST bit in GBLCTL? 

Also, please verify that AUXCLK is coming in to McASP1. If not, you need to check whether there in any additional PLL setting required for this. 

Regards, 
Vaibhav 

-----Original Message----- 
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com]  
Sent: Tuesday, May 11, 2010 10:25 AM 
To: Bedia, Vaibhav; davinci-linux-open-source at linux.davincidsp.com 
Cc: Pasupathy, Visuvanadan 
Subject: RE: DM6467 McASP : unable to set GBLCTL for port1 



  
 Vaibhav,  
Thanks  for the  reply. 
I have  selected intenal  clk  sources  for both ACLKXCTL  and AHCLKXCTL 
ACLKXCTL=0x00000061 
AHCLKXCTL=0x00008033 
PDIR=0x0A000000 
ACLKX1 is  not  produced. The  above  settings  should  produce ACLKX1, so that GBLCTLX  can be  set. Am I correct? 
What  are  the  other  checks  to be  done, so that ACLKX1  is  produced?  Pls  reply 

Regards 
JK 
------- Original Message------- 
Sender: Bedia, Vaibhav<vaibhav.bedia at ti.com> 
Date: May 10, 2010 21:42 (GMT+09:00) 
Title: RE: DM6467 McASP : unable to set GBLCTL for port1 


Jayakrishnan,  

The bit field in GBLCTL register that you are trying to set is synchronized and latched by the corresponding clock(ACLKX in your case).  

Since you want to use AHCLKX1 as master clk for another device I suspect the ACLKX is not already running. If you don't have ACLKX externally generated you need to select the internal clk source in ACLKXCTL (and possibly even in AHCLKXCTL - depends on the use case) before GBLCTL is programmed.  

Regards,  
Vaibhav  


-----Original Message-----  
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com]   
Sent: Monday, May 10, 2010 2:48 PM  
To: davinci-linux-open-source at linux.davincidsp.com; Bedia, Vaibhav  
Subject: DM6467 McASP : unable to set GBLCTL for port1  


I want  to  use  AHCLKX1   (from port 1)  to be used as  master clk  for  another  device in the  system.   
But  I am  not  able  to  set GBLCTL.  for port 1  
bit= 1<<9;  
 bit &= 0x1f00;  
  mcasp_port[port].mcasp_vregs->gblctlx |= bit;  
    while ((mcasp_port[port].mcasp_vregs->gblctlx & bit) != bit);  
It  does come out  from the  while  loop. But  for port 0  no  such problem. Pls  help  


      
Jayakrishnan M M  
Research Engineer  
R&D Team-2 , Group-5  
Security Solutions  Division  
SAMSUNG TECHWIN CO.,LTD  

TEL +82-70-7147-8482  
FAX +82-31-8018-3712  
Mobile +82-10-6409-3619  
E-mail:jaya.krishnan at samsung.com  
   
    

  
     
Jayakrishnan M M 
Research Engineer 
R&D Team-2 , Group-5 
Security Solutions  Division 
SAMSUNG TECHWIN CO.,LTD 

TEL +82-70-7147-8482 
FAX +82-31-8018-3712 
Mobile +82-10-6409-3619 
E-mail:jaya.krishnan at samsung.com 
  
   
  
  

 
    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  
 
 

From vaibhav.bedia at ti.com  Tue May 11 05:44:22 2010
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Tue, 11 May 2010 16:14:22 +0530
Subject: DM6467 McASP : unable to set  GBLCTL   for  port1
In-Reply-To: <424514.107491273571016859.JavaMail.weblogic@epml20>
References: <424514.107491273571016859.JavaMail.weblogic@epml20>
Message-ID: <FCCFB4CDC6E5564B9182F639FC35608703050DE2CA@dbde02.ent.ti.com>

Jayakrishnan,

You need to check whether path for AUDIO_CLK1 is set up properly (CLKCTL and PINMUX0 registers). Please refer to the TRM for these registers.

If port 0 is also not working then you could check the AUXCLK generated from the PLL by attaching a probe to the CLKOUT pin available.

Regards,
Vaibhav

-----Original Message-----
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com] 
Sent: Tuesday, May 11, 2010 3:14 PM
To: Bedia, Vaibhav; davinci-linux-open-source at linux.davincidsp.com
Cc: Pasupathy, Visuvanadan
Subject: Re: DM6467 McASP : unable to set GBLCTL for port1


Thanks Vaibhav.
With  the  settings I  mentioned, the execution goes into infinite while loop, as  the  XHCLKRST write  operation was  not successful.
How  to  check the AUXCLK input  to McASP1?
Regards
JK


 
 
 

------- Original Message-------
Sender: Bedia, Vaibhav<vaibhav.bedia at ti.com>
Date: May 11, 2010 18:26 (GMT+09:00)
Title: RE: DM6467 McASP : unable to set GBLCTL for port1

With the register config as you mentioned, what do you observe when you try to write to XHCLKRST bit followed by a write to XCLKRST bit in GBLCTL? 

Also, please verify that AUXCLK is coming in to McASP1. If not, you need to check whether there in any additional PLL setting required for this. 

Regards, 
Vaibhav 

-----Original Message----- 
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com]  
Sent: Tuesday, May 11, 2010 10:25 AM 
To: Bedia, Vaibhav; davinci-linux-open-source at linux.davincidsp.com 
Cc: Pasupathy, Visuvanadan 
Subject: RE: DM6467 McASP : unable to set GBLCTL for port1 



  
 Vaibhav,  
Thanks  for the  reply. 
I have  selected intenal  clk  sources  for both ACLKXCTL  and AHCLKXCTL 
ACLKXCTL=0x00000061 
AHCLKXCTL=0x00008033 
PDIR=0x0A000000 
ACLKX1 is  not  produced. The  above  settings  should  produce ACLKX1, so that GBLCTLX  can be  set. Am I correct? 
What  are  the  other  checks  to be  done, so that ACLKX1  is  produced?  Pls  reply 

Regards 
JK 
------- Original Message------- 
Sender: Bedia, Vaibhav<vaibhav.bedia at ti.com> 
Date: May 10, 2010 21:42 (GMT+09:00) 
Title: RE: DM6467 McASP : unable to set GBLCTL for port1 


Jayakrishnan,  

The bit field in GBLCTL register that you are trying to set is synchronized and latched by the corresponding clock(ACLKX in your case).  

Since you want to use AHCLKX1 as master clk for another device I suspect the ACLKX is not already running. If you don't have ACLKX externally generated you need to select the internal clk source in ACLKXCTL (and possibly even in AHCLKXCTL - depends on the use case) before GBLCTL is programmed.  

Regards,  
Vaibhav  


-----Original Message-----  
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com]   
Sent: Monday, May 10, 2010 2:48 PM  
To: davinci-linux-open-source at linux.davincidsp.com; Bedia, Vaibhav  
Subject: DM6467 McASP : unable to set GBLCTL for port1  


I want  to  use  AHCLKX1   (from port 1)  to be used as  master clk  for  another  device in the  system.   
But  I am  not  able  to  set GBLCTL.  for port 1  
bit= 1<<9;  
 bit &= 0x1f00;  
  mcasp_port[port].mcasp_vregs->gblctlx |= bit;  
    while ((mcasp_port[port].mcasp_vregs->gblctlx & bit) != bit);  
It  does come out  from the  while  loop. But  for port 0  no  such problem. Pls  help  


      
Jayakrishnan M M  
Research Engineer  
R&D Team-2 , Group-5  
Security Solutions  Division  
SAMSUNG TECHWIN CO.,LTD  

TEL +82-70-7147-8482  
FAX +82-31-8018-3712  
Mobile +82-10-6409-3619  
E-mail:jaya.krishnan at samsung.com  
   
    

  
     
Jayakrishnan M M 
Research Engineer 
R&D Team-2 , Group-5 
Security Solutions  Division 
SAMSUNG TECHWIN CO.,LTD 

TEL +82-70-7147-8482 
FAX +82-31-8018-3712 
Mobile +82-10-6409-3619 
E-mail:jaya.krishnan at samsung.com 
  
   
  
  

 
    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  
 
 

From thomas.koeller at baslerweb.com  Tue May 11 06:40:53 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Tue, 11 May 2010 13:40:53 +0200
Subject: [PATCH 0/2] DM365: More PINMUX configurations
Message-ID: <1273578055-25961-1-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

These patches add some more PINMUX configurations.

Thomas Koeller (2):
  DM365: Make CLKOUTx available
  DM365: Added more PINMUX configurations for AEMIF

 arch/arm/mach-davinci/dm365.c            |    9 ++++++++-
 arch/arm/mach-davinci/include/mach/mux.h |   10 +++++++++-
 2 files changed, 17 insertions(+), 2 deletions(-)


From thomas.koeller at baslerweb.com  Tue May 11 06:40:55 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Tue, 11 May 2010 13:40:55 +0200
Subject: [PATCH 2/2] DM365: Added more PINMUX configurations for AEMIF
In-Reply-To: <1273578055-25961-1-git-send-email-thomas.koeller@baslerweb.com>
References: <1273578055-25961-1-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <1273578055-25961-3-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
---
 arch/arm/mach-davinci/dm365.c            |    5 ++++-
 arch/arm/mach-davinci/include/mach/mux.h |    5 ++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0441d98..ae71805 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -495,11 +495,14 @@ MUX_CFG(DM365,	SD1_DATA0,	4,   22,    3,	  1,	 false)
 MUX_CFG(DM365,	I2C_SDA,	3,   23,    3,	  2,	 false)
 MUX_CFG(DM365,	I2C_SCL,	3,   21,    3,	  2,	 false)
 
-MUX_CFG(DM365,	AEMIF_AR,	2,   0,     3,	  1,	 false)
+MUX_CFG(DM365,	AEMIF_AR_A14,	2,   0,     3,	  1,	 false)
+MUX_CFG(DM365,	AEMIF_AR_BA0,	2,   0,     3,	  2,	 false)
 MUX_CFG(DM365,	AEMIF_A3,	2,   2,     3,	  1,	 false)
 MUX_CFG(DM365,	AEMIF_A7,	2,   4,     3,	  1,	 false)
 MUX_CFG(DM365,	AEMIF_D15_8,	2,   6,     1,	  1,	 false)
 MUX_CFG(DM365,	AEMIF_CE0,	2,   7,     1,	  0,	 false)
+MUX_CFG(DM365,	AEMIF_CE1,	2,   8,     1,    0,     false)
+MUX_CFG(DM365,	AEMIF_WE_OE,	2,   9,     1,    0,     false)
 
 MUX_CFG(DM365,	MCBSP0_BDX,	0,   23,    1,	  1,	 false)
 MUX_CFG(DM365,	MCBSP0_X,	0,   22,    1,	  1,	 false)
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index cf383f9..113f382 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -198,11 +198,14 @@ enum davinci_dm365_index {
 	DM365_I2C_SCL,
 
 	/* AEMIF */
-	DM365_AEMIF_AR,
+	DM365_AEMIF_AR_A14,
+	DM365_AEMIF_AR_BA0,
 	DM365_AEMIF_A3,
 	DM365_AEMIF_A7,
 	DM365_AEMIF_D15_8,
 	DM365_AEMIF_CE0,
+	DM365_AEMIF_CE1,
+	DM365_AEMIF_WE_OE,
 
 	/* ASP0 function */
 	DM365_MCBSP0_BDX,
-- 
1.7.1


From thomas.koeller at baslerweb.com  Tue May 11 06:40:54 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Tue, 11 May 2010 13:40:54 +0200
Subject: [PATCH 1/2] DM365: Make CLKOUTx available
In-Reply-To: <1273578055-25961-1-git-send-email-thomas.koeller@baslerweb.com>
References: <1273578055-25961-1-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <1273578055-25961-2-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

Added PINMUX configurations for the CLKOUT0 .. CLKOUT2
functions.

Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
---
 arch/arm/mach-davinci/dm365.c            |    4 ++++
 arch/arm/mach-davinci/include/mach/mux.h |    5 +++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 8fb7578..0441d98 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -578,6 +578,10 @@ MUX_CFG(DM365,	SPI4_SDO,	4,   16,    3,    1,	 false)
 MUX_CFG(DM365,	SPI4_SDENA0,	4,   20,    3,    1,	 false)
 MUX_CFG(DM365,	SPI4_SDENA1,	4,   16,    3,    2,	 false)
 
+MUX_CFG(DM365,	CLKOUT0,	4,   20,    3,    3,     false)
+MUX_CFG(DM365,	CLKOUT1,	4,   16,    3,    3,     false)
+MUX_CFG(DM365,	CLKOUT2,	4,   8,     3,    3,     false)
+
 MUX_CFG(DM365,	GPIO20,		3,   21,    3,    0,	 false)
 MUX_CFG(DM365,	GPIO30,		4,   6,     3,	  0,	 false)
 MUX_CFG(DM365,	GPIO31,		4,   8,     3,	  0,	 false)
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 49a2f57..cf383f9 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -291,6 +291,11 @@ enum davinci_dm365_index {
 	DM365_SPI4_SDENA0,
 	DM365_SPI4_SDENA1,
 
+	/* Clock */
+	DM365_CLKOUT0,
+	DM365_CLKOUT1,
+	DM365_CLKOUT2,
+
 	/* GPIO */
 	DM365_GPIO20,
 	DM365_GPIO30,
-- 
1.7.1


From schen at mvista.com  Tue May 11 06:52:01 2010
From: schen at mvista.com (Steve Chen)
Date: Tue, 11 May 2010 06:52:01 -0500
Subject: copy files to EVM6446 Hard Drive
In-Reply-To: <1273535025.14416.4.camel@JaxTechIPL>
References: <1273535025.14416.4.camel@JaxTechIPL>
Message-ID: <AANLkTilxZnc-I-76n1EuRudSAqFsFcjDaMbTgJGzUAVq@mail.gmail.com>

On Mon, May 10, 2010 at 6:43 PM, Chris Jackson <surfinbum at mac.com> wrote:
> Hello All,
>
>
> I have a EVM6446 board set-up and configured according to the Getting
> Started Users Guide.
>
> I am booted from the NAND and mounted to my shared NFS directory on Linux
> Host.? My question is:? how can I copy files from my host to the EVM hard
> drive?? I want to run an updated Encode demo application hard drive of the
> EVM, and not over the NFS shared directory.
>
> I know I must be missing something basic here, but I cannot figure out how
> to copy files from host to target.? Any help is greatly appreciated.
>

Assume the hard driver is ready (ie already partitioned with a file
system and mounted), you can use scp to copy files across network or
just cp if the file is already nfs mounted.

Regards,

Steve

From Kloiber at distec.de  Tue May 11 08:06:23 2010
From: Kloiber at distec.de (DISTEC Kloiber Thomas)
Date: Tue, 11 May 2010 15:06:23 +0200
Subject: Audio dropouts since using DM6443 silicon rev. 2.1
In-Reply-To: <84E5692253AB2749AB4C49395A570735082673F2@GTMDHQEXCLUS.optelecom.com>
References: <BFE810BB1BD20E47876F1BB1EA7BF7305C91FF@srv-exchange.datadisplay.de>
	<84E5692253AB2749AB4C49395A570735082673F2@GTMDHQEXCLUS.optelecom.com>
Message-ID: <BFE810BB1BD20E47876F1BB1EA7BF730686F3D@srv-exchange.datadisplay.de>

Hi Arie,

I just wanted to let you know, that you exactly hit the mark with your assumption regarding the priority registers below.

Thank you very much!

Some details for the list:
Due to a silicon bug in DM6443 rev 1.3 the default value 0x00040444 was used for register MSTPRI0 (see silicon errata for details). This register is responsible for "Switched Central Resource (SCR) Bus Priorities". This register was not initialized in our firmware at all. The default value just worked fine.
In silicon rev 2.1 this bug has been fixed and thus the default value has changed to 0x00050111. For us this value caused the problem I described below.
Now I'm setting the register to 0x00040444 in u-boot explicitly and everything works fine for silicon rev 2.1 as well.

Thanks again!

Kind regards
Thomas


-----Urspr?ngliche Nachricht-----
Von: Arie Muijnck [mailto:amuijnck at optelecom-nkf.com] 
Gesendet: Dienstag, 23. M?rz 2010 17:37
An: DISTEC Kloiber Thomas; davinci-linux-open-source at linux.davincidsp.com
Betreff: RE: Audio dropouts since using DM6443 silicon rev. 2.1

In the 2.1 revision the priority registers have been improved. In the old version there was a bug: all peripherals used the bits of one register, the other was unused. Now they are properly connected, but the default values of peripheral priorities are thus not the same as the old
1.3 silicon.

To restore the previous 1.3 priority situation our bootloader just writes V1.3 equivalent values into both registers.

Maybe this is also your problem.

Kind regards,
Arie de Muijnck


-----Original Message-----
From: davinci-linux-open-source-bounces at linux.davincidsp.com
[mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of DISTEC Kloiber Thomas
Sent: Tuesday, March 23, 2010 15:38
To: davinci-linux-open-source at linux.davincidsp.com
Subject: Audio dropouts since using DM6443 silicon rev. 2.1

Hi,

I have a custom board with DaVinci DM6443 with kernel TI LSP 2.0.0.140 (MV 2.6.18), DVSDK 2.0.0.22 and TI gStreamer for video / audio playback.
In parallel to the playback there is a HTTP and a FTP server running on the ARM. The HTTP server is used to configure the board via web browser and the FTP server is used to do content uploads.

Now I received the first boards with silicon rev 2.1 (TMS320DM6443A).
All these boards have the same problem. 
When the HTTP server (as long as the user is configuring the board) or FTP server (as long as the user is uploading new content) is working in parallel to video playback, I get audio dropouts at the line out. Just doing video / audio playback works fine. 
I guess, this has something to do with the extra system load caused by the servers. Playing around with nice levels of the servers did not help.

I don't have this problem with silicon revision 1.3. The only difference between both systems is just the silicon rev. of the DaVinci (same hardware, same firmware).

I found this in the Silicon Errata:
http://focus.ti.com/lit/er/sprz240m/sprz240m.pdf
Page 8:	2.1.3 Audio Serial Port (ASP) Transfers Should be Buffered in
Internal Memory


For me it seems, this issue might be the root cause for the problem I came across?
I guess, TI LSP doesn't use the internal memory to buffer audio? At least I didn't find it...
I currently don't understand, why I have this problem with silicon rev
2.1 only. Does this make sense?

In the archive of this list I found some patches for git kernel, which introduced usage of internal memory to avoid underrun on audio.

I guess, this is what have to implement on my kernel as well?

Has anyone done this before for MV 2.6.18 ?

Unfortunately, I don't have the resources to switch to the git kernel at the moment. And AFAIK, video playback on DM644x is still not supported by TI DVSDK with git kernel.

Thanks in advance!

Kind regards
Thomas

From viral at allaboutif.com  Tue May 11 08:45:15 2010
From: viral at allaboutif.com (Viral Sachde)
Date: Tue, 11 May 2010 19:15:15 +0530
Subject: Audio dropouts since using DM6443 silicon rev. 2.1
In-Reply-To: <BFE810BB1BD20E47876F1BB1EA7BF730686F3D@srv-exchange.datadisplay.de>
References: <BFE810BB1BD20E47876F1BB1EA7BF7305C91FF@srv-exchange.datadisplay.de>
	<84E5692253AB2749AB4C49395A570735082673F2@GTMDHQEXCLUS.optelecom.com>
	<BFE810BB1BD20E47876F1BB1EA7BF730686F3D@srv-exchange.datadisplay.de>
Message-ID: <AANLkTikcUx_4ZENaWFy7RT-3YvizVa5nQctKnnPxP8u7@mail.gmail.com>

On Tue, May 11, 2010 at 6:36 PM, DISTEC Kloiber Thomas
<Kloiber at distec.de> wrote:
> Hi Arie,
> I just wanted to let you know, that you exactly hit the mark with your assumption regarding the priority registers below.
> Thank you very much!
> Some details for the list:
> Due to a silicon bug in DM6443 rev 1.3 the default value 0x00040444 was used for register MSTPRI0 (see silicon errata for details). This register is responsible for "Switched Central Resource (SCR) Bus Priorities". This register was not initialized in our firmware at all. The default value just worked fine.
> In silicon rev 2.1 this bug has been fixed and thus the default value has changed to 0x00050111. For us this value caused the problem I described below.
> Now I'm setting the register to 0x00040444 in u-boot explicitly and everything works fine for silicon rev 2.1 as well.
> Thanks again!
> Kind regards
> Thomas

Hi, I would suggest you to look in to errata. Hope audio buffers are
in IRAM as suggested in it.
Regards, Viral

From thomas.koeller at baslerweb.com  Tue May 11 10:06:46 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Tue, 11 May 2010 17:06:46 +0200
Subject: [PATCH 0/3] More PINMUX definitions
Message-ID: <1273590409-10433-1-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

Patch series is against Kevin's tree this time. They
introduce new PINMUX settings that are required to support
the board I am working on.

Thomas Koeller (3):
  DM365: Added PINMUX definitions for GPIO30..32
  DM365: Make CLKOUTx available
  DM365: Added more PINMUX configurations for AEMIF

 arch/arm/mach-davinci/dm365.c            |   12 +++++++++++-
 arch/arm/mach-davinci/include/mach/mux.h |   13 ++++++++++++-
 2 files changed, 23 insertions(+), 2 deletions(-)


From thomas.koeller at baslerweb.com  Tue May 11 10:06:47 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Tue, 11 May 2010 17:06:47 +0200
Subject: [PATCH 1/3] DM365: Added PINMUX definitions for GPIO30..32
In-Reply-To: <1273590409-10433-1-git-send-email-thomas.koeller@baslerweb.com>
References: <1273590409-10433-1-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <1273590409-10433-2-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

Board code may want to use them.

Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
---
 arch/arm/mach-davinci/dm365.c            |    3 +++
 arch/arm/mach-davinci/include/mach/mux.h |    3 +++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index ed76450..4c04ae5 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -569,6 +569,9 @@ MUX_CFG(DM365,	SPI4_SDENA0,	4,   20,    3,    1,	 false)
 MUX_CFG(DM365,	SPI4_SDENA1,	4,   16,    3,    2,	 false)
 
 MUX_CFG(DM365,	GPIO20,		3,   21,    3,    0,	 false)
+MUX_CFG(DM365,	GPIO30,		4,   6,     3,	  0,	 false)
+MUX_CFG(DM365,	GPIO31,		4,   8,     3,	  0,	 false)
+MUX_CFG(DM365,	GPIO32,		4,   10,    3,	  0,	 false)
 MUX_CFG(DM365,	GPIO33,		4,   12,    3,	  0,	 false)
 MUX_CFG(DM365,	GPIO40,		4,   26,    3,	  0,	 false)
 MUX_CFG(DM365,	GPIO64_57,	2,   6,     1,	  0,	 false)
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 743dbd2..4a1fdd3 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -289,6 +289,9 @@ enum davinci_dm365_index {
 
 	/* GPIO */
 	DM365_GPIO20,
+	DM365_GPIO30,
+	DM365_GPIO31,
+	DM365_GPIO32,
 	DM365_GPIO33,
 	DM365_GPIO40,
 	DM365_GPIO64_57,
-- 
1.7.1


From thomas.koeller at baslerweb.com  Tue May 11 10:06:48 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Tue, 11 May 2010 17:06:48 +0200
Subject: [PATCH 2/3] DM365: Make CLKOUTx available
In-Reply-To: <1273590409-10433-1-git-send-email-thomas.koeller@baslerweb.com>
References: <1273590409-10433-1-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <1273590409-10433-3-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

Added PINMUX configurations for the CLKOUT0 .. CLKOUT2
functions, for boards that want to use these clocks.

Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
---
 arch/arm/mach-davinci/dm365.c            |    4 ++++
 arch/arm/mach-davinci/include/mach/mux.h |    5 +++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 4c04ae5..51ac8e1 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -568,6 +568,10 @@ MUX_CFG(DM365,	SPI4_SDO,	4,   16,    3,    1,	 false)
 MUX_CFG(DM365,	SPI4_SDENA0,	4,   20,    3,    1,	 false)
 MUX_CFG(DM365,	SPI4_SDENA1,	4,   16,    3,    2,	 false)
 
+MUX_CFG(DM365,	CLKOUT0,	4,   20,    3,    3,     false)
+MUX_CFG(DM365,	CLKOUT1,	4,   16,    3,    3,     false)
+MUX_CFG(DM365,	CLKOUT2,	4,   8,     3,    3,     false)
+
 MUX_CFG(DM365,	GPIO20,		3,   21,    3,    0,	 false)
 MUX_CFG(DM365,	GPIO30,		4,   6,     3,	  0,	 false)
 MUX_CFG(DM365,	GPIO31,		4,   8,     3,	  0,	 false)
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 4a1fdd3..07ef83b 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -287,6 +287,11 @@ enum davinci_dm365_index {
 	DM365_SPI4_SDENA0,
 	DM365_SPI4_SDENA1,
 
+	/* Clock */
+	DM365_CLKOUT0,
+	DM365_CLKOUT1,
+	DM365_CLKOUT2,
+
 	/* GPIO */
 	DM365_GPIO20,
 	DM365_GPIO30,
-- 
1.7.1


From thomas.koeller at baslerweb.com  Tue May 11 10:06:49 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Tue, 11 May 2010 17:06:49 +0200
Subject: [PATCH 3/3] DM365: Added more PINMUX configurations for AEMIF
In-Reply-To: <1273590409-10433-1-git-send-email-thomas.koeller@baslerweb.com>
References: <1273590409-10433-1-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <1273590409-10433-4-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

More complete AEMIF support for boards.

Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
---
 arch/arm/mach-davinci/dm365.c            |    5 ++++-
 arch/arm/mach-davinci/include/mach/mux.h |    5 ++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 51ac8e1..01bc7b8 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -485,11 +485,14 @@ MUX_CFG(DM365,	SD1_DATA0,	4,   22,    3,	  1,	 false)
 MUX_CFG(DM365,	I2C_SDA,	3,   23,    3,	  2,	 false)
 MUX_CFG(DM365,	I2C_SCL,	3,   21,    3,	  2,	 false)
 
-MUX_CFG(DM365,	AEMIF_AR,	2,   0,     3,	  1,	 false)
+MUX_CFG(DM365,	AEMIF_AR_A14,	2,   0,     3,	  1,	 false)
+MUX_CFG(DM365,	AEMIF_AR_BA0,	2,   0,     3,	  2,	 false)
 MUX_CFG(DM365,	AEMIF_A3,	2,   2,     3,	  1,	 false)
 MUX_CFG(DM365,	AEMIF_A7,	2,   4,     3,	  1,	 false)
 MUX_CFG(DM365,	AEMIF_D15_8,	2,   6,     1,	  1,	 false)
 MUX_CFG(DM365,	AEMIF_CE0,	2,   7,     1,	  0,	 false)
+MUX_CFG(DM365,	AEMIF_CE1,	2,   8,     1,    0,     false)
+MUX_CFG(DM365,	AEMIF_WE_OE,	2,   9,     1,    0,     false)
 
 MUX_CFG(DM365,	MCBSP0_BDX,	0,   23,    1,	  1,	 false)
 MUX_CFG(DM365,	MCBSP0_X,	0,   22,    1,	  1,	 false)
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 07ef83b..de11aac 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -194,11 +194,14 @@ enum davinci_dm365_index {
 	DM365_I2C_SCL,
 
 	/* AEMIF */
-	DM365_AEMIF_AR,
+	DM365_AEMIF_AR_A14,
+	DM365_AEMIF_AR_BA0,
 	DM365_AEMIF_A3,
 	DM365_AEMIF_A7,
 	DM365_AEMIF_D15_8,
 	DM365_AEMIF_CE0,
+	DM365_AEMIF_CE1,
+	DM365_AEMIF_WE_OE,
 
 	/* ASP0 function */
 	DM365_MCBSP0_BDX,
-- 
1.7.1


From jaya.krishnan at samsung.com  Wed May 12 02:35:07 2010
From: jaya.krishnan at samsung.com (Jaya krishnan)
Date: Wed, 12 May 2010 07:35:07 +0000 (GMT)
Subject: DM6467 McASP : unable to set  GBLCTL   for  port1
Message-ID: <32862071.147561273649707690.JavaMail.weblogic@epml20>



Vaibhav,
 The issue  is solved  now.  McASP1  was turned  off  in the  power  and  sleep  controller.
It started  working  after  I  enabled it. 
Thanks & Regards
JK

 

------- Original Message-------
Sender: Bedia, Vaibhav<vaibhav.bedia at ti.com>
Date: May 11, 2010 19:44 (GMT+09:00)
Title: RE: DM6467 McASP : unable to set GBLCTL for port1

Jayakrishnan, 

You need to check whether path for AUDIO_CLK1 is set up properly (CLKCTL and PINMUX0 registers). Please refer to the TRM for these registers. 

If port 0 is also not working then you could check the AUXCLK generated from the PLL by attaching a probe to the CLKOUT pin available. 

Regards, 
Vaibhav 

-----Original Message----- 
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com]  
Sent: Tuesday, May 11, 2010 3:14 PM 
To: Bedia, Vaibhav; davinci-linux-open-source at linux.davincidsp.com 
Cc: Pasupathy, Visuvanadan 
Subject: Re: DM6467 McASP : unable to set GBLCTL for port1 


Thanks Vaibhav. 
With  the  settings I  mentioned, the execution goes into infinite while loop, as  the  XHCLKRST write  operation was  not successful. 
How  to  check the AUXCLK input  to McASP1? 
Regards 
JK 


  
  
  

------- Original Message------- 
Sender: Bedia, Vaibhav<vaibhav.bedia at ti.com> 
Date: May 11, 2010 18:26 (GMT+09:00) 
Title: RE: DM6467 McASP : unable to set GBLCTL for port1 

With the register config as you mentioned, what do you observe when you try to write to XHCLKRST bit followed by a write to XCLKRST bit in GBLCTL?  

Also, please verify that AUXCLK is coming in to McASP1. If not, you need to check whether there in any additional PLL setting required for this.  

Regards,  
Vaibhav  

-----Original Message-----  
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com]   
Sent: Tuesday, May 11, 2010 10:25 AM  
To: Bedia, Vaibhav; davinci-linux-open-source at linux.davincidsp.com  
Cc: Pasupathy, Visuvanadan  
Subject: RE: DM6467 McASP : unable to set GBLCTL for port1  



   
 Vaibhav,   
Thanks  for the  reply.  
I have  selected intenal  clk  sources  for both ACLKXCTL  and AHCLKXCTL  
ACLKXCTL=0x00000061  
AHCLKXCTL=0x00008033  
PDIR=0x0A000000  
ACLKX1 is  not  produced. The  above  settings  should  produce ACLKX1, so that GBLCTLX  can be  set. Am I correct?  
What  are  the  other  checks  to be  done, so that ACLKX1  is  produced?  Pls  reply  

Regards  
JK  
------- Original Message-------  
Sender: Bedia, Vaibhav<vaibhav.bedia at ti.com>  
Date: May 10, 2010 21:42 (GMT+09:00)  
Title: RE: DM6467 McASP : unable to set GBLCTL for port1  


Jayakrishnan,   

The bit field in GBLCTL register that you are trying to set is synchronized and latched by the corresponding clock(ACLKX in your case).   

Since you want to use AHCLKX1 as master clk for another device I suspect the ACLKX is not already running. If you don't have ACLKX externally generated you need to select the internal clk source in ACLKXCTL (and possibly even in AHCLKXCTL - depends on the use case) before GBLCTL is programmed.   

Regards,   
Vaibhav   


-----Original Message-----   
From: Jaya krishnan [mailto:jaya.krishnan at samsung.com]    
Sent: Monday, May 10, 2010 2:48 PM   
To: davinci-linux-open-source at linux.davincidsp.com; Bedia, Vaibhav   
Subject: DM6467 McASP : unable to set GBLCTL for port1   


I want  to  use  AHCLKX1   (from port 1)  to be used as  master clk  for  another  device in the  system.    
But  I am  not  able  to  set GBLCTL.  for port 1   
bit= 1<<9;   
 bit &= 0x1f00;   
  mcasp_port[port].mcasp_vregs->gblctlx |= bit;   
    while ((mcasp_port[port].mcasp_vregs->gblctlx & bit) != bit);   
It  does come out  from the  while  loop. But  for port 0  no  such problem. Pls  help   


       
Jayakrishnan M M   
Research Engineer   
R&D Team-2 , Group-5   
Security Solutions  Division   
SAMSUNG TECHWIN CO.,LTD   

TEL +82-70-7147-8482   
FAX +82-31-8018-3712   
Mobile +82-10-6409-3619   
E-mail:jaya.krishnan at samsung.com   
    
     

   
      
Jayakrishnan M M  
Research Engineer  
R&D Team-2 , Group-5  
Security Solutions  Division  
SAMSUNG TECHWIN CO.,LTD  

TEL +82-70-7147-8482  
FAX +82-31-8018-3712  
Mobile +82-10-6409-3619  
E-mail:jaya.krishnan at samsung.com  
   
    
   
   

  
     
Jayakrishnan M M 
Research Engineer 
R&D Team-2 , Group-5 
Security Solutions  Division 
SAMSUNG TECHWIN CO.,LTD 

TEL +82-70-7147-8482 
FAX +82-31-8018-3712 
Mobile +82-10-6409-3619 
E-mail:jaya.krishnan at samsung.com 
  
   
  
  

 
    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  
 
 

From sshtylyov at ru.mvista.com  Wed May 12 13:12:11 2010
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Wed, 12 May 2010 22:12:11 +0400
Subject: [PATCH RFC v8] MUSB: DA8xx/OMAP-L1x glue layer
Message-ID: <201005122212.11729.sshtylyov@ru.mvista.com>

Texas Instruments DA8xx/OMAP-L1x glue layer for the MUSBMHRDC driver.

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
Signed-off-by: Yadviga Grigorieva <yadviga at ru.mvista.com>

---
The patch is against the recent Linus' tree.

WARNING: the MUSB and OHCI drivers will only work if your boot loader leaves
the DA8xx boot configuration registers unlocked, otherwise they will lock up
the kernel!

Changes since the previous version:
- removed DMA related code (to be added back by a later patch);
- removed spurious interrupt message from da8xx_interrupt();
- added a check for USB 1.1 being clocked from USB 2.0 PHY to phy_off();
- moved USB register #define's from cppi41_dma.h in another patch, adding
  'DA8XX_' prefix to them;
- s/DA8XX_[RT]X_EP_MASK/DA8XX_USB_[RT]X_EP_MASK/, s/DA8XX_[RT]X_INTR_MASK/
  DA8XX_INTR_[RT]X_MASK/, also reordered these macros;
- used IO_ADDRESS() macro in #define CFGCHIP2 to avoid having to export
  'da8xx_syscfg0_base' for modular build;
- removed setting 'musb->is_active' from the code handling DRVVBUS interrupt;
- moved the transceiver initialization further down in musb_platform_init();
- moved s/ARCH_DAVINCI/ARCH_DAVINCI_DMx/ change into the separate patch;
- fixed up some comments;
- fixed reject in musb_core.h...

 drivers/usb/musb/Kconfig     |    5 
 drivers/usb/musb/Makefile    |    4 
 drivers/usb/musb/da8xx.c     |  492 +++++++++++++++++++++++++++++++++++++++++++
 drivers/usb/musb/musb_core.h |    1 
 4 files changed, 501 insertions(+), 1 deletion(-)

Index: linux-2.6/drivers/usb/musb/Kconfig
===================================================================
--- linux-2.6.orig/drivers/usb/musb/Kconfig
+++ linux-2.6/drivers/usb/musb/Kconfig
@@ -44,6 +44,9 @@ config USB_MUSB_SOC
 comment "DaVinci 35x and 644x USB support"
 	depends on USB_MUSB_HDRC && ARCH_DAVINCI_DMx
 
+comment "DA8xx/OMAP-L1x USB support"
+	depends on USB_MUSB_HDRC && ARCH_DAVINCI_DA8XX
+
 comment "OMAP 243x high speed USB support"
 	depends on USB_MUSB_HDRC && ARCH_OMAP2430
 
@@ -140,7 +143,7 @@ config USB_MUSB_HDRC_HCD
 config MUSB_PIO_ONLY
 	bool 'Disable DMA (always use PIO)'
 	depends on USB_MUSB_HDRC
-	default y if USB_TUSB6010
+	default USB_TUSB6010 || ARCH_DAVINCI_DA8XX
 	help
 	  All data is copied between memory and FIFO by the CPU.
 	  DMA controllers are ignored.
Index: linux-2.6/drivers/usb/musb/Makefile
===================================================================
--- linux-2.6.orig/drivers/usb/musb/Makefile
+++ linux-2.6/drivers/usb/musb/Makefile
@@ -10,6 +10,10 @@ ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y)
 	musb_hdrc-objs	+= davinci.o
 endif
 
+ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y)
+	musb_hdrc-objs	+= da8xx.o
+endif
+
 ifeq ($(CONFIG_USB_TUSB6010),y)
 	musb_hdrc-objs	+= tusb6010.o
 endif
Index: linux-2.6/drivers/usb/musb/da8xx.c
===================================================================
--- /dev/null
+++ linux-2.6/drivers/usb/musb/da8xx.c
@@ -0,0 +1,492 @@
+/*
+ * Texas Instruments DA8xx/OMAP-L1x "glue layer"
+ *
+ * Copyright (c) 2008-2009 MontaVista Software, Inc. <source at mvista.com>
+ *
+ * Based on the DaVinci "glue layer" code.
+ * Copyright (C) 2005-2006 by Texas Instruments
+ *
+ * This file is part of the Inventra Controller Driver for Linux.
+ *
+ * The Inventra Controller Driver for Linux is free software; you
+ * can redistribute it and/or modify it under the terms of the GNU
+ * General Public License version 2 as published by the Free Software
+ * Foundation.
+ *
+ * The Inventra Controller Driver for Linux is distributed in
+ * the hope that it will be useful, but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+ * License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with The Inventra Controller Driver for Linux ; if not,
+ * write to the Free Software Foundation, Inc., 59 Temple Place,
+ * Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/da8xx.h>
+#include <mach/usb.h>
+
+#include "musb_core.h"
+
+/*
+ * DA8XX specific definitions
+ */
+
+/* USB 2.0 OTG module registers */
+#define DA8XX_USB_REVISION_REG	0x00
+#define DA8XX_USB_CTRL_REG	0x04
+#define DA8XX_USB_STAT_REG	0x08
+#define DA8XX_USB_EMULATION_REG 0x0c
+#define DA8XX_USB_MODE_REG	0x10	/* Transparent, CDC, [Generic] RNDIS */
+#define DA8XX_USB_AUTOREQ_REG	0x14
+#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
+#define DA8XX_USB_TEARDOWN_REG	0x1c
+#define DA8XX_USB_INTR_SRC_REG	0x20
+#define DA8XX_USB_INTR_SRC_SET_REG 0x24
+#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
+#define DA8XX_USB_INTR_MASK_REG 0x2c
+#define DA8XX_USB_INTR_MASK_SET_REG 0x30
+#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
+#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
+#define DA8XX_USB_END_OF_INTR_REG 0x3c
+#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
+
+/* Control register bits */
+#define DA8XX_SOFT_RESET_MASK	1
+
+#define DA8XX_USB_TX_EP_MASK	0x1f		/* EP0 + 4 Tx EPs */
+#define DA8XX_USB_RX_EP_MASK	0x1e		/* 4 Rx EPs */
+
+/* USB interrupt register bits */
+#define DA8XX_INTR_USB_SHIFT	16
+#define DA8XX_INTR_USB_MASK	(0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
+					/* interrupts and DRVVBUS interrupt */
+#define DA8XX_INTR_DRVVBUS	0x100
+#define DA8XX_INTR_RX_SHIFT	8
+#define DA8XX_INTR_RX_MASK	(DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
+#define DA8XX_INTR_TX_SHIFT	0
+#define DA8XX_INTR_TX_MASK	(DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
+
+#define DA8XX_MENTOR_CORE_OFFSET 0x400
+
+#define CFGCHIP2	IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
+
+/*
+ * REVISIT (PM): we should be able to keep the PHY in low power mode most
+ * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
+ * and, when in host mode, autosuspending idle root ports... PHY_PLLON
+ * (overriding SUSPENDM?) then likely needs to stay off.
+ */
+
+static inline void phy_on(void)
+{
+	u32 cfgchip2 = __raw_readl(CFGCHIP2);
+
+	/*
+	 * Start the on-chip PHY and its PLL.
+	 */
+	cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
+	cfgchip2 |= CFGCHIP2_PHY_PLLON;
+	__raw_writel(cfgchip2, CFGCHIP2);
+
+	pr_info("Waiting for USB PHY clock good...\n");
+	while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
+		cpu_relax();
+}
+
+static inline void phy_off(void)
+{
+	u32 cfgchip2 = __raw_readl(CFGCHIP2);
+
+	/*
+	 * Ensure that USB 1.1 reference clock is not being sourced from
+	 * USB 2.0 PHY.  Otherwise do not power down the PHY.
+	 */
+	if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
+	     (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
+		pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
+			   "can't power it down\n");
+		return;
+	}
+
+	/*
+	 * Power down the on-chip PHY.
+	 */
+	cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
+	__raw_writel(cfgchip2, CFGCHIP2);
+}
+
+/*
+ * Because we don't set CTRL.UINT, it's "important" to:
+ *	- not read/write INTRUSB/INTRUSBE (except during
+ *	  initial setup, as a workaround);
+ *	- use INTSET/INTCLR instead.
+ */
+
+/**
+ * musb_platform_enable - enable interrupts
+ */
+void musb_platform_enable(struct musb *musb)
+{
+	void __iomem *reg_base = musb->ctrl_base;
+	u32 mask;
+
+	/* Workaround: setup IRQs through both register sets. */
+	mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
+	       ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
+	       DA8XX_INTR_USB_MASK;
+	musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
+
+	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
+	if (is_otg_enabled(musb))
+		musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
+			    DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
+}
+
+/**
+ * musb_platform_disable - disable HDRC and flush interrupts
+ */
+void musb_platform_disable(struct musb *musb)
+{
+	void __iomem *reg_base = musb->ctrl_base;
+
+	musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
+		    DA8XX_INTR_USB_MASK |
+		    DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
+	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
+	musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
+}
+
+#ifdef CONFIG_USB_MUSB_HDRC_HCD
+#define portstate(stmt) 	stmt
+#else
+#define portstate(stmt)
+#endif
+
+static void da8xx_set_vbus(struct musb *musb, int is_on)
+{
+	WARN_ON(is_on && is_peripheral_active(musb));
+}
+
+#define	POLL_SECONDS	2
+
+static struct timer_list otg_workaround;
+
+static void otg_timer(unsigned long _musb)
+{
+	struct musb		*musb = (void *)_musb;
+	void __iomem		*mregs = musb->mregs;
+	u8			devctl;
+	unsigned long		flags;
+
+	/*
+	 * We poll because DaVinci's won't expose several OTG-critical
+	 * status change events (from the transceiver) otherwise.
+	 */
+	devctl = musb_readb(mregs, MUSB_DEVCTL);
+	DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
+
+	spin_lock_irqsave(&musb->lock, flags);
+	switch (musb->xceiv->state) {
+	case OTG_STATE_A_WAIT_BCON:
+		devctl &= ~MUSB_DEVCTL_SESSION;
+		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+
+		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+		if (devctl & MUSB_DEVCTL_BDEVICE) {
+			musb->xceiv->state = OTG_STATE_B_IDLE;
+			MUSB_DEV_MODE(musb);
+		} else {
+			musb->xceiv->state = OTG_STATE_A_IDLE;
+			MUSB_HST_MODE(musb);
+		}
+		break;
+	case OTG_STATE_A_WAIT_VFALL:
+		/*
+		 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
+		 * RTL seems to mis-handle session "start" otherwise (or in
+		 * our case "recover"), in routine "VBUS was valid by the time
+		 * VBUSERR got reported during enumeration" cases.
+		 */
+		if (devctl & MUSB_DEVCTL_VBUS) {
+			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+			break;
+		}
+		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
+		musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
+			    MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
+		break;
+	case OTG_STATE_B_IDLE:
+		if (!is_peripheral_enabled(musb))
+			break;
+
+		/*
+		 * There's no ID-changed IRQ, so we have no good way to tell
+		 * when to switch to the A-Default state machine (by setting
+		 * the DEVCTL.Session bit).
+		 *
+		 * Workaround:  whenever we're in B_IDLE, try setting the
+		 * session flag every few seconds.  If it works, ID was
+		 * grounded and we're now in the A-Default state machine.
+		 *
+		 * NOTE: setting the session flag is _supposed_ to trigger
+		 * SRP but clearly it doesn't.
+		 */
+		musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
+		devctl = musb_readb(mregs, MUSB_DEVCTL);
+		if (devctl & MUSB_DEVCTL_BDEVICE)
+			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+		else
+			musb->xceiv->state = OTG_STATE_A_IDLE;
+		break;
+	default:
+		break;
+	}
+	spin_unlock_irqrestore(&musb->lock, flags);
+}
+
+void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
+{
+	static unsigned long last_timer;
+
+	if (!is_otg_enabled(musb))
+		return;
+
+	if (timeout == 0)
+		timeout = jiffies + msecs_to_jiffies(3);
+
+	/* Never idle if active, or when VBUS timeout is not set as host */
+	if (musb->is_active || (musb->a_wait_bcon == 0 &&
+				musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
+		DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
+		del_timer(&otg_workaround);
+		last_timer = jiffies;
+		return;
+	}
+
+	if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
+		DBG(4, "Longer idle timer already pending, ignoring...\n");
+		return;
+	}
+	last_timer = timeout;
+
+	DBG(4, "%s inactive, starting idle timer for %u ms\n",
+	    otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
+	mod_timer(&otg_workaround, timeout);
+}
+
+static irqreturn_t da8xx_interrupt(int irq, void *hci)
+{
+	struct musb		*musb = hci;
+	void __iomem		*reg_base = musb->ctrl_base;
+	unsigned long		flags;
+	irqreturn_t		ret = IRQ_NONE;
+	u32			status;
+
+	spin_lock_irqsave(&musb->lock, flags);
+
+	/*
+	 * NOTE: DA8XX shadows the Mentor IRQs.  Don't manage them through
+	 * the Mentor registers (except for setup), use the TI ones and EOI.
+	 */
+
+	/* Acknowledge and handle non-CPPI interrupts */
+	status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
+	if (!status)
+		goto eoi;
+
+	musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
+	DBG(4, "USB IRQ %08x\n", status);
+
+	musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
+	musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
+	musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
+
+	/*
+	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
+	 * DA8xx's missing ID change IRQ.  We need an ID change IRQ to
+	 * switch appropriately between halves of the OTG state machine.
+	 * Managing DEVCTL.Session per Mentor docs requires that we know its
+	 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
+	 * Also, DRVVBUS pulses for SRP (but not at 5 V)...
+	 */
+	if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
+		int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
+		void __iomem *mregs = musb->mregs;
+		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
+		int err;
+
+		err = is_host_enabled(musb) && (musb->int_usb &
+						MUSB_INTR_VBUSERROR);
+		if (err) {
+			/*
+			 * The Mentor core doesn't debounce VBUS as needed
+			 * to cope with device connect current spikes. This
+			 * means it's not uncommon for bus-powered devices
+			 * to get VBUS errors during enumeration.
+			 *
+			 * This is a workaround, but newer RTL from Mentor
+			 * seems to allow a better one: "re"-starting sessions
+			 * without waiting for VBUS to stop registering in
+			 * devctl.
+			 */
+			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
+			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
+			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+			WARNING("VBUS error workaround (delay coming)\n");
+		} else if (is_host_enabled(musb) && drvvbus) {
+			MUSB_HST_MODE(musb);
+			musb->xceiv->default_a = 1;
+			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
+			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
+			del_timer(&otg_workaround);
+		} else {
+			musb->is_active = 0;
+			MUSB_DEV_MODE(musb);
+			musb->xceiv->default_a = 0;
+			musb->xceiv->state = OTG_STATE_B_IDLE;
+			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
+		}
+
+		DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
+				drvvbus ? "on" : "off",
+				otg_state_string(musb),
+				err ? " ERROR" : "",
+				devctl);
+		ret = IRQ_HANDLED;
+	}
+
+	if (musb->int_tx || musb->int_rx || musb->int_usb)
+		ret |= musb_interrupt(musb);
+
+ eoi:
+	/* EOI needs to be written for the IRQ to be re-asserted. */
+	if (ret == IRQ_HANDLED || status)
+		musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
+
+	/* Poll for ID change */
+	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
+		mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+
+	spin_unlock_irqrestore(&musb->lock, flags);
+
+	return ret;
+}
+
+int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
+{
+	u32 cfgchip2 = __raw_readl(CFGCHIP2);
+
+	cfgchip2 &= ~CFGCHIP2_OTGMODE;
+	switch (musb_mode) {
+#ifdef	CONFIG_USB_MUSB_HDRC_HCD
+	case MUSB_HOST:		/* Force VBUS valid, ID = 0 */
+		cfgchip2 |= CFGCHIP2_FORCE_HOST;
+		break;
+#endif
+#ifdef	CONFIG_USB_GADGET_MUSB_HDRC
+	case MUSB_PERIPHERAL:	/* Force VBUS valid, ID = 1 */
+		cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
+		break;
+#endif
+#ifdef	CONFIG_USB_MUSB_OTG
+	case MUSB_OTG:		/* Don't override the VBUS/ID comparators */
+		cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
+		break;
+#endif
+	default:
+		DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
+	}
+
+	__raw_writel(cfgchip2, CFGCHIP2);
+	return 0;
+}
+
+int __init musb_platform_init(struct musb *musb)
+{
+	void __iomem *reg_base = musb->ctrl_base;
+	u32 rev;
+
+	musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
+
+	clk_enable(musb->clock);
+
+	/* Returns zero if e.g. not clocked */
+	rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
+	if (!rev) {
+		clk_disable(musb->clock);
+		return -ENODEV;
+	}
+
+	usb_nop_xceiv_register();
+	musb->xceiv = otg_get_transceiver();
+	if (!musb->xceiv)
+		return -ENODEV;
+
+	if (is_host_enabled(musb))
+		setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
+
+	musb->board_set_vbus = da8xx_set_vbus;
+
+	/* Reset the controller */
+	musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
+
+	/* Start the on-chip PHY and its PLL. */
+	phy_on();
+
+	msleep(5);
+
+	/* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
+	pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
+		 rev, __raw_readl(CFGCHIP2),
+		 musb_readb(reg_base, DA8XX_USB_CTRL_REG));
+
+	musb->isr = da8xx_interrupt;
+	return 0;
+}
+
+int musb_platform_exit(struct musb *musb)
+{
+	if (is_host_enabled(musb))
+		del_timer_sync(&otg_workaround);
+
+	/* Delay to avoid problems with module reload... */
+	if (is_host_enabled(musb) && musb->xceiv->default_a) {
+		u8 devctl, warn = 0;
+		int delay;
+
+		/*
+		 * If there's no peripheral connected, VBUS can take a
+		 * long time to fall...
+		 */
+		for (delay = 30; delay > 0; delay--) {
+			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+			if (!(devctl & MUSB_DEVCTL_VBUS))
+				goto done;
+			if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
+				warn = devctl & MUSB_DEVCTL_VBUS;
+				DBG(1, "VBUS %d\n",
+					warn >> MUSB_DEVCTL_VBUS_SHIFT);
+			}
+			msleep(1000);
+		}
+
+		/* In OTG mode, another host might be connected... */
+		DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
+	}
+done:
+	phy_off();
+
+	usb_nop_xceiv_unregister();
+
+	clk_disable(musb->clock);
+
+	return 0;
+}
Index: linux-2.6/drivers/usb/musb/musb_core.h
===================================================================
--- linux-2.6.orig/drivers/usb/musb/musb_core.h
+++ linux-2.6/drivers/usb/musb/musb_core.h
@@ -596,6 +596,7 @@ extern void musb_hnp_stop(struct musb *m
 extern int musb_platform_set_mode(struct musb *musb, u8 musb_mode);
 
 #if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_BLACKFIN) || \
+	defined(CONFIG_ARCH_DAVINCI_DA8XX) || \
 	defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
 extern void musb_platform_try_idle(struct musb *musb, unsigned long timeout);
 #else

From bengardiner at nanometrics.ca  Wed May 12 15:27:45 2010
From: bengardiner at nanometrics.ca (Ben Gardiner)
Date: Wed, 12 May 2010 16:27:45 -0400
Subject: da850-evm: MMC and NAND/NOR are mutually exclusive?
Message-ID: <AANLkTimDKzxTfkb7CI6EhUMJo2w-FEWfts51kBj9AoT7@mail.gmail.com>

We are prototyping a system using the DA850 / L138 EVM from LogicPD.
We noticed that in da850_evm_setup_nor_nand() of
arch/arm/mach-davinci/board-da850-evm.c in both the davinci-linux and
linux-omapl1 trees [1][2] there is a check for !HAS_MMC before NAND
and NOR are initialized. This appears to be making use of SD/MMC cards
and NAND flash mutually exclusive.

We are interested in deploying a system that has both NAND flash and
SD card support. As far as we can tell the restrictions due to SoC
pin-mux are between SD0 and NOR but not NAND. We had a look through
the EVM schematics and can't readily see any NAND vs SD0 conflicts
there either.

We would greatly appreciate any insight this list has into why the
da850 board setup routine makes NAND and MMC support mutually
exclusive.

Best Regards,

Ben Gardiner

[1] http://git.kernel.org/?p=linux/kernel/git/khilman/linux-davinci.git;a=blob;f=arch/arm/mach-davinci/board-da850-evm.c;h=0c7afacd40988c1339da606908dc63f00f8445cb;hb=HEAD#l211

[2] http://arago-project.org/git/projects/?p=linux-omapl1.git;a=blob;f=arch/arm/mach-davinci/board-da850-evm.c;h=cfed439d05aaa9146875dfd7e3cfd099a69179b3;hb=HEAD#l282

-- 
Ben Gardiner
Nanometrics Inc.
+1 (613) 592-6776 x239
http://www.nanometrics.ca

From jon.povey at racelogic.co.uk  Wed May 12 21:33:46 2010
From: jon.povey at racelogic.co.uk (Jon Povey)
Date: Thu, 13 May 2010 11:33:46 +0900
Subject: [PATCH v3] USB: musb: suppress warning about unused flags
Message-ID: <1273718026-14211-1-git-send-email-jon.povey@racelogic.co.uk>

Wrap flags with uninitialized_var() to suppress this:

drivers/usb/musb/cppi_dma.c:1158: warning: 'flags' may be used uninitialized
in this function

Signed-off-by: Jon Povey <jon.povey at racelogic.co.uk>
---
Revised after feedback from davinci mailing list, and signoff added.

 drivers/usb/musb/cppi_dma.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
index 59dc3d3..e3753ba 100644
--- a/drivers/usb/musb/cppi_dma.c
+++ b/drivers/usb/musb/cppi_dma.c
@@ -1155,7 +1155,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
 	struct musb_hw_ep	*hw_ep = NULL;
 	u32			rx, tx;
 	int			i, index;
-	unsigned long		flags;
+	unsigned long		uninitialized_var(flags);
 
 	cppi = container_of(musb->dma_controller, struct cppi, controller);
 	if (cppi->irq)
-- 
1.6.3.3


From sudhakar.raj at ti.com  Wed May 12 22:21:59 2010
From: sudhakar.raj at ti.com (Sudhakar Rajashekhara)
Date: Thu, 13 May 2010 08:51:59 +0530
Subject: da850-evm: MMC and NAND/NOR are mutually exclusive?
In-Reply-To: <AANLkTimDKzxTfkb7CI6EhUMJo2w-FEWfts51kBj9AoT7@mail.gmail.com>
References: <AANLkTimDKzxTfkb7CI6EhUMJo2w-FEWfts51kBj9AoT7@mail.gmail.com>
Message-ID: <005e01caf24b$7283a6e0$578af4a0$@raj@ti.com>

Hi Ben,

On Thu, May 13, 2010 at 01:57:45, Ben Gardiner wrote:
> We are prototyping a system using the DA850 / L138 EVM from LogicPD.
> We noticed that in da850_evm_setup_nor_nand() of
> arch/arm/mach-davinci/board-da850-evm.c in both the davinci-linux and
> linux-omapl1 trees [1][2] there is a check for !HAS_MMC before NAND
> and NOR are initialized. This appears to be making use of SD/MMC cards
> and NAND flash mutually exclusive.
> 
> We are interested in deploying a system that has both NAND flash and
> SD card support. As far as we can tell the restrictions due to SoC
> pin-mux are between SD0 and NOR but not NAND. We had a look through
> the EVM schematics and can't readily see any NAND vs SD0 conflicts
> there either.
> 
> We would greatly appreciate any insight this list has into why the
> da850 board setup routine makes NAND and MMC support mutually
> exclusive.
> 

The MMC/SD card insert and write protect feature will not work properly
if NAND is enabled. So we decided to make them exclusive.

Regards,
Sudhakar



From liuyue18301 at 163.com  Thu May 13 02:44:23 2010
From: liuyue18301 at 163.com (liuyue18301)
Date: Thu, 13 May 2010 15:44:23 +0800 (CST)
Subject: davinci gpio driver
Message-ID: <586bbe1a.92e2.128909f1361.Coremail.liuyue18301@163.com>

hello everybody:
      recently i want to take  GPIO1  as interrupt source in my driver,the work flow as follow:
     1 set GPIO1 as input mode
     2 set the trigger mode 
     3 request_irq(gpio_to_irq(GPIO1),void *)hander,SA_INTERRUPT,xx,xx);
     4 do the work in the interrupt process.
     i do not know whether it is validate?
     
     
 
 

 
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From windlazio at gmail.com  Thu May 13 02:46:06 2010
From: windlazio at gmail.com (Han Jun-peng)
Date: Thu, 13 May 2010 15:46:06 +0800
Subject: The DM355 AEW is very sensitive to YELLOW color?
Message-ID: <AANLkTilH7h0epxJgqIQma38xSn85d-AOFJkMHk9Eo8KX@mail.gmail.com>

Hi,all
I use the APPRO IPNC as my development platform.
The IPNC provides two 2A function:the appro 2A and the TI 2A.
I find if I use the TI 2A, the video is very sensitive to YELLOW color,that
means if I place a piece of yellow paper before the sensor,
the whole video view will become very blue, and if I remove it, the view
will recover to be normal.
How can I solve this problem? Is there any other guys meet this problem?
Thank you very much! Any help or tips will be appreciated!
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From anshuman at ti.com  Thu May 13 03:13:45 2010
From: anshuman at ti.com (Saxena, Anshuman)
Date: Thu, 13 May 2010 13:43:45 +0530
Subject: The DM355 AEW is very sensitive to YELLOW color?
In-Reply-To: <AANLkTilH7h0epxJgqIQma38xSn85d-AOFJkMHk9Eo8KX@mail.gmail.com>
References: <AANLkTilH7h0epxJgqIQma38xSn85d-AOFJkMHk9Eo8KX@mail.gmail.com>
Message-ID: <2A3DCF3DA181AD40BDE86A3150B27B6B030D8FADEB@dbde02.ent.ti.com>

Hi,
Can you please post this query on TI E2E forum (http://e2e.ti.com<http://e2e.ti.com/>) in Davinci Video Processors section? I have anyways forwarded your question to our team and we will reply on the forum itself, so that other users can also benefit from this reply at a later point of time.

Regards,
Anshuman

________________________________
From: davinci-linux-open-source-bounces+anshuman=ti.com at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces+anshuman=ti.com at linux.davincidsp.com] On Behalf Of Han Jun-peng
Sent: Thursday, May 13, 2010 1:16 PM
To: Davinci-linux-open-source at linux.davincidsp.com
Subject: The DM355 AEW is very sensitive to YELLOW color?

Hi,all
I use the APPRO IPNC as my development platform.
The IPNC provides two 2A function:the appro 2A and the TI 2A.
I find if I use the TI 2A, the video is very sensitive to YELLOW color,that means if I place a piece of yellow paper before the sensor,
the whole video view will become very blue, and if I remove it, the view will recover to be normal.
How can I solve this problem? Is there any other guys meet this problem?
Thank you very much! Any help or tips will be appreciated!
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From anshuman at ti.com  Thu May 13 03:15:01 2010
From: anshuman at ti.com (Saxena, Anshuman)
Date: Thu, 13 May 2010 13:45:01 +0530
Subject: The DM355 AEW is very sensitive to YELLOW color?
References: <AANLkTilH7h0epxJgqIQma38xSn85d-AOFJkMHk9Eo8KX@mail.gmail.com> 
Message-ID: <2A3DCF3DA181AD40BDE86A3150B27B6B030D8FADEF@dbde02.ent.ti.com>

Please ignore my last email... Just realized that you have already posted it on E2E forum :( Sorry for unnecessary emails.

Regards,
Anshuman

________________________________
From: Saxena, Anshuman
Sent: Thursday, May 13, 2010 1:44 PM
To: 'Han Jun-peng'; Davinci-linux-open-source at linux.davincidsp.com
Subject: RE: The DM355 AEW is very sensitive to YELLOW color?

Hi,
Can you please post this query on TI E2E forum (http://e2e.ti.com<http://e2e.ti.com/>) in Davinci Video Processors section? I have anyways forwarded your question to our team and we will reply on the forum itself, so that other users can also benefit from this reply at a later point of time.

Regards,
Anshuman

________________________________
From: davinci-linux-open-source-bounces+anshuman=ti.com at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces+anshuman=ti.com at linux.davincidsp.com] On Behalf Of Han Jun-peng
Sent: Thursday, May 13, 2010 1:16 PM
To: Davinci-linux-open-source at linux.davincidsp.com
Subject: The DM355 AEW is very sensitive to YELLOW color?

Hi,all
I use the APPRO IPNC as my development platform.
The IPNC provides two 2A function:the appro 2A and the TI 2A.
I find if I use the TI 2A, the video is very sensitive to YELLOW color,that means if I place a piece of yellow paper before the sensor,
the whole video view will become very blue, and if I remove it, the view will recover to be normal.
How can I solve this problem? Is there any other guys meet this problem?
Thank you very much! Any help or tips will be appreciated!
-------------- next part --------------
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From linux at arm.linux.org.uk  Thu May 13 04:15:05 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 13 May 2010 10:15:05 +0100
Subject: [PATCH 06/34] RTC: DaVinci RTC driver
In-Reply-To: <1273188265-12782-7-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
	<1273188265-12782-7-git-send-email-khilman@deeprootsystems.com>
Message-ID: <20100513091504.GB5382@n2100.arm.linux.org.uk>

This should also go to the RTC people.

On Thu, May 06, 2010 at 04:23:57PM -0700, Kevin Hilman wrote:
> From: Miguel Aguilar <miguel.aguilar at ridgerun.com>
> 
> This driver features:
> 
> * Alarm support.
> * Periodic interrupt by using a timer include into the RTC module.
> * The update interrupt is not supported by this RTC module.
> 
> This driver was tested on a DM365 EVM by using the rtc-test application
> from the Documentation/rtc.txt.
> 
> Signed-off-by: Miguel Aguilar <miguel.aguilar at ridgerun.com>
> Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
> Acked-by: Alessandro Zummo <a.zummo at towertech.it>
> ---
>  drivers/rtc/Kconfig       |   10 +
>  drivers/rtc/Makefile      |    1 +
>  drivers/rtc/rtc-davinci.c |  673 +++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 684 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/rtc/rtc-davinci.c
> 
> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
> index 6a13037..50ac047 100644
> --- a/drivers/rtc/Kconfig
> +++ b/drivers/rtc/Kconfig
> @@ -620,6 +620,16 @@ config RTC_DRV_NUC900
>  
>  comment "on-CPU RTC drivers"
>  
> +config RTC_DRV_DAVINCI
> +	tristate "TI DaVinci RTC"
> +	depends on ARCH_DAVINCI_DM365
> +	help
> +	  If you say yes here you get support for the RTC on the
> +	  DaVinci platforms (DM365).
> +
> +	  This driver can also be built as a module. If so, the module
> +	  will be called rtc-davinci.
> +
>  config RTC_DRV_OMAP
>  	tristate "TI OMAP1"
>  	depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
> index 44ef194..245311a 100644
> --- a/drivers/rtc/Makefile
> +++ b/drivers/rtc/Makefile
> @@ -27,6 +27,7 @@ obj-$(CONFIG_RTC_DRV_BQ32K)	+= rtc-bq32k.o
>  obj-$(CONFIG_RTC_DRV_BQ4802)	+= rtc-bq4802.o
>  obj-$(CONFIG_RTC_DRV_CMOS)	+= rtc-cmos.o
>  obj-$(CONFIG_RTC_DRV_COH901331)	+= rtc-coh901331.o
> +obj-$(CONFIG_RTC_DRV_DAVINCI)	+= rtc-davinci.o
>  obj-$(CONFIG_RTC_DRV_DM355EVM)	+= rtc-dm355evm.o
>  obj-$(CONFIG_RTC_DRV_DS1216)	+= rtc-ds1216.o
>  obj-$(CONFIG_RTC_DRV_DS1286)	+= rtc-ds1286.o
> diff --git a/drivers/rtc/rtc-davinci.c b/drivers/rtc/rtc-davinci.c
> new file mode 100644
> index 0000000..92a8f6c
> --- /dev/null
> +++ b/drivers/rtc/rtc-davinci.c
> @@ -0,0 +1,673 @@
> +/*
> + * DaVinci Power Management and Real Time Clock Driver for TI platforms
> + *
> + * Copyright (C) 2009 Texas Instruments, Inc
> + *
> + * Author: Miguel Aguilar <miguel.aguilar at ridgerun.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + */
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/ioport.h>
> +#include <linux/delay.h>
> +#include <linux/spinlock.h>
> +#include <linux/rtc.h>
> +#include <linux/bcd.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +/*
> + * The DaVinci RTC is a simple RTC with the following
> + * Sec: 0 - 59 : BCD count
> + * Min: 0 - 59 : BCD count
> + * Hour: 0 - 23 : BCD count
> + * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
> + */
> +
> +/* PRTC interface registers */
> +#define DAVINCI_PRTCIF_PID		0x00
> +#define PRTCIF_CTLR			0x04
> +#define PRTCIF_LDATA			0x08
> +#define PRTCIF_UDATA			0x0C
> +#define PRTCIF_INTEN			0x10
> +#define PRTCIF_INTFLG			0x14
> +
> +/* PRTCIF_CTLR bit fields */
> +#define PRTCIF_CTLR_BUSY		BIT(31)
> +#define PRTCIF_CTLR_SIZE		BIT(25)
> +#define PRTCIF_CTLR_DIR			BIT(24)
> +#define PRTCIF_CTLR_BENU_MSB		BIT(23)
> +#define PRTCIF_CTLR_BENU_3RD_BYTE	BIT(22)
> +#define PRTCIF_CTLR_BENU_2ND_BYTE	BIT(21)
> +#define PRTCIF_CTLR_BENU_LSB		BIT(20)
> +#define PRTCIF_CTLR_BENU_MASK		(0x00F00000)
> +#define PRTCIF_CTLR_BENL_MSB		BIT(19)
> +#define PRTCIF_CTLR_BENL_3RD_BYTE	BIT(18)
> +#define PRTCIF_CTLR_BENL_2ND_BYTE	BIT(17)
> +#define PRTCIF_CTLR_BENL_LSB		BIT(16)
> +#define PRTCIF_CTLR_BENL_MASK		(0x000F0000)
> +
> +/* PRTCIF_INTEN bit fields */
> +#define PRTCIF_INTEN_RTCSS		BIT(1)
> +#define PRTCIF_INTEN_RTCIF		BIT(0)
> +#define PRTCIF_INTEN_MASK		(PRTCIF_INTEN_RTCSS \
> +					| PRTCIF_INTEN_RTCIF)
> +
> +/* PRTCIF_INTFLG bit fields */
> +#define PRTCIF_INTFLG_RTCSS		BIT(1)
> +#define PRTCIF_INTFLG_RTCIF		BIT(0)
> +#define PRTCIF_INTFLG_MASK		(PRTCIF_INTFLG_RTCSS \
> +					| PRTCIF_INTFLG_RTCIF)
> +
> +/* PRTC subsystem registers */
> +#define PRTCSS_RTC_INTC_EXTENA1		(0x0C)
> +#define PRTCSS_RTC_CTRL			(0x10)
> +#define PRTCSS_RTC_WDT			(0x11)
> +#define PRTCSS_RTC_TMR0			(0x12)
> +#define PRTCSS_RTC_TMR1			(0x13)
> +#define PRTCSS_RTC_CCTRL		(0x14)
> +#define PRTCSS_RTC_SEC			(0x15)
> +#define PRTCSS_RTC_MIN			(0x16)
> +#define PRTCSS_RTC_HOUR			(0x17)
> +#define PRTCSS_RTC_DAY0			(0x18)
> +#define PRTCSS_RTC_DAY1			(0x19)
> +#define PRTCSS_RTC_AMIN			(0x1A)
> +#define PRTCSS_RTC_AHOUR		(0x1B)
> +#define PRTCSS_RTC_ADAY0		(0x1C)
> +#define PRTCSS_RTC_ADAY1		(0x1D)
> +#define PRTCSS_RTC_CLKC_CNT		(0x20)
> +
> +/* PRTCSS_RTC_INTC_EXTENA1 */
> +#define PRTCSS_RTC_INTC_EXTENA1_MASK	(0x07)
> +
> +/* PRTCSS_RTC_CTRL bit fields */
> +#define PRTCSS_RTC_CTRL_WDTBUS		BIT(7)
> +#define PRTCSS_RTC_CTRL_WEN		BIT(6)
> +#define PRTCSS_RTC_CTRL_WDRT		BIT(5)
> +#define PRTCSS_RTC_CTRL_WDTFLG		BIT(4)
> +#define PRTCSS_RTC_CTRL_TE		BIT(3)
> +#define PRTCSS_RTC_CTRL_TIEN		BIT(2)
> +#define PRTCSS_RTC_CTRL_TMRFLG		BIT(1)
> +#define PRTCSS_RTC_CTRL_TMMD		BIT(0)
> +
> +/* PRTCSS_RTC_CCTRL bit fields */
> +#define PRTCSS_RTC_CCTRL_CALBUSY	BIT(7)
> +#define PRTCSS_RTC_CCTRL_DAEN		BIT(5)
> +#define PRTCSS_RTC_CCTRL_HAEN		BIT(4)
> +#define PRTCSS_RTC_CCTRL_MAEN		BIT(3)
> +#define PRTCSS_RTC_CCTRL_ALMFLG		BIT(2)
> +#define PRTCSS_RTC_CCTRL_AIEN		BIT(1)
> +#define PRTCSS_RTC_CCTRL_CAEN		BIT(0)
> +
> +static DEFINE_SPINLOCK(davinci_rtc_lock);
> +
> +struct davinci_rtc {
> +	struct rtc_device 		*rtc;
> +	void __iomem			*base;
> +	resource_size_t			pbase;
> +	size_t				base_size;
> +	int				irq;
> +};
> +
> +static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
> +			       u32 val, u32 addr)
> +{
> +	writel(val, davinci_rtc->base + addr);
> +}
> +
> +static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
> +{
> +	return readl(davinci_rtc->base + addr);
> +}
> +
> +static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
> +{
> +	while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
> +		cpu_relax();
> +}
> +
> +static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
> +			       unsigned long val, u8 addr)
> +{
> +	rtcif_wait(davinci_rtc);
> +
> +	rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
> +	rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
> +
> +	rtcif_wait(davinci_rtc);
> +}
> +
> +static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
> +{
> +	rtcif_wait(davinci_rtc);
> +
> +	rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
> +		    PRTCIF_CTLR);
> +
> +	rtcif_wait(davinci_rtc);
> +
> +	return rtcif_read(davinci_rtc, PRTCIF_LDATA);
> +}
> +
> +static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
> +{
> +	while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
> +	       PRTCSS_RTC_CCTRL_CALBUSY)
> +		cpu_relax();
> +}
> +
> +static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
> +{
> +	struct davinci_rtc *davinci_rtc = class_dev;
> +	unsigned long events = 0;
> +	u32 irq_flg;
> +	u8 alm_irq, tmr_irq;
> +	u8 rtc_ctrl, rtc_cctrl;
> +	int ret = IRQ_NONE;
> +
> +	irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
> +		  PRTCIF_INTFLG_RTCSS;
> +
> +	alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
> +		  PRTCSS_RTC_CCTRL_ALMFLG;
> +
> +	tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
> +		  PRTCSS_RTC_CTRL_TMRFLG;
> +
> +	if (irq_flg) {
> +		if (alm_irq) {
> +			events |= RTC_IRQF | RTC_AF;
> +			rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
> +			rtc_cctrl |=  PRTCSS_RTC_CCTRL_ALMFLG;
> +			rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
> +		} else if (tmr_irq) {
> +			events |= RTC_IRQF | RTC_PF;
> +			rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
> +			rtc_ctrl |=  PRTCSS_RTC_CTRL_TMRFLG;
> +			rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
> +		}
> +
> +		rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
> +				    PRTCIF_INTFLG);
> +		rtc_update_irq(davinci_rtc->rtc, 1, events);
> +
> +		ret = IRQ_HANDLED;
> +	}
> +
> +	return ret;
> +}
> +
> +static int
> +davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
> +{
> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> +	u8 rtc_ctrl;
> +	unsigned long flags;
> +	int ret = 0;
> +
> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> +	rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
> +
> +	switch (cmd) {
> +	case RTC_WIE_ON:
> +		rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
> +		break;
> +	case RTC_WIE_OFF:
> +		rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
> +		break;
> +	case RTC_UIE_OFF:
> +	case RTC_UIE_ON:
> +		ret = -ENOTTY;
> +		break;
> +	default:
> +		ret = -ENOIOCTLCMD;
> +	}
> +
> +	rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
> +
> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> +	return ret;
> +}
> +
> +static int convertfromdays(u16 days, struct rtc_time *tm)
> +{
> +	int tmp_days, year, mon;
> +
> +	for (year = 2000;; year++) {
> +		tmp_days = rtc_year_days(1, 12, year);
> +		if (days >= tmp_days)
> +			days -= tmp_days;
> +		else {
> +			for (mon = 0;; mon++) {
> +				tmp_days = rtc_month_days(mon, year);
> +				if (days >= tmp_days) {
> +					days -= tmp_days;
> +				} else {
> +					tm->tm_year = year - 1900;
> +					tm->tm_mon = mon;
> +					tm->tm_mday = days + 1;
> +					break;
> +				}
> +			}
> +			break;
> +		}
> +	}
> +	return 0;
> +}
> +
> +static int convert2days(u16 *days, struct rtc_time *tm)
> +{
> +	int i;
> +	*days = 0;
> +
> +	/* epoch == 1900 */
> +	if (tm->tm_year < 100 || tm->tm_year > 199)
> +		return -EINVAL;
> +
> +	for (i = 2000; i < 1900 + tm->tm_year; i++)
> +		*days += rtc_year_days(1, 12, i);
> +
> +	*days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
> +
> +	return 0;
> +}
> +
> +static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
> +{
> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> +	u16 days = 0;
> +	u8 day0, day1;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
> +
> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> +	days |= day1;
> +	days <<= 8;
> +	days |= day0;
> +
> +	if (convertfromdays(days, tm) < 0)
> +		return -EINVAL;
> +
> +	return 0;
> +}
> +
> +static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
> +{
> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> +	u16 days;
> +	u8 rtc_cctrl;
> +	unsigned long flags;
> +
> +	if (convert2days(&days, tm) < 0)
> +		return -EINVAL;
> +
> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
> +
> +	rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
> +	rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
> +	rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
> +
> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> +	return 0;
> +}
> +
> +static int davinci_rtc_alarm_irq_enable(struct device *dev,
> +					unsigned int enabled)
> +{
> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> +	unsigned long flags;
> +	u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
> +
> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> +	if (enabled)
> +		rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
> +			     PRTCSS_RTC_CCTRL_HAEN |
> +			     PRTCSS_RTC_CCTRL_MAEN |
> +			     PRTCSS_RTC_CCTRL_ALMFLG |
> +			     PRTCSS_RTC_CCTRL_AIEN;
> +	else
> +		rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
> +
> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> +	return 0;
> +}
> +
> +static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
> +{
> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> +	u16 days = 0;
> +	u8 day0, day1;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
> +
> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +	days |= day1;
> +	days <<= 8;
> +	days |= day0;
> +
> +	if (convertfromdays(days, &alm->time) < 0)
> +		return -EINVAL;
> +
> +	alm->pending = !!(rtcss_read(davinci_rtc,
> +			  PRTCSS_RTC_CCTRL) &
> +			PRTCSS_RTC_CCTRL_AIEN);
> +	alm->enabled = alm->pending && device_may_wakeup(dev);
> +
> +	return 0;
> +}
> +
> +static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
> +{
> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> +	unsigned long flags;
> +	u16 days;
> +
> +	if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
> +	    && alm->time.tm_year < 0) {
> +		struct rtc_time tm;
> +		unsigned long now, then;
> +
> +		davinci_rtc_read_time(dev, &tm);
> +		rtc_tm_to_time(&tm, &now);
> +
> +		alm->time.tm_mday = tm.tm_mday;
> +		alm->time.tm_mon = tm.tm_mon;
> +		alm->time.tm_year = tm.tm_year;
> +		rtc_tm_to_time(&alm->time, &then);
> +
> +		if (then < now) {
> +			rtc_time_to_tm(now + 24 * 60 * 60, &tm);
> +			alm->time.tm_mday = tm.tm_mday;
> +			alm->time.tm_mon = tm.tm_mon;
> +			alm->time.tm_year = tm.tm_year;
> +		}
> +	}
> +
> +	if (convert2days(&days, &alm->time) < 0)
> +		return -EINVAL;
> +
> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
> +
> +	davinci_rtcss_calendar_wait(davinci_rtc);
> +	rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
> +
> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> +	return 0;
> +}
> +
> +static int davinci_rtc_irq_set_state(struct device *dev, int enabled)
> +{
> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> +	unsigned long flags;
> +	u8 rtc_ctrl;
> +
> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> +	rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
> +
> +	if (enabled) {
> +		while (rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL)
> +		       & PRTCSS_RTC_CTRL_WDTBUS)
> +			cpu_relax();
> +
> +		rtc_ctrl |= PRTCSS_RTC_CTRL_TE;
> +		rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
> +
> +		rtcss_write(davinci_rtc, 0x0, PRTCSS_RTC_CLKC_CNT);
> +
> +		rtc_ctrl |= PRTCSS_RTC_CTRL_TIEN |
> +			    PRTCSS_RTC_CTRL_TMMD |
> +			    PRTCSS_RTC_CTRL_TMRFLG;
> +	} else
> +		rtc_ctrl &= ~PRTCSS_RTC_CTRL_TIEN;
> +
> +	rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
> +
> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> +	return 0;
> +}
> +
> +static int davinci_rtc_irq_set_freq(struct device *dev, int freq)
> +{
> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
> +	unsigned long flags;
> +	u16 tmr_counter = (0x8000 >> (ffs(freq) - 1));
> +
> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
> +
> +	rtcss_write(davinci_rtc, tmr_counter & 0xFF, PRTCSS_RTC_TMR0);
> +	rtcss_write(davinci_rtc, (tmr_counter & 0xFF00) >> 8, PRTCSS_RTC_TMR1);
> +
> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
> +
> +	return 0;
> +}
> +
> +static struct rtc_class_ops davinci_rtc_ops = {
> +	.ioctl			= davinci_rtc_ioctl,
> +	.read_time		= davinci_rtc_read_time,
> +	.set_time		= davinci_rtc_set_time,
> +	.alarm_irq_enable	= davinci_rtc_alarm_irq_enable,
> +	.read_alarm		= davinci_rtc_read_alarm,
> +	.set_alarm		= davinci_rtc_set_alarm,
> +	.irq_set_state		= davinci_rtc_irq_set_state,
> +	.irq_set_freq		= davinci_rtc_irq_set_freq,
> +};
> +
> +static int __init davinci_rtc_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct davinci_rtc *davinci_rtc;
> +	struct resource *res, *mem;
> +	int ret = 0;
> +
> +	davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL);
> +	if (!davinci_rtc) {
> +		dev_dbg(dev, "could not allocate memory for private data\n");
> +		return -ENOMEM;
> +	}
> +
> +	davinci_rtc->irq = platform_get_irq(pdev, 0);
> +	if (davinci_rtc->irq < 0) {
> +		dev_err(dev, "no RTC irq\n");
> +		ret = davinci_rtc->irq;
> +		goto fail1;
> +	}
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		dev_err(dev, "no mem resource\n");
> +		ret = -EINVAL;
> +		goto fail1;
> +	}
> +
> +	davinci_rtc->pbase = res->start;
> +	davinci_rtc->base_size = resource_size(res);
> +
> +	mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size,
> +				 pdev->name);
> +	if (!mem) {
> +		dev_err(dev, "RTC registers at %08x are not free\n",
> +			davinci_rtc->pbase);
> +		ret = -EBUSY;
> +		goto fail1;
> +	}
> +
> +	davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size);
> +	if (!davinci_rtc->base) {
> +		dev_err(dev, "unable to ioremap MEM resource\n");
> +		ret = -ENOMEM;
> +		goto fail2;
> +	}
> +
> +	davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
> +				    &davinci_rtc_ops, THIS_MODULE);
> +	if (IS_ERR(davinci_rtc->rtc)) {
> +		dev_err(dev, "unable to register RTC device, err %ld\n",
> +				PTR_ERR(davinci_rtc->rtc));
> +		goto fail3;
> +	}
> +
> +	rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
> +	rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
> +	rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
> +
> +	rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
> +	rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
> +
> +	ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt,
> +			  IRQF_DISABLED, "davinci_rtc", davinci_rtc);
> +	if (ret < 0) {
> +		dev_err(dev, "unable to register davinci RTC interrupt\n");
> +		goto fail4;
> +	}
> +
> +	/* Enable interrupts */
> +	rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
> +	rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
> +			    PRTCSS_RTC_INTC_EXTENA1);
> +
> +	rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
> +
> +	platform_set_drvdata(pdev, davinci_rtc);
> +
> +	device_init_wakeup(&pdev->dev, 0);
> +
> +	return 0;
> +
> +fail4:
> +	rtc_device_unregister(davinci_rtc->rtc);
> +fail3:
> +	iounmap(davinci_rtc->base);
> +fail2:
> +	release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
> +fail1:
> +	kfree(davinci_rtc);
> +
> +	return ret;
> +}
> +
> +static int __devexit davinci_rtc_remove(struct platform_device *pdev)
> +{
> +	struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
> +
> +	device_init_wakeup(&pdev->dev, 0);
> +
> +	rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
> +
> +	free_irq(davinci_rtc->irq, davinci_rtc);
> +
> +	rtc_device_unregister(davinci_rtc->rtc);
> +
> +	iounmap(davinci_rtc->base);
> +	release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
> +
> +	platform_set_drvdata(pdev, NULL);
> +
> +	kfree(davinci_rtc);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver davinci_rtc_driver = {
> +	.probe		= davinci_rtc_probe,
> +	.remove		= __devexit_p(davinci_rtc_remove),
> +	.driver		= {
> +		.name = "rtc_davinci",
> +		.owner = THIS_MODULE,
> +	},
> +};
> +
> +static int __init rtc_init(void)
> +{
> +	return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe);
> +}
> +module_init(rtc_init);
> +
> +static void __exit rtc_exit(void)
> +{
> +	platform_driver_unregister(&davinci_rtc_driver);
> +}
> +module_exit(rtc_exit);
> +
> +MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar at ridgerun.com>");
> +MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
> +MODULE_LICENSE("GPL");
> -- 
> 1.7.0.2
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

From linux at arm.linux.org.uk  Thu May 13 04:15:54 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 13 May 2010 10:15:54 +0100
Subject: [PATCH 07/34] rtc: omap: let device wakeup capability be
	configured from chip init logic
In-Reply-To: <1273188265-12782-8-git-send-email-khilman@deeprootsystems.com>
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
	<1273188265-12782-8-git-send-email-khilman@deeprootsystems.com>
Message-ID: <20100513091554.GC5382@n2100.arm.linux.org.uk>

-> rtc people

On Thu, May 06, 2010 at 04:23:58PM -0700, Kevin Hilman wrote:
> From: Sekhar Nori <nsekhar at ti.com>
> 
> The rtc-omap driver currently hardcodes the RTC wakeup capability
> to be "not capable". While this seems to be true for existing OMAP1
> boards which are not wired for this, the DA850/OMAP-L138 SoC, the
> RTC can always be wake up source from its "deep sleep" mode.
> 
> This patch lets the wakeup capability to be set from platform data and
> does not override the setting from the driver. For DA850/OMAP-L138, this
> is done from arch/arm/mach-davinci/devices-da8xx.c:da8xx_register_rtc()
> 
> Note that this patch does not change the behavior on any existing OMAP1
> board since the platform device registration sets the wakeup capability
> to 0 by default.
> 
> Signed-off-by: Sekhar Nori <nsekhar at ti.com>
> Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
> ---
>  drivers/rtc/rtc-omap.c |   12 +++++++-----
>  1 files changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
> index 64d9727..73377b0 100644
> --- a/drivers/rtc/rtc-omap.c
> +++ b/drivers/rtc/rtc-omap.c
> @@ -34,7 +34,8 @@
>   * Board-specific wiring options include using split power mode with
>   * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
>   * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
> - * low power modes).  See the BOARD-SPECIFIC CUSTOMIZATION comment.
> + * low power modes) for OMAP1 boards (OMAP-L138 has this built into
> + * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
>   */
>  
>  #define OMAP_RTC_BASE			0xfffb4800
> @@ -401,16 +402,17 @@ static int __init omap_rtc_probe(struct platform_device *pdev)
>  
>  	/* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
>  	 *
> -	 *  - Boards wired so that RTC_WAKE_INT does something, and muxed
> -	 *    right (W13_1610_RTC_WAKE_INT is the default after chip reset),
> -	 *    should initialize the device wakeup flag appropriately.
> +	 *  - Device wake-up capability setting should come through chip
> +	 *    init logic. OMAP1 boards should initialize the "wakeup capable"
> +	 *    flag in the platform device if the board is wired right for
> +	 *    being woken up by RTC alarm. For OMAP-L138, this capability
> +	 *    is built into the SoC by the "Deep Sleep" capability.
>  	 *
>  	 *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
>  	 *    rather than nPWRON_RESET, should forcibly enable split
>  	 *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
>  	 *    is write-only, and always reads as zero...)
>  	 */
> -	device_init_wakeup(&pdev->dev, 0);
>  
>  	if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT)
>  		pr_info("%s: split power mode\n", pdev->name);
> -- 
> 1.7.0.2
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

From huangsw at temobi.com  Thu May 13 07:13:51 2010
From: huangsw at temobi.com (huangsw)
Date: Thu, 13 May 2010 20:13:51 +0800
Subject: Why failed to open mp3 which stored my live555MediaServer?
Message-ID: <201005132013295462619@temobi.com>

I have succeeded to cross compile live555 (version is 2010-04-09),and i run it on my dm6446 ,and i stored a mp3 file on the same dir,

on my pc ,i filed to open the mp3 using  Realplayer and VLC p;ayer,

can you give me some advice?



2010-05-13 



huangsw 
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From khilman at deeprootsystems.com  Thu May 13 08:44:29 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 13 May 2010 06:44:29 -0700
Subject: [PATCH 06/34] RTC: DaVinci RTC driver
In-Reply-To: <20100513091504.GB5382@n2100.arm.linux.org.uk> (Russell King's
	message of "Thu\, 13 May 2010 10\:15\:05 +0100")
References: <1273188265-12782-1-git-send-email-khilman@deeprootsystems.com>
	<1273188265-12782-7-git-send-email-khilman@deeprootsystems.com>
	<20100513091504.GB5382@n2100.arm.linux.org.uk>
Message-ID: <87k4r7q5ky.fsf@deeprootsystems.com>

Russell King - ARM Linux <linux at arm.linux.org.uk> writes:

> This should also go to the RTC people.

Forgot the Cc here, but this has already been discussed ack'd by RTC folks
and agreed that it should merge via my tree.

Kevin

> On Thu, May 06, 2010 at 04:23:57PM -0700, Kevin Hilman wrote:
>> From: Miguel Aguilar <miguel.aguilar at ridgerun.com>
>> 
>> This driver features:
>> 
>> * Alarm support.
>> * Periodic interrupt by using a timer include into the RTC module.
>> * The update interrupt is not supported by this RTC module.
>> 
>> This driver was tested on a DM365 EVM by using the rtc-test application
>> from the Documentation/rtc.txt.
>> 
>> Signed-off-by: Miguel Aguilar <miguel.aguilar at ridgerun.com>
>> Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
>> Acked-by: Alessandro Zummo <a.zummo at towertech.it>
>> ---
>>  drivers/rtc/Kconfig       |   10 +
>>  drivers/rtc/Makefile      |    1 +
>>  drivers/rtc/rtc-davinci.c |  673 +++++++++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 684 insertions(+), 0 deletions(-)
>>  create mode 100644 drivers/rtc/rtc-davinci.c
>> 
>> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
>> index 6a13037..50ac047 100644
>> --- a/drivers/rtc/Kconfig
>> +++ b/drivers/rtc/Kconfig
>> @@ -620,6 +620,16 @@ config RTC_DRV_NUC900
>>  
>>  comment "on-CPU RTC drivers"
>>  
>> +config RTC_DRV_DAVINCI
>> +	tristate "TI DaVinci RTC"
>> +	depends on ARCH_DAVINCI_DM365
>> +	help
>> +	  If you say yes here you get support for the RTC on the
>> +	  DaVinci platforms (DM365).
>> +
>> +	  This driver can also be built as a module. If so, the module
>> +	  will be called rtc-davinci.
>> +
>>  config RTC_DRV_OMAP
>>  	tristate "TI OMAP1"
>>  	depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
>> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
>> index 44ef194..245311a 100644
>> --- a/drivers/rtc/Makefile
>> +++ b/drivers/rtc/Makefile
>> @@ -27,6 +27,7 @@ obj-$(CONFIG_RTC_DRV_BQ32K)	+= rtc-bq32k.o
>>  obj-$(CONFIG_RTC_DRV_BQ4802)	+= rtc-bq4802.o
>>  obj-$(CONFIG_RTC_DRV_CMOS)	+= rtc-cmos.o
>>  obj-$(CONFIG_RTC_DRV_COH901331)	+= rtc-coh901331.o
>> +obj-$(CONFIG_RTC_DRV_DAVINCI)	+= rtc-davinci.o
>>  obj-$(CONFIG_RTC_DRV_DM355EVM)	+= rtc-dm355evm.o
>>  obj-$(CONFIG_RTC_DRV_DS1216)	+= rtc-ds1216.o
>>  obj-$(CONFIG_RTC_DRV_DS1286)	+= rtc-ds1286.o
>> diff --git a/drivers/rtc/rtc-davinci.c b/drivers/rtc/rtc-davinci.c
>> new file mode 100644
>> index 0000000..92a8f6c
>> --- /dev/null
>> +++ b/drivers/rtc/rtc-davinci.c
>> @@ -0,0 +1,673 @@
>> +/*
>> + * DaVinci Power Management and Real Time Clock Driver for TI platforms
>> + *
>> + * Copyright (C) 2009 Texas Instruments, Inc
>> + *
>> + * Author: Miguel Aguilar <miguel.aguilar at ridgerun.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
>> + */
>> +#include <linux/kernel.h>
>> +#include <linux/init.h>
>> +#include <linux/module.h>
>> +#include <linux/ioport.h>
>> +#include <linux/delay.h>
>> +#include <linux/spinlock.h>
>> +#include <linux/rtc.h>
>> +#include <linux/bcd.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/io.h>
>> +
>> +/*
>> + * The DaVinci RTC is a simple RTC with the following
>> + * Sec: 0 - 59 : BCD count
>> + * Min: 0 - 59 : BCD count
>> + * Hour: 0 - 23 : BCD count
>> + * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
>> + */
>> +
>> +/* PRTC interface registers */
>> +#define DAVINCI_PRTCIF_PID		0x00
>> +#define PRTCIF_CTLR			0x04
>> +#define PRTCIF_LDATA			0x08
>> +#define PRTCIF_UDATA			0x0C
>> +#define PRTCIF_INTEN			0x10
>> +#define PRTCIF_INTFLG			0x14
>> +
>> +/* PRTCIF_CTLR bit fields */
>> +#define PRTCIF_CTLR_BUSY		BIT(31)
>> +#define PRTCIF_CTLR_SIZE		BIT(25)
>> +#define PRTCIF_CTLR_DIR			BIT(24)
>> +#define PRTCIF_CTLR_BENU_MSB		BIT(23)
>> +#define PRTCIF_CTLR_BENU_3RD_BYTE	BIT(22)
>> +#define PRTCIF_CTLR_BENU_2ND_BYTE	BIT(21)
>> +#define PRTCIF_CTLR_BENU_LSB		BIT(20)
>> +#define PRTCIF_CTLR_BENU_MASK		(0x00F00000)
>> +#define PRTCIF_CTLR_BENL_MSB		BIT(19)
>> +#define PRTCIF_CTLR_BENL_3RD_BYTE	BIT(18)
>> +#define PRTCIF_CTLR_BENL_2ND_BYTE	BIT(17)
>> +#define PRTCIF_CTLR_BENL_LSB		BIT(16)
>> +#define PRTCIF_CTLR_BENL_MASK		(0x000F0000)
>> +
>> +/* PRTCIF_INTEN bit fields */
>> +#define PRTCIF_INTEN_RTCSS		BIT(1)
>> +#define PRTCIF_INTEN_RTCIF		BIT(0)
>> +#define PRTCIF_INTEN_MASK		(PRTCIF_INTEN_RTCSS \
>> +					| PRTCIF_INTEN_RTCIF)
>> +
>> +/* PRTCIF_INTFLG bit fields */
>> +#define PRTCIF_INTFLG_RTCSS		BIT(1)
>> +#define PRTCIF_INTFLG_RTCIF		BIT(0)
>> +#define PRTCIF_INTFLG_MASK		(PRTCIF_INTFLG_RTCSS \
>> +					| PRTCIF_INTFLG_RTCIF)
>> +
>> +/* PRTC subsystem registers */
>> +#define PRTCSS_RTC_INTC_EXTENA1		(0x0C)
>> +#define PRTCSS_RTC_CTRL			(0x10)
>> +#define PRTCSS_RTC_WDT			(0x11)
>> +#define PRTCSS_RTC_TMR0			(0x12)
>> +#define PRTCSS_RTC_TMR1			(0x13)
>> +#define PRTCSS_RTC_CCTRL		(0x14)
>> +#define PRTCSS_RTC_SEC			(0x15)
>> +#define PRTCSS_RTC_MIN			(0x16)
>> +#define PRTCSS_RTC_HOUR			(0x17)
>> +#define PRTCSS_RTC_DAY0			(0x18)
>> +#define PRTCSS_RTC_DAY1			(0x19)
>> +#define PRTCSS_RTC_AMIN			(0x1A)
>> +#define PRTCSS_RTC_AHOUR		(0x1B)
>> +#define PRTCSS_RTC_ADAY0		(0x1C)
>> +#define PRTCSS_RTC_ADAY1		(0x1D)
>> +#define PRTCSS_RTC_CLKC_CNT		(0x20)
>> +
>> +/* PRTCSS_RTC_INTC_EXTENA1 */
>> +#define PRTCSS_RTC_INTC_EXTENA1_MASK	(0x07)
>> +
>> +/* PRTCSS_RTC_CTRL bit fields */
>> +#define PRTCSS_RTC_CTRL_WDTBUS		BIT(7)
>> +#define PRTCSS_RTC_CTRL_WEN		BIT(6)
>> +#define PRTCSS_RTC_CTRL_WDRT		BIT(5)
>> +#define PRTCSS_RTC_CTRL_WDTFLG		BIT(4)
>> +#define PRTCSS_RTC_CTRL_TE		BIT(3)
>> +#define PRTCSS_RTC_CTRL_TIEN		BIT(2)
>> +#define PRTCSS_RTC_CTRL_TMRFLG		BIT(1)
>> +#define PRTCSS_RTC_CTRL_TMMD		BIT(0)
>> +
>> +/* PRTCSS_RTC_CCTRL bit fields */
>> +#define PRTCSS_RTC_CCTRL_CALBUSY	BIT(7)
>> +#define PRTCSS_RTC_CCTRL_DAEN		BIT(5)
>> +#define PRTCSS_RTC_CCTRL_HAEN		BIT(4)
>> +#define PRTCSS_RTC_CCTRL_MAEN		BIT(3)
>> +#define PRTCSS_RTC_CCTRL_ALMFLG		BIT(2)
>> +#define PRTCSS_RTC_CCTRL_AIEN		BIT(1)
>> +#define PRTCSS_RTC_CCTRL_CAEN		BIT(0)
>> +
>> +static DEFINE_SPINLOCK(davinci_rtc_lock);
>> +
>> +struct davinci_rtc {
>> +	struct rtc_device 		*rtc;
>> +	void __iomem			*base;
>> +	resource_size_t			pbase;
>> +	size_t				base_size;
>> +	int				irq;
>> +};
>> +
>> +static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
>> +			       u32 val, u32 addr)
>> +{
>> +	writel(val, davinci_rtc->base + addr);
>> +}
>> +
>> +static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
>> +{
>> +	return readl(davinci_rtc->base + addr);
>> +}
>> +
>> +static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
>> +{
>> +	while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
>> +		cpu_relax();
>> +}
>> +
>> +static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
>> +			       unsigned long val, u8 addr)
>> +{
>> +	rtcif_wait(davinci_rtc);
>> +
>> +	rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
>> +	rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
>> +
>> +	rtcif_wait(davinci_rtc);
>> +}
>> +
>> +static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
>> +{
>> +	rtcif_wait(davinci_rtc);
>> +
>> +	rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
>> +		    PRTCIF_CTLR);
>> +
>> +	rtcif_wait(davinci_rtc);
>> +
>> +	return rtcif_read(davinci_rtc, PRTCIF_LDATA);
>> +}
>> +
>> +static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
>> +{
>> +	while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
>> +	       PRTCSS_RTC_CCTRL_CALBUSY)
>> +		cpu_relax();
>> +}
>> +
>> +static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
>> +{
>> +	struct davinci_rtc *davinci_rtc = class_dev;
>> +	unsigned long events = 0;
>> +	u32 irq_flg;
>> +	u8 alm_irq, tmr_irq;
>> +	u8 rtc_ctrl, rtc_cctrl;
>> +	int ret = IRQ_NONE;
>> +
>> +	irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
>> +		  PRTCIF_INTFLG_RTCSS;
>> +
>> +	alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
>> +		  PRTCSS_RTC_CCTRL_ALMFLG;
>> +
>> +	tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
>> +		  PRTCSS_RTC_CTRL_TMRFLG;
>> +
>> +	if (irq_flg) {
>> +		if (alm_irq) {
>> +			events |= RTC_IRQF | RTC_AF;
>> +			rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
>> +			rtc_cctrl |=  PRTCSS_RTC_CCTRL_ALMFLG;
>> +			rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
>> +		} else if (tmr_irq) {
>> +			events |= RTC_IRQF | RTC_PF;
>> +			rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
>> +			rtc_ctrl |=  PRTCSS_RTC_CTRL_TMRFLG;
>> +			rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
>> +		}
>> +
>> +		rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
>> +				    PRTCIF_INTFLG);
>> +		rtc_update_irq(davinci_rtc->rtc, 1, events);
>> +
>> +		ret = IRQ_HANDLED;
>> +	}
>> +
>> +	return ret;
>> +}
>> +
>> +static int
>> +davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
>> +{
>> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> +	u8 rtc_ctrl;
>> +	unsigned long flags;
>> +	int ret = 0;
>> +
>> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> +	rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
>> +
>> +	switch (cmd) {
>> +	case RTC_WIE_ON:
>> +		rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
>> +		break;
>> +	case RTC_WIE_OFF:
>> +		rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
>> +		break;
>> +	case RTC_UIE_OFF:
>> +	case RTC_UIE_ON:
>> +		ret = -ENOTTY;
>> +		break;
>> +	default:
>> +		ret = -ENOIOCTLCMD;
>> +	}
>> +
>> +	rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
>> +
>> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> +	return ret;
>> +}
>> +
>> +static int convertfromdays(u16 days, struct rtc_time *tm)
>> +{
>> +	int tmp_days, year, mon;
>> +
>> +	for (year = 2000;; year++) {
>> +		tmp_days = rtc_year_days(1, 12, year);
>> +		if (days >= tmp_days)
>> +			days -= tmp_days;
>> +		else {
>> +			for (mon = 0;; mon++) {
>> +				tmp_days = rtc_month_days(mon, year);
>> +				if (days >= tmp_days) {
>> +					days -= tmp_days;
>> +				} else {
>> +					tm->tm_year = year - 1900;
>> +					tm->tm_mon = mon;
>> +					tm->tm_mday = days + 1;
>> +					break;
>> +				}
>> +			}
>> +			break;
>> +		}
>> +	}
>> +	return 0;
>> +}
>> +
>> +static int convert2days(u16 *days, struct rtc_time *tm)
>> +{
>> +	int i;
>> +	*days = 0;
>> +
>> +	/* epoch == 1900 */
>> +	if (tm->tm_year < 100 || tm->tm_year > 199)
>> +		return -EINVAL;
>> +
>> +	for (i = 2000; i < 1900 + tm->tm_year; i++)
>> +		*days += rtc_year_days(1, 12, i);
>> +
>> +	*days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
>> +
>> +	return 0;
>> +}
>> +
>> +static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
>> +{
>> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> +	u16 days = 0;
>> +	u8 day0, day1;
>> +	unsigned long flags;
>> +
>> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
>> +
>> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> +	days |= day1;
>> +	days <<= 8;
>> +	days |= day0;
>> +
>> +	if (convertfromdays(days, tm) < 0)
>> +		return -EINVAL;
>> +
>> +	return 0;
>> +}
>> +
>> +static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
>> +{
>> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> +	u16 days;
>> +	u8 rtc_cctrl;
>> +	unsigned long flags;
>> +
>> +	if (convert2days(&days, tm) < 0)
>> +		return -EINVAL;
>> +
>> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
>> +
>> +	rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
>> +	rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
>> +	rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
>> +
>> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> +	return 0;
>> +}
>> +
>> +static int davinci_rtc_alarm_irq_enable(struct device *dev,
>> +					unsigned int enabled)
>> +{
>> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> +	unsigned long flags;
>> +	u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
>> +
>> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> +	if (enabled)
>> +		rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
>> +			     PRTCSS_RTC_CCTRL_HAEN |
>> +			     PRTCSS_RTC_CCTRL_MAEN |
>> +			     PRTCSS_RTC_CCTRL_ALMFLG |
>> +			     PRTCSS_RTC_CCTRL_AIEN;
>> +	else
>> +		rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
>> +
>> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> +	return 0;
>> +}
>> +
>> +static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
>> +{
>> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> +	u16 days = 0;
>> +	u8 day0, day1;
>> +	unsigned long flags;
>> +
>> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
>> +
>> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +	days |= day1;
>> +	days <<= 8;
>> +	days |= day0;
>> +
>> +	if (convertfromdays(days, &alm->time) < 0)
>> +		return -EINVAL;
>> +
>> +	alm->pending = !!(rtcss_read(davinci_rtc,
>> +			  PRTCSS_RTC_CCTRL) &
>> +			PRTCSS_RTC_CCTRL_AIEN);
>> +	alm->enabled = alm->pending && device_may_wakeup(dev);
>> +
>> +	return 0;
>> +}
>> +
>> +static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
>> +{
>> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> +	unsigned long flags;
>> +	u16 days;
>> +
>> +	if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
>> +	    && alm->time.tm_year < 0) {
>> +		struct rtc_time tm;
>> +		unsigned long now, then;
>> +
>> +		davinci_rtc_read_time(dev, &tm);
>> +		rtc_tm_to_time(&tm, &now);
>> +
>> +		alm->time.tm_mday = tm.tm_mday;
>> +		alm->time.tm_mon = tm.tm_mon;
>> +		alm->time.tm_year = tm.tm_year;
>> +		rtc_tm_to_time(&alm->time, &then);
>> +
>> +		if (then < now) {
>> +			rtc_time_to_tm(now + 24 * 60 * 60, &tm);
>> +			alm->time.tm_mday = tm.tm_mday;
>> +			alm->time.tm_mon = tm.tm_mon;
>> +			alm->time.tm_year = tm.tm_year;
>> +		}
>> +	}
>> +
>> +	if (convert2days(&days, &alm->time) < 0)
>> +		return -EINVAL;
>> +
>> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
>> +
>> +	davinci_rtcss_calendar_wait(davinci_rtc);
>> +	rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
>> +
>> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> +	return 0;
>> +}
>> +
>> +static int davinci_rtc_irq_set_state(struct device *dev, int enabled)
>> +{
>> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> +	unsigned long flags;
>> +	u8 rtc_ctrl;
>> +
>> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> +	rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
>> +
>> +	if (enabled) {
>> +		while (rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL)
>> +		       & PRTCSS_RTC_CTRL_WDTBUS)
>> +			cpu_relax();
>> +
>> +		rtc_ctrl |= PRTCSS_RTC_CTRL_TE;
>> +		rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
>> +
>> +		rtcss_write(davinci_rtc, 0x0, PRTCSS_RTC_CLKC_CNT);
>> +
>> +		rtc_ctrl |= PRTCSS_RTC_CTRL_TIEN |
>> +			    PRTCSS_RTC_CTRL_TMMD |
>> +			    PRTCSS_RTC_CTRL_TMRFLG;
>> +	} else
>> +		rtc_ctrl &= ~PRTCSS_RTC_CTRL_TIEN;
>> +
>> +	rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
>> +
>> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> +	return 0;
>> +}
>> +
>> +static int davinci_rtc_irq_set_freq(struct device *dev, int freq)
>> +{
>> +	struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
>> +	unsigned long flags;
>> +	u16 tmr_counter = (0x8000 >> (ffs(freq) - 1));
>> +
>> +	spin_lock_irqsave(&davinci_rtc_lock, flags);
>> +
>> +	rtcss_write(davinci_rtc, tmr_counter & 0xFF, PRTCSS_RTC_TMR0);
>> +	rtcss_write(davinci_rtc, (tmr_counter & 0xFF00) >> 8, PRTCSS_RTC_TMR1);
>> +
>> +	spin_unlock_irqrestore(&davinci_rtc_lock, flags);
>> +
>> +	return 0;
>> +}
>> +
>> +static struct rtc_class_ops davinci_rtc_ops = {
>> +	.ioctl			= davinci_rtc_ioctl,
>> +	.read_time		= davinci_rtc_read_time,
>> +	.set_time		= davinci_rtc_set_time,
>> +	.alarm_irq_enable	= davinci_rtc_alarm_irq_enable,
>> +	.read_alarm		= davinci_rtc_read_alarm,
>> +	.set_alarm		= davinci_rtc_set_alarm,
>> +	.irq_set_state		= davinci_rtc_irq_set_state,
>> +	.irq_set_freq		= davinci_rtc_irq_set_freq,
>> +};
>> +
>> +static int __init davinci_rtc_probe(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	struct davinci_rtc *davinci_rtc;
>> +	struct resource *res, *mem;
>> +	int ret = 0;
>> +
>> +	davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL);
>> +	if (!davinci_rtc) {
>> +		dev_dbg(dev, "could not allocate memory for private data\n");
>> +		return -ENOMEM;
>> +	}
>> +
>> +	davinci_rtc->irq = platform_get_irq(pdev, 0);
>> +	if (davinci_rtc->irq < 0) {
>> +		dev_err(dev, "no RTC irq\n");
>> +		ret = davinci_rtc->irq;
>> +		goto fail1;
>> +	}
>> +
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	if (!res) {
>> +		dev_err(dev, "no mem resource\n");
>> +		ret = -EINVAL;
>> +		goto fail1;
>> +	}
>> +
>> +	davinci_rtc->pbase = res->start;
>> +	davinci_rtc->base_size = resource_size(res);
>> +
>> +	mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size,
>> +				 pdev->name);
>> +	if (!mem) {
>> +		dev_err(dev, "RTC registers at %08x are not free\n",
>> +			davinci_rtc->pbase);
>> +		ret = -EBUSY;
>> +		goto fail1;
>> +	}
>> +
>> +	davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size);
>> +	if (!davinci_rtc->base) {
>> +		dev_err(dev, "unable to ioremap MEM resource\n");
>> +		ret = -ENOMEM;
>> +		goto fail2;
>> +	}
>> +
>> +	davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
>> +				    &davinci_rtc_ops, THIS_MODULE);
>> +	if (IS_ERR(davinci_rtc->rtc)) {
>> +		dev_err(dev, "unable to register RTC device, err %ld\n",
>> +				PTR_ERR(davinci_rtc->rtc));
>> +		goto fail3;
>> +	}
>> +
>> +	rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
>> +	rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
>> +	rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
>> +
>> +	rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
>> +	rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
>> +
>> +	ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt,
>> +			  IRQF_DISABLED, "davinci_rtc", davinci_rtc);
>> +	if (ret < 0) {
>> +		dev_err(dev, "unable to register davinci RTC interrupt\n");
>> +		goto fail4;
>> +	}
>> +
>> +	/* Enable interrupts */
>> +	rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
>> +	rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
>> +			    PRTCSS_RTC_INTC_EXTENA1);
>> +
>> +	rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
>> +
>> +	platform_set_drvdata(pdev, davinci_rtc);
>> +
>> +	device_init_wakeup(&pdev->dev, 0);
>> +
>> +	return 0;
>> +
>> +fail4:
>> +	rtc_device_unregister(davinci_rtc->rtc);
>> +fail3:
>> +	iounmap(davinci_rtc->base);
>> +fail2:
>> +	release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
>> +fail1:
>> +	kfree(davinci_rtc);
>> +
>> +	return ret;
>> +}
>> +
>> +static int __devexit davinci_rtc_remove(struct platform_device *pdev)
>> +{
>> +	struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
>> +
>> +	device_init_wakeup(&pdev->dev, 0);
>> +
>> +	rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
>> +
>> +	free_irq(davinci_rtc->irq, davinci_rtc);
>> +
>> +	rtc_device_unregister(davinci_rtc->rtc);
>> +
>> +	iounmap(davinci_rtc->base);
>> +	release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
>> +
>> +	platform_set_drvdata(pdev, NULL);
>> +
>> +	kfree(davinci_rtc);
>> +
>> +	return 0;
>> +}
>> +
>> +static struct platform_driver davinci_rtc_driver = {
>> +	.probe		= davinci_rtc_probe,
>> +	.remove		= __devexit_p(davinci_rtc_remove),
>> +	.driver		= {
>> +		.name = "rtc_davinci",
>> +		.owner = THIS_MODULE,
>> +	},
>> +};
>> +
>> +static int __init rtc_init(void)
>> +{
>> +	return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe);
>> +}
>> +module_init(rtc_init);
>> +
>> +static void __exit rtc_exit(void)
>> +{
>> +	platform_driver_unregister(&davinci_rtc_driver);
>> +}
>> +module_exit(rtc_exit);
>> +
>> +MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar at ridgerun.com>");
>> +MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
>> +MODULE_LICENSE("GPL");
>> -- 
>> 1.7.0.2
>> 
>> 
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

From khilman at deeprootsystems.com  Thu May 13 09:50:50 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 13 May 2010 07:50:50 -0700
Subject: [PATCH v3 0/8] pre-tnetv107x ioremap series
In-Reply-To: <1273266399-17164-1-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Fri\, 7 May 2010 17\:06\:31 -0400")
References: <1273266399-17164-1-git-send-email-cyril@ti.com>
Message-ID: <87bpcjq2id.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> With this patch, various davinci modules (gpio, timer, psc, etc.) now use
> ioremap() instead of having virtual addresses passed in via davinci_soc_info.
> Based on this cleanup, davinci_ioremap() has been modified to search through
> the iotable instead of mapping based on IO_PHYS and IO_VIRT.

Looks good.  Applying.  Adding to davinci-next for 2.6.35.

Thanks again for this major cleanup and improvement!

Kevin


> Cyril Chemparathy (8):
>   Davinci: gpio - use ioremap()
>   Davinci: da8xx: rtc - use ioremap
>   Davinci: jtag_id - use ioremap()
>   Davinci: timer - use ioremap()
>   Davinci: psc - use ioremap()
>   Davinci: aintc/cpintc - use ioremap()
>   Davinci: pinmux - use ioremap()
>   Davinci: iotable based ioremap() interception
>
>  arch/arm/mach-davinci/board-da830-evm.c      |   10 +----
>  arch/arm/mach-davinci/board-da850-evm.c      |   10 +----
>  arch/arm/mach-davinci/board-dm355-evm.c      |    7 +---
>  arch/arm/mach-davinci/board-dm355-leopard.c  |    7 +---
>  arch/arm/mach-davinci/board-dm365-evm.c      |    7 +---
>  arch/arm/mach-davinci/board-dm644x-evm.c     |    7 +---
>  arch/arm/mach-davinci/board-dm646x-evm.c     |    9 +---
>  arch/arm/mach-davinci/board-neuros-osd2.c    |    7 +---
>  arch/arm/mach-davinci/board-sffsdr.c         |    7 +---
>  arch/arm/mach-davinci/clock.c                |   14 +++++-
>  arch/arm/mach-davinci/common.c               |   54 ++++++++++++++-----------
>  arch/arm/mach-davinci/cp_intc.c              |   18 +++++---
>  arch/arm/mach-davinci/da830.c                |   26 +++++--------
>  arch/arm/mach-davinci/da850.c                |   27 +++++--------
>  arch/arm/mach-davinci/devices-da8xx.c        |   11 ++++-
>  arch/arm/mach-davinci/devices.c              |    4 +-
>  arch/arm/mach-davinci/dm355.c                |   12 ++---
>  arch/arm/mach-davinci/dm365.c                |   12 ++---
>  arch/arm/mach-davinci/dm644x.c               |   12 ++---
>  arch/arm/mach-davinci/dm646x.c               |   12 ++---
>  arch/arm/mach-davinci/gpio.c                 |   18 +++++---
>  arch/arm/mach-davinci/include/mach/common.h  |   21 +++++++---
>  arch/arm/mach-davinci/include/mach/cp_intc.h |    3 +-
>  arch/arm/mach-davinci/io.c                   |   20 +++++++--
>  arch/arm/mach-davinci/irq.c                  |    7 +++-
>  arch/arm/mach-davinci/mux.c                  |   17 ++++++--
>  arch/arm/mach-davinci/psc.c                  |    7 ++-
>  arch/arm/mach-davinci/time.c                 |   22 +++++++----
>  28 files changed, 192 insertions(+), 196 deletions(-)

From khilman at deeprootsystems.com  Thu May 13 10:34:48 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 13 May 2010 08:34:48 -0700
Subject: [PATCH v6 1/6] Davinci: generalized debug macros
In-Reply-To: <1273271886-15190-2-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Fri\, 7 May 2010 18\:38\:01 -0400")
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
	<1273271886-15190-2-git-send-email-cyril@ti.com>
Message-ID: <87y6fnolwn.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This patch adopts a debug uart selection similar to the OMAP model.  During
> the boot process, the uncompress code determines the physical and virtual base
> addresses of the board-specific debug uart.  These addresses are then passed
> on to the in-kernel debug macros through a small chunk of memory placed just
> below the page tables (@0x80003ff8).
>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

Tony's updated version[1] for OMAP is not using 0x3ffc offset since only
4 bytes are used.

Any objection to making and testing that change?

Kevin

[1] http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap-2.6.git;a=commit;h=96554d70775e936e870f61d9523c9bab3fd54ad6


From blueskyjb at roadrunner.com  Thu May 13 11:21:22 2010
From: blueskyjb at roadrunner.com (Jimmy Blair)
Date: Thu, 13 May 2010 09:21:22 -0700
Subject: live555
In-Reply-To: <mailman.2135.1273758279.11996.davinci-linux-open-source@linux.davincidsp.com>
References: <mailman.2135.1273758279.11996.davinci-linux-open-source@linux.davincidsp.com>
Message-ID: <4BEC2702.7010108@roadrunner.com>


> Date: Thu, 13 May 2010 20:13:51 +0800
> From: "huangsw" <huangsw at temobi.com>
> 
> I have succeeded to cross compile live555 (version is 2010-04-09),and i run it on my dm6446 ,and i stored a mp3 file on the same dir,
> 
> on my pc ,i filed to open the mp3 using  Realplayer and VLC p;ayer,
> 
> can you give me some advice?
> 
> 

I couldn't get Live555 to stream, either.  Try
an RTSP server called 'feng'.  Just google "libnemesi" and you'll
get to the Lscube website.  There are a few libraries to download
and build.  I use feng to stream from a Linux PC.  Try it that
way first before you cross compile for Davinci.

From khilman at deeprootsystems.com  Thu May 13 12:02:33 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 13 May 2010 10:02:33 -0700
Subject: [PATCH v2 1/2] davinci: edma: use BIT() wherever possible
In-Reply-To: <1273475479-15573-1-git-send-email-nsekhar@ti.com> (Sekhar Nori's
	message of "Mon\, 10 May 2010 12\:41\:18 +0530")
References: <1273475479-15573-1-git-send-email-nsekhar@ti.com>
Message-ID: <87r5lfohue.fsf@deeprootsystems.com>

Sekhar Nori <nsekhar at ti.com> writes:

> This patch replaces occurences of (1 << x) with
> BIT(x) as it makes for much better reading.
>
> Signed-off-by: Sekhar Nori <nsekhar at ti.com>

Looks good, applying both patches and queuing for 2.6.35 in davinci-next.

Kevin

From khilman at deeprootsystems.com  Thu May 13 12:27:27 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 13 May 2010 10:27:27 -0700
Subject: [PATCH v6 1/6] Davinci: generalized debug macros
In-Reply-To: <87y6fnolwn.fsf@deeprootsystems.com> (Kevin Hilman's message of
	"Thu\, 13 May 2010 08\:34\:48 -0700")
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
	<1273271886-15190-2-git-send-email-cyril@ti.com>
	<87y6fnolwn.fsf@deeprootsystems.com>
Message-ID: <87iq6rogow.fsf@deeprootsystems.com>

Kevin Hilman <khilman at deeprootsystems.com> writes:

> Cyril Chemparathy <cyril at ti.com> writes:
>
>> This patch adopts a debug uart selection similar to the OMAP model.  During
>> the boot process, the uncompress code determines the physical and virtual base
>> addresses of the board-specific debug uart.  These addresses are then passed
>> on to the in-kernel debug macros through a small chunk of memory placed just
>> below the page tables (@0x80003ff8).
>>
>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>
> Tony's updated version[1] for OMAP is not using 0x3ffc offset since only
> 4 bytes are used.
>
> Any objection to making and testing that change?

fwiw, I boot tested using 0x3ffc on DMx (dm6446, dm355, dm6467 EVMs)
as well DA8xx (da830 and da850 EVMs) and it works fine for all.

> Kevin
>
> [1] http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap-2.6.git;a=commit;h=96554d70775e936e870f61d9523c9bab3fd54ad6

From khilman at deeprootsystems.com  Thu May 13 12:30:54 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 13 May 2010 10:30:54 -0700
Subject: [PATCH v6 3/6] Davinci: tnetv107x soc support
In-Reply-To: <1273271886-15190-4-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Fri\, 7 May 2010 18\:38\:03 -0400")
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
	<1273271886-15190-4-git-send-email-cyril@ti.com>
Message-ID: <87fx1vogj5.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> TNETV107X is a Texas Instruments SOC that shares a number of common features
> with the Davinci architecture.  Some of the key differences between
> traditional Davincis and this new SOC are as follow:
>
> 1. The SOCs clock architecture includes a new spread-spectrum PLL.  Some
> elements of the clock architecture are reused from Davinci (e.g. LPSC), but
> the PLL related code is overridden using existing interfaces in "struct clk".
>
> 2. The MMR layout on this SOC is substantially different from Davinci.
> Consequently, the fixed I/O map is a whole lot more convoluted (more so than
> DA8xx).  The net impact here is that IO_ADDRESS() will not work on this SoC,
> and therefore all mappings have to be through ioremap().
>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

[...]

> diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
> new file mode 100644
> index 0000000..cc44678
> --- /dev/null
> +++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
> @@ -0,0 +1,56 @@
> +/*
> + * Texas Instruments TNETV107X SoC Specific Defines
> + *
> + * Copyright (C) 2010 Texas Instruments
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
> +#define __ASM_ARCH_DAVINCI_TNETV107X_H
> +
> +#include <asm/sizes.h>
> +
> +#define TNETV107X_DDR_BASE	0x80000000
> +
> +/*
> + * Fixed mapping for early init starts here. If low-level debug is enabled,
> + * this area also gets mapped via io_pg_offset and io_phys by the boot code.
> + * To fit in with the io_pg_offset calculation, the io base address selected
> + * here _must_ be a multiple of 2^20.
> + */
> +#define TNETV107X_IO_BASE	0x08000000
> +#define TNETV107X_IO_VIRT	(IO_VIRT + SZ_1M)
> +
> +#define PINMUX(x)		(4 * (x))

minor nit...

Isn't this a duplicate of what is now in <mach/mux.h> ?

Kevin

From khilman at deeprootsystems.com  Thu May 13 13:05:39 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 13 May 2010 11:05:39 -0700
Subject: [PATCH v6 4/6] Davinci: tnetv107x initial gpio support
In-Reply-To: <1273271886-15190-5-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Fri\, 7 May 2010 18\:38\:04 -0400")
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
	<1273271886-15190-5-git-send-email-cyril@ti.com>
Message-ID: <87wrv7n0cs.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This patch adds support for the tnetv107x gpio controller.
>
> Key differences between davinci and tnetv107x controllers:
>  - register map - davinci's controller is organized into banks of 32 gpios,
>    tnetv107x has a single space with arrays of registers for in, out,
>    direction, etc.
>  - davinci's controller has separate set/clear registers for output, tnetv107x
>    has a single direct mapped register.
>
> This patch does not yet add gpio irq support on this controller.
>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

I know Sergei isn't used to me agreeing with him ;) but I tend to
agree with him on the increased bulk of gpio_set_value().

It's not simply the increased size that is an issue here.  The point
of these inlines (as the comment suggests) is for low-overhead
bit-banging.  With the introduction of different methods depending on
GPIO type, as well as the locking for the tnetv style, this is no
longer low-overhead in my mind.

Below is an alternate solution.

[...]

> @@ -97,14 +98,30 @@ static inline void gpio_set_value(unsigned gpio, int value)
>  {
>  	if (__builtin_constant_p(value) && gpio < davinci_soc_info.gpio_num) {

Here add '&& (ctlr->set_data != ctlr->clr_data)' to the if clause

>  		struct davinci_gpio_controller *ctlr;
> -		u32				mask;
> +		u32				mask, data;
> +		unsigned long			flags;
>  
>  		ctlr = __gpio_to_controller(gpio);
>  		mask = __gpio_mask(gpio);
> -		if (value)
> -			__raw_writel(mask, ctlr->set_data);
> -		else
> -			__raw_writel(mask, ctlr->clr_data);

and then this part can stay as is for the traditional style...

> +
> +		if (ctlr->set_data != ctlr->clr_data) {
> +			/* traditional set/clear registers */
> +			if (value)
> +				__raw_writel(mask, ctlr->set_data);
> +			else
> +				__raw_writel(mask, ctlr->clr_data);
> +		} else {
> +			/* tnetv107x style single out register */
> +			spin_lock_irqsave(&ctlr->lock, flags);
> +			data = __raw_readl(ctlr->set_data);
> +			if (value)
> +				data |= mask;
> +			else
> +				data &= ~mask;
> +			__raw_writel(data, ctlr->set_data);
> +			spin_unlock_irqrestore(&ctlr->lock, flags);
> +		}
> +
>  		return;
>  	}

Then just drop all of this part and let the tnetv-style fall through
to the __gpio_set_value() which will call the GPIO chip's ->set()
method.

Kevin

From khilman at deeprootsystems.com  Thu May 13 13:08:03 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 13 May 2010 11:08:03 -0700
Subject: [PATCH v6 0/6] Davinci: initial tnetv107x patch series
In-Reply-To: <1273271886-15190-1-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Fri\, 7 May 2010 18\:38\:00 -0400")
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
Message-ID: <87mxw3n08s.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This patch series adds support for TNETV107X - a Texas Instruments SOC that
> shares a number of common features with the Davinci architecture.
>
> This version includes minor fixes over the v5 series posted earlier

Hi Cyril,

I had some minor comments on a couple of the patches here, but have
one other question.

Is there anything in the DaVinci-specific parts now that is preventing
a single kernel shared between DMx an tnetv?

I know about the ARM-generic code that has problems when both ARMv5
and ARMv6 are enabled, but am curious about any remaining blocks in
the arch/arm/mach-davinci/* code.

Thanks,

Kevin

From khilman at deeprootsystems.com  Thu May 13 13:14:28 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 13 May 2010 11:14:28 -0700
Subject: [PATCH 0/3] More PINMUX definitions
In-Reply-To: <1273590409-10433-1-git-send-email-thomas.koeller@baslerweb.com>
	(thomas koeller's message of "Tue\, 11 May 2010 17\:06\:46 +0200")
References: <1273590409-10433-1-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <87eihfmzy3.fsf@deeprootsystems.com>

thomas.koeller at baslerweb.com writes:

> From: Thomas Koeller <thomas.koeller at baslerweb.com>
>
> Patch series is against Kevin's tree this time. They
> introduce new PINMUX settings that are required to support
> the board I am working on.
>
> Thomas Koeller (3):
>   DM365: Added PINMUX definitions for GPIO30..32
>   DM365: Make CLKOUTx available
>   DM365: Added more PINMUX configurations for AEMIF
>
>  arch/arm/mach-davinci/dm365.c            |   12 +++++++++++-
>  arch/arm/mach-davinci/include/mach/mux.h |   13 ++++++++++++-
>  2 files changed, 23 insertions(+), 2 deletions(-)

Looks good, applying and queuing for 2.6.35 in davinci-next.

In the future, please report which platforms this was tested on.
Because these are simple enough changes and they passed a visual
sanity check, I'll just apply them this time.

Kevin




From sshtylyov at mvista.com  Thu May 13 13:48:42 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Thu, 13 May 2010 22:48:42 +0400
Subject: [PATCH RFC v8] MUSB: DA8xx/OMAP-L1x glue layer
In-Reply-To: <201005122212.11729.sshtylyov@ru.mvista.com>
References: <201005122212.11729.sshtylyov@ru.mvista.com>
Message-ID: <4BEC498A.6070804@ru.mvista.com>

Sergei Shtylyov wrote:
> Texas Instruments DA8xx/OMAP-L1x glue layer for the MUSBMHRDC driver.
>
> Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
> Signed-off-by: Yadviga Grigorieva <yadviga at ru.mvista.com>
>
> ---
> The patch is against the recent Linus' tree.

   Felipe, I forgot to both CC you and drop RFC from the subject. Please 
queue/ack this.

WBR, Sergei



From sshtylyov at ru.mvista.com  Thu May 13 13:51:51 2010
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Thu, 13 May 2010 22:51:51 +0400
Subject: [PATCH] DA830: fix USB 2.0 clock entry
Message-ID: <201005132251.51518.sshtylyov@ru.mvista.com>

DA8xx OHCI driver fails to load due to failing clk_get() call for the USB 2.0
clock. Arrange matching USB 2.0 clock by the clock name instead of the device.
(Adding another CLK() entry for "ohci.0" device won't do -- in the future I'll
also have to enable USB 2.0 clock to configure CPPI 4.1 module, in which case
I won't have any device at all.)

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>

---
The patch is against the recent DaVinci tree.

 arch/arm/mach-davinci/da830.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Index: linux-davinci/arch/arm/mach-davinci/da830.c
===================================================================
--- linux-davinci.orig/arch/arm/mach-davinci/da830.c
+++ linux-davinci/arch/arm/mach-davinci/da830.c
@@ -411,7 +411,7 @@ static struct clk_lookup da830_clks[] = 
 	CLK("davinci-mcasp.0",	NULL,		&mcasp0_clk),
 	CLK("davinci-mcasp.1",	NULL,		&mcasp1_clk),
 	CLK("davinci-mcasp.2",	NULL,		&mcasp2_clk),
-	CLK("musb_hdrc",	NULL,		&usb20_clk),
+	CLK(NULL,		"usb20",	&usb20_clk),
 	CLK(NULL,		"aemif",	&aemif_clk),
 	CLK(NULL,		"aintc",	&aintc_clk),
 	CLK(NULL,		"secu_mgr",	&secu_mgr_clk),

From sshtylyov at mvista.com  Thu May 13 14:01:00 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Thu, 13 May 2010 23:01:00 +0400
Subject: [PATCH] DA830: fix USB 2.0 clock entry
In-Reply-To: <201005132251.51518.sshtylyov@ru.mvista.com>
References: <201005132251.51518.sshtylyov@ru.mvista.com>
Message-ID: <4BEC4C6C.8000004@mvista.com>

Hello.

I wrote:
> DA8xx OHCI driver fails to load due to failing clk_get() call for the USB 2.0
> clock. Arrange matching USB 2.0 clock by the clock name instead of the device.
> (Adding another CLK() entry for "ohci.0" device won't do -- in the future I'll
> also have to enable USB 2.0 clock to configure CPPI 4.1 module, in which case
> I won't have any device at all.)
>   

   This was actually a part of CPPI 4.1 platform init. patch, but I've 
just realized it's necessary for OHCI too. Didn't notice it before. :-/

> Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
>
> ---
> The patch is against the recent DaVinci tree.
>   

   Kevin, could we squeeze it into 2.6.34?

>  arch/arm/mach-davinci/da830.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> Index: linux-davinci/arch/arm/mach-davinci/da830.c
> ===================================================================
> --- linux-davinci.orig/arch/arm/mach-davinci/da830.c
> +++ linux-davinci/arch/arm/mach-davinci/da830.c
> @@ -411,7 +411,7 @@ static struct clk_lookup da830_clks[] = 
>  	CLK("davinci-mcasp.0",	NULL,		&mcasp0_clk),
>  	CLK("davinci-mcasp.1",	NULL,		&mcasp1_clk),
>  	CLK("davinci-mcasp.2",	NULL,		&mcasp2_clk),
> -	CLK("musb_hdrc",	NULL,		&usb20_clk),
> +	CLK(NULL,		"usb20",	&usb20_clk),
>  	CLK(NULL,		"aemif",	&aemif_clk),
>  	CLK(NULL,		"aintc",	&aintc_clk),
>  	CLK(NULL,		"secu_mgr",	&secu_mgr_clk),

WBR, Sergei


From junxiao.bi at windriver.com  Mon May 10 03:17:03 2010
From: junxiao.bi at windriver.com (Bi Junxiao)
Date: Mon, 10 May 2010 16:17:03 +0800
Subject: question about using DMA for davinci SPI controller
Message-ID: <4BE7C0FF.8070406@windriver.com>

Hi all,

I am trying to fix a bug about full duplex DMA transfer for SPI
controller hang on ti-omapl138 ref borad.
I read the DMA setting code of davinci SPI controller. It's in
drivers/spi/davinci_spi.c:davinci_spi_bufs_dma().
There is a code snippet which I don't understand. List below:

--------------------------------------------------------------------------------
if (t->tx_buf) {
t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
DMA_TO_DEVICE);
if (dma_mapping_error(&spi->dev, t->tx_dma)) {
dev_dbg(sdev, "Unable to DMA map a %d bytes"
" TX buffer\n", count);
return -ENOMEM;
}
temp_count = count;
} else {
/* We need TX clocking for RX transaction */
t->tx_dma = dma_map_single(&spi->dev,
(void *)davinci_spi->tmp_buf, count + 1,
DMA_TO_DEVICE);
if (dma_mapping_error(&spi->dev, t->tx_dma)) {
dev_dbg(sdev, "Unable to DMA map a %d bytes"
" TX tmp buffer\n", count);
return -ENOMEM;
}
temp_count = count + 1;
}
----------------------------------------------------------------------------------
My question is why the transfer count in else logic is count+1 but in if
logic it's only count?
When I changed it from count?1 to count and use a test program to read
a spi flash, I found the DMA rx interrupt can not be triggered.
The test program hung for ever.

Would anybody have any idea about this?

Thanks.

From julia at diku.dk  Thu May 13 14:59:32 2010
From: julia at diku.dk (Julia Lawall)
Date: Thu, 13 May 2010 21:59:32 +0200 (CEST)
Subject: [PATCH 4/20] arch/arm/mach-davinci: Use kzalloc
Message-ID: <Pine.LNX.4.64.1005132159170.6282@ask.diku.dk>

From: Julia Lawall <julia at diku.dk>

Use kzalloc rather than the combination of kmalloc and memset.

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@@
expression x,size,flags;
statement S;
@@

-x = kmalloc(size,flags);
+x = kzalloc(size,flags);
 if (x == NULL) S
-memset(x, 0, size);
// </smpl>

Signed-off-by: Julia Lawall <julia at diku.dk>

---
 arch/arm/mach-davinci/dma.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff -u -p a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -1419,12 +1419,11 @@ static int __init edma_probe(struct plat
 			goto fail1;
 		}
 
-		edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
+		edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
 		if (!edma_cc[j]) {
 			status = -ENOMEM;
 			goto fail1;
 		}
-		memset(edma_cc[j], 0, sizeof(struct edma));
 
 		edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel,
 							EDMA_MAX_DMACH);

From cyril at ti.com  Thu May 13 15:23:37 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu, 13 May 2010 16:23:37 -0400
Subject: [PATCH v6 1/6] Davinci: generalized debug macros
In-Reply-To: <87iq6rogow.fsf@deeprootsystems.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>	<1273271886-15190-2-git-send-email-cyril@ti.com>	<87y6fnolwn.fsf@deeprootsystems.com>
	<87iq6rogow.fsf@deeprootsystems.com>
Message-ID: <4BEC5FC9.5090900@ti.com>

Hi Kevin,

[...]
>> Tony's updated version[1] for OMAP is not using 0x3ffc offset since only
>> 4 bytes are used.

I see that Tony's patch passes just one word through this area.  The
davinci code on the other hand passes both phys and virt, hence the
extra word of allocation.

>> Any objection to making and testing that change?
> 
> fwiw, I boot tested using 0x3ffc on DMx (dm6446, dm355, dm6467 EVMs)
> as well DA8xx (da830 and da850 EVMs) and it works fine for all.

Interesting.  I would think that it would end up clobbering the word @4000.

Regards
Cyril.


From cyril at ti.com  Thu May 13 15:24:38 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu, 13 May 2010 16:24:38 -0400
Subject: [PATCH v6 3/6] Davinci: tnetv107x soc support
In-Reply-To: <87fx1vogj5.fsf@deeprootsystems.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>	<1273271886-15190-4-git-send-email-cyril@ti.com>
	<87fx1vogj5.fsf@deeprootsystems.com>
Message-ID: <4BEC6006.5090403@ti.com>

Hi Kevin,

[...]
>> +#define PINMUX(x)		(4 * (x))
> 
> minor nit...
> 
> Isn't this a duplicate of what is now in <mach/mux.h> ?

Yes, I will remove this unfortunate left over.

Regards
Cyril.

From cyril at ti.com  Thu May 13 15:27:48 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu, 13 May 2010 16:27:48 -0400
Subject: [PATCH v6 4/6] Davinci: tnetv107x initial gpio support
In-Reply-To: <87wrv7n0cs.fsf@deeprootsystems.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>	<1273271886-15190-5-git-send-email-cyril@ti.com>
	<87wrv7n0cs.fsf@deeprootsystems.com>
Message-ID: <4BEC60C4.9030403@ti.com>

Hi Kevin,

[...]
> I know Sergei isn't used to me agreeing with him ;) but I tend to
> agree with him on the increased bulk of gpio_set_value().
> 
> It's not simply the increased size that is an issue here.  The point
> of these inlines (as the comment suggests) is for low-overhead
> bit-banging.  With the introduction of different methods depending on
> GPIO type, as well as the locking for the tnetv style, this is no
> longer low-overhead in my mind.
> 
> Below is an alternate solution.

Agreed on the solution.  This is (somewhat) similar to an earlier
tnetv107x series, in which the inline gpio code wouldn't kick in on the
tnetv107x controller.  Looks like we've gone full circle on this.

I will post an updated series.  Thanks.

Regards
Cyril.

From cyril at ti.com  Thu May 13 15:34:07 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu, 13 May 2010 16:34:07 -0400
Subject: [PATCH v6 0/6] Davinci: initial tnetv107x patch series
In-Reply-To: <87mxw3n08s.fsf@deeprootsystems.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
	<87mxw3n08s.fsf@deeprootsystems.com>
Message-ID: <4BEC623F.10507@ti.com>

Hi Kevin,

[...]
> Is there anything in the DaVinci-specific parts now that is preventing
> a single kernel shared between DMx an tnetv?

No, at least not by design :-)

> I know about the ARM-generic code that has problems when both ARMv5
> and ARMv6 are enabled, but am curious about any remaining blocks in
> the arch/arm/mach-davinci/* code.

Regards
Cyril.

From liuyue18301 at 163.com  Thu May 13 20:18:59 2010
From: liuyue18301 at 163.com (liuyue18301)
Date: Fri, 14 May 2010 09:18:59 +0800 (CST)
Subject: davinci linux kernel updata
Message-ID: <c63752.b818.12894649618.Coremail.liuyue18301@163.com>

hello everybody:
       if i want to updata the davinci linux kernel to the higher.what should i do,i think the  gcc version has to update.now,i have download the kernle version:2.6.32 and gcc 4.3.3,what i do is just update the gcc and linux kernel in the SEED-SDK.the flow is ok?
                                                              thank you  
-------------- next part --------------
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From stanley.miao at windriver.com  Thu May 13 21:48:25 2010
From: stanley.miao at windriver.com (stanley.miao)
Date: Fri, 14 May 2010 10:48:25 +0800
Subject: davinci linux kernel updata
In-Reply-To: <c63752.b818.12894649618.Coremail.liuyue18301@163.com>
References: <c63752.b818.12894649618.Coremail.liuyue18301@163.com>
Message-ID: <4BECB9F9.3000507@windriver.com>

git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git

liuyue18301 wrote:
> hello everybody:
> if i want to updata the davinci linux kernel to the higher.what should 
> i do,i think the gcc version has to update.now,i have download the 
> kernle version:2.6.32 and gcc 4.3.3,what i do is just update the gcc 
> and linux kernel in the SEED-SDK.the flow is ok?
> thank you
>
>
>
> ------------------------------------------------------------------------
> ?????????????????????????????????????????? <http://ym.163.com/?from=od3>
> ------------------------------------------------------------------------
>
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>   


From Jon.Povey at racelogic.co.uk  Thu May 13 21:46:53 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Fri, 14 May 2010 03:46:53 +0100
Subject: davinci linux kernel updata
In-Reply-To: <c63752.b818.12894649618.Coremail.liuyue18301@163.com>
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08E03CFE6E@Cloud.RL.local>

liuyue18301 wrote:
>        if i want to updata the davinci linux kernel to the
> higher.what should i do,i think the  gcc version has to update.now,i
> have download the kernle version:2.6.32 and gcc 4.3.3,what i do is
> just update the gcc and linux kernel in the SEED-SDK.the flow is ok?

I don't know what the SEED-SDK is.
For the git kernel I have been using the CodeSourcery toolchain:

http://www.codesourcery.com/sgpp/lite/arm/portal/release858

As recommended here:

http://processors.wiki.ti.com/index.php?title=DaVinci_GIT_Linux_Kernel#Overview

Hope this helps.


--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

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From ajay.gupta at ti.com  Fri May 14 00:07:35 2010
From: ajay.gupta at ti.com (Gupta, Ajay Kumar)
Date: Fri, 14 May 2010 10:37:35 +0530
Subject: [PATCH RFC v8] MUSB: DA8xx/OMAP-L1x glue layer
In-Reply-To: <201005122212.11729.sshtylyov@ru.mvista.com>
References: <201005122212.11729.sshtylyov@ru.mvista.com>
Message-ID: <19F8576C6E063C45BE387C64729E7394044E4054D1@dbde02.ent.ti.com>

Hi,
> -----Original Message-----
> From: davinci-linux-open-source-
> bounces+ajay.gupta=ti.com at linux.davincidsp.com [mailto:davinci-linux-open-
> source-bounces+ajay.gupta=ti.com at linux.davincidsp.com] On Behalf Of Sergei
> Shtylyov
> Sent: Wednesday, May 12, 2010 11:42 PM
> To: linux-usb at vger.kernel.org
> Cc: davinci-linux-open-source at linux.davincidsp.com
> Subject: [PATCH RFC v8] MUSB: DA8xx/OMAP-L1x glue layer
> 
> Texas Instruments DA8xx/OMAP-L1x glue layer for the MUSBMHRDC driver.
> 
> Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
> Signed-off-by: Yadviga Grigorieva <yadviga at ru.mvista.com>
> 
> ---
> The patch is against the recent Linus' tree.
> 
> WARNING: the MUSB and OHCI drivers will only work if your boot loader
> leaves
> the DA8xx boot configuration registers unlocked, otherwise they will lock
> up
> the kernel!
> 
> Changes since the previous version:
> - removed DMA related code (to be added back by a later patch);
> - removed spurious interrupt message from da8xx_interrupt();
> - added a check for USB 1.1 being clocked from USB 2.0 PHY to phy_off();
> - moved USB register #define's from cppi41_dma.h in another patch, adding
>   'DA8XX_' prefix to them;
> - s/DA8XX_[RT]X_EP_MASK/DA8XX_USB_[RT]X_EP_MASK/, s/DA8XX_[RT]X_INTR_MASK/
>   DA8XX_INTR_[RT]X_MASK/, also reordered these macros;
> - used IO_ADDRESS() macro in #define CFGCHIP2 to avoid having to export
>   'da8xx_syscfg0_base' for modular build;
> - removed setting 'musb->is_active' from the code handling DRVVBUS
> interrupt;
> - moved the transceiver initialization further down in
> musb_platform_init();
> - moved s/ARCH_DAVINCI/ARCH_DAVINCI_DMx/ change into the separate patch;
> - fixed up some comments;
> - fixed reject in musb_core.h...
> 
>  drivers/usb/musb/Kconfig     |    5
>  drivers/usb/musb/Makefile    |    4
>  drivers/usb/musb/da8xx.c     |  492
> +++++++++++++++++++++++++++++++++++++++++++
>  drivers/usb/musb/musb_core.h |    1
>  4 files changed, 501 insertions(+), 1 deletion(-)
> 
[..]
> + * REVISIT (PM): we should be able to keep the PHY in low power mode most
> + * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
> + * and, when in host mode, autosuspending idle root ports... PHY_PLLON
> + * (overriding SUSPENDM?) then likely needs to stay off.
> + */
> +
> +static inline void phy_on(void)
> +{
> +	u32 cfgchip2 = __raw_readl(CFGCHIP2);
> +
> +	/*
> +	 * Start the on-chip PHY and its PLL.
> +	 */
> +	cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN |
> CFGCHIP2_OTGPWRDN);
> +	cfgchip2 |= CFGCHIP2_PHY_PLLON;

How about values USB0REF-FREQ, USB0DATPOL, USB0OTGMODE bits ? Are they
Getting set elsewhere or default value is good to go?

> +	__raw_writel(cfgchip2, CFGCHIP2);
> +
> +	pr_info("Waiting for USB PHY clock good...\n");
> +	while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
> +		cpu_relax();

It's good to have a timeout here. I have seen this bit not
getting updated in some scenarios on AM3517 and also on
PUMA5 platforms which would cause a system lockup here.

-Ajay
> +}
> +
> +static inline void phy_off(void)
> +{

From sshtylyov at mvista.com  Fri May 14 04:28:43 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 14 May 2010 13:28:43 +0400
Subject: [PATCH RFC v8] MUSB: DA8xx/OMAP-L1x glue layer
In-Reply-To: <19F8576C6E063C45BE387C64729E7394044E4054D1@dbde02.ent.ti.com>
References: <201005122212.11729.sshtylyov@ru.mvista.com>
	<19F8576C6E063C45BE387C64729E7394044E4054D1@dbde02.ent.ti.com>
Message-ID: <4BED17CB.90305@mvista.com>

Hello.

Gupta, Ajay Kumar wrote:

>> -----Original Message-----
>> From: davinci-linux-open-source-
>> bounces+ajay.gupta=ti.com at linux.davincidsp.com [mailto:davinci-linux-open-
>> source-bounces+ajay.gupta=ti.com at linux.davincidsp.com] On Behalf Of Sergei
>> Shtylyov
>> Sent: Wednesday, May 12, 2010 11:42 PM
>> To: linux-usb at vger.kernel.org
>> Cc: davinci-linux-open-source at linux.davincidsp.com
>> Subject: [PATCH RFC v8] MUSB: DA8xx/OMAP-L1x glue layer
>>
>> Texas Instruments DA8xx/OMAP-L1x glue layer for the MUSBMHRDC driver.
>>
>> Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
>> Signed-off-by: Yadviga Grigorieva <yadviga at ru.mvista.com>
>>
>> ---
>> The patch is against the recent Linus' tree.
>>
>> WARNING: the MUSB and OHCI drivers will only work if your boot loader
>> leaves
>> the DA8xx boot configuration registers unlocked, otherwise they will lock
>> up
>> the kernel!
>>
>> Changes since the previous version:
>> - removed DMA related code (to be added back by a later patch);
>> - removed spurious interrupt message from da8xx_interrupt();
>> - added a check for USB 1.1 being clocked from USB 2.0 PHY to phy_off();
>> - moved USB register #define's from cppi41_dma.h in another patch, adding
>>   'DA8XX_' prefix to them;
>> - s/DA8XX_[RT]X_EP_MASK/DA8XX_USB_[RT]X_EP_MASK/, s/DA8XX_[RT]X_INTR_MASK/
>>   DA8XX_INTR_[RT]X_MASK/, also reordered these macros;
>> - used IO_ADDRESS() macro in #define CFGCHIP2 to avoid having to export
>>   'da8xx_syscfg0_base' for modular build;
>> - removed setting 'musb->is_active' from the code handling DRVVBUS
>> interrupt;
>> - moved the transceiver initialization further down in
>> musb_platform_init();
>> - moved s/ARCH_DAVINCI/ARCH_DAVINCI_DMx/ change into the separate patch;
>> - fixed up some comments;
>> - fixed reject in musb_core.h...
>>
>>  drivers/usb/musb/Kconfig     |    5
>>  drivers/usb/musb/Makefile    |    4
>>  drivers/usb/musb/da8xx.c     |  492
>> +++++++++++++++++++++++++++++++++++++++++++
>>  drivers/usb/musb/musb_core.h |    1
>>  4 files changed, 501 insertions(+), 1 deletion(-)
>>
> [..]
>> + * REVISIT (PM): we should be able to keep the PHY in low power mode most
>> + * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
>> + * and, when in host mode, autosuspending idle root ports... PHY_PLLON
>> + * (overriding SUSPENDM?) then likely needs to stay off.
>> + */
>> +
>> +static inline void phy_on(void)
>> +{
>> +	u32 cfgchip2 = __raw_readl(CFGCHIP2);
>> +
>> +	/*
>> +	 * Start the on-chip PHY and its PLL.
>> +	 */
>> +	cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN |
>> CFGCHIP2_OTGPWRDN);
>> +	cfgchip2 |= CFGCHIP2_PHY_PLLON;
> 
> How about values USB0REF-FREQ, USB0DATPOL, USB0OTGMODE bits ? Are they
> Getting set elsewhere or default value is good to go?

    Of course, they are initialized in the platfrom code, where this 
stuff really belongs -- see da830_evm_usb_init() in 
arch/arm/mach-davinci/board-da830-evm.c...

>> +	__raw_writel(cfgchip2, CFGCHIP2);
>> +
>> +	pr_info("Waiting for USB PHY clock good...\n");
>> +	while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
>> +		cpu_relax();
> 
> It's good to have a timeout here. I have seen this bit not
> getting updated in some scenarios on AM3517 and also on

    It's not updated if SYSCFG registers are locked by U-Boot on DA8xx.

> PUMA5 platforms which would cause a system lockup here.

    Well, but what to do if it's not set in time? Fail loading of the 
driver?

> -Ajay

WBR, Sergei

From ajay.gupta at ti.com  Fri May 14 04:32:50 2010
From: ajay.gupta at ti.com (Gupta, Ajay Kumar)
Date: Fri, 14 May 2010 15:02:50 +0530
Subject: [PATCH RFC v8] MUSB: DA8xx/OMAP-L1x glue layer
In-Reply-To: <4BED17CB.90305@mvista.com>
References: <201005122212.11729.sshtylyov@ru.mvista.com>
	<19F8576C6E063C45BE387C64729E7394044E4054D1@dbde02.ent.ti.com>
	<4BED17CB.90305@mvista.com>
Message-ID: <19F8576C6E063C45BE387C64729E7394044E4055C4@dbde02.ent.ti.com>

Hi,
> -----Original Message-----
> From: Sergei Shtylyov [mailto:sshtylyov at mvista.com]
> Sent: Friday, May 14, 2010 2:59 PM
> To: Gupta, Ajay Kumar
> Cc: Sergei Shtylyov; linux-usb at vger.kernel.org; davinci-linux-open-
> source at linux.davincidsp.com
> Subject: Re: [PATCH RFC v8] MUSB: DA8xx/OMAP-L1x glue layer
> 
> Hello.
> 
> Gupta, Ajay Kumar wrote:
> 
> >> -----Original Message-----
> >> From: davinci-linux-open-source-
> >> bounces+ajay.gupta=ti.com at linux.davincidsp.com [mailto:davinci-linux-
> open-
> >> source-bounces+ajay.gupta=ti.com at linux.davincidsp.com] On Behalf Of
> Sergei
> >> Shtylyov
> >> Sent: Wednesday, May 12, 2010 11:42 PM
> >> To: linux-usb at vger.kernel.org
> >> Cc: davinci-linux-open-source at linux.davincidsp.com
> >> Subject: [PATCH RFC v8] MUSB: DA8xx/OMAP-L1x glue layer
> >>
> >> Texas Instruments DA8xx/OMAP-L1x glue layer for the MUSBMHRDC driver.
> >>
> >> Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
> >> Signed-off-by: Yadviga Grigorieva <yadviga at ru.mvista.com>
> >>
> >> ---
> >> The patch is against the recent Linus' tree.
> >>
> >> WARNING: the MUSB and OHCI drivers will only work if your boot loader
> >> leaves
> >> the DA8xx boot configuration registers unlocked, otherwise they will
> lock
> >> up
> >> the kernel!
> >>
> >> Changes since the previous version:
> >> - removed DMA related code (to be added back by a later patch);
> >> - removed spurious interrupt message from da8xx_interrupt();
> >> - added a check for USB 1.1 being clocked from USB 2.0 PHY to
> phy_off();
> >> - moved USB register #define's from cppi41_dma.h in another patch,
> adding
> >>   'DA8XX_' prefix to them;
> >> - s/DA8XX_[RT]X_EP_MASK/DA8XX_USB_[RT]X_EP_MASK/,
> s/DA8XX_[RT]X_INTR_MASK/
> >>   DA8XX_INTR_[RT]X_MASK/, also reordered these macros;
> >> - used IO_ADDRESS() macro in #define CFGCHIP2 to avoid having to export
> >>   'da8xx_syscfg0_base' for modular build;
> >> - removed setting 'musb->is_active' from the code handling DRVVBUS
> >> interrupt;
> >> - moved the transceiver initialization further down in
> >> musb_platform_init();
> >> - moved s/ARCH_DAVINCI/ARCH_DAVINCI_DMx/ change into the separate
> patch;
> >> - fixed up some comments;
> >> - fixed reject in musb_core.h...
> >>
> >>  drivers/usb/musb/Kconfig     |    5
> >>  drivers/usb/musb/Makefile    |    4
> >>  drivers/usb/musb/da8xx.c     |  492
> >> +++++++++++++++++++++++++++++++++++++++++++
> >>  drivers/usb/musb/musb_core.h |    1
> >>  4 files changed, 501 insertions(+), 1 deletion(-)
> >>
> > [..]
> >> + * REVISIT (PM): we should be able to keep the PHY in low power mode
> most
> >> + * of the time (24 MHz oscillator and PLL off, etc.) by setting
> POWER.D0
> >> + * and, when in host mode, autosuspending idle root ports... PHY_PLLON
> >> + * (overriding SUSPENDM?) then likely needs to stay off.
> >> + */
> >> +
> >> +static inline void phy_on(void)
> >> +{
> >> +	u32 cfgchip2 = __raw_readl(CFGCHIP2);
> >> +
> >> +	/*
> >> +	 * Start the on-chip PHY and its PLL.
> >> +	 */
> >> +	cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN |
> >> CFGCHIP2_OTGPWRDN);
> >> +	cfgchip2 |= CFGCHIP2_PHY_PLLON;
> >
> > How about values USB0REF-FREQ, USB0DATPOL, USB0OTGMODE bits ? Are they
> > Getting set elsewhere or default value is good to go?
> 
>     Of course, they are initialized in the platfrom code, where this
> stuff really belongs -- see da830_evm_usb_init() in
> arch/arm/mach-davinci/board-da830-evm.c...
> 
> >> +	__raw_writel(cfgchip2, CFGCHIP2);
> >> +
> >> +	pr_info("Waiting for USB PHY clock good...\n");
> >> +	while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
> >> +		cpu_relax();
> >
> > It's good to have a timeout here. I have seen this bit not
> > getting updated in some scenarios on AM3517 and also on
> 
>     It's not updated if SYSCFG registers are locked by U-Boot on DA8xx.
> 
> > PUMA5 platforms which would cause a system lockup here.
> 
>     Well, but what to do if it's not set in time? Fail loading of the
> driver?
Not fail as I have seem OTG port to be working fine even when this
bit is not set. Something strange..

-Ajay

> 
> > -Ajay
> 
> WBR, Sergei

From pjiang at motorola.com  Fri May 14 05:19:56 2010
From: pjiang at motorola.com (Jiang Ivan-A21617)
Date: Fri, 14 May 2010 18:19:56 +0800
Subject: how to configure the USB0 as full speed on OMAP L138? 
Message-ID: <DFC883208F3ED446B46EEE1DBD54BA950728BE73@zmy16exm62.ds.mot.com>

Hi,

 Any one know how to configure the USB0(dual-mode, USB 2.0 ) to full
speed?

Default, this device will function as high speed. I configure USB0 as
GADGET_MUSB currently.

  Thanks

  JP

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From swami.iyer at ti.com  Fri May 14 05:26:31 2010
From: swami.iyer at ti.com (Subbrathnam, Swaminathan)
Date: Fri, 14 May 2010 15:56:31 +0530
Subject: how to configure the USB0 as full speed on OMAP L138? 
In-Reply-To: <DFC883208F3ED446B46EEE1DBD54BA950728BE73@zmy16exm62.ds.mot.com>
References: <DFC883208F3ED446B46EEE1DBD54BA950728BE73@zmy16exm62.ds.mot.com>
Message-ID: <FCCFB4CDC6E5564B9182F639FC35608703051ACF09@dbde02.ent.ti.com>

Ivan,
            High Speed device is backward compatible to full speed operation so no need to configure the device in full speed mode.  If you connect to a full speed port the device will automatically enumerate as a full speed device.

Regards
swami

________________________________
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Jiang Ivan-A21617
Sent: Friday, May 14, 2010 3:50 PM
To: davinci-linux-open-source at linux.davincidsp.com
Subject: how to configure the USB0 as full speed on OMAP L138?

Hi,
 Any one know how to configure the USB0(dual-mode, USB 2.0 ) to full speed?
Default, this device will function as high speed. I configure USB0 as GADGET_MUSB currently.
  Thanks
  JP
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From pjiang at motorola.com  Fri May 14 05:59:19 2010
From: pjiang at motorola.com (Jiang Ivan-A21617)
Date: Fri, 14 May 2010 18:59:19 +0800
Subject: how to configure the USB0 as full speed on OMAP L138? 
In-Reply-To: <FCCFB4CDC6E5564B9182F639FC35608703051ACF09@dbde02.ent.ti.com>
References: <DFC883208F3ED446B46EEE1DBD54BA950728BE73@zmy16exm62.ds.mot.com>
	<FCCFB4CDC6E5564B9182F639FC35608703051ACF09@dbde02.ent.ti.com>
Message-ID: <DFC883208F3ED446B46EEE1DBD54BA950728BE7D@zmy16exm62.ds.mot.com>

Swami,

 Thanks, what I want is just narrow down some hardware issue. So need to change code or configuration to force high speed to full speed.  Already try with bridging with a USB1.1 HUB, need some other method to verify. 

 Do you know any method for that?

 Thanks

 Ivan

 

________________________________

From: Subbrathnam, Swaminathan [mailto:swami.iyer at ti.com] 
Sent: 2010?5?14? 18:27
To: Jiang Ivan-A21617; davinci-linux-open-source at linux.davincidsp.com
Subject: RE: how to configure the USB0 as full speed on OMAP L138? 

 

Ivan,

            High Speed device is backward compatible to full speed operation so no need to configure the device in full speed mode.  If you connect to a full speed port the device will automatically enumerate as a full speed device.

 

Regards

swami

 

________________________________

From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Jiang Ivan-A21617
Sent: Friday, May 14, 2010 3:50 PM
To: davinci-linux-open-source at linux.davincidsp.com
Subject: how to configure the USB0 as full speed on OMAP L138? 

 

Hi,

 Any one know how to configure the USB0(dual-mode, USB 2.0 ) to full speed?

Default, this device will function as high speed. I configure USB0 as GADGET_MUSB currently.

  Thanks

  JP

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From cyril at ti.com  Fri May 14 09:07:43 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 14 May 2010 10:07:43 -0400
Subject: [PATCH v6 1/6] Davinci: generalized debug macros
In-Reply-To: <4BEC5FC9.5090900@ti.com>
References: <1273271886-15190-1-git-send-email-cyril@ti.com>	<1273271886-15190-2-git-send-email-cyril@ti.com>	<87y6fnolwn.fsf@deeprootsystems.com>
	<87iq6rogow.fsf@deeprootsystems.com> <4BEC5FC9.5090900@ti.com>
Message-ID: <4BED592F.3040907@ti.com>

Hi Kevin,

[...]
>>> >> Any objection to making and testing that change?

There is a difference in the way the OMAP and Davinci debug macros work.
 The OMAP uncompress passes in a code (OMAPxUARTy).  The debug macros
then figure out the phys and virt bases of the requested UART.

On Davinci, we unfortunately don't have a consistent memory map across
the family, and here we need to pass in base addresses from uncompress.
 For this, we have been passing both phys and virt bases, so that the
debug macros don't have to rely on IO_ADDRESS() translation internally.
 This flexibility is necessary for tnetv107x, where IO_ADDRESS() does
not translate properly.

Regards
Cyril.

From khilman at deeprootsystems.com  Fri May 14 10:08:21 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Fri, 14 May 2010 08:08:21 -0700
Subject: [PATCH] DA830: fix USB 2.0 clock entry
In-Reply-To: <4BEC4C6C.8000004@mvista.com> (Sergei Shtylyov's message of "Thu\,
	13 May 2010 23\:01\:00 +0400")
References: <201005132251.51518.sshtylyov@ru.mvista.com>
	<4BEC4C6C.8000004@mvista.com>
Message-ID: <87sk5ur062.fsf@deeprootsystems.com>

Sergei Shtylyov <sshtylyov at mvista.com> writes:

> Hello.
>
> I wrote:
>> DA8xx OHCI driver fails to load due to failing clk_get() call for the USB 2.0
>> clock. Arrange matching USB 2.0 clock by the clock name instead of the device.
>> (Adding another CLK() entry for "ohci.0" device won't do -- in the future I'll
>> also have to enable USB 2.0 clock to configure CPPI 4.1 module, in which case
>> I won't have any device at all.)
>>   
>
>   This was actually a part of CPPI 4.1 platform init. patch, but I've
> just realized it's necessary for OHCI too. Didn't notice it
> before. :-/
>
>> Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
>>
>> ---
>> The patch is against the recent DaVinci tree.
>>   
>
>   Kevin, could we squeeze it into 2.6.34?
>

Sure, if you convice me that this doesn't break the clk_get() in the
musb driver.

Kevin

From khilman at deeprootsystems.com  Fri May 14 10:10:23 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Fri, 14 May 2010 08:10:23 -0700
Subject: [PATCH v6 1/6] Davinci: generalized debug macros
In-Reply-To: <4BED592F.3040907@ti.com> (Cyril Chemparathy's message of "Fri\,
	14 May 2010 10\:07\:43 -0400")
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
	<1273271886-15190-2-git-send-email-cyril@ti.com>
	<87y6fnolwn.fsf@deeprootsystems.com>
	<87iq6rogow.fsf@deeprootsystems.com> <4BEC5FC9.5090900@ti.com>
	<4BED592F.3040907@ti.com>
Message-ID: <87mxw2r02o.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> Hi Kevin,
>
> [...]
>>>> >> Any objection to making and testing that change?
>
> There is a difference in the way the OMAP and Davinci debug macros work.
>  The OMAP uncompress passes in a code (OMAPxUARTy).  The debug macros
> then figure out the phys and virt bases of the requested UART.
>
> On Davinci, we unfortunately don't have a consistent memory map across
> the family, and here we need to pass in base addresses from uncompress.
>  For this, we have been passing both phys and virt bases, so that the
> debug macros don't have to rely on IO_ADDRESS() translation internally.
>  This flexibility is necessary for tnetv107x, where IO_ADDRESS() does
> not translate properly.

Understood, thanks for the clarification.  

Kevin


From khilman at deeprootsystems.com  Fri May 14 10:11:43 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Fri, 14 May 2010 08:11:43 -0700
Subject: [PATCH v6 0/6] Davinci: initial tnetv107x patch series
In-Reply-To: <4BEC623F.10507@ti.com> (Cyril Chemparathy's message of "Thu\,
	13 May 2010 16\:34\:07 -0400")
References: <1273271886-15190-1-git-send-email-cyril@ti.com>
	<87mxw3n08s.fsf@deeprootsystems.com> <4BEC623F.10507@ti.com>
Message-ID: <87iq6qr00g.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> Hi Kevin,
>
> [...]
>> Is there anything in the DaVinci-specific parts now that is preventing
>> a single kernel shared between DMx an tnetv?
>
> No, at least not by design :-)
>

Great.  I didn't see anything that would prevent it either, but wanted to
double check.

Thanks,

Kevin

From khilman at deeprootsystems.com  Fri May 14 10:16:04 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Fri, 14 May 2010 08:16:04 -0700
Subject: [PATCH 4/20] arch/arm/mach-davinci: Use kzalloc
In-Reply-To: <Pine.LNX.4.64.1005132159170.6282@ask.diku.dk> (Julia Lawall's
	message of "Thu\, 13 May 2010 21\:59\:32 +0200 \(CEST\)")
References: <Pine.LNX.4.64.1005132159170.6282@ask.diku.dk>
Message-ID: <87d3wyqzt7.fsf@deeprootsystems.com>

Julia Lawall <julia at diku.dk> writes:

> From: Julia Lawall <julia at diku.dk>
>
> Use kzalloc rather than the combination of kmalloc and memset.
>
> The semantic patch that makes this change is as follows:
> (http://coccinelle.lip6.fr/)
>
> // <smpl>
> @@
> expression x,size,flags;
> statement S;
> @@
>
> -x = kmalloc(size,flags);
> +x = kzalloc(size,flags);
>  if (x == NULL) S
> -memset(x, 0, size);
> // </smpl>
>
> Signed-off-by: Julia Lawall <julia at diku.dk>

Acked-by: Kevin Hilman <khilman at deeprootsystems.com>

From sshtylyov at mvista.com  Fri May 14 12:09:09 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 14 May 2010 21:09:09 +0400
Subject: [PATCH] DA830: fix USB 2.0 clock entry
In-Reply-To: <87sk5ur062.fsf@deeprootsystems.com>
References: <201005132251.51518.sshtylyov@ru.mvista.com>	<4BEC4C6C.8000004@mvista.com>
	<87sk5ur062.fsf@deeprootsystems.com>
Message-ID: <4BED83B5.9030005@mvista.com>

Hello.

Kevin Hilman wrote:

>>> DA8xx OHCI driver fails to load due to failing clk_get() call for the USB 2.0
>>> clock. Arrange matching USB 2.0 clock by the clock name instead of the device.
>>> (Adding another CLK() entry for "ohci.0" device won't do -- in the future I'll
>>> also have to enable USB 2.0 clock to configure CPPI 4.1 module, in which case
>>> I won't have any device at all.)
>>>   
>>>       
>>   This was actually a part of CPPI 4.1 platform init. patch, but I've
>> just realized it's necessary for OHCI too. Didn't notice it
>> before. :-/
>>
>>     
>>> Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
>>>
>>> ---
>>> The patch is against the recent DaVinci tree.
>>>   
>>>       
>>   Kevin, could we squeeze it into 2.6.34?
>>
>>     
>
> Sure, if you convice me that this doesn't break the clk_get() in the
> musb driver.
>   

   Sure, it doesn't. MUSB driver calls clk_get(dev, plat->clock). We're 
passing "usb20" as plat->clock, see da8xx_register_usb20() in usb.c...

> Kevin
>   

WBR, Sergei


From khilman at deeprootsystems.com  Fri May 14 13:26:57 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Fri, 14 May 2010 11:26:57 -0700
Subject: [PATCH] DA830: fix USB 2.0 clock entry
In-Reply-To: <4BED83B5.9030005@mvista.com> (Sergei Shtylyov's message of "Fri\,
	14 May 2010 21\:09\:09 +0400")
References: <201005132251.51518.sshtylyov@ru.mvista.com>
	<4BEC4C6C.8000004@mvista.com> <87sk5ur062.fsf@deeprootsystems.com>
	<4BED83B5.9030005@mvista.com>
Message-ID: <87aas2jq4u.fsf@deeprootsystems.com>

Sergei Shtylyov <sshtylyov at mvista.com> writes:

> Hello.
>
> Kevin Hilman wrote:
>
>>>> DA8xx OHCI driver fails to load due to failing clk_get() call for the USB 2.0
>>>> clock. Arrange matching USB 2.0 clock by the clock name instead of the device.
>>>> (Adding another CLK() entry for "ohci.0" device won't do -- in the future I'll
>>>> also have to enable USB 2.0 clock to configure CPPI 4.1 module, in which case
>>>> I won't have any device at all.)
>>>>         
>>>   This was actually a part of CPPI 4.1 platform init. patch, but I've
>>> just realized it's necessary for OHCI too. Didn't notice it
>>> before. :-/
>>>
>>>     
>>>> Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
>>>>
>>>> ---
>>>> The patch is against the recent DaVinci tree.
>>>>         
>>>   Kevin, could we squeeze it into 2.6.34?
>>>
>>>     
>>
>> Sure, if you convice me that this doesn't break the clk_get() in the
>> musb driver.
>>   
>
>   Sure, it doesn't. MUSB driver calls clk_get(dev, plat->clock). We're
> passing "usb20" as plat->clock, see da8xx_register_usb20() in usb.c...

/me convinced.  Thanks.

Will submit for 2.6.34-rc, but may be too late.  If I miss, will queue
for 2.6.35 in davinci-next.

Kevin


From khilman at deeprootsystems.com  Fri May 14 13:35:19 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Fri, 14 May 2010 11:35:19 -0700
Subject: [GIT PULL] one more davinci fix for 2.6.34
Message-ID: <87wrv6ib6g.fsf@deeprootsystems.com>

Linus,

Please pull one last one-liner fix for the DaVinci platform for 2.6.34.

Thanks,

Kevin


The following changes since commit b57f95a38233a2e73b679bea4a5453a1cc2a1cc9:
  Linus Torvalds (1):
        Linux 2.6.34-rc7

are available in the git repository at:

  ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git davinci-fixes-for-linus-2

Sergei Shtylyov (1):
      DA830: fix USB 2.0 clock entry

 arch/arm/mach-davinci/da830.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

From cyril at ti.com  Fri May 14 17:42:23 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 14 May 2010 18:42:23 -0400
Subject: [RFC 0/4] Davinci: mdio-emac separation series
Message-ID: <1273876947-30711-1-git-send-email-cyril@ti.com>

This patch series aims to separate mdio code from the emac driver, with the
intent of reuse on tnetv107x.  Unlike davinci, tnetv107x's mdio controller is
not embedded within an "emac" device.

This series has been (boot) tested on dm365.

Cyril Chemparathy (4):
  Davinci: mdio - separate out mdio controller code
  Davinci: mdio - add clock lookups for mdio
  Davinci: mdio - add platform devices for mdio
  Davinci: mdio - switch to new mdio driver

 arch/arm/mach-davinci/board-da830-evm.c     |    5 -
 arch/arm/mach-davinci/board-da850-evm.c     |    6 -
 arch/arm/mach-davinci/board-dm365-evm.c     |    7 -
 arch/arm/mach-davinci/board-dm644x-evm.c    |    7 -
 arch/arm/mach-davinci/board-dm646x-evm.c    |    8 -
 arch/arm/mach-davinci/board-neuros-osd2.c   |    7 -
 arch/arm/mach-davinci/board-sffsdr.c        |    7 -
 arch/arm/mach-davinci/da830.c               |    1 +
 arch/arm/mach-davinci/da850.c               |    1 +
 arch/arm/mach-davinci/devices-da8xx.c       |   24 ++-
 arch/arm/mach-davinci/dm365.c               |   20 ++-
 arch/arm/mach-davinci/dm644x.c              |   20 ++-
 arch/arm/mach-davinci/dm646x.c              |   20 ++-
 arch/arm/mach-davinci/include/mach/dm365.h  |    2 +-
 arch/arm/mach-davinci/include/mach/dm644x.h |    2 +-
 arch/arm/mach-davinci/include/mach/dm646x.h |    2 +-
 drivers/net/Kconfig                         |   11 +
 drivers/net/Makefile                        |    1 +
 drivers/net/davinci_emac.c                  |  164 ++----------
 drivers/net/davinci_mdio.c                  |  388 +++++++++++++++++++++++++++
 include/linux/davinci_emac.h                |    4 +-
 21 files changed, 509 insertions(+), 198 deletions(-)
 create mode 100644 drivers/net/davinci_mdio.c


From cyril at ti.com  Fri May 14 17:42:25 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 14 May 2010 18:42:25 -0400
Subject: [RFC 2/4] Davinci: mdio - add clock lookups for mdio
In-Reply-To: <1273876947-30711-1-git-send-email-cyril@ti.com>
References: <1273876947-30711-1-git-send-email-cyril@ti.com>
Message-ID: <1273876947-30711-3-git-send-email-cyril@ti.com>

The standalone davinci mdio drivers acquires its own (possible separate)
clock. On existing architectures where MDIO is built into the EMAC subsystem,
the same underlying clock is used by both mdio and emac.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/mach-davinci/da830.c  |    1 +
 arch/arm/mach-davinci/da850.c  |    1 +
 arch/arm/mach-davinci/dm365.c  |    1 +
 arch/arm/mach-davinci/dm644x.c |    1 +
 arch/arm/mach-davinci/dm646x.c |    1 +
 5 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 3a7a96f..8fe0292 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -416,6 +416,7 @@ static struct clk_lookup da830_clks[] = {
 	CLK(NULL,		"aintc",	&aintc_clk),
 	CLK(NULL,		"secu_mgr",	&secu_mgr_clk),
 	CLK("davinci_emac.1",	NULL,		&emac_clk),
+	CLK("davinci_mdio.0",	NULL,		&emac_clk),
 	CLK(NULL,		"gpio",		&gpio_clk),
 	CLK("i2c_davinci.2",	NULL,		&i2c1_clk),
 	CLK(NULL,		"usb11",	&usb11_clk),
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 6b8331b..5cb8a92 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -373,6 +373,7 @@ static struct clk_lookup da850_clks[] = {
 	CLK(NULL,		"arm",		&arm_clk),
 	CLK(NULL,		"rmii",		&rmii_clk),
 	CLK("davinci_emac.1",	NULL,		&emac_clk),
+	CLK("davinci_mdio.0",	NULL,		&emac_clk),
 	CLK("davinci-mcasp.0",	NULL,		&mcasp_clk),
 	CLK("da8xx_lcdc.0",	NULL,		&lcdc_clk),
 	CLK("davinci_mmc.0",	NULL,		&mmcsd_clk),
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index e5e3dce..a2c832f 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -458,6 +458,7 @@ static struct clk_lookup dm365_clks[] = {
 	CLK(NULL, "timer3", &timer3_clk),
 	CLK(NULL, "usb", &usb_clk),
 	CLK("davinci_emac.1", NULL, &emac_clk),
+	CLK("davinci_mdio.0", NULL, &emac_clk),
 	CLK("davinci_voicecodec", NULL, &voicecodec_clk),
 	CLK("davinci-asp.0", NULL, &asp0_clk),
 	CLK(NULL, "rto", &rto_clk),
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 7ad1520..001b9a1 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -300,6 +300,7 @@ static struct clk_lookup dm644x_clks[] = {
 	CLK(NULL, "uart1", &uart1_clk),
 	CLK(NULL, "uart2", &uart2_clk),
 	CLK("davinci_emac.1", NULL, &emac_clk),
+	CLK("davinci_mdio.0", NULL, &emac_clk),
 	CLK("i2c_davinci.1", NULL, &i2c_clk),
 	CLK("palm_bk3710", NULL, &ide_clk),
 	CLK("davinci-asp", NULL, &asp_clk),
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 9404565..60b7a8a 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -343,6 +343,7 @@ static struct clk_lookup dm646x_clks[] = {
 	CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
 	CLK(NULL, "aemif", &aemif_clk),
 	CLK("davinci_emac.1", NULL, &emac_clk),
+	CLK("davinci_mdio.0", NULL, &emac_clk),
 	CLK(NULL, "pwm0", &pwm0_clk),
 	CLK(NULL, "pwm1", &pwm1_clk),
 	CLK(NULL, "timer0", &timer0_clk),
-- 
1.7.0.4


From cyril at ti.com  Fri May 14 17:42:26 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 14 May 2010 18:42:26 -0400
Subject: [RFC 3/4] Davinci: mdio - add platform devices for mdio
In-Reply-To: <1273876947-30711-1-git-send-email-cyril@ti.com>
References: <1273876947-30711-1-git-send-email-cyril@ti.com>
Message-ID: <1273876947-30711-4-git-send-email-cyril@ti.com>

This patch adds mdio platform devices on socs that have the necessary
hardware.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/mach-davinci/devices-da8xx.c       |   20 ++++++++++++++++++++
 arch/arm/mach-davinci/dm365.c               |   16 ++++++++++++++++
 arch/arm/mach-davinci/dm644x.c              |   16 ++++++++++++++++
 arch/arm/mach-davinci/dm646x.c              |   16 ++++++++++++++++
 arch/arm/mach-davinci/include/mach/dm365.h  |    1 +
 arch/arm/mach-davinci/include/mach/dm644x.h |    1 +
 arch/arm/mach-davinci/include/mach/dm646x.h |    1 +
 7 files changed, 71 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 8cda729..0a1e7d4 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -385,8 +385,28 @@ static struct platform_device da8xx_emac_device = {
 	.resource	= da8xx_emac_resources,
 };
 
+static struct resource da8xx_mdio_resources[] = {
+	{
+		.start	= DA8XX_EMAC_MDIO_BASE,
+		.end	= DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device da8xx_mdio_device = {
+	.name		= "davinci_mdio",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(da8xx_mdio_resources),
+	.resource	= da8xx_mdio_resources,
+};
+
 int __init da8xx_register_emac(void)
 {
+	int ret;
+
+	ret = platform_device_register(&da8xx_mdio_device);
+	if (ret < 0)
+		return ret;
 	return platform_device_register(&da8xx_emac_device);
 }
 
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a2c832f..685116f 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -725,6 +725,21 @@ static struct platform_device dm365_emac_device = {
 	.resource	= dm365_emac_resources,
 };
 
+static struct resource dm365_mdio_resources[] = {
+	{
+		.start	= DM365_EMAC_MDIO_BASE,
+		.end	= DM365_EMAC_MDIO_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device dm365_mdio_device = {
+	.name		= "davinci_mdio",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(dm365_mdio_resources),
+	.resource	= dm365_mdio_resources,
+};
+
 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 	[IRQ_VDINT0]			= 2,
 	[IRQ_VDINT1]			= 6,
@@ -1207,6 +1222,7 @@ static int __init dm365_init_devices(void)
 
 	davinci_cfg_reg(DM365_INT_EDMA_CC);
 	platform_device_register(&dm365_edma_device);
+	platform_device_register(&dm365_mdio_device);
 	platform_device_register(&dm365_emac_device);
 	/* Add isif clock alias */
 	clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 001b9a1..8d08047 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -351,6 +351,21 @@ static struct platform_device dm644x_emac_device = {
        .resource	= dm644x_emac_resources,
 };
 
+static struct resource dm644x_mdio_resources[] = {
+	{
+		.start	= DM644X_EMAC_MDIO_BASE,
+		.end	= DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device dm644x_mdio_device = {
+       .name		= "davinci_mdio",
+       .id		= 0,
+       .num_resources	= ARRAY_SIZE(dm644x_mdio_resources),
+       .resource	= dm644x_mdio_resources,
+};
+
 /*
  * Device specific mux setup
  *
@@ -776,6 +791,7 @@ static int __init dm644x_init_devices(void)
 	clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
 	clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
 	platform_device_register(&dm644x_edma_device);
+	platform_device_register(&dm644x_mdio_device);
 	platform_device_register(&dm644x_emac_device);
 	platform_device_register(&dm644x_vpss_device);
 	platform_device_register(&dm644x_ccdc_dev);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 60b7a8a..ecf0ba8 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -402,6 +402,21 @@ static struct platform_device dm646x_emac_device = {
 	.resource	= dm646x_emac_resources,
 };
 
+static struct resource dm646x_mdio_resources[] = {
+	{
+		.start	= DM646X_EMAC_MDIO_BASE,
+		.end	= DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device dm646x_mdio_device = {
+	.name		= "davinci_mdio",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(dm646x_mdio_resources),
+	.resource	= dm646x_mdio_resources,
+};
+
 /*
  * Device specific mux setup
  *
@@ -890,6 +905,7 @@ static int __init dm646x_init_devices(void)
 		return 0;
 
 	platform_device_register(&dm646x_edma_device);
+	platform_device_register(&dm646x_mdio_device);
 	platform_device_register(&dm646x_emac_device);
 	return 0;
 }
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index ea5df3b..dbb5052 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -21,6 +21,7 @@
 #include <media/davinci/vpfe_capture.h>
 
 #define DM365_EMAC_BASE			(0x01D07000)
+#define DM365_EMAC_MDIO_BASE		(DM365_EMAC_BASE + 0x4000)
 #define DM365_EMAC_CNTRL_OFFSET		(0x0000)
 #define DM365_EMAC_CNTRL_MOD_OFFSET	(0x3000)
 #define DM365_EMAC_CNTRL_RAM_OFFSET	(0x1000)
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 6fca568..5159117 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -28,6 +28,7 @@
 #include <media/davinci/vpfe_capture.h>
 
 #define DM644X_EMAC_BASE		(0x01C80000)
+#define DM644X_EMAC_MDIO_BASE		(DM644X_EMAC_BASE + 0x4000)
 #define DM644X_EMAC_CNTRL_OFFSET	(0x0000)
 #define DM644X_EMAC_CNTRL_MOD_OFFSET	(0x1000)
 #define DM644X_EMAC_CNTRL_RAM_OFFSET	(0x2000)
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index add6f79..fc2bdd0 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -19,6 +19,7 @@
 #include <linux/davinci_emac.h>
 
 #define DM646X_EMAC_BASE		(0x01C80000)
+#define DM646X_EMAC_MDIO_BASE		(DM646X_EMAC_BASE + 0x4000)
 #define DM646X_EMAC_CNTRL_OFFSET	(0x0000)
 #define DM646X_EMAC_CNTRL_MOD_OFFSET	(0x1000)
 #define DM646X_EMAC_CNTRL_RAM_OFFSET	(0x2000)
-- 
1.7.0.4


From cyril at ti.com  Fri May 14 17:42:24 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 14 May 2010 18:42:24 -0400
Subject: [RFC 1/4] Davinci: mdio - separate out mdio controller code
In-Reply-To: <1273876947-30711-1-git-send-email-cyril@ti.com>
References: <1273876947-30711-1-git-send-email-cyril@ti.com>
Message-ID: <1273876947-30711-2-git-send-email-cyril@ti.com>

Davinci's MDIO controller is present on other TI devices, without an
accompanying EMAC.  For example, on tnetv107x, the same MDIO module is used in
conjunction with a 3-port switch hardware.

By separating the MDIO controller code into its own platform driver, this
patch allows common logic to be reused on such platforms.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 drivers/net/Kconfig        |   10 ++
 drivers/net/Makefile       |    1 +
 drivers/net/davinci_mdio.c |  388 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 399 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/davinci_mdio.c

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 7b832c7..2f27aeb 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -940,6 +940,16 @@ config TI_DAVINCI_EMAC
 	  To compile this driver as a module, choose M here: the module
 	  will be called davinci_emac_driver.  This is recommended.
 
+config TI_DAVINCI_MDIO
+	tristate "TI DaVinci MDIO Support"
+	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 )
+	select PHYLIB
+	help
+	  This driver supports TI's DaVinci MDIO module.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called davinci_mdio.  This is recommended.
+
 config DM9000
 	tristate "DM9000 support"
 	depends on ARM || BLACKFIN || MIPS
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 12b280a..57d45fd 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_MDIO) += mdio.o
 obj-$(CONFIG_PHYLIB) += phy/
 
 obj-$(CONFIG_TI_DAVINCI_EMAC) += davinci_emac.o
+obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o
 
 obj-$(CONFIG_E1000) += e1000/
 obj-$(CONFIG_E1000E) += e1000e/
diff --git a/drivers/net/davinci_mdio.c b/drivers/net/davinci_mdio.c
new file mode 100644
index 0000000..0a2c265
--- /dev/null
+++ b/drivers/net/davinci_mdio.c
@@ -0,0 +1,388 @@
+/*
+ * DaVinci MDIO Module driver
+ *
+ * Copyright (C) 2010 Texas Instruments.
+ *
+ * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
+ *
+ * Copyright (C) 2009 Texas Instruments.
+ *
+ * ---------------------------------------------------------------------------
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ---------------------------------------------------------------------------
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/phy.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#define PHY_REG_MASK		0x1f
+#define PHY_ID_MASK		0x1f
+
+#define MDIO_OUT_FREQ		1100000		/* 2.2 MHz */
+
+struct davinci_mdio_regs {
+	u32	version;
+	u32	control;
+#define CONTROL_IDLE		BIT(31)
+#define CONTROL_ENABLE		BIT(30)
+#define CONTROL_MAX_DIV		(0xff)
+
+	u32	alive;
+	u32	link;
+	u32	linkintraw;
+	u32	linkintmasked;
+	u32	__reserved_0[2];
+	u32	userintraw;
+	u32	userintmasked;
+	u32	userintmaskset;
+	u32	userintmaskclr;
+	u32	__reserved_1[20];
+
+	struct {
+		u32	access;
+#define USERACCESS_GO		BIT(31)
+#define USERACCESS_WRITE	BIT(30)
+#define USERACCESS_ACK		BIT(29)
+#define USERACCESS_READ		(0)
+#define USERACCESS_DATA		(0xffff)
+
+		u32	physel;
+	}	user[0];
+};
+
+struct davinci_mdio_data {
+	struct davinci_mdio_regs __iomem *regs;
+	spinlock_t	lock;
+	struct clk	*clk;
+	struct device	*dev;
+	struct mii_bus	*bus;
+	bool		suspended;
+};
+
+/* wait until hardware is ready for another user access */
+static inline u32 wait_for_user_access(struct davinci_mdio_data *data)
+{
+	struct davinci_mdio_regs __iomem *regs = data->regs;
+	u32 reg;
+
+	while ((reg = __raw_readl(&regs->user[0].access)) & USERACCESS_GO)
+		;
+
+	return reg;
+}
+
+/* wait until hardware state machine is idle */
+static inline void wait_for_idle(struct davinci_mdio_data *data)
+{
+	struct davinci_mdio_regs __iomem *regs = data->regs;
+
+	while ((__raw_readl(&regs->control) & CONTROL_IDLE) == 0)
+		;
+}
+
+static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
+{
+	struct davinci_mdio_data *data = bus->priv;
+	u32 reg;
+
+	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+		return -EINVAL;
+
+	spin_lock(&data->lock);
+
+	if (data->suspended) {
+		spin_unlock(&data->lock);
+		return -ENODEV;
+	}
+
+	wait_for_user_access(data);
+	reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
+	       (phy_id << 16));
+	__raw_writel(reg, &data->regs->user[0].access);
+	reg = wait_for_user_access(data);
+	spin_unlock(&data->lock);
+
+	return (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
+}
+
+static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
+			      int phy_reg, u16 phy_data)
+{
+	struct davinci_mdio_data *data = bus->priv;
+	u32 reg;
+
+	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+		return -EINVAL;
+
+	spin_lock(&data->lock);
+
+	if (data->suspended) {
+		spin_unlock(&data->lock);
+		return -ENODEV;
+	}
+
+	wait_for_user_access(data);
+	reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
+		   (phy_id << 16) | (phy_data & USERACCESS_DATA));
+	__raw_writel(reg, &data->regs->user[0].access);
+	wait_for_user_access(data);
+	spin_unlock(&data->lock);
+
+	return 0;
+}
+
+static inline int count_bits(u32 data)
+{
+	data = ((data & 0xaaaaaaaa) >>  1) + (data & 0x55555555);
+	data = ((data & 0xcccccccc) >>  2) + (data & 0x33333333);
+	data = ((data & 0xf0f0f0f0) >>  4) + (data & 0x0f0f0f0f);
+	data = ((data & 0xff00ff00) >>  8) + (data & 0x00ff00ff);
+	data = ((data & 0xffff0000) >> 16) + (data & 0x0000ffff);
+	return data;
+}
+
+static int __devinit davinci_mdio_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct davinci_mdio_data *data;
+	struct resource *res;
+	u32 mdio_in_freq, mdio_out_freq, div, phy_mask, ver;
+	struct phy_device *phy;
+	int ret, addr;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data) {
+		dev_err(dev, "failed to alloc device data\n");
+		return -ENOMEM;
+	}
+
+	data->bus = mdiobus_alloc();
+	if (!data->bus) {
+		dev_err(dev, "failed to alloc mii bus\n");
+		ret = -ENOMEM;
+		goto bail_out;
+	}
+
+	data->bus->name		= dev_name(dev);
+	data->bus->read		= davinci_mdio_read,
+	data->bus->write	= davinci_mdio_write,
+	data->bus->parent	= dev;
+	data->bus->priv		= data;
+	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
+
+	data->clk = clk_get(dev, NULL);
+	if (IS_ERR(data->clk)) {
+		data->clk = NULL;
+		dev_err(dev, "failed to get device clock\n");
+		ret = PTR_ERR(data->clk);
+		goto bail_out;
+	}
+
+	clk_enable(data->clk);
+
+	dev_set_drvdata(dev, data);
+	data->dev = dev;
+	spin_lock_init(&data->lock);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "could not find register map resource\n");
+		ret = -ENOENT;
+		goto bail_out;
+	}
+
+	res = devm_request_mem_region(dev, res->start, resource_size(res),
+					    dev_name(dev));
+	if (!res) {
+		dev_err(dev, "could not allocate register map resource\n");
+		ret = -ENXIO;
+		goto bail_out;
+	}
+
+	data->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
+	if (!data->regs) {
+		dev_err(dev, "could not map mdio registers\n");
+		ret = -ENOMEM;
+		goto bail_out;
+	}
+
+	mdio_in_freq = clk_get_rate(data->clk);
+	div = (mdio_in_freq / MDIO_OUT_FREQ) - 1;
+	if (div > CONTROL_MAX_DIV)
+		div = CONTROL_MAX_DIV;
+	mdio_out_freq = mdio_in_freq / (div + 1);
+
+	/* set enable and clock divider */
+	__raw_writel(div | CONTROL_ENABLE, &data->regs->control);
+
+	/*
+	 * wait for scan logic to settle:
+	 * the scan time consists of (a) a large fixed component, and (b) a
+	 * small component that varies with the mii bus frequency.  These
+	 * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
+	 * silicon.  Since the effect of (b) was found to be largely
+	 * negligible, we keep things simple here.
+	 */
+	mdelay(1);
+
+	/* dump hardware version info */
+	ver = __raw_readl(&data->regs->version);
+	dev_info(dev, "davinci mdio revision %d.%d\n",
+			(ver >> 8) & 0xff, ver & 0xff);
+
+	/* get phy mask from the alive register */
+	phy_mask = __raw_readl(&data->regs->alive);
+	if (phy_mask) {
+		/* restrict mdio bus to live phys only */
+		dev_info(dev, "detected %d phys (mask %x)\n",
+			 count_bits(phy_mask), ~phy_mask);
+		phy_mask = ~phy_mask;
+	} else {
+		/* desperately scan all phys */
+		dev_warn(dev, "failed to detect live phys, scanning all\n");
+		phy_mask = 0;
+	}
+	data->bus->phy_mask = phy_mask;
+
+	/* register the mii bus */
+	ret = mdiobus_register(data->bus);
+	if (ret)
+		goto bail_out;
+
+	/* scan and dump the bus */
+	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
+		phy = data->bus->phy_map[addr];
+		if (phy) {
+			dev_info(dev, "phy[%d]: device %s, driver %s\n",
+				 phy->addr, dev_name(&phy->dev),
+				 phy->drv ? phy->drv->name : "unknown");
+		}
+	}
+
+	return 0;
+
+bail_out:
+	if (data->bus)
+		mdiobus_free(data->bus);
+
+	if (data->clk) {
+		clk_disable(data->clk);
+		clk_put(data->clk);
+	}
+
+	kfree(data);
+
+	return 0;
+}
+
+static int __devexit davinci_mdio_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct davinci_mdio_data *data = dev_get_drvdata(dev);
+
+	if (data->bus)
+		mdiobus_free(data->bus);
+
+	if (data->clk) {
+		clk_disable(data->clk);
+		clk_put(data->clk);
+	}
+
+	dev_set_drvdata(dev, NULL);
+
+	kfree(data);
+
+	return 0;
+}
+
+static int davinci_mdio_suspend(struct device *dev)
+{
+	struct davinci_mdio_data *data = dev_get_drvdata(dev);
+	u32 ctrl;
+
+	spin_lock(&data->lock);
+
+	/* shutdown the scan state machine */
+	ctrl = __raw_readl(&data->regs->control);
+	ctrl &= ~CONTROL_ENABLE;
+	__raw_writel(ctrl, &data->regs->control);
+	wait_for_idle(data);
+
+	if (data->clk)
+		clk_disable(data->clk);
+
+	data->suspended = true;
+	spin_unlock(&data->lock);
+
+	return 0;
+}
+
+static int davinci_mdio_resume(struct device *dev)
+{
+	struct davinci_mdio_data *data = dev_get_drvdata(dev);
+	u32 ctrl;
+
+	spin_lock(&data->lock);
+	if (data->clk)
+		clk_enable(data->clk);
+
+	/* restart the scan state machine */
+	ctrl = __raw_readl(&data->regs->control);
+	ctrl |= CONTROL_ENABLE;
+	__raw_writel(ctrl, &data->regs->control);
+
+	data->suspended = false;
+	spin_unlock(&data->lock);
+
+	return 0;
+}
+
+static const struct dev_pm_ops davinci_mdio_pm_ops = {
+	.suspend	= davinci_mdio_suspend,
+	.resume		= davinci_mdio_resume,
+};
+
+static struct platform_driver davinci_mdio_driver = {
+	.driver = {
+		.name	 = "davinci_mdio",
+		.owner	 = THIS_MODULE,
+		.pm	 = &davinci_mdio_pm_ops,
+	},
+	.probe = davinci_mdio_probe,
+	.remove = __devexit_p(davinci_mdio_remove),
+};
+
+static int __init davinci_mdio_init(void)
+{
+	return platform_driver_register(&davinci_mdio_driver);
+}
+device_initcall(davinci_mdio_init);
+
+static void __exit davinci_mdio_exit(void)
+{
+	platform_driver_unregister(&davinci_mdio_driver);
+}
+module_exit(davinci_mdio_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("DaVinci MDIO driver");
-- 
1.7.0.4


From cyril at ti.com  Fri May 14 17:42:27 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 14 May 2010 18:42:27 -0400
Subject: [RFC 4/4] Davinci: mdio - switch to new mdio driver
In-Reply-To: <1273876947-30711-1-git-send-email-cyril@ti.com>
References: <1273876947-30711-1-git-send-email-cyril@ti.com>
Message-ID: <1273876947-30711-5-git-send-email-cyril@ti.com>

This patch strips the existing mdio code in the emac driver, and switches over
to the newly separated driver.

With this, the mdio bus frequency is no longer defined board-specific.
Instead, a safe (2.2MHz) frequency is programmed in the mdio driver.  An
mdio platform data can be added in future if there is a real need to customize
frequency.

Further, the phy identification scheme has been modified to use a phy bus id
instead of a mask.  This largely serves to eliminate the "phy search" code in
emac init.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/mach-davinci/board-da830-evm.c     |    5 -
 arch/arm/mach-davinci/board-da850-evm.c     |    6 -
 arch/arm/mach-davinci/board-dm365-evm.c     |    7 -
 arch/arm/mach-davinci/board-dm644x-evm.c    |    7 -
 arch/arm/mach-davinci/board-dm646x-evm.c    |    8 --
 arch/arm/mach-davinci/board-neuros-osd2.c   |    7 -
 arch/arm/mach-davinci/board-sffsdr.c        |    7 -
 arch/arm/mach-davinci/devices-da8xx.c       |    4 +-
 arch/arm/mach-davinci/dm365.c               |    3 +-
 arch/arm/mach-davinci/dm644x.c              |    3 +-
 arch/arm/mach-davinci/dm646x.c              |    3 +-
 arch/arm/mach-davinci/include/mach/dm365.h  |    1 -
 arch/arm/mach-davinci/include/mach/dm644x.h |    1 -
 arch/arm/mach-davinci/include/mach/dm646x.h |    1 -
 drivers/net/Kconfig                         |    1 +
 drivers/net/davinci_emac.c                  |  164 +++++----------------------
 include/linux/davinci_emac.h                |    4 +-
 17 files changed, 34 insertions(+), 198 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 212d970..76e9a9b 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -30,9 +30,6 @@
 #include <mach/da8xx.h>
 #include <mach/usb.h>
 
-#define DA830_EVM_PHY_MASK		0x0
-#define DA830_EVM_MDIO_FREQUENCY	2200000	/* PHY bus frequency */
-
 /*
  * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
  */
@@ -516,8 +513,6 @@ static __init void da830_evm_init(void)
 
 	da830_evm_usb_init();
 
-	soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK;
-	soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
 	soc_info->emac_pdata->rmii_en = 1;
 
 	ret = davinci_cfg_reg_list(da830_cpgmac_pins);
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index abd0493..53dce72 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -33,9 +33,6 @@
 #include <mach/nand.h>
 #include <mach/mux.h>
 
-#define DA850_EVM_PHY_MASK		0x1
-#define DA850_EVM_MDIO_FREQUENCY	2200000 /* PHY bus frequency */
-
 #define DA850_LCD_PWR_PIN		GPIO_TO_PIN(2, 8)
 #define DA850_LCD_BL_PIN		GPIO_TO_PIN(2, 15)
 
@@ -600,9 +597,6 @@ static int __init da850_evm_config_emac(void)
 	/* Enable/Disable MII MDIO clock */
 	gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
 
-	soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK;
-	soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY;
-
 	ret = da8xx_register_emac();
 	if (ret)
 		pr_warning("da850_evm_init: emac registration failed: %d\n",
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 98814e6..e2a5e20 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -54,9 +54,6 @@ static inline int have_tvp7002(void)
 	return 0;
 }
 
-#define DM365_EVM_PHY_MASK		(0x2)
-#define DM365_EVM_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */
-
 /*
  * A MAX-II CPLD is used for various board control functions.
  */
@@ -525,16 +522,12 @@ fail:
 		/* externally mux MMC1/ENET/AIC33 to imager */
 		mux |= BIT(6) | BIT(5) | BIT(3);
 	} else {
-		struct davinci_soc_info *soc_info = &davinci_soc_info;
-
 		/* we can use MMC1 ... */
 		dm365evm_mmc_configure();
 		davinci_setup_mmc(1, &dm365evm_mmc_config);
 
 		/* ... and ENET ... */
 		dm365evm_emac_configure();
-		soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
-		soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
 		resets &= ~BIT(3);
 
 		/* ... and AIC33 */
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 34c8b41..9e8193e 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -38,9 +38,6 @@
 #include <mach/mmc.h>
 #include <mach/usb.h>
 
-#define DM644X_EVM_PHY_MASK		(0x2)
-#define DM644X_EVM_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */
-
 #define LXT971_PHY_ID	(0x001378e2)
 #define LXT971_PHY_MASK	(0xfffffff0)
 
@@ -660,7 +657,6 @@ static int davinci_phy_fixup(struct phy_device *phydev)
 static __init void davinci_evm_init(void)
 {
 	struct clk *aemif_clk;
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
 
 	aemif_clk = clk_get(NULL, "aemif");
 	clk_enable(aemif_clk);
@@ -695,9 +691,6 @@ static __init void davinci_evm_init(void)
 	davinci_serial_init(&uart_config);
 	dm644x_init_asp(&dm644x_evm_snd_data);
 
-	soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK;
-	soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY;
-
 	/* Register the fixup for PHY on DaVinci */
 	phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
 					davinci_phy_fixup);
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 6d88893..a3ce716 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -718,13 +718,8 @@ static struct davinci_uart_config uart_config __initdata = {
 	.enabled_uarts = (1 << 0),
 };
 
-#define DM646X_EVM_PHY_MASK		(0x2)
-#define DM646X_EVM_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */
-
 static __init void evm_init(void)
 {
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
-
 	evm_init_i2c();
 	davinci_serial_init(&uart_config);
 	dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
@@ -734,9 +729,6 @@ static __init void evm_init(void)
 
 	if (HAS_ATA)
 		davinci_init_ide();
-
-	soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
-	soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
 }
 
 #define DM646X_EVM_REF_FREQ		27000000
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 4c30e92..4b32f0a 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -39,9 +39,6 @@
 #include <mach/mmc.h>
 #include <mach/usb.h>
 
-#define NEUROS_OSD2_PHY_MASK		0x2
-#define NEUROS_OSD2_MDIO_FREQUENCY	2200000 /* PHY bus frequency */
-
 #define LXT971_PHY_ID			0x001378e2
 #define LXT971_PHY_MASK			0xfffffff0
 
@@ -218,7 +215,6 @@ static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
 static __init void davinci_ntosd2_init(void)
 {
 	struct clk *aemif_clk;
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	int	status;
 
 	aemif_clk = clk_get(NULL, "aemif");
@@ -252,9 +248,6 @@ static __init void davinci_ntosd2_init(void)
 	davinci_serial_init(&uart_config);
 	dm644x_init_asp(&dm644x_ntosd2_snd_data);
 
-	soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK;
-	soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;
-
 	davinci_setup_usb(1000, 8);
 	/*
 	 * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 23e664a..b372d7f 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -42,9 +42,6 @@
 #include <mach/mux.h>
 #include <mach/usb.h>
 
-#define SFFSDR_PHY_MASK		(0x2)
-#define SFFSDR_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */
-
 static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
 	/* U-Boot Environment: Block 0
 	 * UBL:                Block 1
@@ -137,14 +134,10 @@ static void __init davinci_sffsdr_map_io(void)
 
 static __init void davinci_sffsdr_init(void)
 {
-	struct davinci_soc_info *soc_info = &davinci_soc_info;
-
 	platform_add_devices(davinci_sffsdr_devices,
 			     ARRAY_SIZE(davinci_sffsdr_devices));
 	sffsdr_init_i2c();
 	davinci_serial_init(&uart_config);
-	soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK;
-	soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY;
 	davinci_setup_usb(0, 0); /* We support only peripheral mode. */
 
 	/* mux VLYNQ pins */
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 0a1e7d4..ebd5518 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -41,7 +41,6 @@
 #define DA8XX_EMAC_CTRL_REG_OFFSET	0x3000
 #define DA8XX_EMAC_MOD_REG_OFFSET	0x2000
 #define DA8XX_EMAC_RAM_OFFSET		0x0000
-#define DA8XX_MDIO_REG_OFFSET		0x4000
 #define DA8XX_EMAC_CTRL_RAM_SIZE	SZ_8K
 
 void __iomem *da8xx_syscfg0_base;
@@ -341,7 +340,7 @@ int __init da8xx_register_watchdog(void)
 static struct resource da8xx_emac_resources[] = {
 	{
 		.start	= DA8XX_EMAC_CPPI_PORT_BASE,
-		.end	= DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
+		.end	= DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
@@ -370,7 +369,6 @@ struct emac_platform_data da8xx_emac_pdata = {
 	.ctrl_reg_offset	= DA8XX_EMAC_CTRL_REG_OFFSET,
 	.ctrl_mod_reg_offset	= DA8XX_EMAC_MOD_REG_OFFSET,
 	.ctrl_ram_offset	= DA8XX_EMAC_RAM_OFFSET,
-	.mdio_reg_offset	= DA8XX_MDIO_REG_OFFSET,
 	.ctrl_ram_size		= DA8XX_EMAC_CTRL_RAM_SIZE,
 	.version		= EMAC_VERSION_2,
 };
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 685116f..578111c 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -682,7 +682,6 @@ static struct emac_platform_data dm365_emac_pdata = {
 	.ctrl_reg_offset	= DM365_EMAC_CNTRL_OFFSET,
 	.ctrl_mod_reg_offset	= DM365_EMAC_CNTRL_MOD_OFFSET,
 	.ctrl_ram_offset	= DM365_EMAC_CNTRL_RAM_OFFSET,
-	.mdio_reg_offset	= DM365_EMAC_MDIO_OFFSET,
 	.ctrl_ram_size		= DM365_EMAC_CNTRL_RAM_SIZE,
 	.version		= EMAC_VERSION_2,
 };
@@ -690,7 +689,7 @@ static struct emac_platform_data dm365_emac_pdata = {
 static struct resource dm365_emac_resources[] = {
 	{
 		.start	= DM365_EMAC_BASE,
-		.end	= DM365_EMAC_BASE + 0x47ff,
+		.end	= DM365_EMAC_BASE + SZ_16K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 8d08047..6720d20 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -323,7 +323,6 @@ static struct emac_platform_data dm644x_emac_pdata = {
 	.ctrl_reg_offset	= DM644X_EMAC_CNTRL_OFFSET,
 	.ctrl_mod_reg_offset	= DM644X_EMAC_CNTRL_MOD_OFFSET,
 	.ctrl_ram_offset	= DM644X_EMAC_CNTRL_RAM_OFFSET,
-	.mdio_reg_offset	= DM644X_EMAC_MDIO_OFFSET,
 	.ctrl_ram_size		= DM644X_EMAC_CNTRL_RAM_SIZE,
 	.version		= EMAC_VERSION_1,
 };
@@ -331,7 +330,7 @@ static struct emac_platform_data dm644x_emac_pdata = {
 static struct resource dm644x_emac_resources[] = {
 	{
 		.start	= DM644X_EMAC_BASE,
-		.end	= DM644X_EMAC_BASE + 0x47ff,
+		.end	= DM644X_EMAC_BASE + SZ_16K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index ecf0ba8..b42c1f0 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -359,7 +359,6 @@ static struct emac_platform_data dm646x_emac_pdata = {
 	.ctrl_reg_offset	= DM646X_EMAC_CNTRL_OFFSET,
 	.ctrl_mod_reg_offset	= DM646X_EMAC_CNTRL_MOD_OFFSET,
 	.ctrl_ram_offset	= DM646X_EMAC_CNTRL_RAM_OFFSET,
-	.mdio_reg_offset	= DM646X_EMAC_MDIO_OFFSET,
 	.ctrl_ram_size		= DM646X_EMAC_CNTRL_RAM_SIZE,
 	.version		= EMAC_VERSION_2,
 };
@@ -367,7 +366,7 @@ static struct emac_platform_data dm646x_emac_pdata = {
 static struct resource dm646x_emac_resources[] = {
 	{
 		.start	= DM646X_EMAC_BASE,
-		.end	= DM646X_EMAC_BASE + 0x47ff,
+		.end	= DM646X_EMAC_BASE + SZ_16K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	{
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index dbb5052..2563bf4 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -25,7 +25,6 @@
 #define DM365_EMAC_CNTRL_OFFSET		(0x0000)
 #define DM365_EMAC_CNTRL_MOD_OFFSET	(0x3000)
 #define DM365_EMAC_CNTRL_RAM_OFFSET	(0x1000)
-#define DM365_EMAC_MDIO_OFFSET		(0x4000)
 #define DM365_EMAC_CNTRL_RAM_SIZE	(0x2000)
 
 /* Base of key scan register bank */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 5159117..5a1b26d 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -32,7 +32,6 @@
 #define DM644X_EMAC_CNTRL_OFFSET	(0x0000)
 #define DM644X_EMAC_CNTRL_MOD_OFFSET	(0x1000)
 #define DM644X_EMAC_CNTRL_RAM_OFFSET	(0x2000)
-#define DM644X_EMAC_MDIO_OFFSET		(0x4000)
 #define DM644X_EMAC_CNTRL_RAM_SIZE	(0x2000)
 
 #define DM644X_ASYNC_EMIF_CONTROL_BASE	0x01E00000
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index fc2bdd0..38e54c6 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -23,7 +23,6 @@
 #define DM646X_EMAC_CNTRL_OFFSET	(0x0000)
 #define DM646X_EMAC_CNTRL_MOD_OFFSET	(0x1000)
 #define DM646X_EMAC_CNTRL_RAM_OFFSET	(0x2000)
-#define DM646X_EMAC_MDIO_OFFSET		(0x4000)
 #define DM646X_EMAC_CNTRL_RAM_SIZE	(0x2000)
 
 #define DM646X_ASYNC_EMIF_CONTROL_BASE	0x20008000
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 2f27aeb..9bee1e6 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -933,6 +933,7 @@ config NET_NETX
 config TI_DAVINCI_EMAC
 	tristate "TI DaVinci EMAC Support"
 	depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 )
+	select TI_DAVINCI_MDIO
 	select PHYLIB
 	help
 	  This driver supports TI's DaVinci Ethernet .
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 2b8edd2..c311b60 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -479,9 +479,7 @@ struct emac_priv {
 	struct timer_list periodic_timer;
 	u32 periodic_ticks;
 	u32 timer_active;
-	u32 phy_mask;
-	/* mii_bus,phy members */
-	struct mii_bus *mii_bus;
+	const char *phy_id;
 	struct phy_device *phydev;
 	spinlock_t lock;
 	/*platform specific members*/
@@ -492,7 +490,6 @@ struct emac_priv {
 /* clock frequency for EMAC */
 static struct clk *emac_clk;
 static unsigned long emac_bus_frequency;
-static unsigned long mdio_max_freq;
 
 #define emac_virt_to_phys(addr, priv) \
 	(((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \
@@ -530,9 +527,6 @@ static char *emac_rxhost_errcodes[16] = {
 #define emac_ctrl_read(reg)	  ioread32((priv->ctrl_base + (reg)))
 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
 
-#define emac_mdio_read(reg)	  ioread32(bus->priv + (reg))
-#define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg)))
-
 /**
  * emac_dump_regs: Dump important EMAC registers to debug terminal
  * @priv: The DaVinci EMAC private adapter structure
@@ -666,7 +660,7 @@ static int emac_get_settings(struct net_device *ndev,
 			     struct ethtool_cmd *ecmd)
 {
 	struct emac_priv *priv = netdev_priv(ndev);
-	if (priv->phy_mask)
+	if (priv->phydev)
 		return phy_ethtool_gset(priv->phydev, ecmd);
 	else
 		return -EOPNOTSUPP;
@@ -684,7 +678,7 @@ static int emac_get_settings(struct net_device *ndev,
 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
 {
 	struct emac_priv *priv = netdev_priv(ndev);
-	if (priv->phy_mask)
+	if (priv->phydev)
 		return phy_ethtool_sset(priv->phydev, ecmd);
 	else
 		return -EOPNOTSUPP;
@@ -722,7 +716,7 @@ static void emac_update_phystatus(struct emac_priv *priv)
 	mac_control = emac_read(EMAC_MACCONTROL);
 	cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
 			DUPLEX_FULL : DUPLEX_HALF;
-	if (priv->phy_mask)
+	if (priv->phydev)
 		new_duplex = priv->phydev->duplex;
 	else
 		new_duplex = DUPLEX_FULL;
@@ -2233,79 +2227,6 @@ void emac_poll_controller(struct net_device *ndev)
 }
 #endif
 
-/* PHY/MII bus related */
-
-/* Wait until mdio is ready for next command */
-#define MDIO_WAIT_FOR_USER_ACCESS\
-		while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
-			MDIO_USERACCESS_GO) != 0)
-
-static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg)
-{
-	unsigned int phy_data = 0;
-	unsigned int phy_control;
-
-	/* Wait until mdio is ready for next command */
-	MDIO_WAIT_FOR_USER_ACCESS;
-
-	phy_control = (MDIO_USERACCESS_GO |
-		       MDIO_USERACCESS_READ |
-		       ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
-		       ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
-		       (phy_data & MDIO_USERACCESS_DATA));
-	emac_mdio_write(MDIO_USERACCESS(0), phy_control);
-
-	/* Wait until mdio is ready for next command */
-	MDIO_WAIT_FOR_USER_ACCESS;
-
-	return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
-
-}
-
-static int emac_mii_write(struct mii_bus *bus, int phy_id,
-			  int phy_reg, u16 phy_data)
-{
-
-	unsigned int control;
-
-	/*  until mdio is ready for next command */
-	MDIO_WAIT_FOR_USER_ACCESS;
-
-	control = (MDIO_USERACCESS_GO |
-		   MDIO_USERACCESS_WRITE |
-		   ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
-		   ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
-		   (phy_data & MDIO_USERACCESS_DATA));
-	emac_mdio_write(MDIO_USERACCESS(0), control);
-
-	return 0;
-}
-
-static int emac_mii_reset(struct mii_bus *bus)
-{
-	unsigned int clk_div;
-	int mdio_bus_freq = emac_bus_frequency;
-
-	if (mdio_max_freq && mdio_bus_freq)
-		clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
-	else
-		clk_div = 0xFF;
-
-	clk_div &= MDIO_CONTROL_CLKDIV;
-
-	/* Set enable and clock divider in MDIOControl */
-	emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
-
-	return 0;
-
-}
-
-static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL };
-
-/* emac_driver: EMAC MII bus structure */
-
-static struct mii_bus *emac_mii;
-
 static void emac_adjust_link(struct net_device *ndev)
 {
 	struct emac_priv *priv = netdev_priv(ndev);
@@ -2370,6 +2291,11 @@ static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
 	return -EOPNOTSUPP;
 }
 
+static int match_first_device(struct device *dev, void *data)
+{
+	return 1;
+}
+
 /**
  * emac_dev_open: EMAC device open
  * @ndev: The DaVinci EMAC network adapter
@@ -2384,7 +2310,6 @@ static int emac_dev_open(struct net_device *ndev)
 {
 	struct device *emac_dev = &ndev->dev;
 	u32 rc, cnt, ch;
-	int phy_addr;
 	struct resource *res;
 	int q, m;
 	int i = 0;
@@ -2437,28 +2362,27 @@ static int emac_dev_open(struct net_device *ndev)
 	/* Start/Enable EMAC hardware */
 	emac_hw_enable(priv);
 
-	/* find the first phy */
 	priv->phydev = NULL;
-	if (priv->phy_mask) {
-		emac_mii_reset(priv->mii_bus);
-		for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
-			if (priv->mii_bus->phy_map[phy_addr]) {
-				priv->phydev = priv->mii_bus->phy_map[phy_addr];
-				break;
-			}
-		}
 
-		if (!priv->phydev) {
-			printk(KERN_ERR "%s: no PHY found\n", ndev->name);
-			return -1;
-		}
+	/* use the first phy on the bus if pdata did not give us a phy id */
+	if (!priv->phy_id) {
+		struct device *phy;
 
-		priv->phydev = phy_connect(ndev, dev_name(&priv->phydev->dev),
-				&emac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
+		phy = bus_find_device(&mdio_bus_type, NULL, NULL,
+				      match_first_device);
+		if (phy)
+			priv->phy_id = dev_name(phy);
+	}
+
+	if (priv->phy_id) {
+		priv->phydev = phy_connect(ndev, priv->phy_id,
+					   &emac_adjust_link, 0,
+					   PHY_INTERFACE_MODE_MII);
 
 		if (IS_ERR(priv->phydev)) {
-			printk(KERN_ERR "%s: Could not attach to PHY\n",
-								ndev->name);
+			dev_err(emac_dev, "could not connect to phy %s\n",
+				priv->phy_id);
+			priv->phydev = NULL;
 			return PTR_ERR(priv->phydev);
 		}
 
@@ -2470,7 +2394,7 @@ static int emac_dev_open(struct net_device *ndev)
 			"(mii_bus:phy_addr=%s, id=%x)\n", ndev->name,
 			priv->phydev->drv->name, dev_name(&priv->phydev->dev),
 			priv->phydev->phy_id);
-	} else{
+	} else {
 		/* No PHY , fix the link, speed and duplex settings */
 		priv->link = 1;
 		priv->speed = SPEED_100;
@@ -2484,7 +2408,7 @@ static int emac_dev_open(struct net_device *ndev)
 	if (netif_msg_drv(priv))
 		dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
 
-	if (priv->phy_mask)
+	if (priv->phydev)
 		phy_start(priv->phydev);
 
 	return 0;
@@ -2671,7 +2595,7 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
 
 	/* MAC addr and PHY mask , RMII enable info from platform_data */
 	memcpy(priv->mac_addr, pdata->mac_addr, 6);
-	priv->phy_mask = pdata->phy_mask;
+	priv->phy_id = pdata->phy_id;
 	priv->rmii_en = pdata->rmii_en;
 	priv->version = pdata->version;
 	priv->int_enable = pdata->interrupt_enable;
@@ -2745,32 +2669,6 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
 	}
 
 
-	/* MII/Phy intialisation, mdio bus registration */
-	emac_mii = mdiobus_alloc();
-	if (emac_mii == NULL) {
-		dev_err(emac_dev, "DaVinci EMAC: Error allocating mii_bus\n");
-		rc = -ENOMEM;
-		goto mdio_alloc_err;
-	}
-
-	priv->mii_bus = emac_mii;
-	emac_mii->name  = "emac-mii",
-	emac_mii->read  = emac_mii_read,
-	emac_mii->write = emac_mii_write,
-	emac_mii->reset = emac_mii_reset,
-	emac_mii->irq   = mii_irqs,
-	emac_mii->phy_mask = ~(priv->phy_mask);
-	emac_mii->parent = &pdev->dev;
-	emac_mii->priv = priv->remap_addr + pdata->mdio_reg_offset;
-	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", priv->pdev->id);
-	mdio_max_freq = pdata->mdio_max_freq;
-	emac_mii->reset(emac_mii);
-
-	/* Register the MII bus */
-	rc = mdiobus_register(emac_mii);
-	if (rc)
-		goto mdiobus_quit;
-
 	if (netif_msg_probe(priv)) {
 		dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
 			   "(regs: %p, irq: %d)\n",
@@ -2778,11 +2676,7 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
 	}
 	return 0;
 
-mdiobus_quit:
-	mdiobus_free(emac_mii);
-
 netdev_reg_err:
-mdio_alloc_err:
 	clk_disable(emac_clk);
 no_irq_res:
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -2812,8 +2706,6 @@ static int __devexit davinci_emac_remove(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, NULL);
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	mdiobus_unregister(priv->mii_bus);
-	mdiobus_free(priv->mii_bus);
 
 	release_mem_region(res->start, res->end - res->start + 1);
 
diff --git a/include/linux/davinci_emac.h b/include/linux/davinci_emac.h
index 7c930db..ff801eb 100644
--- a/include/linux/davinci_emac.h
+++ b/include/linux/davinci_emac.h
@@ -20,10 +20,8 @@ struct emac_platform_data {
 	u32 ctrl_mod_reg_offset;
 	u32 ctrl_ram_offset;
 	u32 hw_ram_addr;
-	u32 mdio_reg_offset;
 	u32 ctrl_ram_size;
-	u32 phy_mask;
-	u32 mdio_max_freq;
+	const char *phy_id;
 	u8 rmii_en;
 	u8 version;
 	void (*interrupt_enable) (void);
-- 
1.7.0.4


From khilman at deeprootsystems.com  Fri May 14 18:00:17 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Fri, 14 May 2010 16:00:17 -0700
Subject: [PATCH] DA830: fix USB 2.0 clock entry
In-Reply-To: <87aas2jq4u.fsf@deeprootsystems.com> (Kevin Hilman's message of
	"Fri\, 14 May 2010 11\:26\:57 -0700")
References: <201005132251.51518.sshtylyov@ru.mvista.com>
	<4BEC4C6C.8000004@mvista.com> <87sk5ur062.fsf@deeprootsystems.com>
	<4BED83B5.9030005@mvista.com> <87aas2jq4u.fsf@deeprootsystems.com>
Message-ID: <878w7m9ji6.fsf@deeprootsystems.com>

Kevin Hilman <khilman at deeprootsystems.com> writes:

> Sergei Shtylyov <sshtylyov at mvista.com> writes:

>>>>   Kevin, could we squeeze it into 2.6.34?

Done.  Linus merged my pull request already. :)

Also pushed an updated davinci git master with this merged.

Kevin

From sshtylyov at mvista.com  Fri May 14 18:02:39 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Sat, 15 May 2010 03:02:39 +0400
Subject: [PATCH] DA830: fix USB 2.0 clock entry
In-Reply-To: <878w7m9ji6.fsf@deeprootsystems.com>
References: <201005132251.51518.sshtylyov@ru.mvista.com>	<4BEC4C6C.8000004@mvista.com>
	<87sk5ur062.fsf@deeprootsystems.com>	<4BED83B5.9030005@mvista.com>
	<87aas2jq4u.fsf@deeprootsystems.com>
	<878w7m9ji6.fsf@deeprootsystems.com>
Message-ID: <4BEDD68F.6050203@mvista.com>

Kevin Hilman wrote:

>> Sergei Shtylyov <sshtylyov at mvista.com> writes:

>>>>>   Kevin, could we squeeze it into 2.6.34?

> Done.  Linus merged my pull request already. :)

    Yeah, I've noticed. :-)

> Also pushed an updated davinci git master with this merged.

    Thanks!

> Kevin

WBR, Sergei

From jaya.krishnan at samsung.com  Sat May 15 04:59:48 2010
From: jaya.krishnan at samsung.com (Jaya krishnan)
Date: Sat, 15 May 2010 09:59:48 +0000 (GMT)
Subject: CDCE949 programming
Message-ID: <17475750.67021273917588623.JavaMail.weblogic@epml07>

Hi
         I want  to use cdce949  clock  synthesizer  to generate  high frequency  clocks to be  used  as  master  clock  for a DAC  chip.
I used TI  clock pro  software  (as local)  to generate the Hex  file and this Hex  file (which contain register values) is  used in a linux module 
to control the PLLs. The problem is , the new  register  values  are not getting loaded into the  internal EEPROM. Does  anybody have any clues?
Regards
JK

    
    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  

From sshtylyov at ru.mvista.com  Sat May 15 13:14:53 2010
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Sat, 15 May 2010 22:14:53 +0400
Subject: [PATCH v5 1/3] ARM: add CPPI 4.1 DMA support
Message-ID: <201005152214.53993.sshtylyov@ru.mvista.com>

Add support for Texas Instuments Communication Port Programming Interface 4.1
(CPPI 4.1) used on OMAP-L1x/DA8xx and AM35x.

At this moment, only the DMA controller and queue manager are supported.
Support for the buffer manager is lacking but these chips don't have it anyway.

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
Signed-off-by: Sekhar Nori <nsekhar at ti.com>

---
Changes since the previous version:
- moved everything from arch/arm/mach-davinci/ to arch/arm/common/;
- s/CONFIG_CPPI41/CONFIG_TI_CPPI41/, made that option invisible;
- added #include <linux/slab.h> for kzalloc();
- switched alloc_queue() and cppi41_queue_free() to using bit operations;
- replaced 'static' linking_ram[] by local variable in cppi41_queue_mgr_init();
- fixed pr_debug() in cppi41_dma_ctrlr_init() to print the real queue manager #.

 arch/arm/common/Kconfig                |    3 
 arch/arm/common/Makefile               |    1 
 arch/arm/common/cppi41.c               |  759 +++++++++++++++++++++++++++++++++
 arch/arm/include/asm/hardware/cppi41.h |  718 +++++++++++++++++++++++++++++++
 4 files changed, 1481 insertions(+)

Index: linux-davinci/arch/arm/common/Kconfig
===================================================================
--- linux-davinci.orig/arch/arm/common/Kconfig
+++ linux-davinci/arch/arm/common/Kconfig
@@ -38,5 +38,8 @@ config SHARP_PARAM
 config SHARP_SCOOP
 	bool
 
+config TI_CPPI41
+	bool
+
 config COMMON_CLKDEV
 	bool
Index: linux-davinci/arch/arm/common/Makefile
===================================================================
--- linux-davinci.orig/arch/arm/common/Makefile
+++ linux-davinci/arch/arm/common/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_TIMER_ACORN)	+= time-acorn.
 obj-$(CONFIG_SHARP_LOCOMO)	+= locomo.o
 obj-$(CONFIG_SHARP_PARAM)	+= sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o
+obj-$(CONFIG_TI_CPPI41) 	+= cppi41.o
 obj-$(CONFIG_ARCH_IXP2000)	+= uengine.o
 obj-$(CONFIG_ARCH_IXP23XX)	+= uengine.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
Index: linux-davinci/arch/arm/common/cppi41.c
===================================================================
--- /dev/null
+++ linux-davinci/arch/arm/common/cppi41.c
@@ -0,0 +1,759 @@
+/*
+ * CPPI 4.1 support
+ *
+ * Copyright (C) 2008-2010 MontaVista Software, Inc. <source at mvista.com>
+ *
+ * Based on the PAL CPPI 4.1 implementation
+ * Copyright (C) 2007, Texas Instruments Inc. http://www.ti.com/
+ *
+ * This file contains the main implementation for CPPI 4.1 common peripherals,
+ * including the DMA Controllers and the Queue Managers.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+
+#undef	DEBUG
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/hardware/cppi41.h>
+
+static unsigned long *allocated_queues[CPPI41_NUM_QUEUE_MGR];
+
+/* First 32 packet descriptors are reserved for unallocated memory regions. */
+static u32 next_desc_index[CPPI41_NUM_QUEUE_MGR] = { 1 << 5 };
+static u8  next_mem_rgn[CPPI41_NUM_QUEUE_MGR];
+
+static struct {
+	size_t rgn_size;
+	void *virt_addr;
+	dma_addr_t phys_addr;
+	struct cppi41_queue_obj queue_obj;
+	u8 mem_rgn;
+} dma_teardown[CPPI41_NUM_DMA_BLOCK];
+
+/******************** CPPI 4.1 Functions (External Interface) *****************/
+
+int __init cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size)
+{
+	static struct {
+		void *virt_addr;
+		dma_addr_t phys_addr;
+	} linking_ram;
+	void __iomem *q_mgr_regs;
+	void *ptr;
+
+	if (q_mgr >= cppi41_num_queue_mgr)
+		return -EINVAL;
+
+	q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
+
+	__raw_writel(rgn0_base, q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG);
+	pr_debug("Linking RAM region 0 base @ %p, value: %x\n",
+		 q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG,
+		 __raw_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG));
+
+	__raw_writel(rgn0_size, q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG);
+	pr_debug("Linking RAM region 0 size @ %p, value: %x\n",
+		 q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG,
+		 __raw_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG));
+
+	ptr = dma_alloc_coherent(NULL, 0x10000 - rgn0_size * 4,
+				 &linking_ram.phys_addr, GFP_KERNEL | GFP_DMA);
+	if (ptr == NULL) {
+		pr_err("ERROR: %s: Unable to allocate linking RAM.\n",
+		       __func__);
+		return -ENOMEM;
+	}
+	linking_ram.virt_addr = ptr;
+
+	__raw_writel(linking_ram.phys_addr,
+		     q_mgr_regs + QMGR_LINKING_RAM_RGN1_BASE_REG);
+	pr_debug("Linking RAM region 1 base @ %p, value: %x\n",
+		 q_mgr_regs + QMGR_LINKING_RAM_RGN1_BASE_REG,
+		 __raw_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN1_BASE_REG));
+
+	ptr = kzalloc(BITS_TO_LONGS(cppi41_queue_mgr[q_mgr].num_queue),
+		      GFP_KERNEL);
+	if (ptr == NULL) {
+		pr_err("ERROR: %s: Unable to allocate queue bitmap.\n",
+		       __func__);
+		dma_free_coherent(NULL, 0x10000 - rgn0_size * 4,
+				  linking_ram.virt_addr, linking_ram.phys_addr);
+		return -ENOMEM;
+	}
+	allocated_queues[q_mgr] = ptr;
+
+	return 0;
+}
+
+int __init cppi41_dma_ctrlr_init(u8 dma_num, u8 q_mgr, u8 num_order)
+{
+	const struct cppi41_dma_block *dma_block;
+	struct cppi41_teardown_desc *curr_td;
+	unsigned num_desc = 1 << num_order;
+	dma_addr_t td_addr;
+	void *ptr;
+	int error, i;
+	u16 q_num;
+
+	if (dma_num >= cppi41_num_dma_block ||
+	    q_mgr >= cppi41_num_queue_mgr)
+		return -EINVAL;
+
+	error = cppi41_queue_alloc(CPPI41_FREE_DESC_QUEUE |
+				   CPPI41_UNASSIGNED_QUEUE, q_mgr, &q_num);
+	if (error) {
+		pr_err("ERROR: %s: Unable to allocate teardown descriptor "
+		       "queue.\n", __func__);
+		return error;
+	}
+	pr_debug("Teardown descriptor queue %d in queue manager %d allocated\n",
+		 q_num, q_mgr);
+
+	/*
+	 * Tell the hardware about the Teardown descriptor
+	 * queue manager and queue number.
+	 */
+	dma_block = &cppi41_dma_block[dma_num];
+	__raw_writel((q_mgr << DMA_TD_DESC_QMGR_SHIFT) |
+		     (q_num << DMA_TD_DESC_QNUM_SHIFT),
+		     dma_block->global_ctrl_base +
+		     DMA_TEARDOWN_FREE_DESC_CTRL_REG);
+	pr_debug("Teardown free descriptor control @ %p, value: %x\n",
+		 dma_block->global_ctrl_base + DMA_TEARDOWN_FREE_DESC_CTRL_REG,
+		 __raw_readl(dma_block->global_ctrl_base +
+			     DMA_TEARDOWN_FREE_DESC_CTRL_REG));
+
+	dma_teardown[dma_num].rgn_size = num_desc *
+					 sizeof(struct cppi41_teardown_desc);
+
+	/* Pre-allocate teardown descriptors. */
+	ptr = dma_alloc_coherent(NULL, dma_teardown[dma_num].rgn_size,
+				 &dma_teardown[dma_num].phys_addr,
+				 GFP_KERNEL | GFP_DMA);
+	if (ptr == NULL) {
+		pr_err("ERROR: %s: Unable to allocate teardown descriptors.\n",
+		       __func__);
+		error = -ENOMEM;
+		goto free_queue;
+	}
+	dma_teardown[dma_num].virt_addr = ptr;
+
+	error = cppi41_mem_rgn_alloc(q_mgr, dma_teardown[dma_num].phys_addr, 5,
+				     num_order, &dma_teardown[dma_num].mem_rgn);
+	if (error) {
+		pr_err("ERROR: %s: Unable to allocate queue manager memory "
+		       "region for teardown descriptors.\n", __func__);
+		goto free_mem;
+	}
+
+	error = cppi41_queue_init(&dma_teardown[dma_num].queue_obj, 0, q_num);
+	if (error) {
+		pr_err("ERROR: %s: Unable to initialize teardown free "
+		       "descriptor queue.\n", __func__);
+		goto free_rgn;
+	}
+
+	/*
+	 * Push all teardown descriptors to the free teardown queue
+	 * for the CPPI 4.1 system.
+	 */
+	curr_td = dma_teardown[dma_num].virt_addr;
+	td_addr = dma_teardown[dma_num].phys_addr;
+
+	for (i = 0; i < num_desc; i++) {
+		cppi41_queue_push(&dma_teardown[dma_num].queue_obj, td_addr,
+				  sizeof(*curr_td), 0);
+		td_addr += sizeof(*curr_td);
+	}
+
+free_rgn:
+	cppi41_mem_rgn_free(q_mgr, dma_teardown[dma_num].mem_rgn);
+free_mem:
+	dma_free_coherent(NULL, dma_teardown[dma_num].rgn_size,
+			  dma_teardown[dma_num].virt_addr,
+			  dma_teardown[dma_num].phys_addr);
+free_queue:
+	cppi41_queue_free(q_mgr, q_num);
+	return error;
+}
+
+int __init cppi41_dma_sched_init(u8 dma_num, const u8 *sched_tbl, u16 tbl_size)
+{
+	const struct cppi41_dma_block *dma_block;
+	unsigned num_reg;
+	int i, j, k;
+	u32 val;
+
+	if (dma_num >= cppi41_num_dma_block ||
+	    !tbl_size || tbl_size > 0x100 || sched_tbl == NULL)
+		return -EINVAL;
+
+	/* Initialize the DMA scheduler. */
+	dma_block = &cppi41_dma_block[dma_num];
+	num_reg = (tbl_size + 3) / 4;
+	for (k = i = 0; i < num_reg; i++) {
+		for (val = j = 0; j < 4; j++, k++) {
+			val >>= 8;
+			if (k < tbl_size)
+				val |= sched_tbl[k] << 24;
+		}
+
+		__raw_writel(val, dma_block->sched_table_base +
+			     DMA_SCHED_TABLE_WORD_REG(i));
+		pr_debug("DMA scheduler table @ %p, value written: %x\n",
+			 dma_block->sched_table_base +
+			 DMA_SCHED_TABLE_WORD_REG(i), val);
+	}
+
+	__raw_writel((tbl_size - 1) << DMA_SCHED_LAST_ENTRY_SHIFT |
+		     DMA_SCHED_ENABLE_MASK,
+		     dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG);
+	pr_debug("DMA scheduler control @ %p, value: %x\n",
+		 dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG,
+		 __raw_readl(dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG));
+
+	return 0;
+}
+
+/*
+ * cppi41_mem_rgn_alloc - allocate a memory region within the queue manager
+ */
+int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
+			 u8 num_order, u8 *mem_rgn)
+{
+	void __iomem *desc_mem_regs;
+	u32 num_desc = 1 << num_order, index, ctrl;
+	int rgn;
+
+	pr_debug("%s called with rgn_addr = %08x, size_order = %d, "
+		 "num_order = %d\n", __func__, rgn_addr, size_order, num_order);
+
+	if (q_mgr >= cppi41_num_queue_mgr ||
+	    size_order < 5 || size_order > 13 ||
+	    num_order  < 5 || num_order  > 12 ||
+	    (rgn_addr & ((1 << size_order) - 1)))
+		return -EINVAL;
+
+	rgn = next_mem_rgn[q_mgr];
+	index = next_desc_index[q_mgr];
+	if (rgn >= CPPI41_MAX_MEM_RGN || index + num_desc > 0x4000)
+		return -ENOSPC;
+
+	next_mem_rgn[q_mgr] = rgn + 1;
+	next_desc_index[q_mgr] = index + num_desc;
+
+	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
+
+	/* Write the base register */
+	__raw_writel(rgn_addr, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn));
+	pr_debug("Descriptor region base @ %p, value: %x\n",
+		 desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn),
+		 __raw_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn)));
+
+	/* Write the control register */
+	ctrl = ((index << QMGR_MEM_RGN_INDEX_SHIFT) &
+		QMGR_MEM_RGN_INDEX_MASK) |
+	       (((size_order - 5) << QMGR_MEM_RGN_DESC_SIZE_SHIFT) &
+		QMGR_MEM_RGN_DESC_SIZE_MASK) |
+	       (((num_order - 5) << QMGR_MEM_RGN_SIZE_SHIFT) &
+		QMGR_MEM_RGN_SIZE_MASK);
+	__raw_writel(ctrl, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn));
+	pr_debug("Descriptor region control @ %p, value: %x\n",
+		 desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn),
+		 __raw_readl(desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn)));
+
+	*mem_rgn = rgn;
+	return 0;
+}
+EXPORT_SYMBOL(cppi41_mem_rgn_alloc);
+
+/*
+ * cppi41_mem_rgn_free - free the memory region within the queue manager
+ */
+int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn)
+{
+	void __iomem *desc_mem_regs;
+
+	pr_debug("%s called.\n", __func__);
+
+	if (q_mgr >= cppi41_num_queue_mgr || mem_rgn >= next_mem_rgn[q_mgr])
+		return -EINVAL;
+
+	desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
+
+	if (__raw_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn)) == 0)
+		return -ENOENT;
+
+	__raw_writel(0, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn));
+	__raw_writel(0, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(mem_rgn));
+
+	return 0;
+}
+EXPORT_SYMBOL(cppi41_mem_rgn_free);
+
+/*
+ * cppi41_tx_ch_init - initialize a CPPI 4.1 Tx channel object
+ *
+ * Verify the channel info (range checking, etc.) and store the channel
+ * information within the object structure.
+ */
+int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
+		      u8 dma_num, u8 ch_num)
+{
+	if (dma_num >= cppi41_num_dma_block ||
+	    ch_num  >= cppi41_dma_block[dma_num].num_tx_ch)
+		return -EINVAL;
+
+	/* Populate the channel object structure */
+	tx_ch_obj->base_addr  = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
+				DMA_CH_TX_GLOBAL_CFG_REG(ch_num);
+	tx_ch_obj->global_cfg = __raw_readl(tx_ch_obj->base_addr);
+	return 0;
+}
+EXPORT_SYMBOL(cppi41_tx_ch_init);
+
+/*
+ * cppi41_rx_ch_init - initialize a CPPI 4.1 Rx channel object
+ *
+ * Verify the channel info (range checking, etc.) and store the channel
+ * information within the object structure.
+ */
+int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
+		      u8 dma_num, u8 ch_num)
+{
+	if (dma_num >= cppi41_num_dma_block ||
+	    ch_num  >= cppi41_dma_block[dma_num].num_rx_ch)
+		return -EINVAL;
+
+	/* Populate the channel object structure */
+	rx_ch_obj->base_addr  = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
+				DMA_CH_RX_GLOBAL_CFG_REG(ch_num);
+	rx_ch_obj->global_cfg = __raw_readl(rx_ch_obj->base_addr);
+	return 0;
+}
+EXPORT_SYMBOL(cppi41_rx_ch_init);
+
+/*
+ * We have to cache the last written Rx/Tx channel global configration register
+ * value due to its bits other than enable/teardown being write-only. Yet there
+ * is a caveat related to caching the enable bit: this bit may be automatically
+ * cleared as a result of teardown, so we can't trust its cached value!
+ * When modifying the write only register fields, we're making use of the fact
+ * that they read back as zeros, and not clearing them explicitly...
+ */
+
+/*
+ * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
+ */
+void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
+				 u8 q_mgr, u16 q_num)
+{
+	u32 val = dma_ch_obj->global_cfg;
+
+	/* Clear the fields to be modified. */
+	val &= ~(DMA_CH_TX_DEFAULT_QMGR_MASK | DMA_CH_TX_DEFAULT_QNUM_MASK |
+		 DMA_CH_TX_ENABLE_MASK);
+
+	/* Set the default completion queue. */
+	val |= ((q_mgr << DMA_CH_TX_DEFAULT_QMGR_SHIFT) &
+		DMA_CH_TX_DEFAULT_QMGR_MASK) |
+	       ((q_num << DMA_CH_TX_DEFAULT_QNUM_SHIFT) &
+		DMA_CH_TX_DEFAULT_QNUM_MASK);
+
+	/* Get the current state of the enable bit. */
+	dma_ch_obj->global_cfg = val |= __raw_readl(dma_ch_obj->base_addr);
+	__raw_writel(val, dma_ch_obj->base_addr);
+	pr_debug("Channel global configuration @ %p, value written: %x, "
+		 "value read: %x\n", dma_ch_obj->base_addr, val,
+		 __raw_readl(dma_ch_obj->base_addr));
+
+}
+EXPORT_SYMBOL(cppi41_dma_ch_default_queue);
+
+/*
+ * cppi41_rx_ch_configure - configure CPPI 4.1 Rx channel
+ */
+void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
+			    struct cppi41_rx_ch_cfg  *cfg)
+{
+	void __iomem *base = rx_ch_obj->base_addr;
+	u32 val = __raw_readl(rx_ch_obj->base_addr);
+
+	val |= ((cfg->sop_offset << DMA_CH_RX_SOP_OFFSET_SHIFT) &
+		DMA_CH_RX_SOP_OFFSET_MASK) |
+	       ((cfg->default_desc_type << DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT) &
+		DMA_CH_RX_DEFAULT_DESC_TYPE_MASK) |
+	       ((cfg->retry_starved << DMA_CH_RX_ERROR_HANDLING_SHIFT) &
+		DMA_CH_RX_ERROR_HANDLING_MASK) |
+	       ((cfg->rx_queue.q_mgr << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT) &
+		DMA_CH_RX_DEFAULT_RQ_QMGR_MASK) |
+	       ((cfg->rx_queue.q_num << DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT) &
+		DMA_CH_RX_DEFAULT_RQ_QNUM_MASK);
+
+	rx_ch_obj->global_cfg = val;
+	__raw_writel(val, base);
+	pr_debug("Rx channel global configuration @ %p, value written: %x, "
+		 "value read: %x\n", base, val, __raw_readl(base));
+
+	base -= DMA_CH_RX_GLOBAL_CFG_REG(0);
+
+	/*
+	 * Set up the packet configuration register
+	 * based on the descriptor type...
+	 */
+	switch (cfg->default_desc_type) {
+	case DMA_CH_RX_DEFAULT_DESC_EMBED:
+		val = ((cfg->cfg.embed_pkt.fd_queue.q_mgr <<
+			DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT) &
+		       DMA_CH_RX_EMBED_FDQ_QMGR_MASK) |
+		      ((cfg->cfg.embed_pkt.fd_queue.q_num <<
+			DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT) &
+		       DMA_CH_RX_EMBED_FDQ_QNUM_MASK) |
+		      ((cfg->cfg.embed_pkt.num_buf_slot <<
+			DMA_CH_RX_EMBED_NUM_SLOT_SHIFT) &
+		       DMA_CH_RX_EMBED_NUM_SLOT_MASK) |
+		      ((cfg->cfg.embed_pkt.sop_slot_num <<
+			DMA_CH_RX_EMBED_SOP_SLOT_SHIFT) &
+		       DMA_CH_RX_EMBED_SOP_SLOT_MASK);
+
+		__raw_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0));
+		pr_debug("Rx channel embedded packet configuration B @ %p, "
+			 "value written: %x\n",
+			 base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0), val);
+
+		val = ((cfg->cfg.embed_pkt.free_buf_pool[0].b_pool <<
+			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(0)) &
+		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(0)) |
+		      ((cfg->cfg.embed_pkt.free_buf_pool[0].b_mgr <<
+			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(0)) &
+		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(0)) |
+		      ((cfg->cfg.embed_pkt.free_buf_pool[1].b_pool <<
+			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(1)) &
+		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(1)) |
+		      ((cfg->cfg.embed_pkt.free_buf_pool[1].b_mgr <<
+			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(1)) &
+		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(1)) |
+		      ((cfg->cfg.embed_pkt.free_buf_pool[2].b_pool <<
+			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(2)) &
+		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(2)) |
+		      ((cfg->cfg.embed_pkt.free_buf_pool[2].b_mgr <<
+			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(2)) &
+		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(2)) |
+		      ((cfg->cfg.embed_pkt.free_buf_pool[3].b_pool <<
+			DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(3)) &
+		       DMA_CH_RX_EMBED_FBP_PNUM_MASK(3)) |
+		      ((cfg->cfg.embed_pkt.free_buf_pool[3].b_mgr <<
+			DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(3)) &
+		       DMA_CH_RX_EMBED_FBP_BMGR_MASK(3));
+
+		__raw_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0));
+		pr_debug("Rx channel embedded packet configuration A @ %p, "
+			 "value written: %x\n",
+			 base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0), val);
+		break;
+	case DMA_CH_RX_DEFAULT_DESC_HOST:
+		val = ((cfg->cfg.host_pkt.fdb_queue[0].q_num <<
+			DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(0)) &
+		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(0)) |
+		      ((cfg->cfg.host_pkt.fdb_queue[0].q_mgr <<
+			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(0)) &
+		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(0)) |
+		      ((cfg->cfg.host_pkt.fdb_queue[1].q_num <<
+			DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(1)) &
+		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(1)) |
+		      ((cfg->cfg.host_pkt.fdb_queue[1].q_mgr <<
+			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(1)) &
+		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(1));
+
+		__raw_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0));
+		pr_debug("Rx channel host packet configuration A @ %p, "
+			 "value written: %x\n",
+			 base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0), val);
+
+		val = ((cfg->cfg.host_pkt.fdb_queue[2].q_num <<
+			DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(2)) &
+		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(2)) |
+		      ((cfg->cfg.host_pkt.fdb_queue[2].q_mgr <<
+			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(2)) &
+		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(2)) |
+		      ((cfg->cfg.host_pkt.fdb_queue[3].q_num <<
+		       DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(3)) &
+		       DMA_CH_RX_HOST_FDQ_QNUM_MASK(3)) |
+		      ((cfg->cfg.host_pkt.fdb_queue[3].q_mgr <<
+			DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(3)) &
+		       DMA_CH_RX_HOST_FDQ_QMGR_MASK(3));
+
+		__raw_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0));
+		pr_debug("Rx channel host packet configuration B @ %p, "
+			 "value written: %x\n",
+			 base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0), val);
+		break;
+	case DMA_CH_RX_DEFAULT_DESC_MONO:
+		val = ((cfg->cfg.mono_pkt.fd_queue.q_num <<
+			DMA_CH_RX_MONO_FDQ_QNUM_SHIFT) &
+		       DMA_CH_RX_MONO_FDQ_QNUM_MASK) |
+		      ((cfg->cfg.mono_pkt.fd_queue.q_mgr <<
+			DMA_CH_RX_MONO_FDQ_QMGR_SHIFT) &
+		       DMA_CH_RX_MONO_FDQ_QMGR_MASK) |
+		      ((cfg->cfg.mono_pkt.sop_offset <<
+			DMA_CH_RX_MONO_SOP_OFFSET_SHIFT) &
+		       DMA_CH_RX_MONO_SOP_OFFSET_MASK);
+
+		__raw_writel(val, base + DMA_CH_RX_MONO_PKT_CFG_REG(0));
+		pr_debug("Rx channel monolithic packet configuration @ %p, "
+			 "value written: %x\n",
+			 base + DMA_CH_RX_MONO_PKT_CFG_REG(0), val);
+		break;
+	}
+}
+EXPORT_SYMBOL(cppi41_rx_ch_configure);
+
+/*
+ * cppi41_dma_ch_teardown - teardown a given Tx/Rx channel
+ */
+void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj)
+{
+	u32 val = __raw_readl(dma_ch_obj->base_addr);
+
+	/* Initiate channel teardown. */
+	val |= dma_ch_obj->global_cfg & ~DMA_CH_TX_ENABLE_MASK;
+	dma_ch_obj->global_cfg = val |= DMA_CH_TX_TEARDOWN_MASK;
+	__raw_writel(val, dma_ch_obj->base_addr);
+	pr_debug("Tear down channel @ %p, value written: %x, value read: %x\n",
+		 dma_ch_obj->base_addr, val,
+		 __raw_readl(dma_ch_obj->base_addr));
+}
+EXPORT_SYMBOL(cppi41_dma_ch_teardown);
+
+/*
+ * cppi41_dma_ch_enable - enable Tx/Rx DMA channel in hardware
+ *
+ * Makes the channel ready for data transmission/reception.
+ */
+void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj)
+{
+	u32 val = dma_ch_obj->global_cfg | DMA_CH_TX_ENABLE_MASK;
+
+	/* Teardown bit remains set after completion, so clear it now... */
+	dma_ch_obj->global_cfg = val &= ~DMA_CH_TX_TEARDOWN_MASK;
+	__raw_writel(val, dma_ch_obj->base_addr);
+	pr_debug("Enable channel @ %p, value written: %x, value read: %x\n",
+		 dma_ch_obj->base_addr, val,
+		 __raw_readl(dma_ch_obj->base_addr));
+}
+EXPORT_SYMBOL(cppi41_dma_ch_enable);
+
+/*
+ * cppi41_dma_ch_disable - disable Tx/Rx DMA channel in hardware
+ */
+void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj)
+{
+	dma_ch_obj->global_cfg &= ~DMA_CH_TX_ENABLE_MASK;
+	__raw_writel(dma_ch_obj->global_cfg, dma_ch_obj->base_addr);
+	pr_debug("Disable channel @ %p, value written: %x, value read: %x\n",
+		 dma_ch_obj->base_addr, dma_ch_obj->global_cfg,
+		 __raw_readl(dma_ch_obj->base_addr));
+}
+EXPORT_SYMBOL(cppi41_dma_ch_disable);
+
+/**
+ * alloc_queue - allocate a queue in the given range
+ * @allocated:	pointer to the bitmap of the allocated queues
+ * @excluded:	pointer to the bitmap of the queues excluded from allocation
+ *		(optional)
+ * @start:	starting queue number
+ * @count:	number of queues available
+ *
+ * Returns queue number on success, -ENOSPC otherwise.
+ */
+static int alloc_queue(unsigned long *allocated, const unsigned long *excluded,
+		       unsigned start, unsigned count)
+{
+	unsigned n, end = start + count;
+
+	do {
+		n = find_next_zero_bit(allocated, end, start);
+		if (n >= end)
+			return -ENOSPC;
+		start = n + 1;
+	} while (test_bit(n, excluded) || test_and_set_bit(n, allocated));
+
+	return n;
+}
+
+/*
+ * cppi41_queue_alloc - allocate a queue of a given type in the queue manager
+ */
+int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num)
+{
+	int res = -ENOSPC;
+
+	if (q_mgr >= cppi41_num_queue_mgr)
+		return -EINVAL;
+
+	/* Mask out the unsupported queue types */
+	type &= cppi41_queue_mgr[q_mgr].queue_types;
+	/* First see if a free descriptor queue was requested... */
+	if (type & CPPI41_FREE_DESC_QUEUE)
+		res = alloc_queue(allocated_queues[q_mgr], NULL,
+				  cppi41_queue_mgr[q_mgr].base_fdq_num,  16);
+
+	/* Then see if a free descriptor/buffer queue was requested... */
+	if (res < 0 && (type & CPPI41_FREE_DESC_BUF_QUEUE))
+		res = alloc_queue(allocated_queues[q_mgr], NULL,
+				  cppi41_queue_mgr[q_mgr].base_fdbq_num, 16);
+
+	/* Last see if an unassigned queue was requested... */
+	if (res < 0 && (type & CPPI41_UNASSIGNED_QUEUE))
+		res = alloc_queue(allocated_queues[q_mgr],
+				  cppi41_queue_mgr[q_mgr].assigned, 0,
+				  cppi41_queue_mgr[q_mgr].num_queue);
+
+	/* See if any queue was allocated... */
+	if (res < 0)
+		return res;
+
+	/* Return the queue allocated */
+	*q_num = res;
+	return 0;
+}
+EXPORT_SYMBOL(cppi41_queue_alloc);
+
+/*
+ * cppi41_queue_free - free the given queue in the queue manager
+ */
+int cppi41_queue_free(u8 q_mgr, u16 q_num)
+{
+	if (q_mgr >= cppi41_num_queue_mgr ||
+	    q_num >= cppi41_queue_mgr[q_mgr].num_queue ||
+	    !test_and_clear_bit(q_num, allocated_queues[q_mgr]))
+		return -EINVAL;
+	else
+		return 0;
+}
+EXPORT_SYMBOL(cppi41_queue_free);
+
+/*
+ * cppi41_queue_init - initialize a CPPI 4.1 queue object
+ */
+int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num)
+{
+	if (q_mgr >= cppi41_num_queue_mgr ||
+	    q_num >= cppi41_queue_mgr[q_mgr].num_queue)
+		return -EINVAL;
+
+	queue_obj->base_addr = cppi41_queue_mgr[q_mgr].q_mgmt_rgn_base +
+			       QMGR_QUEUE_STATUS_REG_A(q_num);
+
+	return 0;
+}
+EXPORT_SYMBOL(cppi41_queue_init);
+
+/*
+ * cppi41_queue_push - push a descriptor into the given queue
+ */
+void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
+		       u32 desc_size, u32 pkt_size)
+{
+	u32 val;
+
+	/*
+	 * Write to the tail of the queue.
+	 * TODO: Can't think of a reason why a queue to head may be required.
+	 * If it is, the API may have to be extended.
+	 */
+#if 0
+	/*
+	 * Also, can't understand why packet size is required to queue up a
+	 * descriptor. The spec says packet size *must* be written prior to
+	 * the packet write operation.
+	 */
+	if (pkt_size)
+		val = (pkt_size << QMGR_QUEUE_PKT_SIZE_SHIFT) &
+		      QMGR_QUEUE_PKT_SIZE_MASK;
+	__raw_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_C(0));
+#endif
+
+	val = (((desc_size - 24) >> (2 - QMGR_QUEUE_DESC_SIZE_SHIFT)) &
+	       QMGR_QUEUE_DESC_SIZE_MASK) |
+	      (desc_addr & QMGR_QUEUE_DESC_PTR_MASK);
+
+	pr_debug("Pushing value %x to queue @ %p\n", val, queue_obj->base_addr);
+
+	__raw_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
+}
+EXPORT_SYMBOL(cppi41_queue_push);
+
+/*
+ * cppi41_queue_pop - pop a descriptor from a given queue
+ */
+unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj)
+{
+	u32 val = __raw_readl(queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
+
+	pr_debug("Popping value %x from queue @ %p\n",
+		 val, queue_obj->base_addr);
+
+	return val & QMGR_QUEUE_DESC_PTR_MASK;
+}
+EXPORT_SYMBOL(cppi41_queue_pop);
+
+/*
+ * cppi41_get_teardown_info - extract information from a teardown descriptor
+ */
+int cppi41_get_teardown_info(unsigned long addr, u32 *info)
+{
+	struct cppi41_teardown_desc *desc;
+	int dma_num;
+
+	for (dma_num = 0; dma_num < cppi41_num_dma_block; dma_num++)
+		if (addr >= dma_teardown[dma_num].phys_addr &&
+		    addr <  dma_teardown[dma_num].phys_addr +
+			    dma_teardown[dma_num].rgn_size)
+			break;
+
+	if (dma_num == cppi41_num_dma_block)
+		return -EINVAL;
+
+	desc = addr - dma_teardown[dma_num].phys_addr +
+	       dma_teardown[dma_num].virt_addr;
+
+	if ((desc->teardown_info & CPPI41_DESC_TYPE_MASK) !=
+	    (CPPI41_DESC_TYPE_TEARDOWN << CPPI41_DESC_TYPE_SHIFT))
+		return -EINVAL;
+
+	*info = desc->teardown_info;
+#if 1
+	/* Hardware is not giving the current DMA number as of now. :-/ */
+	*info |= (dma_num << CPPI41_TEARDOWN_DMA_NUM_SHIFT) &
+		 CPPI41_TEARDOWN_DMA_NUM_MASK;
+#else
+	dma_num = (desc->teardown_info & CPPI41_TEARDOWN_DMA_NUM_MASK) >>
+		 CPPI41_TEARDOWN_DMA_NUM_SHIFT;
+#endif
+
+	cppi41_queue_push(&dma_teardown[dma_num].queue_obj, addr,
+			  sizeof(struct cppi41_teardown_desc), 0);
+
+	return 0;
+}
+EXPORT_SYMBOL(cppi41_get_teardown_info);
Index: linux-davinci/arch/arm/include/asm/hardware/cppi41.h
===================================================================
--- /dev/null
+++ linux-davinci/arch/arm/include/asm/hardware/cppi41.h
@@ -0,0 +1,718 @@
+/*
+ * CPPI 4.1 definitions
+ *
+ * Copyright (c) 2008-2010, MontaVista Software, Inc. <source at mvista.com>
+ *
+ * Based on the PAL CPPI 4.1 implementation
+ * Copyright (C) 2007, Texas Instruments, Inc. http://www.ti.com/
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+
+#include <linux/types.h>
+
+/*
+ * Queue Manager - Control Registers Region
+ */
+#define QMGR_REVISION_REG		0x00	/* Major and minor versions */
+						/* of the module */
+#define QMGR_QUEUE_DIVERSION_REG	0x08	/* Queue Diversion register */
+#define QMGR_FREE_DESC_BUF_STARVED_REG(n) (0x20 + ((n) << 2)) /* Free Desc./ */
+						/* Buffer Starvation Count */
+#define QMGR_FREE_DESC_STARVED_REG(n)	(0x30 + ((n) << 2)) /* Free Desc. */
+						/* Starvation Count */
+#define QMGR_LINKING_RAM_RGN0_BASE_REG	0x80	/* Linking RAM Region 0 Base */
+						/* Address */
+#define QMGR_LINKING_RAM_RGN0_SIZE_REG	0x84	/* Linking RAM Region 0 Size */
+#define QMGR_LINKING_RAM_RGN1_BASE_REG	0x88	/* Linking RAM Region 1 Base */
+						/* Address */
+#define QMGR_QUEUE_PENDING_REG(n)	(0x90 + ((n) << 2)) /* Pending status */
+						/* for all queues */
+
+/*
+ * Queue Manager - Memory Region Registers
+ */
+#define QMGR_MEM_RGN_BASE_REG(r)	(0x00 + ((r) << 4))
+#define QMGR_MEM_RGN_CTRL_REG(r)	(0x04 + ((r) << 4))
+
+/* Memory Region R Control Register bits */
+#define QMGR_MEM_RGN_INDEX_SHIFT	16
+#define QMGR_MEM_RGN_INDEX_MASK 	(0x3fff << QMGR_MEM_RGN_INDEX_SHIFT)
+#define QMGR_MEM_RGN_DESC_SIZE_SHIFT	8
+#define QMGR_MEM_RGN_DESC_SIZE_MASK	(0xf << QMGR_MEM_RGN_DESC_SIZE_SHIFT)
+#define QMGR_MEM_RGN_SIZE_SHIFT 	0
+#define QMGR_MEM_RGN_SIZE_MASK		(7 << QMGR_MEM_RGN_SIZE_SHIFT)
+
+/*
+ * Queue Manager - Queues Region
+ */
+#define QMGR_QUEUE_REG_A(n)		(0x00 + ((n) << 4))
+#define QMGR_QUEUE_REG_B(n)		(0x04 + ((n) << 4))
+#define QMGR_QUEUE_REG_C(n)		(0x08 + ((n) << 4))
+#define QMGR_QUEUE_REG_D(n)		(0x0C + ((n) << 4))
+
+/* Queue N Register C bits */
+#define QMGR_QUEUE_HEAD_TAIL_SHIFT	31
+#define QMGR_QUEUE_HEAD_TAIL_MASK	(1 << QMGR_QUEUE_HEAD_TAIL_SHIFT)
+#define QMGR_QUEUE_PKT_SIZE_SHIFT	0
+#define QMGR_QUEUE_PKT_SIZE_MASK	(0x3fff << QMGR_QUEUE_PKT_SIZE_SHIFT)
+/* Queue N Register D bits */
+#define QMGR_QUEUE_DESC_PTR_SHIFT	5
+#define QMGR_QUEUE_DESC_PTR_MASK	(0x7ffffff << QMGR_QUEUE_DESC_PTR_SHIFT)
+#define QMGR_QUEUE_DESC_SIZE_SHIFT	0
+#define QMGR_QUEUE_DESC_SIZE_MASK	(0x1f << QMGR_QUEUE_DESC_SIZE_SHIFT)
+
+/*
+ * Queue Manager - Queue Status Region
+ */
+#define QMGR_QUEUE_STATUS_REG_A(n)	(0x00 + ((n) << 4))
+#define QMGR_QUEUE_STATUS_REG_B(n)	(0x04 + ((n) << 4))
+#define QMGR_QUEUE_STATUS_REG_C(n)	(0x08 + ((n) << 4))
+
+/*
+ * DMA Controller - Global Control Registers Region
+ */
+#define DMA_REVISION_REG		0x00	/* Major and minor versions */
+						/* of the module */
+#define DMA_TEARDOWN_FREE_DESC_CTRL_REG 0x04	/* Queue  manager and queue */
+						/* number for Teardown free */
+						/* descriptor queue */
+#define DMA_EMULATION_CTRL_REG		0x08	/* Emulation control register */
+
+/* Teardown Free Descriptor Queue Control Register bits */
+#define DMA_TD_DESC_QMGR_SHIFT		12
+#define DMA_TD_DESC_QMGR_MASK		(3 << DMA_TD_DESC_QMGR_SHIFT)
+#define DMA_TD_DESC_QNUM_SHIFT		0
+#define DMA_TD_DESC_QNUM_MASK		(0xfff << DMA_TD_DESC_QNUM_SHIFT)
+
+/*
+ * DMA Controller - Channel Control / Status Registers Region
+ */
+#define DMA_CH_TX_GLOBAL_CFG_REG(n)	 (0x00 + ((n) << 5))
+#define DMA_CH_RX_GLOBAL_CFG_REG(n)	 (0x08 + ((n) << 5))
+#define DMA_CH_RX_HOST_PKT_CFG_REG_A(n)  (0x0C + ((n) << 5))
+#define DMA_CH_RX_HOST_PKT_CFG_REG_B(n)  (0x10 + ((n) << 5))
+#define DMA_CH_RX_EMBED_PKT_CFG_REG_A(n) (0x14 + ((n) << 5))
+#define DMA_CH_RX_EMBED_PKT_CFG_REG_B(n) (0x18 + ((n) << 5))
+#define DMA_CH_RX_MONO_PKT_CFG_REG(n)	 (0x1C + ((n) << 5))
+
+/* Tx Channel N Global Configuration Register bits */
+#define DMA_CH_TX_ENABLE_SHIFT		31
+#define DMA_CH_TX_ENABLE_MASK		(1 << DMA_CH_TX_ENABLE_SHIFT)
+#define DMA_CH_TX_TEARDOWN_SHIFT	30
+#define DMA_CH_TX_TEARDOWN_MASK		(1 << DMA_CH_TX_TEARDOWN_SHIFT)
+#define DMA_CH_TX_DEFAULT_QMGR_SHIFT	12
+#define DMA_CH_TX_DEFAULT_QMGR_MASK	(3 << DMA_CH_TX_DEFAULT_QMGR_SHIFT)
+#define DMA_CH_TX_DEFAULT_QNUM_SHIFT	0
+#define DMA_CH_TX_DEFAULT_QNUM_MASK	(0xfff << DMA_CH_TX_DEFAULT_QNUM_SHIFT)
+
+/* Rx Channel N Global Configuration Register bits */
+#define DMA_CH_RX_ENABLE_SHIFT		31
+#define DMA_CH_RX_ENABLE_MASK		(1 << DMA_CH_RX_ENABLE_SHIFT)
+#define DMA_CH_RX_TEARDOWN_SHIFT	30
+#define DMA_CH_RX_TEARDOWN_MASK		(1 << DMA_CH_RX_TEARDOWN_SHIFT)
+#define DMA_CH_RX_ERROR_HANDLING_SHIFT	24
+#define DMA_CH_RX_ERROR_HANDLING_MASK	(1 << DMA_CH_RX_ERROR_HANDLING_SHIFT)
+#define DMA_CH_RX_SOP_OFFSET_SHIFT	16
+#define DMA_CH_RX_SOP_OFFSET_MASK	(0xff << DMA_CH_RX_SOP_OFFSET_SHIFT)
+#define DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT 14
+#define DMA_CH_RX_DEFAULT_DESC_TYPE_MASK  (3 << \
+					   DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT)
+#define DMA_CH_RX_DEFAULT_DESC_EMBED	0
+#define DMA_CH_RX_DEFAULT_DESC_HOST	1
+#define DMA_CH_RX_DEFAULT_DESC_MONO	2
+#define DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT 12
+#define DMA_CH_RX_DEFAULT_RQ_QMGR_MASK	(3 << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT)
+#define DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT 0
+#define DMA_CH_RX_DEFAULT_RQ_QNUM_MASK	(0xfff << \
+					 DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT)
+
+/* Rx Channel N Host Packet Configuration Register A/B bits */
+#define DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(n) (12 + 16 * ((n) & 1))
+#define DMA_CH_RX_HOST_FDQ_QMGR_MASK(n)  (3 << DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(n))
+#define DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(n) (0 + 16 * ((n) & 1))
+#define DMA_CH_RX_HOST_FDQ_QNUM_MASK(n)  (0xfff << \
+					  DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(n))
+
+/* Rx Channel N Embedded Packet Configuration Register A bits */
+#define DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(n) (6 + 8 * (n))
+#define DMA_CH_RX_EMBED_FBP_BMGR_MASK(n)  (3 << \
+					   DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(n))
+#define DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(n) (0 + 8 * (n))
+#define DMA_CH_RX_EMBED_FBP_PNUM_MASK(n)  (0x1f << \
+					   DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(n))
+
+/* Rx Channel N Embedded Packet Configuration Register B bits */
+#define DMA_CH_RX_EMBED_NUM_SLOT_SHIFT	24
+#define DMA_CH_RX_EMBED_NUM_SLOT_MASK	(7 << DMA_CH_RX_EMBED_NUM_SLOT_SHIFT)
+#define DMA_CH_RX_EMBED_SOP_SLOT_SHIFT	16
+#define DMA_CH_RX_EMBED_SOP_SLOT_MASK	(7 << DMA_CH_RX_EMBED_SOP_SLOT_SHIFT)
+#define DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT	12
+#define DMA_CH_RX_EMBED_FDQ_QMGR_MASK	(3 << DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT)
+#define DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT	0
+#define DMA_CH_RX_EMBED_FDQ_QNUM_MASK	(0xfff << \
+					 DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT)
+
+/* Rx Channel N Monolithic Packet Configuration Register bits */
+#define DMA_CH_RX_MONO_SOP_OFFSET_SHIFT 16
+#define DMA_CH_RX_MONO_SOP_OFFSET_MASK	(0xff << \
+					 DMA_CH_RX_MONO_SOP_OFFSET_SHIFT)
+#define DMA_CH_RX_MONO_FDQ_QMGR_SHIFT	12
+#define DMA_CH_RX_MONO_FDQ_QMGR_MASK	(3 << DMA_CH_RX_MONO_FDQ_QMGR_SHIFT)
+#define DMA_CH_RX_MONO_FDQ_QNUM_SHIFT	0
+#define DMA_CH_RX_MONO_FDQ_QNUM_MASK	(0xfff << DMA_CH_RX_MONO_FDQ_QNUM_SHIFT)
+
+/*
+ * DMA Scheduler - Control Region
+ */
+#define DMA_SCHED_CTRL_REG		0x00
+
+/* DMA Scheduler Control Register bits */
+#define DMA_SCHED_ENABLE_SHIFT		31
+#define DMA_SCHED_ENABLE_MASK		(1 << DMA_SCHED_ENABLE_SHIFT)
+#define DMA_SCHED_LAST_ENTRY_SHIFT	0
+#define DMA_SCHED_LAST_ENTRY_MASK	(0xff << DMA_SCHED_LAST_ENTRY_SHIFT)
+
+/*
+ * DMA Scheduler - Table Region
+ */
+#define DMA_SCHED_TABLE_WORD_REG(n)	((n) << 2)
+
+/*
+ * CPPI 4.1 Host Packet Descriptor
+ */
+struct cppi41_host_pkt_desc {
+	u32 desc_info;		/* Descriptor type, protocol specific word */
+				/* count, packet length */
+	u32 tag_info;		/* Source tag (31:16), destination tag (15:0) */
+	u32 pkt_info;		/* Packet error state, type, protocol flags, */
+				/* return info, descriptor location */
+	u32 buf_len;		/* Number of valid data bytes in the buffer */
+	u32 buf_ptr;		/* Pointer to the buffer associated with */
+				/* this descriptor */
+	u32 next_desc_ptr;	/* Pointer to the next buffer descriptor */
+	u32 orig_buf_len;	/* Original buffer length */
+	u32 orig_buf_ptr;	/* Original buffer pointer */
+	u32 stk_comms_info[2];	/* Network stack private communications info */
+};
+
+/*
+ * CPPI 4.1 Host Buffer Descriptor
+ */
+struct cppi41_host_buf_desc {
+	u32 reserved[2];
+	u32 buf_recl_info;	/* Return info, descriptor location */
+	u32 buf_len;		/* Number of valid data bytes in the buffer */
+	u32 buf_ptr;		/* Pointer to the buffer associated with */
+				/* this descriptor */
+	u32 next_desc_ptr;	/* Pointer to the next buffer descriptor */
+	u32 orig_buf_len;	/* Original buffer length */
+	u32 orig_buf_ptr;	/* Original buffer pointer */
+};
+
+#define CPPI41_DESC_TYPE_SHIFT		27
+#define CPPI41_DESC_TYPE_MASK		(0x1f << CPPI41_DESC_TYPE_SHIFT)
+#define CPPI41_DESC_TYPE_HOST		16
+#define CPPI41_DESC_TYPE_MONOLITHIC	18
+#define CPPI41_DESC_TYPE_TEARDOWN	19
+#define CPPI41_PROT_VALID_WORD_CNT_SHIFT 22
+#define CPPI41_PROT_VALID_WORD_CNT_MASK	(0x1f << CPPI41_PROT_WORD_CNT_SHIFT)
+#define CPPI41_PKT_LEN_SHIFT		0
+#define CPPI41_PKT_LEN_MASK		(0x1fffff << CPPI41_PKT_LEN_SHIFT)
+
+#define CPPI41_PKT_ERROR_SHIFT		31
+#define CPPI41_PKT_ERROR_MASK		(1 << CPPI41_PKT_ERROR_SHIFT)
+#define CPPI41_PKT_TYPE_SHIFT		26
+#define CPPI41_PKT_TYPE_MASK		(0x1f << CPPI41_PKT_TYPE_SHIFT)
+#define CPPI41_PKT_TYPE_ATM_AAL5	0
+#define CPPI41_PKT_TYPE_ATM_NULL_AAL	1
+#define CPPI41_PKT_TYPE_ATM_OAM		2
+#define CPPI41_PKT_TYPE_ATM_TRANSPARENT	3
+#define CPPI41_PKT_TYPE_EFM		4
+#define CPPI41_PKT_TYPE_USB		5
+#define CPPI41_PKT_TYPE_GENERIC		6
+#define CPPI41_PKT_TYPE_ETHERNET 	7
+#define CPPI41_RETURN_POLICY_SHIFT	15
+#define CPPI41_RETURN_POLICY_MASK 	(1 << CPPI41_RETURN_POLICY_SHIFT)
+#define CPPI41_RETURN_LINKED		0
+#define CPPI41_RETURN_UNLINKED		1
+#define CPPI41_ONCHIP_SHIFT		14
+#define CPPI41_ONCHIP_MASK		(1 << CPPI41_ONCHIP_SHIFT)
+#define CPPI41_RETURN_QMGR_SHIFT 	12
+#define CPPI41_RETURN_QMGR_MASK		(3 << CPPI41_RETURN_QMGR_SHIFT)
+#define CPPI41_RETURN_QNUM_SHIFT 	0
+#define CPPI41_RETURN_QNUM_MASK		(0xfff << CPPI41_RETURN_QNUM_SHIFT)
+
+#define CPPI41_SRC_TAG_PORT_NUM_SHIFT	27
+#define CPPI41_SRC_TAG_PORT_NUM_MASK	(0x1f << CPPI41_SRC_TAG_PORT_NUM_SHIFT)
+#define CPPI41_SRC_TAG_CH_NUM_SHIFT	21
+#define CPPI41_SRC_TAG_CH_NUM_MASK	(0x3f << CPPI41_SRC_TAG_CH_NUM_SHIFT)
+#define CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT 16
+#define CPPI41_SRC_TAG_SUB_CH_NUM_MASK	(0x1f << \
+					CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT)
+#define CPPI41_DEST_TAG_SHIFT		0
+#define CPPI41_DEST_TAG_MASK		(0xffff << CPPI41_DEST_TAG_SHIFT)
+
+/*
+ * CPPI 4.1 Teardown Descriptor
+ */
+struct cppi41_teardown_desc {
+	u32 teardown_info;	/* Teardown information */
+	u32 reserved[7];	/* 28 byte padding */
+};
+
+#define CPPI41_TEARDOWN_TX_RX_SHIFT	16
+#define CPPI41_TEARDOWN_TX_RX_MASK	(1 << CPPI41_TEARDOWN_TX_RX_SHIFT)
+#define CPPI41_TEARDOWN_DMA_NUM_SHIFT	10
+#define CPPI41_TEARDOWN_DMA_NUM_MASK	(0x3f << CPPI41_TEARDOWN_DMA_NUM_SHIFT)
+#define CPPI41_TEARDOWN_CHAN_NUM_SHIFT	0
+#define CPPI41_TEARDOWN_CHAN_NUM_MASK	(0x3f << CPPI41_TEARDOWN_CHAN_NUM_SHIFT)
+
+#define CPPI41_MAX_MEM_RGN		16
+
+/* CPPI 4.1 configuration for DA8xx */
+#define CPPI41_NUM_QUEUE_MGR		1	/* 4  max */
+#define CPPI41_NUM_DMA_BLOCK		4	/* 64 max */
+
+/**
+ * struct cppi41_queue - Queue Tuple
+ *
+ * The basic queue tuple in CPPI 4.1 used across all data structures
+ * where a definition of a queue is required.
+ */
+struct cppi41_queue {
+	u8  q_mgr;		/* The queue manager number */
+	u16 q_num;		/* The queue number */
+};
+
+/**
+ * struct cppi41_buf_pool - Buffer Pool Tuple
+ *
+ * The basic buffer pool tuple in CPPI 4.1 used across all data structures
+ * where a definition of a buffer pool is required.
+ */
+struct cppi41_buf_pool {
+	u8  b_mgr;		/* The buffer manager number */
+	u16 b_pool;		/* The buffer pool number */
+};
+
+/**
+ * struct cppi41_queue_mgr - Queue Manager information
+ *
+ * Contains the information about the queue manager which should be copied from
+ * the hardware spec as is.
+ */
+struct cppi41_queue_mgr {
+	void __iomem *q_mgr_rgn_base; /* Base address of the Control region. */
+	void __iomem *desc_mem_rgn_base; /* Base address of the descriptor */
+				/* memory region. */
+	void __iomem *q_mgmt_rgn_base; /* Base address of the queues region. */
+	void __iomem *q_stat_rgn_base; /* Base address of the queue status */
+				/* region. */
+	u16 num_queue;		/* Number of the queues supported. */
+	u8  queue_types; 	/* Bitmask of the supported queue types. */
+	u16 base_fdq_num;	/* The base free descriptor queue number. */
+				/* If present, there's always 16 such queues. */
+	u16 base_fdbq_num;	/* The base free descriptor/buffer queue */
+				/* number.  If present, there's always 16 */
+				/* such queues. */
+	const unsigned long *assigned; /* Pointer to the bitmask of the */
+				/* pre-assigned queues. */
+};
+
+/* Queue type flags */
+#define CPPI41_FREE_DESC_QUEUE		0x01
+#define CPPI41_FREE_DESC_BUF_QUEUE	0x02
+#define CPPI41_UNASSIGNED_QUEUE 	0x04
+
+/**
+ * struct cppi41_embed_pkt_cfg - Rx Channel Embedded packet configuration
+ *
+ * An instance of this structure forms part of the Rx channel information
+ * structure.
+ */
+struct cppi41_embed_pkt_cfg {
+	struct cppi41_queue fd_queue; /* Free Descriptor queue.*/
+	u8 num_buf_slot;	/* Number of buffer slots in the descriptor */
+	u8 sop_slot_num;	/* SOP buffer slot number. */
+	struct cppi41_buf_pool free_buf_pool[4]; /* Free Buffer pool. Element */
+				/* 0 used for the 1st Rx buffer, etc. */
+};
+
+/**
+ * struct cppi41_host_pkt_cfg - Rx Channel Host Packet Configuration
+ *
+ * An instance of this structure forms part of the Rx channel information
+ * structure.
+ */
+struct cppi41_host_pkt_cfg {
+	struct cppi41_queue fdb_queue[4]; /* Free Desc/Buffer queue. Element */
+				/* 0 used for 1st Rx buffer, etc. */
+};
+
+/**
+ * struct cppi41_mono_pkt_cfg - Rx Channel Monolithic Packet Configuration
+ *
+ * An instance of this structure forms part of the Rx channel information
+ * structure.
+ */
+struct cppi41_mono_pkt_cfg {
+	struct cppi41_queue fd_queue; /* Free descriptor queue */
+	u8 sop_offset;		/* Number of bytes to skip before writing */
+				/* payload */
+};
+
+enum cppi41_rx_desc_type {
+	cppi41_rx_embed_desc,
+	cppi41_rx_host_desc,
+	cppi41_rx_mono_desc,
+};
+
+/**
+ * struct cppi41_rx_ch_cfg - Rx Channel Configuration
+ *
+ * Must be allocated and filled by the caller of cppi41_rx_ch_configure().
+ *
+ * The same channel can be configured to receive different descripor type
+ * packets (not simultaneously). When the Rx packets on a port need to be sent
+ * to the SR, the channel's default descriptor type is set to Embedded and the
+ * Rx completion queue is set to the queue which CPU polls for input packets.
+ * When in SR bypass mode, the same channel's default descriptor type will be
+ * set to Host and the Rx completion queue set to one of the queues which host
+ * can get interrupted on (via the Queuing proxy/accumulator). In this example,
+ * the embedded mode configuration fetches free descriptor from the Free
+ * descriptor queue (as defined by struct cppi41_embed_pkt_cfg) and host
+ * mode configuration fetches free descriptors/buffers from the free descriptor/
+ * buffer queue (as defined by struct cppi41_host_pkt_cfg).
+ *
+ * NOTE: There seems to be no separate configuration for teardown completion
+ * descriptor. The assumption is rxQueue tuple is used for this purpose as well.
+ */
+struct cppi41_rx_ch_cfg {
+	enum cppi41_rx_desc_type default_desc_type; /* Describes which queue */
+				/* configuration is used for the free */
+				/* descriptors and/or buffers */
+	u8 sop_offset;		/* Number of bytes to skip in SOP buffer */
+				/* before writing payload */
+	u8 retry_starved;	/* 0 = Drop packet on descriptor/buffer */
+				/* starvartion, 1 = DMA retries FIFO block */
+				/* transfer at a later time */
+	struct cppi41_queue rx_queue; /* Rx complete packets queue */
+	union {
+		struct cppi41_host_pkt_cfg host_pkt; /* Host packet */
+				/* configuration. This defines where channel */
+				/* picks free descriptors from. */
+		struct cppi41_embed_pkt_cfg embed_pkt; /* Embedded packet */
+				/* configuration. This defines where channel */
+				/* picks free descriptors/buffers from. */
+				/* from. */
+		struct cppi41_mono_pkt_cfg mono_pkt; /* Monolithic packet */
+				/* configuration. This defines where channel */
+				/* picks free descriptors from. */
+	} cfg;			/* Union of packet configuration structures */
+				/* to be filled in depending on the */
+				/* defDescType field. */
+};
+
+/**
+ * struct cppi41_tx_ch - Tx channel information
+ *
+ * NOTE: The queues that feed into the Tx channel are fixed at SoC design time.
+ */
+struct cppi41_tx_ch {
+	u8 port_num;		/* Port number. */
+	u8 ch_num;		/* Channel number within port. */
+	u8 sub_ch_num;		/* Sub-channel number within channel. */
+	u8 num_tx_queue;	/* Number of queues from which the channel */
+				/* can feed. */
+	struct cppi41_queue tx_queue[4]; /* List of queues from which the */
+				/* channel can feed. */
+};
+
+/**
+ * struct cppi41_dma_block - CPPI 4.1 DMA configuration
+ *
+ * Configuration information for CPPI DMA functionality. Includes the Global
+ * configuration, Channel configuration, and the Scheduler configuration.
+ */
+struct cppi41_dma_block {
+	void __iomem *global_ctrl_base; /* Base address of the Global Control */
+				/* registers. */
+	void __iomem *ch_ctrl_stat_base; /* Base address of the Channel */
+				/* Control/Status registers. */
+	void __iomem *sched_ctrl_base; /* Base address of the Scheduler */
+				/* Control register. */
+	void __iomem *sched_table_base; /* Base address of the Scheduler */
+				/* Table registers. */
+	u8 num_tx_ch;		/* Number of the Tx channels. */
+	u8 num_rx_ch;		/* Number of the Rx channels. */
+	const struct cppi41_tx_ch *tx_ch_info;
+};
+
+extern const struct cppi41_queue_mgr cppi41_queue_mgr[];
+extern const struct cppi41_dma_block cppi41_dma_block[];
+extern const u8 cppi41_num_queue_mgr;
+extern const u8 cppi41_num_dma_block;
+
+/**
+ * struct cppi41_dma_ch_obj - CPPI 4.1 DMA Channel object
+ */
+struct cppi41_dma_ch_obj {
+	void __iomem *base_addr; /* The address of the channel global */
+				/* configuration register */
+	u32 global_cfg;		/* Tx/Rx global configuration backed-up value */
+};
+
+/**
+ * struct cppi41_queue_obj - CPPI 4.1 queue object
+ */
+struct cppi41_queue_obj {
+	void __iomem *base_addr; /* The base address of the queue management */
+				/* registers */
+};
+
+/**
+ * cppi41_queue_mgr_init - CPPI 4.1 queue manager initialization.
+ * @q_mgr:	the queue manager to initialize
+ * @rgn0_base:	linking RAM region 0 physical address
+ * @rgn0_size:	linking RAM region 0 size in 32-bit words (0 to 0x3fff)
+ *
+ * Returns 0 on success, error otherwise.
+ */
+int cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size);
+
+/*
+ * CPPI 4.1 Queue Manager Memory Region Allocation and De-allocation APIs.
+ */
+
+/**
+ * cppi41_mem_rgn_alloc - CPPI 4.1 queue manager memory region allocation.
+ * @q_mgr:	the queue manager whose memory region to allocate
+ * @rgn_addr:	physical address of the memory region
+ * @size_order:	descriptor size as a power of two (between 5 and 13)
+ * @num_order:	number of descriptors as a power of two (between 5 and 12)
+ * @mem_rgn:	pointer to the index of the memory region allocated
+ *
+ * This function allocates a memory region within the queue manager
+ * consisiting of the descriptors of paricular size and number.
+ *
+ * Returns 0 on success, error otherwise.
+ */
+int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
+			 u8 num_order, u8 *mem_rgn);
+
+/**
+ * cppi41_mem_rgn_free - CPPI 4.1 queue manager memory region de-allocation.
+ * @q_mgr:	the queue manager whose memory region was allocated
+ * @mem_rgn:	index of the memory region
+ *
+ * This function frees the memory region allocated by cppi41_mem_rgn_alloc().
+ *
+ * Returns 0 on success, -EINVAL otherwise.
+ */
+int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn);
+
+/**
+ * cppi41_dma_ctrlr_init - CPPI 4.1 DMA controller initialization.
+ * @dma_num:	number of the DMA block
+ * @q_mgr:	the queue manager in which to allocate the free teardown
+ *		descriptor queue
+ * @num_order:	number of teardown descriptors as a power of two (at least 5)
+ *
+ * Returns 0 on success, error otherwise.
+ */
+int cppi41_dma_ctrlr_init(u8 dma_num, u8 q_mgr, u8 num_order);
+
+/**
+ * cppi41_dma_sched_init - CPPI 4.1 DMA scheduler initialization.
+ * @dma_num:	number of the DMA block
+ * @sched_tbl:	the DMA scheduler table
+ * @tbl_size:	number of entries in the DMA scheduler table
+ *
+ * Returns 0 on success, error otherwise.
+ */
+int cppi41_dma_sched_init(u8 dma_num, const u8 *sched_tbl, u16 tbl_size);
+
+/*
+ * CPPI 4.1 DMA Channel Management APIs
+ */
+
+/**
+ * cppi41_tx_ch_init - initialize CPPI 4.1 transmit channel object
+ * @tx_ch_obj:	pointer to Tx channel object
+ * @dma_num:	DMA block to which this channel belongs
+ * @ch_num:	DMA channel number
+ *
+ * Returns 0 if valid Tx channel, -EINVAL otherwise.
+ */
+int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
+		      u8 dma_num, u8 ch_num);
+
+/**
+ * cppi41_rx_ch_init - initialize CPPI 4.1 receive channel object
+ * @rx_ch_obj:	pointer to Rx channel object
+ * @dma_num:	DMA block to which this channel belongs
+ * @ch_num:	DMA channel number
+ *
+ * Returns 0 if valid Rx channel, -EINVAL otherwise.
+ */
+int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
+		      u8 dma_num, u8 ch_num);
+
+/**
+ * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
+ * @dma_ch_obj: pointer to DMA channel object
+ * @q_mgr:	default queue manager
+ * @q_num:	default queue number
+ *
+ * This function configures the specified channel.  The caller is required to
+ * provide the default queue onto which the teardown descriptors will be queued.
+ */
+void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
+				 u8 q_mgr, u16 q_num);
+
+/**
+ * cppi41_rx_ch_configure - configure CPPI 4.1 receive channel
+ * @rx_ch_obj:	pointer to Rx channel object
+ * @cfg:	pointer to Rx channel configuration
+ *
+ * This function configures and opens the specified Rx channel.  The caller
+ * is required to provide channel configuration information by initializing
+ * a struct cppi41_rx_ch_cfg.
+ */
+void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
+			    struct cppi41_rx_ch_cfg  *cfg);
+
+/**
+ * cppi41_dma_ch_enable - enable CPPI 4.1 Tx/Rx DMA channel
+ * @dma_ch_obj:	pointer to DMA channel object
+ *
+ * This function enables  a specified Tx channel.  The caller is required to
+ * provide a reference to a channel object initialized by an earlier call of
+ * the cppi41_dma_ch_init() function.  After the successful completion of this
+ * function, the Tx DMA channel will be active and ready for data transmission.
+ */
+void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj);
+
+/**
+ * cppi41_dma_ch_disable - disable CPPI 4.1 Tx/Rx DMA channel
+ * @dma_ch_obj:	pointer to DMA channel object
+ *
+ * This function disables a specific Tx channel.  The caller is required to
+ * provide a reference to a channel object initialized by an earlier call of
+ * the cppi41_dma_ch_init() function.  After the successful completion of this
+ * function, the Tx DMA channel will be deactived.
+ */
+void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj);
+
+/**
+ * cppi41_dma_ch_teardown - tear down CPPI 4.1 transmit channel
+ * @dma_ch_obj:	pointer DMA channel object
+ *
+ * This function triggers the teardown of the given DMA channel.
+ *
+ * ATTENTION: Channel disable should not be called before the teardown is
+ * completed as a disable will stop the DMA scheduling on the channel resulting
+ * in the teardown complete event not being registered at all.
+ *
+ * NOTE: A successful channel teardown event is reported via queueing of a
+ * teardown descriptor.
+ *
+ * This function just sets up for the teardown of the channel and returns. The
+ * caller must detect the channel teardown event to assume that the channel is
+ * disabled.
+ *
+ * See cppi41_get_teardown_info() for the teardown completion processing.
+ */
+void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj);
+
+/*
+ * CPPI 4.1 Queue Allocation and De-allocation APIs.
+ */
+
+/**
+ * cppi41_queue_alloc - allocate CPPI 4.1 queue
+ * @type:	queue type bitmask
+ * @q_mgr:	queue manager
+ * @q_num:	pointer to the queue number
+ *
+ * Returns 0 if queue allocated, error otherwise.
+ */
+int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num);
+
+/**
+ * cppi41_queue_free - de-allocate CPPI 4.1 queue
+ * @q_mgr:	queue manager
+ * @q_num:	queue number
+ *
+ * Returns 0 on success, -EINVAL otherwise.
+ */
+int cppi41_queue_free(u8 q_mgr, u16 q_num);
+
+/*
+ *  CPPI 4.1 Queue Management APIs
+ */
+
+/**
+ * cppi41_queue_init - initialize CPPI 4.1 queue object
+ * @queue_obj:	pointer to the queue object
+ * @q_mgr:	queue manager
+ * @q_num:	queue number
+ *
+ * Returns 0 if valid queue, -EINVAL otherwise.
+ */
+int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num);
+
+/**
+ * cppi41_queue_push - push to CPPI 4.1 queue
+ * @queue_obj:	pointer to the queue object
+ * @desc_addr:	descriptor physical address
+ * @desc_size:	descriptor size
+ * @pkt_size:	packet size
+ *
+ * This function is called to queue a descriptor onto a queue.
+ * NOTE: pSize parameter is optional. Pass 0 in case not required.
+ */
+void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
+		       u32 desc_size, u32 pkt_size);
+
+/**
+ * cppi41_queue_pop - pop from CPPI 4.1 queue
+ * @queue_obj:	pointer to the queue object
+ *
+ * This function is called to pop a single descriptor from the queue.
+ *
+ * Returns a packet descriptor's physical address.
+ */
+unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj);
+
+/*
+ * CPPI 4.1 Miscellaneous APIs
+ */
+
+/**
+ * cppi41_get_teardown_info - CPPI 4.1 teardown completion processing function
+ *
+ * @addr:	physical address of teardown descriptor
+ * @info:	pointer to the teardown information word
+ *
+ * This function is called to complete the teardown processing on a channel
+ * and provides teardown information from the teardown descriptor passed to it.
+ * It also recycles the teardown descriptor back to the teardown descriptor
+ * queue.
+ *
+ * Returns 0 if valid descriptor, -EINVAL otherwise.
+ */
+int cppi41_get_teardown_info(unsigned long addr, u32 *info);

From sshtylyov at ru.mvista.com  Sat May 15 13:16:54 2010
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Sat, 15 May 2010 22:16:54 +0400
Subject: [PATCH v6 2/3] DA8xx: CPPI 4.1 platform code
Message-ID: <201005152216.54242.sshtylyov@ru.mvista.com>

Add da8xx_cppi41_init() function to initialize the CPPI 4.1 subsystem along
with the data describing the CPPI 4.1 queue manager and the DMA block found
in OMAP-L1x/DA8xx chips.

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>

---
The patch is against the recent DaVinci tree.

Changes since the previous version (mostly due to move of the CPPI 4.1 support
to arch/arm/common/):
- replaced #include <mach/cppi41.h> with #include <asm/hardware/cppi41.h>;
- added 'select TI_CPPI41' to DA8[35]0 entries in Kconfig;
- removed #ifdef CONFIG_CPPI41 around da8xx_cppi41_init() and its data;
- exported cppi41_queue_mgr[];
- moved USB 2.0 clock entry change to another, already merged patch...

 arch/arm/mach-davinci/Kconfig              |    2 
 arch/arm/mach-davinci/include/mach/da8xx.h |    2 
 arch/arm/mach-davinci/usb.c                |  106 +++++++++++++++++++++++++++++
 3 files changed, 110 insertions(+)

Index: linux-davinci/arch/arm/mach-davinci/Kconfig
===================================================================
--- linux-davinci.orig/arch/arm/mach-davinci/Kconfig
+++ linux-davinci/arch/arm/mach-davinci/Kconfig
@@ -32,12 +32,14 @@ config ARCH_DAVINCI_DM646x
 config ARCH_DAVINCI_DA830
         bool "DA830/OMAP-L137 based system"
 	select CP_INTC
+	select TI_CPPI41
 	select ARCH_DAVINCI_DA8XX
 	select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1
 
 config ARCH_DAVINCI_DA850
 	bool "DA850/OMAP-L138 based system"
 	select CP_INTC
+	select TI_CPPI41
 	select ARCH_DAVINCI_DA8XX
 	select ARCH_HAS_CPUFREQ
 
Index: linux-davinci/arch/arm/mach-davinci/include/mach/da8xx.h
===================================================================
--- linux-davinci.orig/arch/arm/mach-davinci/include/mach/da8xx.h
+++ linux-davinci/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -67,6 +67,8 @@ extern void __iomem *da8xx_syscfg1_base;
 void __init da830_init(void);
 void __init da850_init(void);
 
+int da8xx_cppi41_init(void);
+
 int da8xx_register_edma(void);
 int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
 int da8xx_register_watchdog(void);
Index: linux-davinci/arch/arm/mach-davinci/usb.c
===================================================================
--- linux-davinci.orig/arch/arm/mach-davinci/usb.c
+++ linux-davinci/arch/arm/mach-davinci/usb.c
@@ -2,11 +2,14 @@
  * USB
  */
 #include <linux/init.h>
+#include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
 #include <linux/usb/musb.h>
 
+#include <asm/hardware/cppi41.h>
+
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/cputype.h>
@@ -173,4 +176,107 @@ int __init da8xx_register_usb11(struct d
 	da8xx_usb11_device.dev.platform_data = pdata;
 	return platform_device_register(&da8xx_usb11_device);
 }
+
+static const struct cppi41_tx_ch tx_ch_info[] = {
+	[0] = {
+		.port_num	= 1,
+		.num_tx_queue	= 2,
+		.tx_queue	= { { 0, 16 }, { 0, 17 } }
+	},
+	[1] = {
+		.port_num	= 2,
+		.num_tx_queue	= 2,
+		.tx_queue	= { { 0, 18 }, { 0, 19 } }
+	},
+	[2] = {
+		.port_num	= 3,
+		.num_tx_queue	= 2,
+		.tx_queue	= { { 0, 20 }, { 0, 21 } }
+	},
+	[3] = {
+		.port_num	= 4,
+		.num_tx_queue	= 2,
+		.tx_queue	= { { 0, 22 }, { 0, 23 } }
+	}
+};
+
+/* DMA block configuration */
+const struct cppi41_dma_block cppi41_dma_block[1] = {
+	[0] = {
+		.global_ctrl_base	= IO_ADDRESS(DA8XX_USB0_BASE + 0x1000),
+		.ch_ctrl_stat_base	= IO_ADDRESS(DA8XX_USB0_BASE + 0x1800),
+		.sched_ctrl_base	= IO_ADDRESS(DA8XX_USB0_BASE + 0x2000),
+		.sched_table_base	= IO_ADDRESS(DA8XX_USB0_BASE + 0x2800),
+		.num_tx_ch		= 4,
+		.num_rx_ch		= 4,
+		.tx_ch_info		= tx_ch_info
+	}
+};
+EXPORT_SYMBOL(cppi41_dma_block);
+
+/* Queues 0 to 27 are pre-assigned, others are spare */
+static const unsigned long assigned_queues[] = { 0x0fffffff, 0 };
+
+/* Queue manager information */
+const struct cppi41_queue_mgr cppi41_queue_mgr[1] = {
+	[0] = {
+		.q_mgr_rgn_base 	= IO_ADDRESS(DA8XX_USB0_BASE + 0x4000),
+		.desc_mem_rgn_base	= IO_ADDRESS(DA8XX_USB0_BASE + 0x5000),
+		.q_mgmt_rgn_base	= IO_ADDRESS(DA8XX_USB0_BASE + 0x6000),
+		.q_stat_rgn_base	= IO_ADDRESS(DA8XX_USB0_BASE + 0x6800),
+
+		.num_queue		= 64,
+		.queue_types		= CPPI41_FREE_DESC_BUF_QUEUE |
+					  CPPI41_UNASSIGNED_QUEUE,
+		.base_fdbq_num		= 0,
+		.assigned		= assigned_queues
+	}
+};
+EXPORT_SYMBOL(cppi41_queue_mgr);
+
+const u8 cppi41_num_queue_mgr = 1;
+const u8 cppi41_num_dma_block = 1;
+
+/* Fair DMA scheduling */
+static const u8 dma_sched_table[] = {
+	0x00, 0x80, 0x01, 0x81, 0x02, 0x82, 0x03, 0x83
+};
+
+int __init da8xx_cppi41_init(void)
+{
+	struct clk *usb20_clk;
+	int ret;
+
+	/* CPPI 4.1 is clocked by USB 2.0 clock. */
+	usb20_clk = clk_get(NULL, "usb20");
+	if (IS_ERR(usb20_clk)) {
+		ret = PTR_ERR(usb20_clk);
+		pr_warning("%s: clk_get() call failed: %d\n", __func__, ret);
+		return ret;
+	}
+	clk_enable(usb20_clk);
+
+	/* We provide no memory for the queue manager's linking RAM region 0. */
+	ret = cppi41_queue_mgr_init(0, 0, 0);
+	if (ret) {
+		pr_warning("%s: queue manager initialization failed: %d\n",
+			   __func__, ret);
+		return ret;
+	}
+
+	/* Allocate 32 (2^5) DMA teardown descriptors from queue manager 0. */
+	ret = cppi41_dma_ctrlr_init(0, 0, 5);
+	if (ret) {
+		pr_warning("%s: DMA controller initialization failed: %d\n",
+			   __func__, ret);
+		return ret;
+	}
+
+	ret = cppi41_dma_sched_init(0, dma_sched_table,
+				    sizeof(dma_sched_table));
+	if (ret)
+		pr_warning("%s: DMA scheduler initialization failed: %d\n",
+			   __func__, ret);
+	return ret;
+}
 #endif	/* CONFIG_DAVINCI_DA8XX */

From sshtylyov at ru.mvista.com  Sat May 15 13:23:52 2010
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Sat, 15 May 2010 22:23:52 +0400
Subject: [PATCH v3 3/3] DA8x0 EVM: CPPI 4.1 initialization
Message-ID: <201005152223.52448.sshtylyov@ru.mvista.com>

Initialize the CPPI 4.1 subsystem.

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>

---
The patch is against the recent DaVinci tree.

Changes from the previous version:
- made apply in the new context...

 arch/arm/mach-davinci/board-da830-evm.c |    2 ++
 arch/arm/mach-davinci/board-da850-evm.c |    2 ++
 2 files changed, 4 insertions(+)

Index: linux-davinci/arch/arm/mach-davinci/board-da830-evm.c
===================================================================
--- linux-davinci.orig/arch/arm/mach-davinci/board-da830-evm.c
+++ linux-davinci/arch/arm/mach-davinci/board-da830-evm.c
@@ -502,6 +502,8 @@ static __init void da830_evm_init(void)
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	int ret;
 
+	da8xx_cppi41_init();
+
 	ret = da8xx_register_edma();
 	if (ret)
 		pr_warning("da830_evm_init: edma registration failed: %d\n",
Index: linux-davinci/arch/arm/mach-davinci/board-da850-evm.c
===================================================================
--- linux-davinci.orig/arch/arm/mach-davinci/board-da850-evm.c
+++ linux-davinci/arch/arm/mach-davinci/board-da850-evm.c
@@ -616,6 +616,8 @@ static __init void da850_evm_init(void)
 {
 	int ret;
 
+	da8xx_cppi41_init();
+
 	ret = pmic_tps65070_init();
 	if (ret)
 		pr_warning("da850_evm_init: TPS65070 PMIC init failed: %d\n",

From zhangke839 at sohu.com  Sat May 15 21:13:41 2010
From: zhangke839 at sohu.com (zhangke839 at sohu.com)
Date: Sun, 16 May 2010 02:13:41 GMT
Subject: =?utf-8?b?5Zue5aSNOiBDRENFOTQ5IHByb2dyYW1taW5n?=
In-Reply-To: <17475750.67021273917588623.JavaMail.weblogic@epml07>
Message-ID: <1273976021.6e212334bad34c3baaabe4f72a01f69d.zhangke839@sohu.com>

Generic Configuration Register 6&nbsp;bit 0:
&nbsp;Initiate EEPROM Write Cycle(4) (9)0 EEWRITE 0b 0 ? no EEPROM write cycle1 ? start EEPROM write cycle (internal configuration register are saved to the EEPROM)
&nbsp;
&nbsp;
The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are written into the EEPROM.The EEWRITE cycle is initiated by the rising edge of the EEWRITE-Bit. A static level high does not trigger an EEPROM WRITE cycle.The EEWRITE-Bit must be reset low after the programming is completed. The programming status can be monitored by readout EEPIP.If EELOCK is set high, no EEPROM programming will be possible.



----- ?? ----- ???: Jaya krishnan ???: CDCE949 programming???: 2010?5?15? 17:59:48???: jaeyeon.park at samsung.com, &nbsp;kjw.koo at samsung.com, &nbsp;
HiI want to use cdce949 clock synthesizer to generate high frequency clocks to be used as master clock for a DAC chip.I used TI clock pro software (as local) to generate the Hex file and this Hex file (which contain register values) is used in a linux module to control the PLLs. The problem is , the new register values are not getting loaded into the internal EEPROM. Does anybody have any clues?RegardsJKJayakrishnan M MResearch EngineerR&amp;D Team-2 , Group-5Security Solutions DivisionSAMSUNG TECHWIN CO.,LTDTEL +82-70-7147-8482FAX +82-31-8018-3712Mobile +82-10-6409-3619E-mail:jaya.krishnan at samsung.com_______________________________________________Davinci-linux-open-source mailing listDavinci-linux-open-source at linux.davincidsp.comhttp://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
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From Wee-chang.Liew at leica-microsystems.com  Sun May 16 15:01:38 2010
From: Wee-chang.Liew at leica-microsystems.com (Wee-chang.Liew at leica-microsystems.com)
Date: Mon, 17 May 2010 04:01:38 +0800
Subject: Wee-chang Liew is out of the office.
Message-ID: <OF6F21B97C.FD44A544-ON48257725.006E0348-48257725.006E0348@leica-microsystems.com>


I will be out of the office starting  17-05-2010 and will not return until
26-05-2010.

I will respond to your message when I return.


______________________________________________________________________
This email has been scanned by the MessageLabs Email Security System.
For more information please visit http://www.messagelabs.com/email 
______________________________________________________________________

From david-b at pacbell.net  Sun May 16 20:23:02 2010
From: david-b at pacbell.net (David Brownell)
Date: Sun, 16 May 2010 18:23:02 -0700 (PDT)
Subject: WARNING: at drivers/gpio/gpiolib.c:1288 __gpio_get_value
In-Reply-To: <4BE7EE7F.3040402@gmail.com>
Message-ID: <64418.1102.qm@web180315.mail.gq1.yahoo.com>


> 
> I'm getting this Warning littered everywhere in my Kernel
> Bootlog... (arago-2.6.32-rc2 dm365)
> 
> Does anyone understand why the GPIO lib thinks it needs to
> WARN_ON?
> 
> ? WARN_ON(extra_checks &&
> chip->can_sleep);
> 
> Is this just overkill warnings ? or are they legitimate?

The warning means that you enabled debugging, and that the GPIO
you're accessing through the spinlock-safe call may need to sleep.

So yes, legit:  callers expect no sleeping via those calls.

Presuming those GPIOs can really block (canonical example being needing to go over I2C or SPI), the bug is in the caller not using the cansleep() variants, and/or possibly being mis-structured.


From ajay.gupta at ti.com  Sun May 16 23:58:12 2010
From: ajay.gupta at ti.com (Gupta, Ajay Kumar)
Date: Mon, 17 May 2010 10:28:12 +0530
Subject: [PATCH RFC v8] MUSB: DA8xx/OMAP-L1x glue layer
In-Reply-To: <201005122212.11729.sshtylyov@ru.mvista.com>
References: <201005122212.11729.sshtylyov@ru.mvista.com>
Message-ID: <19F8576C6E063C45BE387C64729E7394044E53516A@dbde02.ent.ti.com>

Hi,
> Subject: [PATCH RFC v8] MUSB: DA8xx/OMAP-L1x glue layer
> 
> Texas Instruments DA8xx/OMAP-L1x glue layer for the MUSBMHRDC driver.
> 
> Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
> Signed-off-by: Yadviga Grigorieva <yadviga at ru.mvista.com>
> 
> ---
> The patch is against the recent Linus' tree.
> 
> WARNING: the MUSB and OHCI drivers will only work if your boot loader
> leaves
> the DA8xx boot configuration registers unlocked, otherwise they will lock
> up
> the kernel!
> 
> Changes since the previous version:
> - removed DMA related code (to be added back by a later patch);
> - removed spurious interrupt message from da8xx_interrupt();
> - added a check for USB 1.1 being clocked from USB 2.0 PHY to phy_off();
> - moved USB register #define's from cppi41_dma.h in another patch, adding
>   'DA8XX_' prefix to them;
> - s/DA8XX_[RT]X_EP_MASK/DA8XX_USB_[RT]X_EP_MASK/, s/DA8XX_[RT]X_INTR_MASK/
>   DA8XX_INTR_[RT]X_MASK/, also reordered these macros;
> - used IO_ADDRESS() macro in #define CFGCHIP2 to avoid having to export
>   'da8xx_syscfg0_base' for modular build;
> - removed setting 'musb->is_active' from the code handling DRVVBUS
> interrupt;
> - moved the transceiver initialization further down in
> musb_platform_init();
> - moved s/ARCH_DAVINCI/ARCH_DAVINCI_DMx/ change into the separate patch;
> - fixed up some comments;
> - fixed reject in musb_core.h...
> 
>  drivers/usb/musb/Kconfig     |    5
>  drivers/usb/musb/Makefile    |    4
>  drivers/usb/musb/da8xx.c     |  492
> +++++++++++++++++++++++++++++++++++++++++++
>  drivers/usb/musb/musb_core.h |    1
>  4 files changed, 501 insertions(+), 1 deletion(-)
[...]

> +int __init musb_platform_init(struct musb *musb)

I just saw a patch in Greg's queue changing signature of this function
so better create the patch against [linus's tree + all patches in Greg's
queue] to avoid any compilation error with this patch. I am also doing
the same for AM35x patches.

Ajay

> +{
> +	void __iomem *reg_base = musb->ctrl_base;
> +	u32 rev;
[...]

From vij_soni at yahoo.com  Mon May 17 01:05:47 2010
From: vij_soni at yahoo.com (Vijay Soni)
Date: Sun, 16 May 2010 23:05:47 -0700 (PDT)
Subject: Symbol names in kernel Oops
Message-ID: <970207.16587.qm@web38805.mail.mud.yahoo.com>

How I can get symbols names from their addresses. I am trying to debug an kernel oops which gives function addresses in the Backtrace . I know I can turn on KALLSYMS but at this time I cannot rebuild my kernel because of other module dependency. Can we get this info from vmlinux? If so how?


      
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From lamiaposta71 at gmail.com  Mon May 17 01:31:48 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Mon, 17 May 2010 08:31:48 +0200
Subject: DM355 codecs on recent kernel[was Re: Porting DSPLink and CMem to
	newer Linux Kernel(...)]
In-Reply-To: <201003251936.24193.rsanchezs@infoglobal.es>
References: <818EF96F5A7CC84789DD014773DB09548F1EB943@dlee01.ent.ti.com>
	<201003251804.10123.rsanchezs@infoglobal.es>
	<20100325183214.GT2451@ramuh>
	<201003251936.24193.rsanchezs@infoglobal.es>
Message-ID: <AANLkTinaMuTb2sNjdMrZLuwh7lNLyfdBF048ylZTDVTp@mail.gmail.com>

Hi,
I'm doing the same work for dm365.
Looking at Arago or Openembedded I see that codecs are built against Arago
kernel, but I moved to 2.6.34 git kernel a month ago.
Now, building dvsdk changing Rules.make pointing to git kernel I see
obviously some errors due to different defines.

I have evm-dm365 with arago kernel and dvsdk working.
I'm changing hardware and kernel and so I need to rebuild dvsdk fixing
compilation issues.
Are there any dvsdk patches available or a git tree?
I think at dvsdk as a whole so a git tree should be a good idea?

I looked at Openembedded/Arago, but there is not a clear match with dvdsdk
packages versions.

Any help is appreciated,
Raffaele

2010/3/25 Ra?l S?nchez Siles <rsanchezs at infoglobal.es>

>  Thank you very much for this answer.
>
> El Jueves, 25 de Marzo de 2010 19:32:14 Steve Poulsen escribi?:
> > Yes, we used the TI provided codecs.  We needed to give the
> > capture/display drivers a workover and some ALSA mods, but the codec
> > engine seemed to be fine.  A complete build of everything against the new
> > kernel was in order.
> >
> > We are using MPEG-4 encode/decode and have not tried the JPEG codec.
> > Also, there was some work done to CMEM to support memory mapping.  Also,
> > the RSZCOPY needed some changes.
> >
> > Now that I recall, the DMA enable/disable masks for the board needed to
> be
> > changed so that the kernel did not hand out DMAs that are in use by the
> > codecs.
> >
> > Steve
> >
> > On Thu, Mar 25, 2010 at 06:04:09PM +0100, Ra?l S?nchez Siles wrote:
> > >   Hello:
> > >
> > > El Jueves, 25 de Marzo de 2010 12:16:34 Steve Poulsen escribi?:
> > > > Bin,
> > > >
> > > > We have the DVSDK running on kernel 2.6.28 for a DM355 project.  We
> > > > made some changes made to the memory mapping of Cmem for the newer
> > > > kernel. The changes are not large nor difficult.  We did not change
> > > > DSPLink at all for the newer kernel.
> > >
> > >   Did you use the TI provided video codecs, for instance the mpeg4
> codec?
> > > and in this case, did you need to do anything special to make them
> work?
> > >
> > >   Thanks
> > >
> > > > Steve
> > > >
> > > > On 03/24/2010 03:20 PM, Zhou, Bin wrote:
> > > > > Hi,
> > > > >
> > > > > TI DSPLink and Cmem supports kernel 2.6.18. If anybody ported them
> to
> > > > > a newer kernel (say some version close to 2.6.33), could you please
> > > > > share some porting experience?
> > > > >
> > > > > Thanks in advance.
> > > > >
> > > > > Bin
> >
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>



-- 
www.opensurf.it
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From linxiao.li at gmail.com  Mon May 17 02:07:10 2010
From: linxiao.li at gmail.com (Linxiao)
Date: Mon, 17 May 2010 15:07:10 +0800
Subject: Symbol names in kernel Oops
In-Reply-To: <970207.16587.qm@web38805.mail.mud.yahoo.com>
References: <970207.16587.qm@web38805.mail.mud.yahoo.com>
Message-ID: <AANLkTikfLp-ckkelA4vwIKDx6sgzmTc_4RIWvixFboag@mail.gmail.com>

Try this command:

$ arm_v5t_le-nm vmlinux     # or just using nm vmlinux

On Mon, May 17, 2010 at 2:05 PM, Vijay Soni <vij_soni at yahoo.com> wrote:

> How I can get symbols names from their addresses. I am trying to debug an
> kernel oops which gives function addresses in the Backtrace . I know I can
> turn on KALLSYMS but at this time I cannot rebuild my kernel because of
> other module dependency. Can we get this info from vmlinux? If so how?
>
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>
>


-- 
leal @ http://linxiao.net
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From magnus at alefors.se  Mon May 17 02:17:37 2010
From: magnus at alefors.se (Magnus H)
Date: Mon, 17 May 2010 09:17:37 +0200
Subject: UBL needs to be loaded twice over UART on dm365
Message-ID: <00bf01caf591$078fad40$16af07c0$@se>

Hi. I'm successfully booting Linux over uart and tftp without using any
flash but there is one annoying thing left to fix. The first time after a
reset the slt_DM36x.bin is loaded it doesn't work and writes this on the
console:

8==Q5 BOOTME BOOTME BOOTME ....

The I use dv_host to load slt_DM36x.bin again and then it works as expected
and writes BOOTUBL and I can download u-boot and my Linux system. Any ideas
why the ubl doesn't work the first time? Using slh_DM36x.exe gives the same
result, I have to run it twice.

/Magnus H



From nsekhar at ti.com  Mon May 17 05:06:17 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Mon, 17 May 2010 15:36:17 +0530
Subject: UBL needs to be loaded twice over UART on dm365
In-Reply-To: <00bf01caf591$078fad40$16af07c0$@se>
References: <00bf01caf591$078fad40$16af07c0$@se>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6F97222@dbde02.ent.ti.com>


Hi Magnus,

On Mon, May 17, 2010 at 12:47:37, Magnus H wrote:
> Hi. I'm successfully booting Linux over uart and tftp without using any
> flash but there is one annoying thing left to fix. The first time after a
> reset the slt_DM36x.bin is loaded it doesn't work and writes this on the
> console:
>
> 8==Q5 BOOTME BOOTME BOOTME ....
>
> The I use dv_host to load slt_DM36x.bin again and then it works as expected
> and writes BOOTUBL and I can download u-boot and my Linux system. Any ideas
> why the ubl doesn't work the first time? Using slh_DM36x.exe gives the same
> result, I have to run it twice.

Most probably this is because of UBL resetting itself to
workaround 'Advisory 1.2.1' in http://focus.ti.com/lit/er/sprz316/sprz316.pdf

Thanks,
Sekhar

From nsekhar at ti.com  Mon May 17 05:21:48 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Mon, 17 May 2010 15:51:48 +0530
Subject: CDCE949 programming
In-Reply-To: <17475750.67021273917588623.JavaMail.weblogic@epml07>
References: <17475750.67021273917588623.JavaMail.weblogic@epml07>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6F97279@dbde02.ent.ti.com>

Hi JK,

On Sat, May 15, 2010 at 15:29:48, Jaya krishnan wrote:
> Hi
>          I want  to use cdce949  clock  synthesizer  to generate  high frequency  clocks to be  used  as  master  clock  for a DAC  chip.
> I used TI  clock pro  software  (as local)  to generate the Hex  file and this Hex  file (which contain register values) is  used in a linux module
> to control the PLLs. The problem is , the new  register  values  are not getting loaded into the  internal EEPROM. Does  anybody have any clues?

There is a cdce949 'driver' in Kevin's tree which uses I2C to program
the CDCE949 and fits into the clock framework (arch/arm/mach-davinci/cdce949.c)

Can you consider using/extending this driver?

Thanks,
Sekhar


From kieranbingham at gmail.com  Mon May 17 06:00:07 2010
From: kieranbingham at gmail.com (Kieran Bingham)
Date: Mon, 17 May 2010 12:00:07 +0100
Subject: WARNING: at drivers/gpio/gpiolib.c:1288 __gpio_get_value
In-Reply-To: <64418.1102.qm@web180315.mail.gq1.yahoo.com>
References: <64418.1102.qm@web180315.mail.gq1.yahoo.com>
Message-ID: <4BF121B7.6030204@gmail.com>

Aha,

Starting to make sense - I'd not found the _cansleep variants.

We have some buttons and LEDs attached to an I2C GPIO expander ( using 
the pca953x driver )
We'd taken a copy of the input/keyboard/gpio_keys.c as a way of 
implementing button events tied to the physical buttons.

I've changed the reads to use the _cansleep variants :)
The calls occur in a scheduled_task() following from the ISR - so I 
don't believe it matters that they sleep.

Thanks for your help
Regards
--
Kieran

David Brownell wrote:
>> I'm getting this Warning littered everywhere in my Kernel
>> Bootlog... (arago-2.6.32-rc2 dm365)
>>
>> Does anyone understand why the GPIO lib thinks it needs to
>> WARN_ON?
>>
>>   WARN_ON(extra_checks &&
>> chip->can_sleep);
>>
>> Is this just overkill warnings ? or are they legitimate?
>>     
>
> The warning means that you enabled debugging, and that the GPIO
> you're accessing through the spinlock-safe call may need to sleep.
>
> So yes, legit:  callers expect no sleeping via those calls.
>
> Presuming those GPIOs can really block (canonical example being needing to go over I2C or SPI), the bug is in the caller not using the cansleep() variants, and/or possibly being mis-structured.
>
>
>   


From kieranbingham at gmail.com  Mon May 17 06:08:56 2010
From: kieranbingham at gmail.com (Kieran Bingham)
Date: Mon, 17 May 2010 12:08:56 +0100
Subject: Davinci MUSB/USB Driver @ 12Mbps
Message-ID: <4BF123C8.1080308@gmail.com>

Hi Guys,

We are having some USB issues on our davinci platform, and the hardware 
guys have asked if I can slow the bus down to 12Mbps for them to perform 
some testing.

Is this possible using the davinci musb driver on the Arago-2.6.32-rc2?

Regards
Kieran Bingham

From swami.iyer at ti.com  Mon May 17 09:57:57 2010
From: swami.iyer at ti.com (Subbrathnam, Swaminathan)
Date: Mon, 17 May 2010 20:27:57 +0530
Subject: Davinci MUSB/USB Driver @ 12Mbps
In-Reply-To: <4BF123C8.1080308@gmail.com>
References: <4BF123C8.1080308@gmail.com>
Message-ID: <FCCFB4CDC6E5564B9182F639FC3560870303E763CC@dbde02.ent.ti.com>

Kieran,

Pl. remove the HSENAB define in the musb_core.c file.

regards
swami

________________________________________
From: davinci-linux-open-source-bounces at linux.davincidsp.com [davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Kieran Bingham [kieranbingham at gmail.com]
Sent: Monday, May 17, 2010 4:38 PM
To: davinci-linux-open-source at linux.davincidsp.com
Subject: Davinci MUSB/USB Driver @ 12Mbps

Hi Guys,

We are having some USB issues on our davinci platform, and the hardware
guys have asked if I can slow the bus down to 12Mbps for them to perform
some testing.

Is this possible using the davinci musb driver on the Arago-2.6.32-rc2?

Regards
Kieran Bingham
_______________________________________________
Davinci-linux-open-source mailing list
Davinci-linux-open-source at linux.davincidsp.com
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source

From kieranbingham at gmail.com  Mon May 17 12:08:41 2010
From: kieranbingham at gmail.com (Kieran Bingham)
Date: Mon, 17 May 2010 18:08:41 +0100
Subject: Davinci MUSB/USB Driver @ 12Mbps
In-Reply-To: <FCCFB4CDC6E5564B9182F639FC3560870303E763CC@dbde02.ent.ti.com>
References: <4BF123C8.1080308@gmail.com>
	<FCCFB4CDC6E5564B9182F639FC3560870303E763CC@dbde02.ent.ti.com>
Message-ID: <4BF17819.8000303@gmail.com>

Subbrathnam, Swaminathan wrote:
> Kieran,
>
> Pl. remove the HSENAB define in the musb_core.c file.
>
> regards
> swami
>
>   
I've just tried as you suggested modifying musb_core.c : line 846

    /* put into basic highspeed mode and start session */
    musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
                        | MUSB_POWER_SOFTCONN
                    /*    | MUSB_POWER_HSENAB *****KPB: Prevent HSENAB 
***** */
                        /* ENSUSPEND wedges tusb */
                        /* | MUSB_POWER_ENSUSPEND */
                        );

However, this seems to have converted my Host controller - into a 
Peripheral Controller ... is this right ?


cat /proc/driver_musb_hdrc
Status: MHDRC, Mode=Peripheral (Power=d0, DevCtl=98)
OTG state: b_idle; inactive
Options: cppi-dma, host, debug=3 [eps=5]
Root port status: 00000401
DaVinci: ctrl=00 stat=0 phy=21e0
        rndis=00000 auto=0000 intsrc=00000000 intmsk=01ff1e1f
CPPI: txcr=1 txsrc=0 txena=f; rxcr=1 rxsrc=0 rxena=f


I now find that none of my attached devices are enumerating! :(


Without effecting the HSENAB bit - I get the following debug out from 
the musb_hdrc file

Status: MHDRC, Mode=Host (Power=f0, DevCtl=5d)
OTG state: a_host; active
Options: cppi-dma, host, debug=3 [eps=5]
Root port status: 00000503
DaVinci: ctrl=00 stat=1 phy=21e0
        rndis=00000 auto=0000 intsrc=00000000 intmsk=01ff1e1f
CPPI: txcr=1 txsrc=0 txena=f; rxcr=1 rxsrc=0 rxena=f

RX4: 1buf rxcsr 3020 interval 0c max 0001 type 71; dev 2 hub 0 port 0
    rx dma3: 3 left, 00000000 84ab70e0, 84ab70e0 84ab70e0; 84a67021 
00010000 00000001 .. 84ab70e0
    qh c27fb3e0 dev2 ep1-int max1
        in urb c4ab8ec0 0/1


--
Regards
Kieran
> ________________________________________
> From: davinci-linux-open-source-bounces at linux.davincidsp.com [davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Kieran Bingham [kieranbingham at gmail.com]
> Sent: Monday, May 17, 2010 4:38 PM
> To: davinci-linux-open-source at linux.davincidsp.com
> Subject: Davinci MUSB/USB Driver @ 12Mbps
>
> Hi Guys,
>
> We are having some USB issues on our davinci platform, and the hardware
> guys have asked if I can slow the bus down to 12Mbps for them to perform
> some testing.
>
> Is this possible using the davinci musb driver on the Arago-2.6.32-rc2?
>
> Regards
> Kieran Bingham
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>   


From nsekhar at ti.com  Tue May 18 00:24:49 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Tue, 18 May 2010 10:54:49 +0530
Subject: [RFC 1/4] Davinci: mdio - separate out mdio controller code
In-Reply-To: <1273876947-30711-2-git-send-email-cyril@ti.com>
References: <1273876947-30711-1-git-send-email-cyril@ti.com>
	<1273876947-30711-2-git-send-email-cyril@ti.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E6F97620@dbde02.ent.ti.com>

Hi Cyril,

On Sat, May 15, 2010 at 04:12:24, Chemparathy, Cyril wrote:
> Davinci's MDIO controller is present on other TI devices, without an
> accompanying EMAC.  For example, on tnetv107x, the same MDIO module is used in
> conjunction with a 3-port switch hardware.
>
> By separating the MDIO controller code into its own platform driver, this
> patch allows common logic to be reused on such platforms.
>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> ---
>  drivers/net/Kconfig        |   10 ++
>  drivers/net/Makefile       |    1 +
>  drivers/net/davinci_mdio.c |  388 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 399 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/net/davinci_mdio.c
>

[...]

> diff --git a/drivers/net/davinci_mdio.c b/drivers/net/davinci_mdio.c
> new file mode 100644
> index 0000000..0a2c265
> --- /dev/null
> +++ b/drivers/net/davinci_mdio.c
> @@ -0,0 +1,388 @@
> +/*
> + * DaVinci MDIO Module driver
> + *
> + * Copyright (C) 2010 Texas Instruments.
> + *
> + * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
> + *
> + * Copyright (C) 2009 Texas Instruments.
> + *
> + * ---------------------------------------------------------------------------
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + * ---------------------------------------------------------------------------
> + */
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/platform_device.h>
> +#include <linux/delay.h>
> +#include <linux/sched.h>
> +#include <linux/slab.h>
> +#include <linux/phy.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +
> +#define PHY_REG_MASK         0x1f
> +#define PHY_ID_MASK          0x1f
> +
> +#define MDIO_OUT_FREQ                1100000         /* 2.2 MHz */

The comment says 2.2 MHz, but the value is 1.1 MHz?

Also, can you keep this as a platform variable (with
a 2.2 MHz default)? The frequency depends on the board,
and although most boards work at 2.2 MHz, not having it
as a platform variable will make adding a board with a
different frequency requirement difficult.

> +
> +struct davinci_mdio_regs {
> +     u32     version;
> +     u32     control;
> +#define CONTROL_IDLE         BIT(31)
> +#define CONTROL_ENABLE               BIT(30)
> +#define CONTROL_MAX_DIV              (0xff)
> +
> +     u32     alive;
> +     u32     link;
> +     u32     linkintraw;
> +     u32     linkintmasked;
> +     u32     __reserved_0[2];
> +     u32     userintraw;
> +     u32     userintmasked;
> +     u32     userintmaskset;
> +     u32     userintmaskclr;
> +     u32     __reserved_1[20];
> +
> +     struct {
> +             u32     access;
> +#define USERACCESS_GO                BIT(31)
> +#define USERACCESS_WRITE     BIT(30)
> +#define USERACCESS_ACK               BIT(29)
> +#define USERACCESS_READ              (0)
> +#define USERACCESS_DATA              (0xffff)
> +
> +             u32     physel;
> +     }       user[0];
> +};

Structure overlays are usually not preferred and
is difficult to debug. Can you please keep the
direct register access method that was being
followed in the original driver?

> +
> +struct davinci_mdio_data {
> +     struct davinci_mdio_regs __iomem *regs;
> +     spinlock_t      lock;
> +     struct clk      *clk;
> +     struct device   *dev;
> +     struct mii_bus  *bus;
> +     bool            suspended;
> +};
> +
> +/* wait until hardware is ready for another user access */
> +static inline u32 wait_for_user_access(struct davinci_mdio_data *data)
> +{
> +     struct davinci_mdio_regs __iomem *regs = data->regs;
> +     u32 reg;
> +
> +     while ((reg = __raw_readl(&regs->user[0].access)) & USERACCESS_GO)
> +             ;

I know the original code had this issue too, but there should be a
timeout here to avoid permanent lockup. Also, a cpu_relax() while
looping tight.

> +
> +     return reg;
> +}
> +
> +/* wait until hardware state machine is idle */
> +static inline void wait_for_idle(struct davinci_mdio_data *data)
> +{
> +     struct davinci_mdio_regs __iomem *regs = data->regs;
> +
> +     while ((__raw_readl(&regs->control) & CONTROL_IDLE) == 0)
> +             ;

Same as above.

> +}
> +
> +static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
> +{
> +     struct davinci_mdio_data *data = bus->priv;
> +     u32 reg;
> +
> +     if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
> +             return -EINVAL;
> +
> +     spin_lock(&data->lock);

The mdiobus serializes the bus access anyway so is this
lock really needed?

> +
> +     if (data->suspended) {
> +             spin_unlock(&data->lock);
> +             return -ENODEV;
> +     }

Hmm, the devices should be suspended before the bus is.
So, there should probably be a WARN_ON() here since this
indicates some issue elsewhere in the system.

Or may be this is too paranoid and can be rid of altogether?

> +
> +     wait_for_user_access(data);
> +     reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
> +            (phy_id << 16));
> +     __raw_writel(reg, &data->regs->user[0].access);
> +     reg = wait_for_user_access(data);
> +     spin_unlock(&data->lock);
> +
> +     return (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
> +}
> +
> +static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
> +                           int phy_reg, u16 phy_data)
> +{
> +     struct davinci_mdio_data *data = bus->priv;
> +     u32 reg;
> +
> +     if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
> +             return -EINVAL;
> +
> +     spin_lock(&data->lock);
> +
> +     if (data->suspended) {
> +             spin_unlock(&data->lock);
> +             return -ENODEV;
> +     }
> +
> +     wait_for_user_access(data);
> +     reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
> +                (phy_id << 16) | (phy_data & USERACCESS_DATA));
> +     __raw_writel(reg, &data->regs->user[0].access);
> +     wait_for_user_access(data);
> +     spin_unlock(&data->lock);
> +
> +     return 0;
> +}
> +
> +static inline int count_bits(u32 data)
> +{
> +     data = ((data & 0xaaaaaaaa) >>  1) + (data & 0x55555555);
> +     data = ((data & 0xcccccccc) >>  2) + (data & 0x33333333);
> +     data = ((data & 0xf0f0f0f0) >>  4) + (data & 0x0f0f0f0f);
> +     data = ((data & 0xff00ff00) >>  8) + (data & 0x00ff00ff);
> +     data = ((data & 0xffff0000) >> 16) + (data & 0x0000ffff);
> +     return data;
> +}

Kernel already has a function to calculate the hamming weight
on u32. See hweight32() in lib/hweight.c

> +
> +static int __devinit davinci_mdio_probe(struct platform_device *pdev)
> +{
> +     struct device *dev = &pdev->dev;
> +     struct davinci_mdio_data *data;
> +     struct resource *res;
> +     u32 mdio_in_freq, mdio_out_freq, div, phy_mask, ver;
> +     struct phy_device *phy;
> +     int ret, addr;
> +
> +     data = kzalloc(sizeof(*data), GFP_KERNEL);
> +     if (!data) {
> +             dev_err(dev, "failed to alloc device data\n");
> +             return -ENOMEM;
> +     }
> +
> +     data->bus = mdiobus_alloc();
> +     if (!data->bus) {
> +             dev_err(dev, "failed to alloc mii bus\n");
> +             ret = -ENOMEM;
> +             goto bail_out;
> +     }
> +
> +     data->bus->name         = dev_name(dev);
> +     data->bus->read         = davinci_mdio_read,
> +     data->bus->write        = davinci_mdio_write,
> +     data->bus->parent       = dev;
> +     data->bus->priv         = data;
> +     snprintf(data->bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
> +
> +     data->clk = clk_get(dev, NULL);
> +     if (IS_ERR(data->clk)) {
> +             data->clk = NULL;
> +             dev_err(dev, "failed to get device clock\n");
> +             ret = PTR_ERR(data->clk);
> +             goto bail_out;
> +     }
> +
> +     clk_enable(data->clk);
> +
> +     dev_set_drvdata(dev, data);
> +     data->dev = dev;
> +     spin_lock_init(&data->lock);
> +
> +     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +     if (!res) {
> +             dev_err(dev, "could not find register map resource\n");
> +             ret = -ENOENT;
> +             goto bail_out;
> +     }
> +
> +     res = devm_request_mem_region(dev, res->start, resource_size(res),
> +                                         dev_name(dev));
> +     if (!res) {
> +             dev_err(dev, "could not allocate register map resource\n");
> +             ret = -ENXIO;
> +             goto bail_out;
> +     }
> +
> +     data->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
> +     if (!data->regs) {
> +             dev_err(dev, "could not map mdio registers\n");
> +             ret = -ENOMEM;
> +             goto bail_out;
> +     }
> +
> +     mdio_in_freq = clk_get_rate(data->clk);
> +     div = (mdio_in_freq / MDIO_OUT_FREQ) - 1;
> +     if (div > CONTROL_MAX_DIV)
> +             div = CONTROL_MAX_DIV;

Hmm, just wondering if it is safe to just default on
the max possible value? It could be a result of an issue
elsewhere and so should be reported?

> +     mdio_out_freq = mdio_in_freq / (div + 1);
> +
> +     /* set enable and clock divider */
> +     __raw_writel(div | CONTROL_ENABLE, &data->regs->control);
> +
> +     /*
> +      * wait for scan logic to settle:
> +      * the scan time consists of (a) a large fixed component, and (b) a
> +      * small component that varies with the mii bus frequency.  These
> +      * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
> +      * silicon.  Since the effect of (b) was found to be largely
> +      * negligible, we keep things simple here.
> +      */
> +     mdelay(1);
> +
> +     /* dump hardware version info */
> +     ver = __raw_readl(&data->regs->version);
> +     dev_info(dev, "davinci mdio revision %d.%d\n",
> +                     (ver >> 8) & 0xff, ver & 0xff);
> +
> +     /* get phy mask from the alive register */
> +     phy_mask = __raw_readl(&data->regs->alive);
> +     if (phy_mask) {
> +             /* restrict mdio bus to live phys only */
> +             dev_info(dev, "detected %d phys (mask %x)\n",
> +                      count_bits(phy_mask), ~phy_mask);
> +             phy_mask = ~phy_mask;
> +     } else {
> +             /* desperately scan all phys */
> +             dev_warn(dev, "failed to detect live phys, scanning all\n");
> +             phy_mask = 0;

phy_mask is already zero.

> +     }
> +     data->bus->phy_mask = phy_mask;

Looks like phy_mask local variable can be eliminated?

> +
> +     /* register the mii bus */
> +     ret = mdiobus_register(data->bus);
> +     if (ret)
> +             goto bail_out;
> +
> +     /* scan and dump the bus */
> +     for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
> +             phy = data->bus->phy_map[addr];
> +             if (phy) {
> +                     dev_info(dev, "phy[%d]: device %s, driver %s\n",
> +                              phy->addr, dev_name(&phy->dev),
> +                              phy->drv ? phy->drv->name : "unknown");
> +             }
> +     }
> +
> +     return 0;
> +
> +bail_out:
> +     if (data->bus)
> +             mdiobus_free(data->bus);
> +
> +     if (data->clk) {
> +             clk_disable(data->clk);
> +             clk_put(data->clk);
> +     }
> +
> +     kfree(data);
> +
> +     return 0;

return ret?

Thanks,
Sekhar

From vij_soni at yahoo.com  Tue May 18 00:40:30 2010
From: vij_soni at yahoo.com (Vijay Soni)
Date: Mon, 17 May 2010 22:40:30 -0700 (PDT)
Subject: sd card eject and reinsert while files being written to the card
Message-ID: <968427.37982.qm@web38805.mail.mud.yahoo.com>

I am having an issue with sd card in the scenario when it is ejected out and reinserted while files are being written to it. My application is always writing 3-4 files to the card and when device node is removed(on ejection), the application unmounts the mmc/sd and when the device nodes comes back again (on reinsert) , it mounts the mmc/sd and continues with recording. But I am getting kernel Oops on removing the card in the mmc queue thread.
Anybody with ideas?


      
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From deepali at ti.com  Tue May 18 05:32:20 2010
From: deepali at ti.com (Uppal, Deepali)
Date: Tue, 18 May 2010 16:02:20 +0530
Subject: Linux patch for CHIPINT Errata in davinci SoC's?
In-Reply-To: <B85A65D85D7EB246BE421B3FB0FBB59301E6F97971@dbde02.ent.ti.com>
References: <2A3DCF3DA181AD40BDE86A3150B27B6B030D99150C@dbde02.ent.ti.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E6F97971@dbde02.ent.ti.com>
Message-ID: <2A3DCF3DA181AD40BDE86A3150B27B6B030D991525@dbde02.ent.ti.com>

Nick

For which use case do you require the DSP->ARM signal?

Are you using DSPLink? DSPLink which is IPC software primarily uses the DSP->Arm and ARM->DSP interrupts for communication.

See further comments inline:

-----Original Message-----
 From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci- linux-
pen-
 source-bounces at linux.davincidsp.com] On Behalf Of Nick Thompson
 Sent: Friday, May 07, 2010 1:56 PM
 To: davinci-linux-open-source at linux.davincidsp.com
 Subject: Linux patch for CHIPINT Errata in davinci SoC's?

 I'm developing on the da830 and am just about to try an figure out
 a way to deal with Advisory 1.1.13 on that device:

 "A Single CHIPINTn Interrupt Event Will Register Multiple Times in
 the DSP Event Combiner Module (ECM)"

[Deepali]: DSPLink does not use the Event Combiner Module so it does not    get affected by the first issue.

 Although that description implies a problem on the DSP side, I
 think this also causes a problem on the ARM AINTC as well. da850
 errata does mention this more explicitly in Advisory 2.0.12:

 "A Single CHIPINTn Interrupt Event Can Register Multiple Times in
 the AINTC"

[Deepali]: Regarding  "A Single CHIPINTn Interrupt Event Can Register Multiple Times in  the AINTC". This might generate spurious interrupts for DSPLink but it does not affect the run time logic. The DSPLink logic which sits in the ISR sees that there is no associated DSPLink work with this interrupt and hence does nothing for the spurious interrupt. It might cause some performance impact though.

 That advisory gives a couple of workarounds which I think could
 work on da830 as well.

 So, my query: Is there a proposed Linux patch for these issues for
 all the effected platforms? Is this the real reason I'm getting
 two-for-one interrupts from the CHIPSIG[0] DSP->ARM signal on da830?
[Deepali]: Can you clarify your use case so that I can comment further on this.

 Thanks,
 Nick.
 _______________________________________________
 Davinci-linux-open-source mailing list
 Davinci-linux-open-source at linux.davincidsp.com
 http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source


From gilles.chanteperdrix at nexvision.fr  Tue May 18 07:54:56 2010
From: gilles.chanteperdrix at nexvision.fr (Gilles Chanteperdrix)
Date: Tue, 18 May 2010 14:54:56 +0200
Subject: [PATCH 0/4] Assorted davinci fixes.
Message-ID: <4BF28E20.3070701@nexvision.fr>


Hi,

while experimenting with a davinci DM368, I had a few issues which the
following patches serie try and fix.

Thanks in advance for your review.
Regards.

-- 
					    Gilles.

From gilles.chanteperdrix at nexvision.fr  Tue May 18 07:56:22 2010
From: gilles.chanteperdrix at nexvision.fr (Gilles Chanteperdrix)
Date: Tue, 18 May 2010 14:56:22 +0200
Subject: [PATCH 1/4] Install davincifb_ioctl header.
In-Reply-To: <4BF28E20.3070701@nexvision.fr>
References: <4BF28E20.3070701@nexvision.fr>
Message-ID: <1274187385-10969-1-git-send-email-gilles.chanteperdrix@nexvision.fr>

Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix at nexvision.fr>
---
 include/video/Kbuild |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/include/video/Kbuild b/include/video/Kbuild
index 0e406f7..0784677 100644
--- a/include/video/Kbuild
+++ b/include/video/Kbuild
@@ -1,2 +1,4 @@
 unifdef-y += sisfb.h uvesafb.h
 unifdef-y += edid.h
+
+header-y += davincifb_ioctl.h
-- 
1.5.6.5


From gilles.chanteperdrix at nexvision.fr  Tue May 18 07:56:24 2010
From: gilles.chanteperdrix at nexvision.fr (Gilles Chanteperdrix)
Date: Tue, 18 May 2010 14:56:24 +0200
Subject: [PATCH 3/4] davinci: Allow the OSD framebuffers to be disabled on the
	kernel command line.
In-Reply-To: <1274187385-10969-2-git-send-email-gilles.chanteperdrix@nexvision.fr>
References: <4BF28E20.3070701@nexvision.fr>
	<1274187385-10969-1-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<1274187385-10969-2-git-send-email-gilles.chanteperdrix@nexvision.fr>
Message-ID: <1274187385-10969-3-git-send-email-gilles.chanteperdrix@nexvision.fr>

Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix at nexvision.fr>
---
 drivers/video/davincifb.c |   42 ++++++++++++++++++++++--------------------
 1 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/drivers/video/davincifb.c b/drivers/video/davincifb.c
index ccb27d7..01e5220 100644
--- a/drivers/video/davincifb.c
+++ b/drivers/video/davincifb.c
@@ -1485,7 +1485,7 @@ davincifb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 	struct fb_videomode *mode = &win->dm->mode;
 	struct davinci_layer_config lconfig;
 	struct fb_fix_screeninfo fix;
-		
+
 	/*
 	 * Get an updated copy of the video mode from the encoder manager, just
 	 * in case the display has been switched.
@@ -1562,7 +1562,7 @@ davincifb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 		return -EINVAL;
 	if (lconfig.xpos != win->xpos || lconfig.ypos != win->ypos)
 		return -EINVAL;
-	
+
 	/*
 	 * At this point we have accepted the var, so now we convert our layer
 	 * configuration struct back to the var in order to make all of the
@@ -2192,8 +2192,8 @@ static void parse_win_params(struct vpbe_dm_win_info *win,
  * Pass boot-time options by adding the following string to the boot params:
  *	video=davincifb:options
  * Valid options:
- *	osd0=[MxNxP,S at X,Y]
- *      osd1=[MxNxP,S at X,Y]
+ *	osd0=[off|MxNxP,S at X,Y]
+ *      osd1=[off|MxNxP,S at X,Y]
  *	vid0=[off|MxNxP,S at X,Y]
  *	vid1=[off|MxNxP,S at X,Y]
  *		MxN are the horizontal and vertical window size
@@ -2201,8 +2201,8 @@ static void parse_win_params(struct vpbe_dm_win_info *win,
  *		S is the framebuffer size with a size suffix such as 'K' or 'M'
  *		X,Y are the window position
  *
- * Only video windows can be turned off.  Turning off a video window means that
- * no framebuffer device will be registered for it,
+ * Turning off a video window means that no framebuffer device will be
+ * registered for it,
  *
  * To cause a window to be supported by the framebuffer driver but not displayed
  * initially, pass a value of 0 for the window size.
@@ -2310,13 +2310,14 @@ static int davincifb_probe(struct device *dev)
 	dm->win[WIN_OSD0].layer = WIN_OSD0;
 	dm->win[WIN_OSD0].dm = dm;
 	dm->win[WIN_OSD0].sdram_address = 0;
-	davincifb_get_default_win_config(dev, &dm->win[WIN_OSD0], &lconfig,
-					 &fb_size, options);
-	err =
-	    davincifb_init_window(dev, &dm->win[WIN_OSD0], &lconfig, fb_size,
-				  OSD0_FBNAME);
-	if (err)
-		goto osd0_out;
+	if (!davincifb_get_default_win_config
+	    (dev, &dm->win[WIN_OSD0], &lconfig, &fb_size, options)) {
+		err =
+			davincifb_init_window(dev, &dm->win[WIN_OSD0], &lconfig,
+					      fb_size, OSD0_FBNAME);
+		if (err)
+			goto osd0_out;
+	}
 
 	/* initialize VID0 */
 	dm->win[WIN_VID0].layer = WIN_VID0;
@@ -2335,13 +2336,14 @@ static int davincifb_probe(struct device *dev)
 	dm->win[WIN_OSD1].layer = WIN_OSD1;
 	dm->win[WIN_OSD1].dm = dm;
 	dm->win[WIN_OSD1].sdram_address = 0;
-	davincifb_get_default_win_config(dev, &dm->win[WIN_OSD1], &lconfig,
-					 &fb_size, options);
-	err =
-	    davincifb_init_window(dev, &dm->win[WIN_OSD1], &lconfig, fb_size,
-				  OSD1_FBNAME);
-	if (err)
-		goto osd1_out;
+	if (!davincifb_get_default_win_config
+	    (dev, &dm->win[WIN_OSD1], &lconfig, &fb_size, options)) {
+		err =
+			davincifb_init_window(dev, &dm->win[WIN_OSD1], &lconfig,
+					      fb_size, OSD1_FBNAME);
+		if (err)
+			goto osd1_out;
+	}
 
 	/* initialize VID1 */
 	dm->win[WIN_VID1].layer = WIN_VID1;
-- 
1.5.6.5


From gilles.chanteperdrix at nexvision.fr  Tue May 18 07:56:25 2010
From: gilles.chanteperdrix at nexvision.fr (Gilles Chanteperdrix)
Date: Tue, 18 May 2010 14:56:25 +0200
Subject: [PATCH 4/4] davinci: Fix transparency handling with dm365.
In-Reply-To: <1274187385-10969-3-git-send-email-gilles.chanteperdrix@nexvision.fr>
References: <4BF28E20.3070701@nexvision.fr>
	<1274187385-10969-1-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<1274187385-10969-2-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<1274187385-10969-3-git-send-email-gilles.chanteperdrix@nexvision.fr>
Message-ID: <1274187385-10969-4-git-send-email-gilles.chanteperdrix@nexvision.fr>

Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix at nexvision.fr>
---
 drivers/media/video/davinci/davinci_osd.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/media/video/davinci/davinci_osd.c b/drivers/media/video/davinci/davinci_osd.c
index c285f99..a5fc01d 100644
--- a/drivers/media/video/davinci/davinci_osd.c
+++ b/drivers/media/video/davinci/davinci_osd.c
@@ -1231,7 +1231,7 @@ static void _davinci_disp_enable_color_key(enum davinci_osd_layer osdwin,
 	case PIXFMT_2BPP:
 	case PIXFMT_4BPP:
 	case PIXFMT_8BPP:
-		if (cpu_is_davinci_dm355()) {
+		if (cpu_is_davinci_dm355() || cpu_is_davinci_dm365()) {
 			switch (osdwin) {
 			case OSDWIN_OSD0:
 				osd_merge(OSD_TRANSPBMPIDX_BMP0,
@@ -1252,18 +1252,18 @@ static void _davinci_disp_enable_color_key(enum davinci_osd_layer osdwin,
 		if (cpu_is_davinci_dm644x()) {
 			osd_write(colorkey & OSD_TRANSPVAL_RGBTRANS,
 				  OSD_TRANSPVAL);
-		} else if (cpu_is_davinci_dm355()) {
+		} else if (cpu_is_davinci_dm355() || cpu_is_davinci_dm365()) {
 			osd_write(colorkey & OSD_TRANSPVALL_RGBL,
 				  OSD_TRANSPVALL);
 		}
 		break;
 	case PIXFMT_YCbCrI:
 	case PIXFMT_YCrCbI:
-		if (cpu_is_davinci_dm355())
+		if (cpu_is_davinci_dm355() || cpu_is_davinci_dm365())
 			osd_merge(OSD_TRANSPVALU_Y, colorkey, OSD_TRANSPVALU);
 		break;
 	case PIXFMT_RGB888:
-		if (cpu_is_davinci_dm355()) {
+		if (cpu_is_davinci_dm355() || cpu_is_davinci_dm365()) {
 			osd_write(colorkey & OSD_TRANSPVALL_RGBL,
 				  OSD_TRANSPVALL);
 			osd_merge(OSD_TRANSPVALU_RGBU, colorkey >> 16,
-- 
1.5.6.5


From gilles.chanteperdrix at nexvision.fr  Tue May 18 07:56:23 2010
From: gilles.chanteperdrix at nexvision.fr (Gilles Chanteperdrix)
Date: Tue, 18 May 2010 14:56:23 +0200
Subject: [PATCH 2/4] davinci: Update window size after enabling OSD
	zoom/expansion.
In-Reply-To: <1274187385-10969-1-git-send-email-gilles.chanteperdrix@nexvision.fr>
References: <4BF28E20.3070701@nexvision.fr>
	<1274187385-10969-1-git-send-email-gilles.chanteperdrix@nexvision.fr>
Message-ID: <1274187385-10969-2-git-send-email-gilles.chanteperdrix@nexvision.fr>

When enabling expansion or zoom, the window size must be updated. We
implement a davinci_disp_set_vid_size function computing the window
size registers from the window parameters and zoom/expansion factors,
and call it every time the framebuffer size is updated or the
zoom/expansion factors are updated.

Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix at nexvision.fr>
---
 drivers/media/video/davinci/davinci_display.c |   36 +++---
 drivers/media/video/davinci/davinci_osd.c     |  200 ++++++++++++++++---------
 2 files changed, 146 insertions(+), 90 deletions(-)

diff --git a/drivers/media/video/davinci/davinci_display.c b/drivers/media/video/davinci/davinci_display.c
index 4c4efef..0ab682c 100644
--- a/drivers/media/video/davinci/davinci_display.c
+++ b/drivers/media/video/davinci/davinci_display.c
@@ -280,7 +280,7 @@ static void davinci_display_isr(unsigned int event, void *dispObj)
 			list_del(&layer->nextFrm->queue);
 			/* Mark status of the buffer as active */
 			layer->nextFrm->state = VIDEOBUF_ACTIVE;
-			
+
 			addr = videobuf_to_dma_contig(layer->nextFrm);
 			davinci_disp_start_layer(layer->layer_info.id,
 						 addr,
@@ -712,7 +712,7 @@ static int vpbe_querycap(struct file *file, void  *priv,
 
 	dev_dbg(davinci_display_dev, "VIDIOC_QUERYCAP, layer id = %d\n",
 			layer->device_id);
-	
+
 	memset(cap, 0, sizeof(*cap));
 	*cap = davinci_display_videocap;
 
@@ -750,7 +750,7 @@ static int vpbe_s_crop(struct file *file, void *priv,
 		ret = mutex_lock_interruptible(&davinci_dm.lock);
 		if (ret)
 			return ret;
-				
+
 		davinci_disp_get_layer_config(layer->layer_info.id,
 						&layer->layer_info.config);
 
@@ -761,7 +761,7 @@ static int vpbe_s_crop(struct file *file, void *priv,
 
 		if (davinci_disp_set_layer_config(layer->layer_info.id,
 			&layer->layer_info.config)) {
-		
+
 			dev_err(davinci_display_dev,
 					"Error in S_CROP params\n");
 			mutex_unlock(&davinci_dm.lock);
@@ -789,7 +789,7 @@ static int vpbe_s_crop(struct file *file, void *priv,
 		dev_err(davinci_display_dev, "Invalid buf type \n");
 		return -EINVAL;
 	}
-	
+
 	return ret;
 }
 
@@ -799,7 +799,7 @@ static int vpbe_g_crop(struct file *file, void *priv,
 	int ret = 0;
 	struct davinci_fh *fh = file->private_data;
 	struct display_obj *layer = fh->layer;
-	
+
 	dev_dbg(davinci_display_dev, "VIDIOC_G_CROP, layer id = %d\n",
 			layer->device_id);
 
@@ -808,7 +808,7 @@ static int vpbe_g_crop(struct file *file, void *priv,
 		ret = mutex_lock_interruptible(&davinci_dm.lock);
 		if (ret)
 			return ret;
-				
+
 		davinci_disp_get_layer_config(layer->layer_info.id,
 						&layer->layer_info.config);
 		rect->top = layer->layer_info.config.ypos;
@@ -820,7 +820,7 @@ static int vpbe_g_crop(struct file *file, void *priv,
 		dev_err(davinci_display_dev,"Invalid buf type \n");
 		ret = -EINVAL;
 	}
-	
+
 	return ret;
 }
 
@@ -830,18 +830,18 @@ static int vpbe_cropcap(struct file *file, void *priv,
 	int ret = 0;
 
 	dev_dbg(davinci_display_dev, "\nStart of VIDIOC_CROPCAP ioctl");
-			
+
 	if (davinci_enc_get_mode(0, &davinci_dm.mode_info)) {
 		dev_err(davinci_display_dev,
 			"Error in getting current display mode"
 			" from enc mngr\n");
 		return -EINVAL;
 	}
-			
+
 	ret = mutex_lock_interruptible(&davinci_dm.lock);
 	if (ret)
 		return ret;
-			
+
 	cropcap->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
 	if (!strcmp(davinci_dm.mode_info.name, VID_ENC_STD_NTSC)) {
 		cropcap->bounds = cropcap->defrect = ntsc_bounds;
@@ -870,7 +870,7 @@ static int vpbe_cropcap(struct file *file, void *priv,
 		dev_err(davinci_display_dev, "Unknown encoder display mode\n");
 		return -EINVAL;
 	}
-	
+
 	mutex_unlock(&davinci_dm.lock);
 	dev_dbg(davinci_display_dev, "\nEnd of VIDIOC_CROPCAP ioctl");
 
@@ -891,14 +891,14 @@ static int vpbe_streamoff(struct file *file, void *priv,
 		dev_err(davinci_display_dev, "No io_allowed\n");
 		return -EACCES;
 	}
-			
+
 	/* If streaming is not started, return error */
 	if (!layer->started) {
 		dev_err(davinci_display_dev, "streaming not started in layer"
 			" id = %d\n", layer->device_id);
 		return -EINVAL;
 	}
-			
+
 	ret = mutex_lock_interruptible(&davinci_dm.lock);
 	if (ret)
 		return ret;
@@ -973,7 +973,7 @@ static int vpbe_streamon(struct file *file, void *priv,
 	layer->started = 1;
 	dev_dbg(davinci_display_dev, "Started streaming on layer id = %d,"
 		" ret = %d\n", layer->device_id, ret);
-			
+
 	layer_first_int = 1;
 	mutex_unlock(&davinci_dm.lock);
 
@@ -1059,7 +1059,7 @@ static int vpbe_reqbufs(struct file *file, void *priv,
 	if (ret)
 		return ret;
 	/* Initialize videobuf queue as per the buffer type */
-			
+
 	videobuf_queue_dma_contig_init(&layer->buffer_queue,
 					    &video_qops, davinci_display_dev,
 					    &layer->irqlock,
@@ -1131,7 +1131,7 @@ static int vpbe_s_fmt(struct file *file, void *priv,
 			return -EBUSY;
 		}
 	}
-				
+
 	/* store the pixel format in the layer object */
 	davinci_disp_get_layer_config(layer->layer_info.id,
 		&layer->layer_info.config);
@@ -1162,7 +1162,7 @@ static int vpbe_s_fmt(struct file *file, void *priv,
 	/* readback and fill the local copy of current pix format */
 	davinci_disp_get_layer_config(layer->layer_info.id,
 					&layer->layer_info.config);
-		
+
 	/* verify if readback values are as expected */
 	if (layer->pix_fmt.width != layer->layer_info.config.xsize ||
 		layer->pix_fmt.height != layer->layer_info.config.ysize ||
diff --git a/drivers/media/video/davinci/davinci_osd.c b/drivers/media/video/davinci/davinci_osd.c
index 2c498ad..c285f99 100644
--- a/drivers/media/video/davinci/davinci_osd.c
+++ b/drivers/media/video/davinci/davinci_osd.c
@@ -146,7 +146,7 @@ u32 osd_read_upper_margin(void)
 	return __raw_readl(osd->osd_base + OSD_BASEPY);
 }
 EXPORT_SYMBOL(osd_read_upper_margin);
-	
+
 
 /* define some macros for layer and pixfmt classification */
 #define is_osd_win(layer) (((layer) == WIN_OSD0) || ((layer) == WIN_OSD1))
@@ -546,6 +546,127 @@ void davinci_disp_get_vid_expansion(enum davinci_h_exp_ratio *h_exp,
 }
 EXPORT_SYMBOL(davinci_disp_get_vid_expansion);
 
+void davinci_disp_set_vid_size(enum davinci_disp_layer layer,
+	 const struct davinci_layer_config *lconfig)
+{
+	struct davinci_window_state *win = &osd->win[layer];
+	unsigned xsize, ysize;
+
+	xsize = lconfig->xsize << win->h_zoom;
+	ysize = lconfig->ysize << win->v_zoom;
+	switch (osd->osd_h_exp) {
+	case H_EXP_OFF:
+		break;
+	case H_EXP_9_OVER_8:
+		xsize = xsize * 9 / 8;
+		break;
+	case H_EXP_3_OVER_2:
+		xsize = xsize * 3 / 2;
+		break;
+	}
+
+	switch (osd->osd_v_exp) {
+	case V_EXP_OFF:
+		break;
+	case V_EXP_6_OVER_5:
+		ysize = ysize * 6 / 5;
+		break;
+	}
+
+	switch(layer) {
+	case WIN_OSD0:
+		osd_write(lconfig->xpos, OSD_OSDWIN0XP);
+		osd_write(xsize, OSD_OSDWIN0XL);
+		if (lconfig->interlaced) {
+			osd_write(lconfig->ypos >> 1, OSD_OSDWIN0YP);
+			osd_write(ysize >> 1, OSD_OSDWIN0YL);
+		} else {
+			osd_write(lconfig->ypos, OSD_OSDWIN0YP);
+			osd_write(ysize, OSD_OSDWIN0YL);
+		}
+		break;
+
+	case WIN_VID0:
+		osd_write(lconfig->xpos, OSD_VIDWIN0XP);
+		osd_write(xsize, OSD_VIDWIN0XL);
+		if (cpu_is_davinci_dm365()) {
+			if (lconfig->pixfmt == PIXFMT_NV12) {
+				osd_write(lconfig->xpos, OSD_VIDWIN1XP);
+				osd_write(xsize, OSD_VIDWIN1XL);
+				/* if NV21 pixfmt and line length not 32B
+				 * aligned (e.g. NTSC), Need to set window
+				 * X pixel size to be 32B aligned as well
+				 */
+				if (lconfig->xsize % 32) {
+					osd_write(((xsize + 31) & ~31),
+						  OSD_VIDWIN1XL);
+					osd_write(((xsize + 31) & ~31),
+						  OSD_VIDWIN0XL);
+				}
+			}
+		}
+		if (lconfig->interlaced) {
+			osd_write(lconfig->ypos >> 1, OSD_VIDWIN0YP);
+			osd_write(ysize >> 1, OSD_VIDWIN0YL);
+			if (cpu_is_davinci_dm365()
+			    && lconfig->pixfmt == PIXFMT_NV12) {
+				osd_write(lconfig->ypos >> 1, OSD_VIDWIN1YP);
+				osd_write(ysize >> 1, OSD_VIDWIN1YL);
+			}
+		} else {
+			osd_write(lconfig->ypos, OSD_VIDWIN0YP);
+			osd_write(ysize, OSD_VIDWIN0YL);
+			if (cpu_is_davinci_dm365()
+			    && lconfig->pixfmt == PIXFMT_NV12) {
+				osd_write(lconfig->ypos, OSD_VIDWIN1YP);
+				osd_write(ysize, OSD_VIDWIN1YL);
+			}
+		}
+		break;
+
+	case WIN_OSD1:
+		osd_write(lconfig->xpos, OSD_OSDWIN1XP);
+		osd_write(xsize, OSD_OSDWIN1XL);
+		if (lconfig->interlaced) {
+			osd_write(lconfig->ypos >> 1, OSD_OSDWIN1YP);
+			osd_write(ysize >> 1, OSD_OSDWIN1YL);
+		} else {
+			osd_write(lconfig->ypos, OSD_OSDWIN1YP);
+			osd_write(ysize, OSD_OSDWIN1YL);
+		}
+		break;
+
+	case WIN_VID1:
+		osd_write(lconfig->xpos, OSD_VIDWIN1XP);
+		osd_write(lconfig->xsize, OSD_VIDWIN1XL);
+		if (cpu_is_davinci_dm365()) {
+			if (lconfig->pixfmt == PIXFMT_NV12) {
+				osd_write(lconfig->xpos, OSD_VIDWIN0XP);
+				osd_write(lconfig->xsize, OSD_VIDWIN0XL);
+			}
+		}
+
+		if (lconfig->interlaced) {
+			osd_write(lconfig->ypos >> 1, OSD_VIDWIN1YP);
+			osd_write(ysize >> 1, OSD_VIDWIN1YL);
+			if (cpu_is_davinci_dm365()
+			    && lconfig->pixfmt == PIXFMT_NV12) {
+				osd_write(lconfig->ypos >> 1, OSD_VIDWIN0YP);
+				osd_write(ysize >> 1, OSD_VIDWIN0YL);
+			}
+		} else {
+			osd_write(lconfig->ypos, OSD_VIDWIN1YP);
+			osd_write(ysize, OSD_VIDWIN1YL);
+			if (cpu_is_davinci_dm365()
+			    && lconfig->pixfmt == PIXFMT_NV12) {
+				osd_write(lconfig->ypos, OSD_VIDWIN0YP);
+				osd_write(ysize, OSD_VIDWIN0YL);
+			}
+		}
+		break;
+	}
+}
+
 static void _davinci_disp_set_vid_expansion(enum davinci_h_exp_ratio h_exp,
 					    enum davinci_v_exp_ratio v_exp)
 {
@@ -649,6 +770,9 @@ int davinci_disp_set_osd_expansion(enum davinci_h_exp_ratio h_exp,
 
 	osd->osd_h_exp = h_exp;
 	osd->osd_v_exp = v_exp;
+	davinci_disp_set_vid_size(WIN_OSD0, &(osd->win[WIN_OSD0].lconfig));
+	davinci_disp_set_vid_size(WIN_OSD1, &(osd->win[WIN_OSD1].lconfig));
+
 	_davinci_disp_set_osd_expansion(h_exp, v_exp);
 
 	spin_unlock_irqrestore(&osd->lock, flags);
@@ -1289,6 +1413,8 @@ void davinci_disp_set_zoom(enum davinci_disp_layer layer,
 
 	win->h_zoom = h_zoom;
 	win->v_zoom = v_zoom;
+	davinci_disp_set_vid_size(layer, &win->lconfig);
+
 	_davinci_disp_set_zoom(layer, h_zoom, v_zoom);
 
 	spin_unlock_irqrestore(&osd->lock, flags);
@@ -1856,15 +1982,6 @@ static void _davinci_disp_set_layer_config(enum davinci_disp_layer layer,
 
 		osd_merge(winmd_mask, winmd, OSD_OSDWIN0MD);
 		osd_write(lconfig->line_length >> 5, OSD_OSDWIN0OFST);
-		osd_write(lconfig->xpos, OSD_OSDWIN0XP);
-		osd_write(lconfig->xsize, OSD_OSDWIN0XL);
-		if (lconfig->interlaced) {
-			osd_write(lconfig->ypos >> 1, OSD_OSDWIN0YP);
-			osd_write(lconfig->ysize >> 1, OSD_OSDWIN0YL);
-		} else {
-			osd_write(lconfig->ypos, OSD_OSDWIN0YP);
-			osd_write(lconfig->ysize, OSD_OSDWIN0YL);
-		}
 		break;
 	case WIN_VID0:
 		winmd_mask |= OSD_VIDWINMD_VFF0;
@@ -1873,8 +1990,6 @@ static void _davinci_disp_set_layer_config(enum davinci_disp_layer layer,
 
 		osd_merge(winmd_mask, winmd, OSD_VIDWINMD);
 		osd_write(lconfig->line_length >> 5, OSD_VIDWIN0OFST);
-		osd_write(lconfig->xpos, OSD_VIDWIN0XP);
-		osd_write(lconfig->xsize, OSD_VIDWIN0XL);
 		/*
 		 * For YUV420P format the register contents are
 		 * duplicated in both VID registers
@@ -1893,39 +2008,10 @@ static void _davinci_disp_set_layer_config(enum davinci_disp_layer layer,
 					  OSD_MISCCTL);
 				osd_write(lconfig->line_length >> 5,
 					  OSD_VIDWIN1OFST);
-				osd_write(lconfig->xpos, OSD_VIDWIN1XP);
-				osd_write(lconfig->xsize, OSD_VIDWIN1XL);
-				/* if NV21 pixfmt and line length not 32B
-				 * aligned (e.g. NTSC), Need to set window
-				 * X pixel size to be 32B aligned as well
-				 */
-				if (lconfig->xsize % 32) {
-					osd_write(((lconfig->xsize + 31) & ~31),
-						  OSD_VIDWIN1XL);
-					osd_write(((lconfig->xsize + 31) & ~31),
-						  OSD_VIDWIN0XL);
-				}
 			} else
 				osd_merge(OSD_MISCCTL_S420D, ~OSD_MISCCTL_S420D,
 					  OSD_MISCCTL);
 		}
-		if (lconfig->interlaced) {
-			osd_write(lconfig->ypos >> 1, OSD_VIDWIN0YP);
-			osd_write(lconfig->ysize >> 1, OSD_VIDWIN0YL);
-			if (cpu_is_davinci_dm365()
-			    && lconfig->pixfmt == PIXFMT_NV12) {
-				osd_write(lconfig->ypos >> 1, OSD_VIDWIN1YP);
-				osd_write(lconfig->ysize >> 1, OSD_VIDWIN1YL);
-			}
-		} else {
-			osd_write(lconfig->ypos, OSD_VIDWIN0YP);
-			osd_write(lconfig->ysize, OSD_VIDWIN0YL);
-			if (cpu_is_davinci_dm365()
-			    && lconfig->pixfmt == PIXFMT_NV12) {
-				osd_write(lconfig->ypos, OSD_VIDWIN1YP);
-				osd_write(lconfig->ysize, OSD_VIDWIN1YL);
-			}
-		}
 		break;
 	case WIN_OSD1:
 		/*
@@ -1999,15 +2085,6 @@ static void _davinci_disp_set_layer_config(enum davinci_disp_layer layer,
 
 		osd_merge(winmd_mask, winmd, OSD_OSDWIN1MD);
 		osd_write(lconfig->line_length >> 5, OSD_OSDWIN1OFST);
-		osd_write(lconfig->xpos, OSD_OSDWIN1XP);
-		osd_write(lconfig->xsize, OSD_OSDWIN1XL);
-		if (lconfig->interlaced) {
-			osd_write(lconfig->ypos >> 1, OSD_OSDWIN1YP);
-			osd_write(lconfig->ysize >> 1, OSD_OSDWIN1YL);
-		} else {
-			osd_write(lconfig->ypos, OSD_OSDWIN1YP);
-			osd_write(lconfig->ysize, OSD_OSDWIN1YL);
-		}
 		break;
 	case WIN_VID1:
 		winmd_mask |= OSD_VIDWINMD_VFF1;
@@ -2016,8 +2093,6 @@ static void _davinci_disp_set_layer_config(enum davinci_disp_layer layer,
 
 		osd_merge(winmd_mask, winmd, OSD_VIDWINMD);
 		osd_write(lconfig->line_length >> 5, OSD_VIDWIN1OFST);
-		osd_write(lconfig->xpos, OSD_VIDWIN1XP);
-		osd_write(lconfig->xsize, OSD_VIDWIN1XL);
 		/*
 		 * For YUV420P format the register contents are
 		 * duplicated in both VID registers
@@ -2035,32 +2110,13 @@ static void _davinci_disp_set_layer_config(enum davinci_disp_layer layer,
 					  OSD_MISCCTL);
 				osd_write(lconfig->line_length >> 5,
 					  OSD_VIDWIN0OFST);
-				osd_write(lconfig->xpos, OSD_VIDWIN0XP);
-				osd_write(lconfig->xsize, OSD_VIDWIN0XL);
 		} else
 			osd_merge(OSD_MISCCTL_S420D, ~OSD_MISCCTL_S420D,
 				  OSD_MISCCTL);
 		}
-
-		if (lconfig->interlaced) {
-			osd_write(lconfig->ypos >> 1, OSD_VIDWIN1YP);
-			osd_write(lconfig->ysize >> 1, OSD_VIDWIN1YL);
-			if (cpu_is_davinci_dm365()
-			    && lconfig->pixfmt == PIXFMT_NV12) {
-				osd_write(lconfig->ypos >> 1, OSD_VIDWIN0YP);
-				osd_write(lconfig->ysize >> 1, OSD_VIDWIN0YL);
-			}
-		} else {
-			osd_write(lconfig->ypos, OSD_VIDWIN1YP);
-			osd_write(lconfig->ysize, OSD_VIDWIN1YL);
-			if (cpu_is_davinci_dm365()
-			    && lconfig->pixfmt == PIXFMT_NV12) {
-				osd_write(lconfig->ypos, OSD_VIDWIN0YP);
-				osd_write(lconfig->ysize, OSD_VIDWIN0YL);
-			}
-		}
 		break;
 	}
+	davinci_disp_set_vid_size(layer, lconfig);
 }
 
 int davinci_disp_set_layer_config(enum davinci_disp_layer layer,
-- 
1.5.6.5


From sshtylyov at mvista.com  Tue May 18 08:02:47 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Tue, 18 May 2010 17:02:47 +0400
Subject: [PATCH 2/4] davinci: Update window size after enabling OSD
	zoom/expansion.
In-Reply-To: <1274187385-10969-2-git-send-email-gilles.chanteperdrix@nexvision.fr>
References: <4BF28E20.3070701@nexvision.fr>	<1274187385-10969-1-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<1274187385-10969-2-git-send-email-gilles.chanteperdrix@nexvision.fr>
Message-ID: <4BF28FF7.9050801@mvista.com>

Hello.

Gilles Chanteperdrix wrote:

> When enabling expansion or zoom, the window size must be updated. We
> implement a davinci_disp_set_vid_size function computing the window
> size registers from the window parameters and zoom/expansion factors,
> and call it every time the framebuffer size is updated or the
> zoom/expansion factors are updated.
>
> Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix at nexvision.fr>
> ---
>  drivers/media/video/davinci/davinci_display.c |   36 +++---
>  drivers/media/video/davinci/davinci_osd.c     |  200 ++++++++++++++++---------
>  2 files changed, 146 insertions(+), 90 deletions(-)
>
> diff --git a/drivers/media/video/davinci/davinci_display.c b/drivers/media/video/davinci/davinci_display.c
> index 4c4efef..0ab682c 100644
> --- a/drivers/media/video/davinci/davinci_display.c
> +++ b/drivers/media/video/davinci/davinci_display.c
> @@ -280,7 +280,7 @@ static void davinci_display_isr(unsigned int event, void *dispObj)
>  			list_del(&layer->nextFrm->queue);
>  			/* Mark status of the buffer as active */
>  			layer->nextFrm->state = VIDEOBUF_ACTIVE;
> -			
> +
>  			addr = videobuf_to_dma_contig(layer->nextFrm);
>  			davinci_disp_start_layer(layer->layer_info.id,
>  						 addr,
> @@ -712,7 +712,7 @@ static int vpbe_querycap(struct file *file, void  *priv,
>  
>  	dev_dbg(davinci_display_dev, "VIDIOC_QUERYCAP, layer id = %d\n",
>  			layer->device_id);
> -	
> +
>  	memset(cap, 0, sizeof(*cap));
>  	*cap = davinci_display_videocap;
>  
> @@ -750,7 +750,7 @@ static int vpbe_s_crop(struct file *file, void *priv,
>  		ret = mutex_lock_interruptible(&davinci_dm.lock);
>  		if (ret)
>  			return ret;
> -				
> +
>  		davinci_disp_get_layer_config(layer->layer_info.id,
>  						&layer->layer_info.config);
>  
> @@ -761,7 +761,7 @@ static int vpbe_s_crop(struct file *file, void *priv,
>  
>  		if (davinci_disp_set_layer_config(layer->layer_info.id,
>  			&layer->layer_info.config)) {
> -		
> +
>  			dev_err(davinci_display_dev,
>  					"Error in S_CROP params\n");
>  			mutex_unlock(&davinci_dm.lock);
> @@ -789,7 +789,7 @@ static int vpbe_s_crop(struct file *file, void *priv,
>  		dev_err(davinci_display_dev, "Invalid buf type \n");
>  		return -EINVAL;
>  	}
> -	
> +
>  	return ret;
>  }
>  
> @@ -799,7 +799,7 @@ static int vpbe_g_crop(struct file *file, void *priv,
>  	int ret = 0;
>  	struct davinci_fh *fh = file->private_data;
>  	struct display_obj *layer = fh->layer;
> -	
> +
>  	dev_dbg(davinci_display_dev, "VIDIOC_G_CROP, layer id = %d\n",
>  			layer->device_id);
>  
> @@ -808,7 +808,7 @@ static int vpbe_g_crop(struct file *file, void *priv,
>  		ret = mutex_lock_interruptible(&davinci_dm.lock);
>  		if (ret)
>  			return ret;
> -				
> +
>  		davinci_disp_get_layer_config(layer->layer_info.id,
>  						&layer->layer_info.config);
>  		rect->top = layer->layer_info.config.ypos;
> @@ -820,7 +820,7 @@ static int vpbe_g_crop(struct file *file, void *priv,
>  		dev_err(davinci_display_dev,"Invalid buf type \n");
>  		ret = -EINVAL;
>  	}
> -	
> +
>  	return ret;
>  }
>  
> @@ -830,18 +830,18 @@ static int vpbe_cropcap(struct file *file, void *priv,
>  	int ret = 0;
>  
>  	dev_dbg(davinci_display_dev, "\nStart of VIDIOC_CROPCAP ioctl");
> -			
> +
>  	if (davinci_enc_get_mode(0, &davinci_dm.mode_info)) {
>  		dev_err(davinci_display_dev,
>  			"Error in getting current display mode"
>  			" from enc mngr\n");
>  		return -EINVAL;
>  	}
> -			
> +
>  	ret = mutex_lock_interruptible(&davinci_dm.lock);
>  	if (ret)
>  		return ret;
> -			
> +
>  	cropcap->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
>  	if (!strcmp(davinci_dm.mode_info.name, VID_ENC_STD_NTSC)) {
>  		cropcap->bounds = cropcap->defrect = ntsc_bounds;
> @@ -870,7 +870,7 @@ static int vpbe_cropcap(struct file *file, void *priv,
>  		dev_err(davinci_display_dev, "Unknown encoder display mode\n");
>  		return -EINVAL;
>  	}
> -	
> +
>  	mutex_unlock(&davinci_dm.lock);
>  	dev_dbg(davinci_display_dev, "\nEnd of VIDIOC_CROPCAP ioctl");
>  
> @@ -891,14 +891,14 @@ static int vpbe_streamoff(struct file *file, void *priv,
>  		dev_err(davinci_display_dev, "No io_allowed\n");
>  		return -EACCES;
>  	}
> -			
> +
>  	/* If streaming is not started, return error */
>  	if (!layer->started) {
>  		dev_err(davinci_display_dev, "streaming not started in layer"
>  			" id = %d\n", layer->device_id);
>  		return -EINVAL;
>  	}
> -			
> +
>  	ret = mutex_lock_interruptible(&davinci_dm.lock);
>  	if (ret)
>  		return ret;
> @@ -973,7 +973,7 @@ static int vpbe_streamon(struct file *file, void *priv,
>  	layer->started = 1;
>  	dev_dbg(davinci_display_dev, "Started streaming on layer id = %d,"
>  		" ret = %d\n", layer->device_id, ret);
> -			
> +
>  	layer_first_int = 1;
>  	mutex_unlock(&davinci_dm.lock);
>  
> @@ -1059,7 +1059,7 @@ static int vpbe_reqbufs(struct file *file, void *priv,
>  	if (ret)
>  		return ret;
>  	/* Initialize videobuf queue as per the buffer type */
> -			
> +
>  	videobuf_queue_dma_contig_init(&layer->buffer_queue,
>  					    &video_qops, davinci_display_dev,
>  					    &layer->irqlock,
> @@ -1131,7 +1131,7 @@ static int vpbe_s_fmt(struct file *file, void *priv,
>  			return -EBUSY;
>  		}
>  	}
> -				
> +
>  	/* store the pixel format in the layer object */
>  	davinci_disp_get_layer_config(layer->layer_info.id,
>  		&layer->layer_info.config);
> @@ -1162,7 +1162,7 @@ static int vpbe_s_fmt(struct file *file, void *priv,
>  	/* readback and fill the local copy of current pix format */
>  	davinci_disp_get_layer_config(layer->layer_info.id,
>  					&layer->layer_info.config);
> -		
> +
>  	/* verify if readback values are as expected */
>  	if (layer->pix_fmt.width != layer->layer_info.config.xsize ||
>  		layer->pix_fmt.height != layer->layer_info.config.ysize ||
> diff --git a/drivers/media/video/davinci/davinci_osd.c b/drivers/media/video/davinci/davinci_osd.c
> index 2c498ad..c285f99 100644
> --- a/drivers/media/video/davinci/davinci_osd.c
> +++ b/drivers/media/video/davinci/davinci_osd.c
> @@ -146,7 +146,7 @@ u32 osd_read_upper_margin(void)
>  	return __raw_readl(osd->osd_base + OSD_BASEPY);
>  }
>  EXPORT_SYMBOL(osd_read_upper_margin);
> -	
> +
>  
>  /* define some macros for layer and pixfmt classification */
>  #define is_osd_win(layer) (((layer) == WIN_OSD0) || ((layer) == WIN_OSD1))
>   

   White space fixes should be in a separate patch.

WBR, Sergei


From gilles.chanteperdrix at nexvision.fr  Tue May 18 08:16:24 2010
From: gilles.chanteperdrix at nexvision.fr (Gilles Chanteperdrix)
Date: Tue, 18 May 2010 15:16:24 +0200
Subject: [PATCH 2/4] davinci: Update window size after enabling OSD
	zoom/expansion.
In-Reply-To: <4BF28FF7.9050801@mvista.com>
References: <4BF28E20.3070701@nexvision.fr>	<1274187385-10969-1-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<1274187385-10969-2-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<4BF28FF7.9050801@mvista.com>
Message-ID: <4BF29328.1060907@nexvision.fr>

Sergei Shtylyov wrote:
>    White space fixes should be in a separate patch.

Sorry for this. My editor is the culprit. Shall I wait for other
comments, or would you want another post ASAP?

-- 
					    Gilles.

From sshtylyov at mvista.com  Tue May 18 08:20:03 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Tue, 18 May 2010 17:20:03 +0400
Subject: [PATCH 2/4] davinci: Update window size after enabling OSD
	zoom/expansion.
In-Reply-To: <4BF29328.1060907@nexvision.fr>
References: <4BF28E20.3070701@nexvision.fr>	<1274187385-10969-1-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<1274187385-10969-2-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<4BF28FF7.9050801@mvista.com> <4BF29328.1060907@nexvision.fr>
Message-ID: <4BF29403.9060904@mvista.com>

Gilles Chanteperdrix wrote:

> Sergei Shtylyov wrote:
>   
>>    White space fixes should be in a separate patch.
>>     
>
> Sorry for this. My editor is the culprit. Shall I wait for other
> comments, or would you want another post ASAP?

   Up to you.

WBR, Sergei


From vij_soni at yahoo.com  Mon May 17 00:42:07 2010
From: vij_soni at yahoo.com (Vijay Soni)
Date: Sun, 16 May 2010 22:42:07 -0700 (PDT)
Subject: Symbol names
Message-ID: <880572.16919.qm@web38804.mail.mud.yahoo.com>

Does anyone know how I can get symbols names from their addresses. I am trying to debug an kernel oops which gives function address in the Backtrace. I know I can turn on KALLSYMS but I cannot rebuild my kernel because of other module dependency. Can we get this info from vmlinux? If so how?


      
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From cyril at ti.com  Tue May 18 08:58:28 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Tue, 18 May 2010 09:58:28 -0400
Subject: [RFC 1/4] Davinci: mdio - separate out mdio controller code
In-Reply-To: <B85A65D85D7EB246BE421B3FB0FBB59301E6F97620@dbde02.ent.ti.com>
References: <1273876947-30711-1-git-send-email-cyril@ti.com>
	<1273876947-30711-2-git-send-email-cyril@ti.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E6F97620@dbde02.ent.ti.com>
Message-ID: <4BF29D04.4010500@ti.com>

Hi Sekhar,

Thanks for looking at this.

[...]
>> +#define MDIO_OUT_FREQ                1100000         /* 2.2 MHz */
> 
> The comment says 2.2 MHz, but the value is 1.1 MHz?

Thanks.

> Also, can you keep this as a platform variable (with
> a 2.2 MHz default)? The frequency depends on the board,
> and although most boards work at 2.2 MHz, not having it
> as a platform variable will make adding a board with a
> different frequency requirement difficult.

I am not quite convinced that you'll have too many boards deviate from
the 2MHz ballpark.  That seems to be a nice and safe frequency that
works well across phys, socs, and boards.

That said, if we see the need to override the bus frequency in future, I
am all for a patch at that time.  As it stands, I don't see the value in
adding platform data definitions for a capability that is not going to
be used at present.

[...]
>> +     struct {
>> +             u32     access;
>> +#define USERACCESS_GO                BIT(31)
>> +#define USERACCESS_WRITE     BIT(30)
>> +#define USERACCESS_ACK               BIT(29)
>> +#define USERACCESS_READ              (0)
>> +#define USERACCESS_DATA              (0xffff)
>> +
>> +             u32     physel;
>> +     }       user[0];
>> +};
> 
> Structure overlays are usually not preferred and
> is difficult to debug. Can you please keep the
> direct register access method that was being
> followed in the original driver?

Agreed, will change since the multiple user modules are not being used
anyway.

[...]
>> +     while ((reg = __raw_readl(&regs->user[0].access)) & USERACCESS_GO)
>> +             ;
> 
> I know the original code had this issue too, but there should be a
> timeout here to avoid permanent lockup. Also, a cpu_relax() while
> looping tight.

True. Thanks.

[...]
>> +static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
>> +{
>> +     struct davinci_mdio_data *data = bus->priv;
>> +     u32 reg;
>> +
>> +     if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
>> +             return -EINVAL;
>> +
>> +     spin_lock(&data->lock);
> 
> The mdiobus serializes the bus access anyway so is this
> lock really needed?

Not needed.

>> +
>> +     if (data->suspended) {
>> +             spin_unlock(&data->lock);
>> +             return -ENODEV;
>> +     }
> 
> Hmm, the devices should be suspended before the bus is.
> So, there should probably be a WARN_ON() here since this
> indicates some issue elsewhere in the system.
> 
> Or may be this is too paranoid and can be rid of altogether?

I wasn't entirely sure of the suspend sequence (and hence the paranoia).

[...]
>> +static inline int count_bits(u32 data)
>> +{
>> +     data = ((data & 0xaaaaaaaa) >>  1) + (data & 0x55555555);
>> +     data = ((data & 0xcccccccc) >>  2) + (data & 0x33333333);
>> +     data = ((data & 0xf0f0f0f0) >>  4) + (data & 0x0f0f0f0f);
>> +     data = ((data & 0xff00ff00) >>  8) + (data & 0x00ff00ff);
>> +     data = ((data & 0xffff0000) >> 16) + (data & 0x0000ffff);
>> +     return data;
>> +}
> 
> Kernel already has a function to calculate the hamming weight
> on u32. See hweight32() in lib/hweight.c

Will modify. Thanks.

[...]
>> +     mdio_in_freq = clk_get_rate(data->clk);
>> +     div = (mdio_in_freq / MDIO_OUT_FREQ) - 1;
>> +     if (div > CONTROL_MAX_DIV)
>> +             div = CONTROL_MAX_DIV;
> 
> Hmm, just wondering if it is safe to just default on
> the max possible value? It could be a result of an issue
> elsewhere and so should be reported?

Should spew a warn at the least.

[...]
>> +     if (phy_mask) {
>> +             /* restrict mdio bus to live phys only */
>> +             dev_info(dev, "detected %d phys (mask %x)\n",
>> +                      count_bits(phy_mask), ~phy_mask);
>> +             phy_mask = ~phy_mask;
>> +     } else {
>> +             /* desperately scan all phys */
>> +             dev_warn(dev, "failed to detect live phys, scanning all\n");
>> +             phy_mask = 0;
> 
> phy_mask is already zero.

Indeed, it is! :-)

>> +     data->bus->phy_mask = phy_mask;
> 
> Looks like phy_mask local variable can be eliminated?

Not at the expense of readability.  I'd rather not have
data->bus->phy_mask references all over.

[...]
>> +     kfree(data);
>> +
>> +     return 0;
> 
> return ret?

Absolutely, what was I thinking?

Regards
Cyril.

From cyril at ti.com  Tue May 18 09:23:42 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Tue, 18 May 2010 10:23:42 -0400
Subject: [PATCH v5 1/3] ARM: add CPPI 4.1 DMA support
In-Reply-To: <201005152214.53993.sshtylyov@ru.mvista.com>
References: <201005152214.53993.sshtylyov@ru.mvista.com>
Message-ID: <4BF2A2EE.7010103@ti.com>

Hi Peter,

Have you had a chance to dig into this posting yet?

Would you mind a brief call about this patch after we've had a chance to
analyze this?

Regards
Cyril.


On 05/15/10 14:14, Sergei Shtylyov wrote:
> Add support for Texas Instuments Communication Port Programming Interface 4.1
> (CPPI 4.1) used on OMAP-L1x/DA8xx and AM35x.
> 
> At this moment, only the DMA controller and queue manager are supported.
> Support for the buffer manager is lacking but these chips don't have it anyway.
> 
> Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
> Signed-off-by: Sekhar Nori <nsekhar at ti.com>
> 
> ---
> Changes since the previous version:
> - moved everything from arch/arm/mach-davinci/ to arch/arm/common/;
> - s/CONFIG_CPPI41/CONFIG_TI_CPPI41/, made that option invisible;
> - added #include <linux/slab.h> for kzalloc();
> - switched alloc_queue() and cppi41_queue_free() to using bit operations;
> - replaced 'static' linking_ram[] by local variable in cppi41_queue_mgr_init();
> - fixed pr_debug() in cppi41_dma_ctrlr_init() to print the real queue manager #.
> 
>  arch/arm/common/Kconfig                |    3
>  arch/arm/common/Makefile               |    1
>  arch/arm/common/cppi41.c               |  759 +++++++++++++++++++++++++++++++++
>  arch/arm/include/asm/hardware/cppi41.h |  718 +++++++++++++++++++++++++++++++
>  4 files changed, 1481 insertions(+)
> 
> Index: linux-davinci/arch/arm/common/Kconfig
> ===================================================================
> --- linux-davinci.orig/arch/arm/common/Kconfig
> +++ linux-davinci/arch/arm/common/Kconfig
> @@ -38,5 +38,8 @@ config SHARP_PARAM
>  config SHARP_SCOOP
>         bool
> 
> +config TI_CPPI41
> +       bool
> +
>  config COMMON_CLKDEV
>         bool
> Index: linux-davinci/arch/arm/common/Makefile
> ===================================================================
> --- linux-davinci.orig/arch/arm/common/Makefile
> +++ linux-davinci/arch/arm/common/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_TIMER_ACORN)     += time-acorn.
>  obj-$(CONFIG_SHARP_LOCOMO)     += locomo.o
>  obj-$(CONFIG_SHARP_PARAM)      += sharpsl_param.o
>  obj-$(CONFIG_SHARP_SCOOP)      += scoop.o
> +obj-$(CONFIG_TI_CPPI41)        += cppi41.o
>  obj-$(CONFIG_ARCH_IXP2000)     += uengine.o
>  obj-$(CONFIG_ARCH_IXP23XX)     += uengine.o
>  obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
> Index: linux-davinci/arch/arm/common/cppi41.c
> ===================================================================
> --- /dev/null
> +++ linux-davinci/arch/arm/common/cppi41.c
> @@ -0,0 +1,759 @@
> +/*
> + * CPPI 4.1 support
> + *
> + * Copyright (C) 2008-2010 MontaVista Software, Inc. <source at mvista.com>
> + *
> + * Based on the PAL CPPI 4.1 implementation
> + * Copyright (C) 2007, Texas Instruments Inc. http://www.ti.com/
> + *
> + * This file contains the main implementation for CPPI 4.1 common peripherals,
> + * including the DMA Controllers and the Queue Managers.
> + *
> + * This program is free software; you can distribute it and/or modify it
> + * under the terms of the GNU General Public License (Version 2) as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
> + * for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
> + *
> + */
> +
> +#undef DEBUG
> +
> +#include <linux/io.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/dma-mapping.h>
> +
> +#include <asm/hardware/cppi41.h>
> +
> +static unsigned long *allocated_queues[CPPI41_NUM_QUEUE_MGR];
> +
> +/* First 32 packet descriptors are reserved for unallocated memory regions. */
> +static u32 next_desc_index[CPPI41_NUM_QUEUE_MGR] = { 1 << 5 };
> +static u8  next_mem_rgn[CPPI41_NUM_QUEUE_MGR];
> +
> +static struct {
> +       size_t rgn_size;
> +       void *virt_addr;
> +       dma_addr_t phys_addr;
> +       struct cppi41_queue_obj queue_obj;
> +       u8 mem_rgn;
> +} dma_teardown[CPPI41_NUM_DMA_BLOCK];
> +
> +/******************** CPPI 4.1 Functions (External Interface) *****************/
> +
> +int __init cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size)
> +{
> +       static struct {
> +               void *virt_addr;
> +               dma_addr_t phys_addr;
> +       } linking_ram;
> +       void __iomem *q_mgr_regs;
> +       void *ptr;
> +
> +       if (q_mgr >= cppi41_num_queue_mgr)
> +               return -EINVAL;
> +
> +       q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
> +
> +       __raw_writel(rgn0_base, q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG);
> +       pr_debug("Linking RAM region 0 base @ %p, value: %x\n",
> +                q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG,
> +                __raw_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG));
> +
> +       __raw_writel(rgn0_size, q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG);
> +       pr_debug("Linking RAM region 0 size @ %p, value: %x\n",
> +                q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG,
> +                __raw_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG));
> +
> +       ptr = dma_alloc_coherent(NULL, 0x10000 - rgn0_size * 4,
> +                                &linking_ram.phys_addr, GFP_KERNEL | GFP_DMA);
> +       if (ptr == NULL) {
> +               pr_err("ERROR: %s: Unable to allocate linking RAM.\n",
> +                      __func__);
> +               return -ENOMEM;
> +       }
> +       linking_ram.virt_addr = ptr;
> +
> +       __raw_writel(linking_ram.phys_addr,
> +                    q_mgr_regs + QMGR_LINKING_RAM_RGN1_BASE_REG);
> +       pr_debug("Linking RAM region 1 base @ %p, value: %x\n",
> +                q_mgr_regs + QMGR_LINKING_RAM_RGN1_BASE_REG,
> +                __raw_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN1_BASE_REG));
> +
> +       ptr = kzalloc(BITS_TO_LONGS(cppi41_queue_mgr[q_mgr].num_queue),
> +                     GFP_KERNEL);
> +       if (ptr == NULL) {
> +               pr_err("ERROR: %s: Unable to allocate queue bitmap.\n",
> +                      __func__);
> +               dma_free_coherent(NULL, 0x10000 - rgn0_size * 4,
> +                                 linking_ram.virt_addr, linking_ram.phys_addr);
> +               return -ENOMEM;
> +       }
> +       allocated_queues[q_mgr] = ptr;
> +
> +       return 0;
> +}
> +
> +int __init cppi41_dma_ctrlr_init(u8 dma_num, u8 q_mgr, u8 num_order)
> +{
> +       const struct cppi41_dma_block *dma_block;
> +       struct cppi41_teardown_desc *curr_td;
> +       unsigned num_desc = 1 << num_order;
> +       dma_addr_t td_addr;
> +       void *ptr;
> +       int error, i;
> +       u16 q_num;
> +
> +       if (dma_num >= cppi41_num_dma_block ||
> +           q_mgr >= cppi41_num_queue_mgr)
> +               return -EINVAL;
> +
> +       error = cppi41_queue_alloc(CPPI41_FREE_DESC_QUEUE |
> +                                  CPPI41_UNASSIGNED_QUEUE, q_mgr, &q_num);
> +       if (error) {
> +               pr_err("ERROR: %s: Unable to allocate teardown descriptor "
> +                      "queue.\n", __func__);
> +               return error;
> +       }
> +       pr_debug("Teardown descriptor queue %d in queue manager %d allocated\n",
> +                q_num, q_mgr);
> +
> +       /*
> +        * Tell the hardware about the Teardown descriptor
> +        * queue manager and queue number.
> +        */
> +       dma_block = &cppi41_dma_block[dma_num];
> +       __raw_writel((q_mgr << DMA_TD_DESC_QMGR_SHIFT) |
> +                    (q_num << DMA_TD_DESC_QNUM_SHIFT),
> +                    dma_block->global_ctrl_base +
> +                    DMA_TEARDOWN_FREE_DESC_CTRL_REG);
> +       pr_debug("Teardown free descriptor control @ %p, value: %x\n",
> +                dma_block->global_ctrl_base + DMA_TEARDOWN_FREE_DESC_CTRL_REG,
> +                __raw_readl(dma_block->global_ctrl_base +
> +                            DMA_TEARDOWN_FREE_DESC_CTRL_REG));
> +
> +       dma_teardown[dma_num].rgn_size = num_desc *
> +                                        sizeof(struct cppi41_teardown_desc);
> +
> +       /* Pre-allocate teardown descriptors. */
> +       ptr = dma_alloc_coherent(NULL, dma_teardown[dma_num].rgn_size,
> +                                &dma_teardown[dma_num].phys_addr,
> +                                GFP_KERNEL | GFP_DMA);
> +       if (ptr == NULL) {
> +               pr_err("ERROR: %s: Unable to allocate teardown descriptors.\n",
> +                      __func__);
> +               error = -ENOMEM;
> +               goto free_queue;
> +       }
> +       dma_teardown[dma_num].virt_addr = ptr;
> +
> +       error = cppi41_mem_rgn_alloc(q_mgr, dma_teardown[dma_num].phys_addr, 5,
> +                                    num_order, &dma_teardown[dma_num].mem_rgn);
> +       if (error) {
> +               pr_err("ERROR: %s: Unable to allocate queue manager memory "
> +                      "region for teardown descriptors.\n", __func__);
> +               goto free_mem;
> +       }
> +
> +       error = cppi41_queue_init(&dma_teardown[dma_num].queue_obj, 0, q_num);
> +       if (error) {
> +               pr_err("ERROR: %s: Unable to initialize teardown free "
> +                      "descriptor queue.\n", __func__);
> +               goto free_rgn;
> +       }
> +
> +       /*
> +        * Push all teardown descriptors to the free teardown queue
> +        * for the CPPI 4.1 system.
> +        */
> +       curr_td = dma_teardown[dma_num].virt_addr;
> +       td_addr = dma_teardown[dma_num].phys_addr;
> +
> +       for (i = 0; i < num_desc; i++) {
> +               cppi41_queue_push(&dma_teardown[dma_num].queue_obj, td_addr,
> +                                 sizeof(*curr_td), 0);
> +               td_addr += sizeof(*curr_td);
> +       }
> +
> +free_rgn:
> +       cppi41_mem_rgn_free(q_mgr, dma_teardown[dma_num].mem_rgn);
> +free_mem:
> +       dma_free_coherent(NULL, dma_teardown[dma_num].rgn_size,
> +                         dma_teardown[dma_num].virt_addr,
> +                         dma_teardown[dma_num].phys_addr);
> +free_queue:
> +       cppi41_queue_free(q_mgr, q_num);
> +       return error;
> +}
> +
> +int __init cppi41_dma_sched_init(u8 dma_num, const u8 *sched_tbl, u16 tbl_size)
> +{
> +       const struct cppi41_dma_block *dma_block;
> +       unsigned num_reg;
> +       int i, j, k;
> +       u32 val;
> +
> +       if (dma_num >= cppi41_num_dma_block ||
> +           !tbl_size || tbl_size > 0x100 || sched_tbl == NULL)
> +               return -EINVAL;
> +
> +       /* Initialize the DMA scheduler. */
> +       dma_block = &cppi41_dma_block[dma_num];
> +       num_reg = (tbl_size + 3) / 4;
> +       for (k = i = 0; i < num_reg; i++) {
> +               for (val = j = 0; j < 4; j++, k++) {
> +                       val >>= 8;
> +                       if (k < tbl_size)
> +                               val |= sched_tbl[k] << 24;
> +               }
> +
> +               __raw_writel(val, dma_block->sched_table_base +
> +                            DMA_SCHED_TABLE_WORD_REG(i));
> +               pr_debug("DMA scheduler table @ %p, value written: %x\n",
> +                        dma_block->sched_table_base +
> +                        DMA_SCHED_TABLE_WORD_REG(i), val);
> +       }
> +
> +       __raw_writel((tbl_size - 1) << DMA_SCHED_LAST_ENTRY_SHIFT |
> +                    DMA_SCHED_ENABLE_MASK,
> +                    dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG);
> +       pr_debug("DMA scheduler control @ %p, value: %x\n",
> +                dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG,
> +                __raw_readl(dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG));
> +
> +       return 0;
> +}
> +
> +/*
> + * cppi41_mem_rgn_alloc - allocate a memory region within the queue manager
> + */
> +int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
> +                        u8 num_order, u8 *mem_rgn)
> +{
> +       void __iomem *desc_mem_regs;
> +       u32 num_desc = 1 << num_order, index, ctrl;
> +       int rgn;
> +
> +       pr_debug("%s called with rgn_addr = %08x, size_order = %d, "
> +                "num_order = %d\n", __func__, rgn_addr, size_order, num_order);
> +
> +       if (q_mgr >= cppi41_num_queue_mgr ||
> +           size_order < 5 || size_order > 13 ||
> +           num_order  < 5 || num_order  > 12 ||
> +           (rgn_addr & ((1 << size_order) - 1)))
> +               return -EINVAL;
> +
> +       rgn = next_mem_rgn[q_mgr];
> +       index = next_desc_index[q_mgr];
> +       if (rgn >= CPPI41_MAX_MEM_RGN || index + num_desc > 0x4000)
> +               return -ENOSPC;
> +
> +       next_mem_rgn[q_mgr] = rgn + 1;
> +       next_desc_index[q_mgr] = index + num_desc;
> +
> +       desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
> +
> +       /* Write the base register */
> +       __raw_writel(rgn_addr, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn));
> +       pr_debug("Descriptor region base @ %p, value: %x\n",
> +                desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn),
> +                __raw_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn)));
> +
> +       /* Write the control register */
> +       ctrl = ((index << QMGR_MEM_RGN_INDEX_SHIFT) &
> +               QMGR_MEM_RGN_INDEX_MASK) |
> +              (((size_order - 5) << QMGR_MEM_RGN_DESC_SIZE_SHIFT) &
> +               QMGR_MEM_RGN_DESC_SIZE_MASK) |
> +              (((num_order - 5) << QMGR_MEM_RGN_SIZE_SHIFT) &
> +               QMGR_MEM_RGN_SIZE_MASK);
> +       __raw_writel(ctrl, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn));
> +       pr_debug("Descriptor region control @ %p, value: %x\n",
> +                desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn),
> +                __raw_readl(desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn)));
> +
> +       *mem_rgn = rgn;
> +       return 0;
> +}
> +EXPORT_SYMBOL(cppi41_mem_rgn_alloc);
> +
> +/*
> + * cppi41_mem_rgn_free - free the memory region within the queue manager
> + */
> +int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn)
> +{
> +       void __iomem *desc_mem_regs;
> +
> +       pr_debug("%s called.\n", __func__);
> +
> +       if (q_mgr >= cppi41_num_queue_mgr || mem_rgn >= next_mem_rgn[q_mgr])
> +               return -EINVAL;
> +
> +       desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
> +
> +       if (__raw_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn)) == 0)
> +               return -ENOENT;
> +
> +       __raw_writel(0, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn));
> +       __raw_writel(0, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(mem_rgn));
> +
> +       return 0;
> +}
> +EXPORT_SYMBOL(cppi41_mem_rgn_free);
> +
> +/*
> + * cppi41_tx_ch_init - initialize a CPPI 4.1 Tx channel object
> + *
> + * Verify the channel info (range checking, etc.) and store the channel
> + * information within the object structure.
> + */
> +int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
> +                     u8 dma_num, u8 ch_num)
> +{
> +       if (dma_num >= cppi41_num_dma_block ||
> +           ch_num  >= cppi41_dma_block[dma_num].num_tx_ch)
> +               return -EINVAL;
> +
> +       /* Populate the channel object structure */
> +       tx_ch_obj->base_addr  = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
> +                               DMA_CH_TX_GLOBAL_CFG_REG(ch_num);
> +       tx_ch_obj->global_cfg = __raw_readl(tx_ch_obj->base_addr);
> +       return 0;
> +}
> +EXPORT_SYMBOL(cppi41_tx_ch_init);
> +
> +/*
> + * cppi41_rx_ch_init - initialize a CPPI 4.1 Rx channel object
> + *
> + * Verify the channel info (range checking, etc.) and store the channel
> + * information within the object structure.
> + */
> +int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
> +                     u8 dma_num, u8 ch_num)
> +{
> +       if (dma_num >= cppi41_num_dma_block ||
> +           ch_num  >= cppi41_dma_block[dma_num].num_rx_ch)
> +               return -EINVAL;
> +
> +       /* Populate the channel object structure */
> +       rx_ch_obj->base_addr  = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
> +                               DMA_CH_RX_GLOBAL_CFG_REG(ch_num);
> +       rx_ch_obj->global_cfg = __raw_readl(rx_ch_obj->base_addr);
> +       return 0;
> +}
> +EXPORT_SYMBOL(cppi41_rx_ch_init);
> +
> +/*
> + * We have to cache the last written Rx/Tx channel global configration register
> + * value due to its bits other than enable/teardown being write-only. Yet there
> + * is a caveat related to caching the enable bit: this bit may be automatically
> + * cleared as a result of teardown, so we can't trust its cached value!
> + * When modifying the write only register fields, we're making use of the fact
> + * that they read back as zeros, and not clearing them explicitly...
> + */
> +
> +/*
> + * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
> + */
> +void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
> +                                u8 q_mgr, u16 q_num)
> +{
> +       u32 val = dma_ch_obj->global_cfg;
> +
> +       /* Clear the fields to be modified. */
> +       val &= ~(DMA_CH_TX_DEFAULT_QMGR_MASK | DMA_CH_TX_DEFAULT_QNUM_MASK |
> +                DMA_CH_TX_ENABLE_MASK);
> +
> +       /* Set the default completion queue. */
> +       val |= ((q_mgr << DMA_CH_TX_DEFAULT_QMGR_SHIFT) &
> +               DMA_CH_TX_DEFAULT_QMGR_MASK) |
> +              ((q_num << DMA_CH_TX_DEFAULT_QNUM_SHIFT) &
> +               DMA_CH_TX_DEFAULT_QNUM_MASK);
> +
> +       /* Get the current state of the enable bit. */
> +       dma_ch_obj->global_cfg = val |= __raw_readl(dma_ch_obj->base_addr);
> +       __raw_writel(val, dma_ch_obj->base_addr);
> +       pr_debug("Channel global configuration @ %p, value written: %x, "
> +                "value read: %x\n", dma_ch_obj->base_addr, val,
> +                __raw_readl(dma_ch_obj->base_addr));
> +
> +}
> +EXPORT_SYMBOL(cppi41_dma_ch_default_queue);
> +
> +/*
> + * cppi41_rx_ch_configure - configure CPPI 4.1 Rx channel
> + */
> +void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
> +                           struct cppi41_rx_ch_cfg  *cfg)
> +{
> +       void __iomem *base = rx_ch_obj->base_addr;
> +       u32 val = __raw_readl(rx_ch_obj->base_addr);
> +
> +       val |= ((cfg->sop_offset << DMA_CH_RX_SOP_OFFSET_SHIFT) &
> +               DMA_CH_RX_SOP_OFFSET_MASK) |
> +              ((cfg->default_desc_type << DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT) &
> +               DMA_CH_RX_DEFAULT_DESC_TYPE_MASK) |
> +              ((cfg->retry_starved << DMA_CH_RX_ERROR_HANDLING_SHIFT) &
> +               DMA_CH_RX_ERROR_HANDLING_MASK) |
> +              ((cfg->rx_queue.q_mgr << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT) &
> +               DMA_CH_RX_DEFAULT_RQ_QMGR_MASK) |
> +              ((cfg->rx_queue.q_num << DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT) &
> +               DMA_CH_RX_DEFAULT_RQ_QNUM_MASK);
> +
> +       rx_ch_obj->global_cfg = val;
> +       __raw_writel(val, base);
> +       pr_debug("Rx channel global configuration @ %p, value written: %x, "
> +                "value read: %x\n", base, val, __raw_readl(base));
> +
> +       base -= DMA_CH_RX_GLOBAL_CFG_REG(0);
> +
> +       /*
> +        * Set up the packet configuration register
> +        * based on the descriptor type...
> +        */
> +       switch (cfg->default_desc_type) {
> +       case DMA_CH_RX_DEFAULT_DESC_EMBED:
> +               val = ((cfg->cfg.embed_pkt.fd_queue.q_mgr <<
> +                       DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT) &
> +                      DMA_CH_RX_EMBED_FDQ_QMGR_MASK) |
> +                     ((cfg->cfg.embed_pkt.fd_queue.q_num <<
> +                       DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT) &
> +                      DMA_CH_RX_EMBED_FDQ_QNUM_MASK) |
> +                     ((cfg->cfg.embed_pkt.num_buf_slot <<
> +                       DMA_CH_RX_EMBED_NUM_SLOT_SHIFT) &
> +                      DMA_CH_RX_EMBED_NUM_SLOT_MASK) |
> +                     ((cfg->cfg.embed_pkt.sop_slot_num <<
> +                       DMA_CH_RX_EMBED_SOP_SLOT_SHIFT) &
> +                      DMA_CH_RX_EMBED_SOP_SLOT_MASK);
> +
> +               __raw_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0));
> +               pr_debug("Rx channel embedded packet configuration B @ %p, "
> +                        "value written: %x\n",
> +                        base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0), val);
> +
> +               val = ((cfg->cfg.embed_pkt.free_buf_pool[0].b_pool <<
> +                       DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(0)) &
> +                      DMA_CH_RX_EMBED_FBP_PNUM_MASK(0)) |
> +                     ((cfg->cfg.embed_pkt.free_buf_pool[0].b_mgr <<
> +                       DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(0)) &
> +                      DMA_CH_RX_EMBED_FBP_BMGR_MASK(0)) |
> +                     ((cfg->cfg.embed_pkt.free_buf_pool[1].b_pool <<
> +                       DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(1)) &
> +                      DMA_CH_RX_EMBED_FBP_PNUM_MASK(1)) |
> +                     ((cfg->cfg.embed_pkt.free_buf_pool[1].b_mgr <<
> +                       DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(1)) &
> +                      DMA_CH_RX_EMBED_FBP_BMGR_MASK(1)) |
> +                     ((cfg->cfg.embed_pkt.free_buf_pool[2].b_pool <<
> +                       DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(2)) &
> +                      DMA_CH_RX_EMBED_FBP_PNUM_MASK(2)) |
> +                     ((cfg->cfg.embed_pkt.free_buf_pool[2].b_mgr <<
> +                       DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(2)) &
> +                      DMA_CH_RX_EMBED_FBP_BMGR_MASK(2)) |
> +                     ((cfg->cfg.embed_pkt.free_buf_pool[3].b_pool <<
> +                       DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(3)) &
> +                      DMA_CH_RX_EMBED_FBP_PNUM_MASK(3)) |
> +                     ((cfg->cfg.embed_pkt.free_buf_pool[3].b_mgr <<
> +                       DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(3)) &
> +                      DMA_CH_RX_EMBED_FBP_BMGR_MASK(3));
> +
> +               __raw_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0));
> +               pr_debug("Rx channel embedded packet configuration A @ %p, "
> +                        "value written: %x\n",
> +                        base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0), val);
> +               break;
> +       case DMA_CH_RX_DEFAULT_DESC_HOST:
> +               val = ((cfg->cfg.host_pkt.fdb_queue[0].q_num <<
> +                       DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(0)) &
> +                      DMA_CH_RX_HOST_FDQ_QNUM_MASK(0)) |
> +                     ((cfg->cfg.host_pkt.fdb_queue[0].q_mgr <<
> +                       DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(0)) &
> +                      DMA_CH_RX_HOST_FDQ_QMGR_MASK(0)) |
> +                     ((cfg->cfg.host_pkt.fdb_queue[1].q_num <<
> +                       DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(1)) &
> +                      DMA_CH_RX_HOST_FDQ_QNUM_MASK(1)) |
> +                     ((cfg->cfg.host_pkt.fdb_queue[1].q_mgr <<
> +                       DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(1)) &
> +                      DMA_CH_RX_HOST_FDQ_QMGR_MASK(1));
> +
> +               __raw_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0));
> +               pr_debug("Rx channel host packet configuration A @ %p, "
> +                        "value written: %x\n",
> +                        base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0), val);
> +
> +               val = ((cfg->cfg.host_pkt.fdb_queue[2].q_num <<
> +                       DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(2)) &
> +                      DMA_CH_RX_HOST_FDQ_QNUM_MASK(2)) |
> +                     ((cfg->cfg.host_pkt.fdb_queue[2].q_mgr <<
> +                       DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(2)) &
> +                      DMA_CH_RX_HOST_FDQ_QMGR_MASK(2)) |
> +                     ((cfg->cfg.host_pkt.fdb_queue[3].q_num <<
> +                      DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(3)) &
> +                      DMA_CH_RX_HOST_FDQ_QNUM_MASK(3)) |
> +                     ((cfg->cfg.host_pkt.fdb_queue[3].q_mgr <<
> +                       DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(3)) &
> +                      DMA_CH_RX_HOST_FDQ_QMGR_MASK(3));
> +
> +               __raw_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0));
> +               pr_debug("Rx channel host packet configuration B @ %p, "
> +                        "value written: %x\n",
> +                        base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0), val);
> +               break;
> +       case DMA_CH_RX_DEFAULT_DESC_MONO:
> +               val = ((cfg->cfg.mono_pkt.fd_queue.q_num <<
> +                       DMA_CH_RX_MONO_FDQ_QNUM_SHIFT) &
> +                      DMA_CH_RX_MONO_FDQ_QNUM_MASK) |
> +                     ((cfg->cfg.mono_pkt.fd_queue.q_mgr <<
> +                       DMA_CH_RX_MONO_FDQ_QMGR_SHIFT) &
> +                      DMA_CH_RX_MONO_FDQ_QMGR_MASK) |
> +                     ((cfg->cfg.mono_pkt.sop_offset <<
> +                       DMA_CH_RX_MONO_SOP_OFFSET_SHIFT) &
> +                      DMA_CH_RX_MONO_SOP_OFFSET_MASK);
> +
> +               __raw_writel(val, base + DMA_CH_RX_MONO_PKT_CFG_REG(0));
> +               pr_debug("Rx channel monolithic packet configuration @ %p, "
> +                        "value written: %x\n",
> +                        base + DMA_CH_RX_MONO_PKT_CFG_REG(0), val);
> +               break;
> +       }
> +}
> +EXPORT_SYMBOL(cppi41_rx_ch_configure);
> +
> +/*
> + * cppi41_dma_ch_teardown - teardown a given Tx/Rx channel
> + */
> +void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj)
> +{
> +       u32 val = __raw_readl(dma_ch_obj->base_addr);
> +
> +       /* Initiate channel teardown. */
> +       val |= dma_ch_obj->global_cfg & ~DMA_CH_TX_ENABLE_MASK;
> +       dma_ch_obj->global_cfg = val |= DMA_CH_TX_TEARDOWN_MASK;
> +       __raw_writel(val, dma_ch_obj->base_addr);
> +       pr_debug("Tear down channel @ %p, value written: %x, value read: %x\n",
> +                dma_ch_obj->base_addr, val,
> +                __raw_readl(dma_ch_obj->base_addr));
> +}
> +EXPORT_SYMBOL(cppi41_dma_ch_teardown);
> +
> +/*
> + * cppi41_dma_ch_enable - enable Tx/Rx DMA channel in hardware
> + *
> + * Makes the channel ready for data transmission/reception.
> + */
> +void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj)
> +{
> +       u32 val = dma_ch_obj->global_cfg | DMA_CH_TX_ENABLE_MASK;
> +
> +       /* Teardown bit remains set after completion, so clear it now... */
> +       dma_ch_obj->global_cfg = val &= ~DMA_CH_TX_TEARDOWN_MASK;
> +       __raw_writel(val, dma_ch_obj->base_addr);
> +       pr_debug("Enable channel @ %p, value written: %x, value read: %x\n",
> +                dma_ch_obj->base_addr, val,
> +                __raw_readl(dma_ch_obj->base_addr));
> +}
> +EXPORT_SYMBOL(cppi41_dma_ch_enable);
> +
> +/*
> + * cppi41_dma_ch_disable - disable Tx/Rx DMA channel in hardware
> + */
> +void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj)
> +{
> +       dma_ch_obj->global_cfg &= ~DMA_CH_TX_ENABLE_MASK;
> +       __raw_writel(dma_ch_obj->global_cfg, dma_ch_obj->base_addr);
> +       pr_debug("Disable channel @ %p, value written: %x, value read: %x\n",
> +                dma_ch_obj->base_addr, dma_ch_obj->global_cfg,
> +                __raw_readl(dma_ch_obj->base_addr));
> +}
> +EXPORT_SYMBOL(cppi41_dma_ch_disable);
> +
> +/**
> + * alloc_queue - allocate a queue in the given range
> + * @allocated: pointer to the bitmap of the allocated queues
> + * @excluded:  pointer to the bitmap of the queues excluded from allocation
> + *             (optional)
> + * @start:     starting queue number
> + * @count:     number of queues available
> + *
> + * Returns queue number on success, -ENOSPC otherwise.
> + */
> +static int alloc_queue(unsigned long *allocated, const unsigned long *excluded,
> +                      unsigned start, unsigned count)
> +{
> +       unsigned n, end = start + count;
> +
> +       do {
> +               n = find_next_zero_bit(allocated, end, start);
> +               if (n >= end)
> +                       return -ENOSPC;
> +               start = n + 1;
> +       } while (test_bit(n, excluded) || test_and_set_bit(n, allocated));
> +
> +       return n;
> +}
> +
> +/*
> + * cppi41_queue_alloc - allocate a queue of a given type in the queue manager
> + */
> +int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num)
> +{
> +       int res = -ENOSPC;
> +
> +       if (q_mgr >= cppi41_num_queue_mgr)
> +               return -EINVAL;
> +
> +       /* Mask out the unsupported queue types */
> +       type &= cppi41_queue_mgr[q_mgr].queue_types;
> +       /* First see if a free descriptor queue was requested... */
> +       if (type & CPPI41_FREE_DESC_QUEUE)
> +               res = alloc_queue(allocated_queues[q_mgr], NULL,
> +                                 cppi41_queue_mgr[q_mgr].base_fdq_num,  16);
> +
> +       /* Then see if a free descriptor/buffer queue was requested... */
> +       if (res < 0 && (type & CPPI41_FREE_DESC_BUF_QUEUE))
> +               res = alloc_queue(allocated_queues[q_mgr], NULL,
> +                                 cppi41_queue_mgr[q_mgr].base_fdbq_num, 16);
> +
> +       /* Last see if an unassigned queue was requested... */
> +       if (res < 0 && (type & CPPI41_UNASSIGNED_QUEUE))
> +               res = alloc_queue(allocated_queues[q_mgr],
> +                                 cppi41_queue_mgr[q_mgr].assigned, 0,
> +                                 cppi41_queue_mgr[q_mgr].num_queue);
> +
> +       /* See if any queue was allocated... */
> +       if (res < 0)
> +               return res;
> +
> +       /* Return the queue allocated */
> +       *q_num = res;
> +       return 0;
> +}
> +EXPORT_SYMBOL(cppi41_queue_alloc);
> +
> +/*
> + * cppi41_queue_free - free the given queue in the queue manager
> + */
> +int cppi41_queue_free(u8 q_mgr, u16 q_num)
> +{
> +       if (q_mgr >= cppi41_num_queue_mgr ||
> +           q_num >= cppi41_queue_mgr[q_mgr].num_queue ||
> +           !test_and_clear_bit(q_num, allocated_queues[q_mgr]))
> +               return -EINVAL;
> +       else
> +               return 0;
> +}
> +EXPORT_SYMBOL(cppi41_queue_free);
> +
> +/*
> + * cppi41_queue_init - initialize a CPPI 4.1 queue object
> + */
> +int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num)
> +{
> +       if (q_mgr >= cppi41_num_queue_mgr ||
> +           q_num >= cppi41_queue_mgr[q_mgr].num_queue)
> +               return -EINVAL;
> +
> +       queue_obj->base_addr = cppi41_queue_mgr[q_mgr].q_mgmt_rgn_base +
> +                              QMGR_QUEUE_STATUS_REG_A(q_num);
> +
> +       return 0;
> +}
> +EXPORT_SYMBOL(cppi41_queue_init);
> +
> +/*
> + * cppi41_queue_push - push a descriptor into the given queue
> + */
> +void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
> +                      u32 desc_size, u32 pkt_size)
> +{
> +       u32 val;
> +
> +       /*
> +        * Write to the tail of the queue.
> +        * TODO: Can't think of a reason why a queue to head may be required.
> +        * If it is, the API may have to be extended.
> +        */
> +#if 0
> +       /*
> +        * Also, can't understand why packet size is required to queue up a
> +        * descriptor. The spec says packet size *must* be written prior to
> +        * the packet write operation.
> +        */
> +       if (pkt_size)
> +               val = (pkt_size << QMGR_QUEUE_PKT_SIZE_SHIFT) &
> +                     QMGR_QUEUE_PKT_SIZE_MASK;
> +       __raw_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_C(0));
> +#endif
> +
> +       val = (((desc_size - 24) >> (2 - QMGR_QUEUE_DESC_SIZE_SHIFT)) &
> +              QMGR_QUEUE_DESC_SIZE_MASK) |
> +             (desc_addr & QMGR_QUEUE_DESC_PTR_MASK);
> +
> +       pr_debug("Pushing value %x to queue @ %p\n", val, queue_obj->base_addr);
> +
> +       __raw_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
> +}
> +EXPORT_SYMBOL(cppi41_queue_push);
> +
> +/*
> + * cppi41_queue_pop - pop a descriptor from a given queue
> + */
> +unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj)
> +{
> +       u32 val = __raw_readl(queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
> +
> +       pr_debug("Popping value %x from queue @ %p\n",
> +                val, queue_obj->base_addr);
> +
> +       return val & QMGR_QUEUE_DESC_PTR_MASK;
> +}
> +EXPORT_SYMBOL(cppi41_queue_pop);
> +
> +/*
> + * cppi41_get_teardown_info - extract information from a teardown descriptor
> + */
> +int cppi41_get_teardown_info(unsigned long addr, u32 *info)
> +{
> +       struct cppi41_teardown_desc *desc;
> +       int dma_num;
> +
> +       for (dma_num = 0; dma_num < cppi41_num_dma_block; dma_num++)
> +               if (addr >= dma_teardown[dma_num].phys_addr &&
> +                   addr <  dma_teardown[dma_num].phys_addr +
> +                           dma_teardown[dma_num].rgn_size)
> +                       break;
> +
> +       if (dma_num == cppi41_num_dma_block)
> +               return -EINVAL;
> +
> +       desc = addr - dma_teardown[dma_num].phys_addr +
> +              dma_teardown[dma_num].virt_addr;
> +
> +       if ((desc->teardown_info & CPPI41_DESC_TYPE_MASK) !=
> +           (CPPI41_DESC_TYPE_TEARDOWN << CPPI41_DESC_TYPE_SHIFT))
> +               return -EINVAL;
> +
> +       *info = desc->teardown_info;
> +#if 1
> +       /* Hardware is not giving the current DMA number as of now. :-/ */
> +       *info |= (dma_num << CPPI41_TEARDOWN_DMA_NUM_SHIFT) &
> +                CPPI41_TEARDOWN_DMA_NUM_MASK;
> +#else
> +       dma_num = (desc->teardown_info & CPPI41_TEARDOWN_DMA_NUM_MASK) >>
> +                CPPI41_TEARDOWN_DMA_NUM_SHIFT;
> +#endif
> +
> +       cppi41_queue_push(&dma_teardown[dma_num].queue_obj, addr,
> +                         sizeof(struct cppi41_teardown_desc), 0);
> +
> +       return 0;
> +}
> +EXPORT_SYMBOL(cppi41_get_teardown_info);
> Index: linux-davinci/arch/arm/include/asm/hardware/cppi41.h
> ===================================================================
> --- /dev/null
> +++ linux-davinci/arch/arm/include/asm/hardware/cppi41.h
> @@ -0,0 +1,718 @@
> +/*
> + * CPPI 4.1 definitions
> + *
> + * Copyright (c) 2008-2010, MontaVista Software, Inc. <source at mvista.com>
> + *
> + * Based on the PAL CPPI 4.1 implementation
> + * Copyright (C) 2007, Texas Instruments, Inc. http://www.ti.com/
> + *
> + * This program is free software; you can distribute it and/or modify it
> + * under the terms of the GNU General Public License (Version 2) as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
> + * for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
> + *
> + */
> +
> +#include <linux/types.h>
> +
> +/*
> + * Queue Manager - Control Registers Region
> + */
> +#define QMGR_REVISION_REG              0x00    /* Major and minor versions */
> +                                               /* of the module */
> +#define QMGR_QUEUE_DIVERSION_REG       0x08    /* Queue Diversion register */
> +#define QMGR_FREE_DESC_BUF_STARVED_REG(n) (0x20 + ((n) << 2)) /* Free Desc./ */
> +                                               /* Buffer Starvation Count */
> +#define QMGR_FREE_DESC_STARVED_REG(n)  (0x30 + ((n) << 2)) /* Free Desc. */
> +                                               /* Starvation Count */
> +#define QMGR_LINKING_RAM_RGN0_BASE_REG 0x80    /* Linking RAM Region 0 Base */
> +                                               /* Address */
> +#define QMGR_LINKING_RAM_RGN0_SIZE_REG 0x84    /* Linking RAM Region 0 Size */
> +#define QMGR_LINKING_RAM_RGN1_BASE_REG 0x88    /* Linking RAM Region 1 Base */
> +                                               /* Address */
> +#define QMGR_QUEUE_PENDING_REG(n)      (0x90 + ((n) << 2)) /* Pending status */
> +                                               /* for all queues */
> +
> +/*
> + * Queue Manager - Memory Region Registers
> + */
> +#define QMGR_MEM_RGN_BASE_REG(r)       (0x00 + ((r) << 4))
> +#define QMGR_MEM_RGN_CTRL_REG(r)       (0x04 + ((r) << 4))
> +
> +/* Memory Region R Control Register bits */
> +#define QMGR_MEM_RGN_INDEX_SHIFT       16
> +#define QMGR_MEM_RGN_INDEX_MASK        (0x3fff << QMGR_MEM_RGN_INDEX_SHIFT)
> +#define QMGR_MEM_RGN_DESC_SIZE_SHIFT   8
> +#define QMGR_MEM_RGN_DESC_SIZE_MASK    (0xf << QMGR_MEM_RGN_DESC_SIZE_SHIFT)
> +#define QMGR_MEM_RGN_SIZE_SHIFT        0
> +#define QMGR_MEM_RGN_SIZE_MASK         (7 << QMGR_MEM_RGN_SIZE_SHIFT)
> +
> +/*
> + * Queue Manager - Queues Region
> + */
> +#define QMGR_QUEUE_REG_A(n)            (0x00 + ((n) << 4))
> +#define QMGR_QUEUE_REG_B(n)            (0x04 + ((n) << 4))
> +#define QMGR_QUEUE_REG_C(n)            (0x08 + ((n) << 4))
> +#define QMGR_QUEUE_REG_D(n)            (0x0C + ((n) << 4))
> +
> +/* Queue N Register C bits */
> +#define QMGR_QUEUE_HEAD_TAIL_SHIFT     31
> +#define QMGR_QUEUE_HEAD_TAIL_MASK      (1 << QMGR_QUEUE_HEAD_TAIL_SHIFT)
> +#define QMGR_QUEUE_PKT_SIZE_SHIFT      0
> +#define QMGR_QUEUE_PKT_SIZE_MASK       (0x3fff << QMGR_QUEUE_PKT_SIZE_SHIFT)
> +/* Queue N Register D bits */
> +#define QMGR_QUEUE_DESC_PTR_SHIFT      5
> +#define QMGR_QUEUE_DESC_PTR_MASK       (0x7ffffff << QMGR_QUEUE_DESC_PTR_SHIFT)
> +#define QMGR_QUEUE_DESC_SIZE_SHIFT     0
> +#define QMGR_QUEUE_DESC_SIZE_MASK      (0x1f << QMGR_QUEUE_DESC_SIZE_SHIFT)
> +
> +/*
> + * Queue Manager - Queue Status Region
> + */
> +#define QMGR_QUEUE_STATUS_REG_A(n)     (0x00 + ((n) << 4))
> +#define QMGR_QUEUE_STATUS_REG_B(n)     (0x04 + ((n) << 4))
> +#define QMGR_QUEUE_STATUS_REG_C(n)     (0x08 + ((n) << 4))
> +
> +/*
> + * DMA Controller - Global Control Registers Region
> + */
> +#define DMA_REVISION_REG               0x00    /* Major and minor versions */
> +                                               /* of the module */
> +#define DMA_TEARDOWN_FREE_DESC_CTRL_REG 0x04   /* Queue  manager and queue */
> +                                               /* number for Teardown free */
> +                                               /* descriptor queue */
> +#define DMA_EMULATION_CTRL_REG         0x08    /* Emulation control register */
> +
> +/* Teardown Free Descriptor Queue Control Register bits */
> +#define DMA_TD_DESC_QMGR_SHIFT         12
> +#define DMA_TD_DESC_QMGR_MASK          (3 << DMA_TD_DESC_QMGR_SHIFT)
> +#define DMA_TD_DESC_QNUM_SHIFT         0
> +#define DMA_TD_DESC_QNUM_MASK          (0xfff << DMA_TD_DESC_QNUM_SHIFT)
> +
> +/*
> + * DMA Controller - Channel Control / Status Registers Region
> + */
> +#define DMA_CH_TX_GLOBAL_CFG_REG(n)     (0x00 + ((n) << 5))
> +#define DMA_CH_RX_GLOBAL_CFG_REG(n)     (0x08 + ((n) << 5))
> +#define DMA_CH_RX_HOST_PKT_CFG_REG_A(n)  (0x0C + ((n) << 5))
> +#define DMA_CH_RX_HOST_PKT_CFG_REG_B(n)  (0x10 + ((n) << 5))
> +#define DMA_CH_RX_EMBED_PKT_CFG_REG_A(n) (0x14 + ((n) << 5))
> +#define DMA_CH_RX_EMBED_PKT_CFG_REG_B(n) (0x18 + ((n) << 5))
> +#define DMA_CH_RX_MONO_PKT_CFG_REG(n)   (0x1C + ((n) << 5))
> +
> +/* Tx Channel N Global Configuration Register bits */
> +#define DMA_CH_TX_ENABLE_SHIFT         31
> +#define DMA_CH_TX_ENABLE_MASK          (1 << DMA_CH_TX_ENABLE_SHIFT)
> +#define DMA_CH_TX_TEARDOWN_SHIFT       30
> +#define DMA_CH_TX_TEARDOWN_MASK                (1 << DMA_CH_TX_TEARDOWN_SHIFT)
> +#define DMA_CH_TX_DEFAULT_QMGR_SHIFT   12
> +#define DMA_CH_TX_DEFAULT_QMGR_MASK    (3 << DMA_CH_TX_DEFAULT_QMGR_SHIFT)
> +#define DMA_CH_TX_DEFAULT_QNUM_SHIFT   0
> +#define DMA_CH_TX_DEFAULT_QNUM_MASK    (0xfff << DMA_CH_TX_DEFAULT_QNUM_SHIFT)
> +
> +/* Rx Channel N Global Configuration Register bits */
> +#define DMA_CH_RX_ENABLE_SHIFT         31
> +#define DMA_CH_RX_ENABLE_MASK          (1 << DMA_CH_RX_ENABLE_SHIFT)
> +#define DMA_CH_RX_TEARDOWN_SHIFT       30
> +#define DMA_CH_RX_TEARDOWN_MASK                (1 << DMA_CH_RX_TEARDOWN_SHIFT)
> +#define DMA_CH_RX_ERROR_HANDLING_SHIFT 24
> +#define DMA_CH_RX_ERROR_HANDLING_MASK  (1 << DMA_CH_RX_ERROR_HANDLING_SHIFT)
> +#define DMA_CH_RX_SOP_OFFSET_SHIFT     16
> +#define DMA_CH_RX_SOP_OFFSET_MASK      (0xff << DMA_CH_RX_SOP_OFFSET_SHIFT)
> +#define DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT 14
> +#define DMA_CH_RX_DEFAULT_DESC_TYPE_MASK  (3 << \
> +                                          DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT)
> +#define DMA_CH_RX_DEFAULT_DESC_EMBED   0
> +#define DMA_CH_RX_DEFAULT_DESC_HOST    1
> +#define DMA_CH_RX_DEFAULT_DESC_MONO    2
> +#define DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT 12
> +#define DMA_CH_RX_DEFAULT_RQ_QMGR_MASK (3 << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT)
> +#define DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT 0
> +#define DMA_CH_RX_DEFAULT_RQ_QNUM_MASK (0xfff << \
> +                                        DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT)
> +
> +/* Rx Channel N Host Packet Configuration Register A/B bits */
> +#define DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(n) (12 + 16 * ((n) & 1))
> +#define DMA_CH_RX_HOST_FDQ_QMGR_MASK(n)  (3 << DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(n))
> +#define DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(n) (0 + 16 * ((n) & 1))
> +#define DMA_CH_RX_HOST_FDQ_QNUM_MASK(n)  (0xfff << \
> +                                         DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(n))
> +
> +/* Rx Channel N Embedded Packet Configuration Register A bits */
> +#define DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(n) (6 + 8 * (n))
> +#define DMA_CH_RX_EMBED_FBP_BMGR_MASK(n)  (3 << \
> +                                          DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(n))
> +#define DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(n) (0 + 8 * (n))
> +#define DMA_CH_RX_EMBED_FBP_PNUM_MASK(n)  (0x1f << \
> +                                          DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(n))
> +
> +/* Rx Channel N Embedded Packet Configuration Register B bits */
> +#define DMA_CH_RX_EMBED_NUM_SLOT_SHIFT 24
> +#define DMA_CH_RX_EMBED_NUM_SLOT_MASK  (7 << DMA_CH_RX_EMBED_NUM_SLOT_SHIFT)
> +#define DMA_CH_RX_EMBED_SOP_SLOT_SHIFT 16
> +#define DMA_CH_RX_EMBED_SOP_SLOT_MASK  (7 << DMA_CH_RX_EMBED_SOP_SLOT_SHIFT)
> +#define DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT 12
> +#define DMA_CH_RX_EMBED_FDQ_QMGR_MASK  (3 << DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT)
> +#define DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT 0
> +#define DMA_CH_RX_EMBED_FDQ_QNUM_MASK  (0xfff << \
> +                                        DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT)
> +
> +/* Rx Channel N Monolithic Packet Configuration Register bits */
> +#define DMA_CH_RX_MONO_SOP_OFFSET_SHIFT 16
> +#define DMA_CH_RX_MONO_SOP_OFFSET_MASK (0xff << \
> +                                        DMA_CH_RX_MONO_SOP_OFFSET_SHIFT)
> +#define DMA_CH_RX_MONO_FDQ_QMGR_SHIFT  12
> +#define DMA_CH_RX_MONO_FDQ_QMGR_MASK   (3 << DMA_CH_RX_MONO_FDQ_QMGR_SHIFT)
> +#define DMA_CH_RX_MONO_FDQ_QNUM_SHIFT  0
> +#define DMA_CH_RX_MONO_FDQ_QNUM_MASK   (0xfff << DMA_CH_RX_MONO_FDQ_QNUM_SHIFT)
> +
> +/*
> + * DMA Scheduler - Control Region
> + */
> +#define DMA_SCHED_CTRL_REG             0x00
> +
> +/* DMA Scheduler Control Register bits */
> +#define DMA_SCHED_ENABLE_SHIFT         31
> +#define DMA_SCHED_ENABLE_MASK          (1 << DMA_SCHED_ENABLE_SHIFT)
> +#define DMA_SCHED_LAST_ENTRY_SHIFT     0
> +#define DMA_SCHED_LAST_ENTRY_MASK      (0xff << DMA_SCHED_LAST_ENTRY_SHIFT)
> +
> +/*
> + * DMA Scheduler - Table Region
> + */
> +#define DMA_SCHED_TABLE_WORD_REG(n)    ((n) << 2)
> +
> +/*
> + * CPPI 4.1 Host Packet Descriptor
> + */
> +struct cppi41_host_pkt_desc {
> +       u32 desc_info;          /* Descriptor type, protocol specific word */
> +                               /* count, packet length */
> +       u32 tag_info;           /* Source tag (31:16), destination tag (15:0) */
> +       u32 pkt_info;           /* Packet error state, type, protocol flags, */
> +                               /* return info, descriptor location */
> +       u32 buf_len;            /* Number of valid data bytes in the buffer */
> +       u32 buf_ptr;            /* Pointer to the buffer associated with */
> +                               /* this descriptor */
> +       u32 next_desc_ptr;      /* Pointer to the next buffer descriptor */
> +       u32 orig_buf_len;       /* Original buffer length */
> +       u32 orig_buf_ptr;       /* Original buffer pointer */
> +       u32 stk_comms_info[2];  /* Network stack private communications info */
> +};
> +
> +/*
> + * CPPI 4.1 Host Buffer Descriptor
> + */
> +struct cppi41_host_buf_desc {
> +       u32 reserved[2];
> +       u32 buf_recl_info;      /* Return info, descriptor location */
> +       u32 buf_len;            /* Number of valid data bytes in the buffer */
> +       u32 buf_ptr;            /* Pointer to the buffer associated with */
> +                               /* this descriptor */
> +       u32 next_desc_ptr;      /* Pointer to the next buffer descriptor */
> +       u32 orig_buf_len;       /* Original buffer length */
> +       u32 orig_buf_ptr;       /* Original buffer pointer */
> +};
> +
> +#define CPPI41_DESC_TYPE_SHIFT         27
> +#define CPPI41_DESC_TYPE_MASK          (0x1f << CPPI41_DESC_TYPE_SHIFT)
> +#define CPPI41_DESC_TYPE_HOST          16
> +#define CPPI41_DESC_TYPE_MONOLITHIC    18
> +#define CPPI41_DESC_TYPE_TEARDOWN      19
> +#define CPPI41_PROT_VALID_WORD_CNT_SHIFT 22
> +#define CPPI41_PROT_VALID_WORD_CNT_MASK        (0x1f << CPPI41_PROT_WORD_CNT_SHIFT)
> +#define CPPI41_PKT_LEN_SHIFT           0
> +#define CPPI41_PKT_LEN_MASK            (0x1fffff << CPPI41_PKT_LEN_SHIFT)
> +
> +#define CPPI41_PKT_ERROR_SHIFT         31
> +#define CPPI41_PKT_ERROR_MASK          (1 << CPPI41_PKT_ERROR_SHIFT)
> +#define CPPI41_PKT_TYPE_SHIFT          26
> +#define CPPI41_PKT_TYPE_MASK           (0x1f << CPPI41_PKT_TYPE_SHIFT)
> +#define CPPI41_PKT_TYPE_ATM_AAL5       0
> +#define CPPI41_PKT_TYPE_ATM_NULL_AAL   1
> +#define CPPI41_PKT_TYPE_ATM_OAM                2
> +#define CPPI41_PKT_TYPE_ATM_TRANSPARENT        3
> +#define CPPI41_PKT_TYPE_EFM            4
> +#define CPPI41_PKT_TYPE_USB            5
> +#define CPPI41_PKT_TYPE_GENERIC                6
> +#define CPPI41_PKT_TYPE_ETHERNET       7
> +#define CPPI41_RETURN_POLICY_SHIFT     15
> +#define CPPI41_RETURN_POLICY_MASK      (1 << CPPI41_RETURN_POLICY_SHIFT)
> +#define CPPI41_RETURN_LINKED           0
> +#define CPPI41_RETURN_UNLINKED         1
> +#define CPPI41_ONCHIP_SHIFT            14
> +#define CPPI41_ONCHIP_MASK             (1 << CPPI41_ONCHIP_SHIFT)
> +#define CPPI41_RETURN_QMGR_SHIFT       12
> +#define CPPI41_RETURN_QMGR_MASK                (3 << CPPI41_RETURN_QMGR_SHIFT)
> +#define CPPI41_RETURN_QNUM_SHIFT       0
> +#define CPPI41_RETURN_QNUM_MASK                (0xfff << CPPI41_RETURN_QNUM_SHIFT)
> +
> +#define CPPI41_SRC_TAG_PORT_NUM_SHIFT  27
> +#define CPPI41_SRC_TAG_PORT_NUM_MASK   (0x1f << CPPI41_SRC_TAG_PORT_NUM_SHIFT)
> +#define CPPI41_SRC_TAG_CH_NUM_SHIFT    21
> +#define CPPI41_SRC_TAG_CH_NUM_MASK     (0x3f << CPPI41_SRC_TAG_CH_NUM_SHIFT)
> +#define CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT 16
> +#define CPPI41_SRC_TAG_SUB_CH_NUM_MASK (0x1f << \
> +                                       CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT)
> +#define CPPI41_DEST_TAG_SHIFT          0
> +#define CPPI41_DEST_TAG_MASK           (0xffff << CPPI41_DEST_TAG_SHIFT)
> +
> +/*
> + * CPPI 4.1 Teardown Descriptor
> + */
> +struct cppi41_teardown_desc {
> +       u32 teardown_info;      /* Teardown information */
> +       u32 reserved[7];        /* 28 byte padding */
> +};
> +
> +#define CPPI41_TEARDOWN_TX_RX_SHIFT    16
> +#define CPPI41_TEARDOWN_TX_RX_MASK     (1 << CPPI41_TEARDOWN_TX_RX_SHIFT)
> +#define CPPI41_TEARDOWN_DMA_NUM_SHIFT  10
> +#define CPPI41_TEARDOWN_DMA_NUM_MASK   (0x3f << CPPI41_TEARDOWN_DMA_NUM_SHIFT)
> +#define CPPI41_TEARDOWN_CHAN_NUM_SHIFT 0
> +#define CPPI41_TEARDOWN_CHAN_NUM_MASK  (0x3f << CPPI41_TEARDOWN_CHAN_NUM_SHIFT)
> +
> +#define CPPI41_MAX_MEM_RGN             16
> +
> +/* CPPI 4.1 configuration for DA8xx */
> +#define CPPI41_NUM_QUEUE_MGR           1       /* 4  max */
> +#define CPPI41_NUM_DMA_BLOCK           4       /* 64 max */
> +
> +/**
> + * struct cppi41_queue - Queue Tuple
> + *
> + * The basic queue tuple in CPPI 4.1 used across all data structures
> + * where a definition of a queue is required.
> + */
> +struct cppi41_queue {
> +       u8  q_mgr;              /* The queue manager number */
> +       u16 q_num;              /* The queue number */
> +};
> +
> +/**
> + * struct cppi41_buf_pool - Buffer Pool Tuple
> + *
> + * The basic buffer pool tuple in CPPI 4.1 used across all data structures
> + * where a definition of a buffer pool is required.
> + */
> +struct cppi41_buf_pool {
> +       u8  b_mgr;              /* The buffer manager number */
> +       u16 b_pool;             /* The buffer pool number */
> +};
> +
> +/**
> + * struct cppi41_queue_mgr - Queue Manager information
> + *
> + * Contains the information about the queue manager which should be copied from
> + * the hardware spec as is.
> + */
> +struct cppi41_queue_mgr {
> +       void __iomem *q_mgr_rgn_base; /* Base address of the Control region. */
> +       void __iomem *desc_mem_rgn_base; /* Base address of the descriptor */
> +                               /* memory region. */
> +       void __iomem *q_mgmt_rgn_base; /* Base address of the queues region. */
> +       void __iomem *q_stat_rgn_base; /* Base address of the queue status */
> +                               /* region. */
> +       u16 num_queue;          /* Number of the queues supported. */
> +       u8  queue_types;        /* Bitmask of the supported queue types. */
> +       u16 base_fdq_num;       /* The base free descriptor queue number. */
> +                               /* If present, there's always 16 such queues. */
> +       u16 base_fdbq_num;      /* The base free descriptor/buffer queue */
> +                               /* number.  If present, there's always 16 */
> +                               /* such queues. */
> +       const unsigned long *assigned; /* Pointer to the bitmask of the */
> +                               /* pre-assigned queues. */
> +};
> +
> +/* Queue type flags */
> +#define CPPI41_FREE_DESC_QUEUE         0x01
> +#define CPPI41_FREE_DESC_BUF_QUEUE     0x02
> +#define CPPI41_UNASSIGNED_QUEUE        0x04
> +
> +/**
> + * struct cppi41_embed_pkt_cfg - Rx Channel Embedded packet configuration
> + *
> + * An instance of this structure forms part of the Rx channel information
> + * structure.
> + */
> +struct cppi41_embed_pkt_cfg {
> +       struct cppi41_queue fd_queue; /* Free Descriptor queue.*/
> +       u8 num_buf_slot;        /* Number of buffer slots in the descriptor */
> +       u8 sop_slot_num;        /* SOP buffer slot number. */
> +       struct cppi41_buf_pool free_buf_pool[4]; /* Free Buffer pool. Element */
> +                               /* 0 used for the 1st Rx buffer, etc. */
> +};
> +
> +/**
> + * struct cppi41_host_pkt_cfg - Rx Channel Host Packet Configuration
> + *
> + * An instance of this structure forms part of the Rx channel information
> + * structure.
> + */
> +struct cppi41_host_pkt_cfg {
> +       struct cppi41_queue fdb_queue[4]; /* Free Desc/Buffer queue. Element */
> +                               /* 0 used for 1st Rx buffer, etc. */
> +};
> +
> +/**
> + * struct cppi41_mono_pkt_cfg - Rx Channel Monolithic Packet Configuration
> + *
> + * An instance of this structure forms part of the Rx channel information
> + * structure.
> + */
> +struct cppi41_mono_pkt_cfg {
> +       struct cppi41_queue fd_queue; /* Free descriptor queue */
> +       u8 sop_offset;          /* Number of bytes to skip before writing */
> +                               /* payload */
> +};
> +
> +enum cppi41_rx_desc_type {
> +       cppi41_rx_embed_desc,
> +       cppi41_rx_host_desc,
> +       cppi41_rx_mono_desc,
> +};
> +
> +/**
> + * struct cppi41_rx_ch_cfg - Rx Channel Configuration
> + *
> + * Must be allocated and filled by the caller of cppi41_rx_ch_configure().
> + *
> + * The same channel can be configured to receive different descripor type
> + * packets (not simultaneously). When the Rx packets on a port need to be sent
> + * to the SR, the channel's default descriptor type is set to Embedded and the
> + * Rx completion queue is set to the queue which CPU polls for input packets.
> + * When in SR bypass mode, the same channel's default descriptor type will be
> + * set to Host and the Rx completion queue set to one of the queues which host
> + * can get interrupted on (via the Queuing proxy/accumulator). In this example,
> + * the embedded mode configuration fetches free descriptor from the Free
> + * descriptor queue (as defined by struct cppi41_embed_pkt_cfg) and host
> + * mode configuration fetches free descriptors/buffers from the free descriptor/
> + * buffer queue (as defined by struct cppi41_host_pkt_cfg).
> + *
> + * NOTE: There seems to be no separate configuration for teardown completion
> + * descriptor. The assumption is rxQueue tuple is used for this purpose as well.
> + */
> +struct cppi41_rx_ch_cfg {
> +       enum cppi41_rx_desc_type default_desc_type; /* Describes which queue */
> +                               /* configuration is used for the free */
> +                               /* descriptors and/or buffers */
> +       u8 sop_offset;          /* Number of bytes to skip in SOP buffer */
> +                               /* before writing payload */
> +       u8 retry_starved;       /* 0 = Drop packet on descriptor/buffer */
> +                               /* starvartion, 1 = DMA retries FIFO block */
> +                               /* transfer at a later time */
> +       struct cppi41_queue rx_queue; /* Rx complete packets queue */
> +       union {
> +               struct cppi41_host_pkt_cfg host_pkt; /* Host packet */
> +                               /* configuration. This defines where channel */
> +                               /* picks free descriptors from. */
> +               struct cppi41_embed_pkt_cfg embed_pkt; /* Embedded packet */
> +                               /* configuration. This defines where channel */
> +                               /* picks free descriptors/buffers from. */
> +                               /* from. */
> +               struct cppi41_mono_pkt_cfg mono_pkt; /* Monolithic packet */
> +                               /* configuration. This defines where channel */
> +                               /* picks free descriptors from. */
> +       } cfg;                  /* Union of packet configuration structures */
> +                               /* to be filled in depending on the */
> +                               /* defDescType field. */
> +};
> +
> +/**
> + * struct cppi41_tx_ch - Tx channel information
> + *
> + * NOTE: The queues that feed into the Tx channel are fixed at SoC design time.
> + */
> +struct cppi41_tx_ch {
> +       u8 port_num;            /* Port number. */
> +       u8 ch_num;              /* Channel number within port. */
> +       u8 sub_ch_num;          /* Sub-channel number within channel. */
> +       u8 num_tx_queue;        /* Number of queues from which the channel */
> +                               /* can feed. */
> +       struct cppi41_queue tx_queue[4]; /* List of queues from which the */
> +                               /* channel can feed. */
> +};
> +
> +/**
> + * struct cppi41_dma_block - CPPI 4.1 DMA configuration
> + *
> + * Configuration information for CPPI DMA functionality. Includes the Global
> + * configuration, Channel configuration, and the Scheduler configuration.
> + */
> +struct cppi41_dma_block {
> +       void __iomem *global_ctrl_base; /* Base address of the Global Control */
> +                               /* registers. */
> +       void __iomem *ch_ctrl_stat_base; /* Base address of the Channel */
> +                               /* Control/Status registers. */
> +       void __iomem *sched_ctrl_base; /* Base address of the Scheduler */
> +                               /* Control register. */
> +       void __iomem *sched_table_base; /* Base address of the Scheduler */
> +                               /* Table registers. */
> +       u8 num_tx_ch;           /* Number of the Tx channels. */
> +       u8 num_rx_ch;           /* Number of the Rx channels. */
> +       const struct cppi41_tx_ch *tx_ch_info;
> +};
> +
> +extern const struct cppi41_queue_mgr cppi41_queue_mgr[];
> +extern const struct cppi41_dma_block cppi41_dma_block[];
> +extern const u8 cppi41_num_queue_mgr;
> +extern const u8 cppi41_num_dma_block;
> +
> +/**
> + * struct cppi41_dma_ch_obj - CPPI 4.1 DMA Channel object
> + */
> +struct cppi41_dma_ch_obj {
> +       void __iomem *base_addr; /* The address of the channel global */
> +                               /* configuration register */
> +       u32 global_cfg;         /* Tx/Rx global configuration backed-up value */
> +};
> +
> +/**
> + * struct cppi41_queue_obj - CPPI 4.1 queue object
> + */
> +struct cppi41_queue_obj {
> +       void __iomem *base_addr; /* The base address of the queue management */
> +                               /* registers */
> +};
> +
> +/**
> + * cppi41_queue_mgr_init - CPPI 4.1 queue manager initialization.
> + * @q_mgr:     the queue manager to initialize
> + * @rgn0_base: linking RAM region 0 physical address
> + * @rgn0_size: linking RAM region 0 size in 32-bit words (0 to 0x3fff)
> + *
> + * Returns 0 on success, error otherwise.
> + */
> +int cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size);
> +
> +/*
> + * CPPI 4.1 Queue Manager Memory Region Allocation and De-allocation APIs.
> + */
> +
> +/**
> + * cppi41_mem_rgn_alloc - CPPI 4.1 queue manager memory region allocation.
> + * @q_mgr:     the queue manager whose memory region to allocate
> + * @rgn_addr:  physical address of the memory region
> + * @size_order:        descriptor size as a power of two (between 5 and 13)
> + * @num_order: number of descriptors as a power of two (between 5 and 12)
> + * @mem_rgn:   pointer to the index of the memory region allocated
> + *
> + * This function allocates a memory region within the queue manager
> + * consisiting of the descriptors of paricular size and number.
> + *
> + * Returns 0 on success, error otherwise.
> + */
> +int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
> +                        u8 num_order, u8 *mem_rgn);
> +
> +/**
> + * cppi41_mem_rgn_free - CPPI 4.1 queue manager memory region de-allocation.
> + * @q_mgr:     the queue manager whose memory region was allocated
> + * @mem_rgn:   index of the memory region
> + *
> + * This function frees the memory region allocated by cppi41_mem_rgn_alloc().
> + *
> + * Returns 0 on success, -EINVAL otherwise.
> + */
> +int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn);
> +
> +/**
> + * cppi41_dma_ctrlr_init - CPPI 4.1 DMA controller initialization.
> + * @dma_num:   number of the DMA block
> + * @q_mgr:     the queue manager in which to allocate the free teardown
> + *             descriptor queue
> + * @num_order: number of teardown descriptors as a power of two (at least 5)
> + *
> + * Returns 0 on success, error otherwise.
> + */
> +int cppi41_dma_ctrlr_init(u8 dma_num, u8 q_mgr, u8 num_order);
> +
> +/**
> + * cppi41_dma_sched_init - CPPI 4.1 DMA scheduler initialization.
> + * @dma_num:   number of the DMA block
> + * @sched_tbl: the DMA scheduler table
> + * @tbl_size:  number of entries in the DMA scheduler table
> + *
> + * Returns 0 on success, error otherwise.
> + */
> +int cppi41_dma_sched_init(u8 dma_num, const u8 *sched_tbl, u16 tbl_size);
> +
> +/*
> + * CPPI 4.1 DMA Channel Management APIs
> + */
> +
> +/**
> + * cppi41_tx_ch_init - initialize CPPI 4.1 transmit channel object
> + * @tx_ch_obj: pointer to Tx channel object
> + * @dma_num:   DMA block to which this channel belongs
> + * @ch_num:    DMA channel number
> + *
> + * Returns 0 if valid Tx channel, -EINVAL otherwise.
> + */
> +int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
> +                     u8 dma_num, u8 ch_num);
> +
> +/**
> + * cppi41_rx_ch_init - initialize CPPI 4.1 receive channel object
> + * @rx_ch_obj: pointer to Rx channel object
> + * @dma_num:   DMA block to which this channel belongs
> + * @ch_num:    DMA channel number
> + *
> + * Returns 0 if valid Rx channel, -EINVAL otherwise.
> + */
> +int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
> +                     u8 dma_num, u8 ch_num);
> +
> +/**
> + * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
> + * @dma_ch_obj: pointer to DMA channel object
> + * @q_mgr:     default queue manager
> + * @q_num:     default queue number
> + *
> + * This function configures the specified channel.  The caller is required to
> + * provide the default queue onto which the teardown descriptors will be queued.
> + */
> +void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
> +                                u8 q_mgr, u16 q_num);
> +
> +/**
> + * cppi41_rx_ch_configure - configure CPPI 4.1 receive channel
> + * @rx_ch_obj: pointer to Rx channel object
> + * @cfg:       pointer to Rx channel configuration
> + *
> + * This function configures and opens the specified Rx channel.  The caller
> + * is required to provide channel configuration information by initializing
> + * a struct cppi41_rx_ch_cfg.
> + */
> +void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
> +                           struct cppi41_rx_ch_cfg  *cfg);
> +
> +/**
> + * cppi41_dma_ch_enable - enable CPPI 4.1 Tx/Rx DMA channel
> + * @dma_ch_obj:        pointer to DMA channel object
> + *
> + * This function enables  a specified Tx channel.  The caller is required to
> + * provide a reference to a channel object initialized by an earlier call of
> + * the cppi41_dma_ch_init() function.  After the successful completion of this
> + * function, the Tx DMA channel will be active and ready for data transmission.
> + */
> +void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj);
> +
> +/**
> + * cppi41_dma_ch_disable - disable CPPI 4.1 Tx/Rx DMA channel
> + * @dma_ch_obj:        pointer to DMA channel object
> + *
> + * This function disables a specific Tx channel.  The caller is required to
> + * provide a reference to a channel object initialized by an earlier call of
> + * the cppi41_dma_ch_init() function.  After the successful completion of this
> + * function, the Tx DMA channel will be deactived.
> + */
> +void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj);
> +
> +/**
> + * cppi41_dma_ch_teardown - tear down CPPI 4.1 transmit channel
> + * @dma_ch_obj:        pointer DMA channel object
> + *
> + * This function triggers the teardown of the given DMA channel.
> + *
> + * ATTENTION: Channel disable should not be called before the teardown is
> + * completed as a disable will stop the DMA scheduling on the channel resulting
> + * in the teardown complete event not being registered at all.
> + *
> + * NOTE: A successful channel teardown event is reported via queueing of a
> + * teardown descriptor.
> + *
> + * This function just sets up for the teardown of the channel and returns. The
> + * caller must detect the channel teardown event to assume that the channel is
> + * disabled.
> + *
> + * See cppi41_get_teardown_info() for the teardown completion processing.
> + */
> +void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj);
> +
> +/*
> + * CPPI 4.1 Queue Allocation and De-allocation APIs.
> + */
> +
> +/**
> + * cppi41_queue_alloc - allocate CPPI 4.1 queue
> + * @type:      queue type bitmask
> + * @q_mgr:     queue manager
> + * @q_num:     pointer to the queue number
> + *
> + * Returns 0 if queue allocated, error otherwise.
> + */
> +int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num);
> +
> +/**
> + * cppi41_queue_free - de-allocate CPPI 4.1 queue
> + * @q_mgr:     queue manager
> + * @q_num:     queue number
> + *
> + * Returns 0 on success, -EINVAL otherwise.
> + */
> +int cppi41_queue_free(u8 q_mgr, u16 q_num);
> +
> +/*
> + *  CPPI 4.1 Queue Management APIs
> + */
> +
> +/**
> + * cppi41_queue_init - initialize CPPI 4.1 queue object
> + * @queue_obj: pointer to the queue object
> + * @q_mgr:     queue manager
> + * @q_num:     queue number
> + *
> + * Returns 0 if valid queue, -EINVAL otherwise.
> + */
> +int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num);
> +
> +/**
> + * cppi41_queue_push - push to CPPI 4.1 queue
> + * @queue_obj: pointer to the queue object
> + * @desc_addr: descriptor physical address
> + * @desc_size: descriptor size
> + * @pkt_size:  packet size
> + *
> + * This function is called to queue a descriptor onto a queue.
> + * NOTE: pSize parameter is optional. Pass 0 in case not required.
> + */
> +void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
> +                      u32 desc_size, u32 pkt_size);
> +
> +/**
> + * cppi41_queue_pop - pop from CPPI 4.1 queue
> + * @queue_obj: pointer to the queue object
> + *
> + * This function is called to pop a single descriptor from the queue.
> + *
> + * Returns a packet descriptor's physical address.
> + */
> +unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj);
> +
> +/*
> + * CPPI 4.1 Miscellaneous APIs
> + */
> +
> +/**
> + * cppi41_get_teardown_info - CPPI 4.1 teardown completion processing function
> + *
> + * @addr:      physical address of teardown descriptor
> + * @info:      pointer to the teardown information word
> + *
> + * This function is called to complete the teardown processing on a channel
> + * and provides teardown information from the teardown descriptor passed to it.
> + * It also recycles the teardown descriptor back to the teardown descriptor
> + * queue.
> + *
> + * Returns 0 if valid descriptor, -EINVAL otherwise.
> + */
> +int cppi41_get_teardown_info(unsigned long addr, u32 *info);
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source

From cyril at ti.com  Tue May 18 09:25:33 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Tue, 18 May 2010 10:25:33 -0400
Subject: [PATCH v5 1/3] ARM: add CPPI 4.1 DMA support
In-Reply-To: <4BF2A2EE.7010103@ti.com>
References: <201005152214.53993.sshtylyov@ru.mvista.com>
	<4BF2A2EE.7010103@ti.com>
Message-ID: <4BF2A35D.5030100@ti.com>

Hi,

> Would you mind a brief call about this patch after we've had a chance to
> analyze this?

Apologies for the spam, hitting "reply" didn't function as expected :-)

Regards
Cyril.

From cyril at ti.com  Tue May 18 09:35:19 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Tue, 18 May 2010 10:35:19 -0400
Subject: [PATCH 4/4] davinci: Fix transparency handling with dm365.
In-Reply-To: <1274187385-10969-4-git-send-email-gilles.chanteperdrix@nexvision.fr>
References: <4BF28E20.3070701@nexvision.fr>	<1274187385-10969-1-git-send-email-gilles.chanteperdrix@nexvision.fr>	<1274187385-10969-2-git-send-email-gilles.chanteperdrix@nexvision.fr>	<1274187385-10969-3-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<1274187385-10969-4-git-send-email-gilles.chanteperdrix@nexvision.fr>
Message-ID: <4BF2A5A7.1060002@ti.com>

Hi,

[...]
> -		if (cpu_is_davinci_dm355()) {
> +		if (cpu_is_davinci_dm355() || cpu_is_davinci_dm365()) {

Why does this driver have cpu_is_ macros all over the place?

Isn't there a way to pass in the device capabilities via pdata?

Regards
Cyril.

From blueskyjb at roadrunner.com  Tue May 18 10:58:34 2010
From: blueskyjb at roadrunner.com (Jimmy Blair)
Date: Tue, 18 May 2010 08:58:34 -0700
Subject: symbols
In-Reply-To: <mailman.2182.1274192625.11996.davinci-linux-open-source@linux.davincidsp.com>
References: <mailman.2182.1274192625.11996.davinci-linux-open-source@linux.davincidsp.com>
Message-ID: <4BF2B92A.1010702@roadrunner.com>

> Message: 4
> Date: Sun, 16 May 2010 22:42:07 -0700 (PDT)
> From: Vijay Soni <vij_soni at yahoo.com>
> To: Davinci-linux-open-source at linux.davincidsp.com
> Subject: Symbol names
> Message-ID: <880572.16919.qm at web38804.mail.mud.yahoo.com>
> Content-Type: text/plain; charset="us-ascii"
> 
> Does anyone know how I can get symbols names from their addresses. I am trying to debug an kernel oops which gives function address in the Backtrace. I know I can turn on KALLSYMS but I cannot rebuild my kernel because of other module dependency. Can we get this info from vmlinux? If so how?

Brute force:  objdump --disassemble-all vmlinux

From schen at mvista.com  Tue May 18 11:50:59 2010
From: schen at mvista.com (Steve Chen)
Date: Tue, 18 May 2010 11:50:59 -0500
Subject: symbols
In-Reply-To: <4BF2B92A.1010702@roadrunner.com>
References: <mailman.2182.1274192625.11996.davinci-linux-open-source@linux.davincidsp.com>
	<4BF2B92A.1010702@roadrunner.com>
Message-ID: <AANLkTimQPV1c3o58Ij8-I49J7CZU4bR8i-FpPVUYCIp2@mail.gmail.com>

On Tue, May 18, 2010 at 10:58 AM, Jimmy Blair <blueskyjb at roadrunner.com> wrote:
>> Message: 4
>> Date: Sun, 16 May 2010 22:42:07 -0700 (PDT)
>> From: Vijay Soni <vij_soni at yahoo.com>
>> To: Davinci-linux-open-source at linux.davincidsp.com
>> Subject: Symbol names
>> Message-ID: <880572.16919.qm at web38804.mail.mud.yahoo.com>
>> Content-Type: text/plain; charset="us-ascii"
>>
>> Does anyone know how I can get symbols names from their addresses. I am
>> trying to debug an kernel oops which gives function address in the
>> Backtrace. I know I can turn on KALLSYMS but I cannot rebuild my kernel
>> because of other module dependency. Can we get this info from vmlinux? If so
>> how?
>
> Brute force: ?objdump --disassemble-all vmlinux

Take a look at System.map.

Steve

From cyril at ti.com  Tue May 18 11:51:16 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Tue, 18 May 2010 12:51:16 -0400
Subject: [PATCH v7 0/6] Davinci: initial tnetv107x patch series
Message-ID: <1274201482-15994-1-git-send-email-cyril@ti.com>

This patch series adds support for TNETV107X - a Texas Instruments SOC that
shares a number of common features with the Davinci architecture.

This version includes two minor fixes over the v6 series posted earlier.

Cyril Chemparathy (6):
  Davinci: generalized debug macros
  Davinci: tnetv107x decompresser uart definitions
  Davinci: tnetv107x soc support
  Davinci: tnetv107x initial gpio support
  Davinci: tnetv107x evm board initial support
  Davinci: tnetv107x default configuration

 arch/arm/configs/tnetv107x_defconfig             | 1741 ++++++++++++++++++++++
 arch/arm/mach-davinci/Kconfig                    |   12 +
 arch/arm/mach-davinci/Makefile                   |    3 +
 arch/arm/mach-davinci/board-tnetv107x-evm.c      |  174 +++
 arch/arm/mach-davinci/devices-tnetv107x.c        |  318 ++++
 arch/arm/mach-davinci/gpio-tnetv107x.c           |  205 +++
 arch/arm/mach-davinci/include/mach/debug-macro.S |   50 +-
 arch/arm/mach-davinci/include/mach/gpio.h        |   22 +-
 arch/arm/mach-davinci/include/mach/serial.h      |   21 +
 arch/arm/mach-davinci/include/mach/tnetv107x.h   |   55 +
 arch/arm/mach-davinci/include/mach/uncompress.h  |   87 +-
 arch/arm/mach-davinci/tnetv107x.c                |  753 ++++++++++
 12 files changed, 3402 insertions(+), 39 deletions(-)
 create mode 100644 arch/arm/configs/tnetv107x_defconfig
 create mode 100644 arch/arm/mach-davinci/board-tnetv107x-evm.c
 create mode 100644 arch/arm/mach-davinci/devices-tnetv107x.c
 create mode 100644 arch/arm/mach-davinci/gpio-tnetv107x.c
 create mode 100644 arch/arm/mach-davinci/include/mach/tnetv107x.h
 create mode 100644 arch/arm/mach-davinci/tnetv107x.c


From cyril at ti.com  Tue May 18 11:51:17 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Tue, 18 May 2010 12:51:17 -0400
Subject: [PATCH v7 1/6] Davinci: generalized debug macros
In-Reply-To: <1274201482-15994-1-git-send-email-cyril@ti.com>
References: <1274201482-15994-1-git-send-email-cyril@ti.com>
Message-ID: <1274201482-15994-2-git-send-email-cyril@ti.com>

This patch adopts a debug uart selection similar to the OMAP model.  During
the boot process, the uncompress code determines the physical and virtual base
addresses of the board-specific debug uart.  These addresses are then passed
on to the in-kernel debug macros through a small chunk of memory placed just
below the page tables (@0x80003ff8).

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v7: unchanged from v6
v6: unchanged from v5
v5: removed redundant mmu enable check
v4: unchanged from v3

 arch/arm/mach-davinci/include/mach/debug-macro.S |   50 +++++++++++---
 arch/arm/mach-davinci/include/mach/serial.h      |   13 ++++
 arch/arm/mach-davinci/include/mach/uncompress.h  |   80 ++++++++++++++++------
 3 files changed, 111 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index 3cd93a8..f761dfd 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -17,22 +17,50 @@
  */
 
 #include <linux/serial_reg.h>
+
+#include <asm/memory.h>
+
+#include <mach/serial.h>
+
 #define UART_SHIFT	2
 
+		.pushsection .data
+davinci_uart_phys:	.word	0
+davinci_uart_virt:	.word	0
+		.popsection
+
 		.macro addruart, rx, tmp
+
+		/* Use davinci_uart_phys/virt if already configured */
+10:		mrc	p15, 0, \rx, c1, c0
+		tst	\rx, #1			@ MMU enabled?
+		ldreq	\rx, =__virt_to_phys(davinci_uart_phys)
+		ldrne	\rx, =davinci_uart_virt
+		ldr	\rx, [\rx]
+		cmp	\rx, #0			@ is port configured?
+		bne	99f			@ already configured
+
 		mrc	p15, 0, \rx, c1, c0
 		tst	\rx, #1			@ MMU enabled?
-		moveq	\rx, #0x01000000	@ physical base address
-		movne	\rx, #0xfe000000	@ virtual base
-#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
-#error Cannot enable DaVinci and DA8XX platforms concurrently
-#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \
-	defined(CONFIG_MACH_DAVINCI_DA850_EVM)
-		orr	\rx, \rx, #0x00d00000	@ physical base address
-		orr	\rx, \rx, #0x0000d000	@ of UART 2
-#else
-		orr	\rx, \rx, #0x00c20000   @ UART 0
-#endif
+
+		/* Copy uart phys address from decompressor uart info */
+		ldreq	\tmp, =__virt_to_phys(davinci_uart_phys)
+		ldrne	\tmp, =davinci_uart_phys
+		ldreq	\rx, =DAVINCI_UART_INFO
+		ldrne	\rx, =__phys_to_virt(DAVINCI_UART_INFO)
+		ldr	\rx, [\rx, #0]
+		str	\rx, [\tmp]
+
+		/* Copy uart virt address from decompressor uart info */
+		ldreq	\tmp, =__virt_to_phys(davinci_uart_virt)
+		ldrne	\tmp, =davinci_uart_virt
+		ldreq	\rx, =DAVINCI_UART_INFO
+		ldrne	\rx, =__phys_to_virt(DAVINCI_UART_INFO)
+		ldr	\rx, [\rx, #4]
+		str	\rx, [\tmp]
+
+		b	10b
+99:
 		.endm
 
 		.macro	senduart,rd,rx
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index f6c4f34..b21ec22 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -11,8 +11,19 @@
 #ifndef __ASM_ARCH_SERIAL_H
 #define __ASM_ARCH_SERIAL_H
 
+#include <asm/memory.h>
+
 #include <mach/hardware.h>
 
+/*
+ * Stolen area that contains debug uart physical and virtual addresses.  These
+ * addresses are filled in by the uncompress.h code, and are used by the debug
+ * macros in debug-macro.S.
+ *
+ * This area sits just below the page tables (see arch/arm/kernel/head.S).
+ */
+#define DAVINCI_UART_INFO	(PHYS_OFFSET + 0x3ff8)
+
 #define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
@@ -26,11 +37,13 @@
 #define UART_DM646X_SCR			0x10
 #define UART_DM646X_SCR_TX_WATERMARK	0x08
 
+#ifndef __ASSEMBLY__
 struct davinci_uart_config {
 	/* Bit field of UARTs present; bit 0 --> UART1 */
 	unsigned int enabled_uarts;
 };
 
 extern int davinci_serial_init(struct davinci_uart_config *);
+#endif
 
 #endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 33796b4..20c23a3 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -1,8 +1,17 @@
 /*
  * Serial port stubs for kernel decompress status messages
  *
- *  Author:     Anant Gole
- * (C) Copyright (C) 2006, Texas Instruments, Inc
+ * Initially based on:
+ * arch/arm/plat-omap/include/mach/uncompress.h
+ *
+ * Original copyrights follow.
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon at ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source at mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2. This program is licensed "as is" without any warranty of any
@@ -11,30 +20,17 @@
 
 #include <linux/types.h>
 #include <linux/serial_reg.h>
-#include <mach/serial.h>
 
 #include <asm/mach-types.h>
 
-extern unsigned int __machine_arch_type;
+#include <mach/serial.h>
 
 static u32 *uart;
-
-static u32 *get_uart_base(void)
-{
-	if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM ||
-		__machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM)
-		return (u32 *)DA8XX_UART2_BASE;
-	else
-		return (u32 *)DAVINCI_UART0_BASE;
-}
+static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
 
 /* PORT_16C550A, in polled non-fifo mode */
-
 static void putc(char c)
 {
-	if (!uart)
-		uart = get_uart_base();
-
 	while (!(uart[UART_LSR] & UART_LSR_THRE))
 		barrier();
 	uart[UART_TX] = c;
@@ -42,12 +38,54 @@ static void putc(char c)
 
 static inline void flush(void)
 {
-	if (!uart)
-		uart = get_uart_base();
-
 	while (!(uart[UART_LSR] & UART_LSR_THRE))
 		barrier();
 }
 
-#define arch_decomp_setup()
+static inline void set_uart_info(u32 phys, void * __iomem virt)
+{
+	uart = (u32 *)phys;
+	uart_info[0] = phys;
+	uart_info[1] = (u32)virt;
+}
+
+#define _DEBUG_LL_ENTRY(machine, phys, virt)			\
+	if (machine_is_##machine()) {				\
+		set_uart_info(phys, virt);			\
+		break;						\
+	}
+
+#define DEBUG_LL_DAVINCI(machine, port)				\
+	_DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE,	\
+			IO_ADDRESS(DAVINCI_UART##port##_BASE))
+
+#define DEBUG_LL_DA8XX(machine, port)				\
+	_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE,	\
+			IO_ADDRESS(DA8XX_UART##port##_BASE))
+
+static inline void __arch_decomp_setup(unsigned long arch_id)
+{
+	/*
+	 * Initialize the port based on the machine ID from the bootloader.
+	 * Note that we're using macros here instead of switch statement
+	 * as machine_is functions are optimized out for the boards that
+	 * are not selected.
+	 */
+	do {
+		/* Davinci boards */
+		DEBUG_LL_DAVINCI(davinci_evm,		0);
+		DEBUG_LL_DAVINCI(sffsdr,		0);
+		DEBUG_LL_DAVINCI(neuros_osd2,		0);
+		DEBUG_LL_DAVINCI(davinci_dm355_evm,	0);
+		DEBUG_LL_DAVINCI(dm355_leopard,		0);
+		DEBUG_LL_DAVINCI(davinci_dm6467_evm,	0);
+		DEBUG_LL_DAVINCI(davinci_dm365_evm,	0);
+
+		/* DA8xx boards */
+		DEBUG_LL_DA8XX(davinci_da830_evm,	2);
+		DEBUG_LL_DA8XX(davinci_da850_evm,	2);
+	} while (0);
+}
+
+#define arch_decomp_setup()	__arch_decomp_setup(arch_id)
 #define arch_decomp_wdog()
-- 
1.7.0.4


From cyril at ti.com  Tue May 18 11:51:18 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Tue, 18 May 2010 12:51:18 -0400
Subject: [PATCH v7 2/6] Davinci: tnetv107x decompresser uart definitions
In-Reply-To: <1274201482-15994-1-git-send-email-cyril@ti.com>
References: <1274201482-15994-1-git-send-email-cyril@ti.com>
Message-ID: <1274201482-15994-3-git-send-email-cyril@ti.com>

Added definitions for tnetv107x uart base addresses, and modified base address
selection for kernel decompressor to check for tnetv107x machine type.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v7: unchanged from v6
v6: unchanged from v5
v5: unchanged from v4
v4: unchanged from v3
v3: migrated to uncompress.h based implementation added earlier in this series

 arch/arm/mach-davinci/include/mach/serial.h     |    8 ++++++++
 arch/arm/mach-davinci/include/mach/uncompress.h |    7 +++++++
 2 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index b21ec22..56cc338 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -32,6 +32,14 @@
 #define DA8XX_UART1_BASE	(IO_PHYS + 0x10c000)
 #define DA8XX_UART2_BASE	(IO_PHYS + 0x10d000)
 
+#define TNETV107X_UART0_BASE	(0x08108100)
+#define TNETV107X_UART1_BASE	(0x08088400)
+#define TNETV107X_UART2_BASE	(0x08108300)
+
+#define TNETV107X_UART0_VIRT	IOMEM(0xfee08100)
+#define TNETV107X_UART1_VIRT	IOMEM(0xfed88400)
+#define TNETV107X_UART2_VIRT	IOMEM(0xfee08300)
+
 /* DaVinci UART register offsets */
 #define UART_DAVINCI_PWREMU		0x0c
 #define UART_DM646X_SCR			0x10
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 20c23a3..15a6192 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -63,6 +63,10 @@ static inline void set_uart_info(u32 phys, void * __iomem virt)
 	_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE,	\
 			IO_ADDRESS(DA8XX_UART##port##_BASE))
 
+#define DEBUG_LL_TNETV107X(machine, port)			\
+	_DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE,	\
+			TNETV107X_UART##port##_VIRT)
+
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
 	/*
@@ -84,6 +88,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 		/* DA8xx boards */
 		DEBUG_LL_DA8XX(davinci_da830_evm,	2);
 		DEBUG_LL_DA8XX(davinci_da850_evm,	2);
+
+		/* TNETV107x boards */
+		DEBUG_LL_TNETV107X(tnetv107x,		1);
 	} while (0);
 }
 
-- 
1.7.0.4


From cyril at ti.com  Tue May 18 11:51:20 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Tue, 18 May 2010 12:51:20 -0400
Subject: [PATCH v7 4/6] Davinci: tnetv107x initial gpio support
In-Reply-To: <1274201482-15994-1-git-send-email-cyril@ti.com>
References: <1274201482-15994-1-git-send-email-cyril@ti.com>
Message-ID: <1274201482-15994-5-git-send-email-cyril@ti.com>

This patch adds support for the tnetv107x gpio controller.

Key differences between davinci and tnetv107x controllers:
 - register map - davinci's controller is organized into banks of 32 gpios,
   tnetv107x has a single space with arrays of registers for in, out,
   direction, etc.
 - davinci's controller has separate set/clear registers for output, tnetv107x
   has a single direct mapped register.

This patch does not yet add gpio irq support on this controller.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v7: gpio inlines take effect only if set and clr registers are distinct
v6: allow tnetv107x style out registers
v5: changes as per ioremap patch series, gpio base is no longer virt
v4: range check against number of tnetv107x gpios
v3: switched to spin_lock_irq from local_irq_save/restore
v3: migrated to restructured gpio framework from earlier patches in this
    series

 arch/arm/mach-davinci/Makefile            |    1 +
 arch/arm/mach-davinci/gpio-tnetv107x.c    |  205 +++++++++++++++++++++++++++++
 arch/arm/mach-davinci/include/mach/gpio.h |   22 ++-
 3 files changed, 221 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/mach-davinci/gpio-tnetv107x.c

diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 1c7bcfe..62c5116 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= dm365.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += tnetv107x.o devices-tnetv107x.o
+obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += gpio-tnetv107x.o
 
 obj-$(CONFIG_AINTC)			+= irq.o
 obj-$(CONFIG_CP_INTC)			+= cp_intc.o
diff --git a/arch/arm/mach-davinci/gpio-tnetv107x.c b/arch/arm/mach-davinci/gpio-tnetv107x.c
new file mode 100644
index 0000000..d102986
--- /dev/null
+++ b/arch/arm/mach-davinci/gpio-tnetv107x.c
@@ -0,0 +1,205 @@
+/*
+ * Texas Instruments TNETV107X GPIO Controller
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <mach/common.h>
+#include <mach/tnetv107x.h>
+
+struct tnetv107x_gpio_regs {
+	u32	idver;
+	u32	data_in[3];
+	u32	data_out[3];
+	u32	direction[3];
+	u32	enable[3];
+};
+
+#define gpio_reg_index(gpio)	((gpio) >> 5)
+#define gpio_reg_bit(gpio)	BIT((gpio) & 0x1f)
+
+#define gpio_reg_rmw(reg, mask, val)	\
+	__raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg))
+
+#define gpio_reg_set_bit(reg, gpio)	\
+	gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio))
+
+#define gpio_reg_clear_bit(reg, gpio)	\
+	gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0)
+
+#define gpio_reg_get_bit(reg, gpio)	\
+	(__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio))
+
+#define chip2controller(chip)		\
+	container_of(chip, struct davinci_gpio_controller, chip)
+
+#define TNETV107X_GPIO_CTLRS	DIV_ROUND_UP(TNETV107X_N_GPIO, 32)
+
+static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS];
+
+static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	gpio_reg_set_bit(&regs->enable, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+
+	return 0;
+}
+
+static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	gpio_reg_clear_bit(&regs->enable, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+}
+
+static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	gpio_reg_set_bit(&regs->direction, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+
+	return 0;
+}
+
+static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
+		unsigned offset, int value)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	if (value)
+		gpio_reg_set_bit(&regs->data_out, gpio);
+	else
+		gpio_reg_clear_bit(&regs->data_out, gpio);
+
+	gpio_reg_clear_bit(&regs->direction, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+
+	return 0;
+}
+
+static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	int ret;
+
+	ret = gpio_reg_get_bit(&regs->data_in, gpio);
+
+	return ret ? 1 : 0;
+}
+
+static void tnetv107x_gpio_set(struct gpio_chip *chip,
+		unsigned offset, int value)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	if (value)
+		gpio_reg_set_bit(&regs->data_out, gpio);
+	else
+		gpio_reg_clear_bit(&regs->data_out, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+}
+
+static int __init tnetv107x_gpio_setup(void)
+{
+	int i, base;
+	unsigned ngpio;
+	struct davinci_soc_info *soc_info = &davinci_soc_info;
+	struct tnetv107x_gpio_regs *regs;
+	struct davinci_gpio_controller *ctlr;
+
+	if (soc_info->gpio_type != GPIO_TYPE_TNETV107X)
+		return 0;
+
+	ngpio = soc_info->gpio_num;
+	if (ngpio == 0) {
+		pr_err("GPIO setup:  how many GPIOs?\n");
+		return -EINVAL;
+	}
+
+	if (WARN_ON(TNETV107X_N_GPIO < ngpio))
+		ngpio = TNETV107X_N_GPIO;
+
+	regs = ioremap(soc_info->gpio_base, SZ_4K);
+	if (WARN_ON(!regs))
+		return -EINVAL;
+
+	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
+		ctlr = &chips[i];
+
+		ctlr->chip.label	= "tnetv107x";
+		ctlr->chip.can_sleep	= 0;
+		ctlr->chip.base		= base;
+		ctlr->chip.ngpio	= ngpio - base;
+		if (ctlr->chip.ngpio > 32)
+			ctlr->chip.ngpio = 32;
+
+		ctlr->chip.request		= tnetv107x_gpio_request;
+		ctlr->chip.free			= tnetv107x_gpio_free;
+		ctlr->chip.direction_input	= tnetv107x_gpio_dir_in;
+		ctlr->chip.get			= tnetv107x_gpio_get;
+		ctlr->chip.direction_output	= tnetv107x_gpio_dir_out;
+		ctlr->chip.set			= tnetv107x_gpio_set;
+
+		spin_lock_init(&ctlr->lock);
+
+		ctlr->regs	= regs;
+		ctlr->set_data	= &regs->data_out[i];
+		ctlr->clr_data	= &regs->data_out[i];
+		ctlr->in_data	= &regs->data_in[i];
+
+		gpiochip_add(&ctlr->chip);
+	}
+
+	soc_info->gpio_ctlrs = chips;
+	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
+	return 0;
+}
+pure_initcall(tnetv107x_gpio_setup);
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 504cc18..fbece12 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -25,6 +25,7 @@
 
 enum davinci_gpio_type {
 	GPIO_TYPE_DAVINCI = 0,
+	GPIO_TYPE_TNETV107X,
 };
 
 /*
@@ -87,9 +88,13 @@ static inline u32 __gpio_mask(unsigned gpio)
 	return 1 << (gpio % 32);
 }
 
-/* The get/set/clear functions will inline when called with constant
+/*
+ * The get/set/clear functions will inline when called with constant
  * parameters referencing built-in GPIOs, for low-overhead bitbanging.
  *
+ * gpio_set_value() will inline only on traditional Davinci style controllers
+ * with distinct set/clear registers.
+ *
  * Otherwise, calls with variable parameters or referencing external
  * GPIOs (e.g. on GPIO expander chips) use outlined functions.
  */
@@ -100,12 +105,15 @@ static inline void gpio_set_value(unsigned gpio, int value)
 		u32				mask;
 
 		ctlr = __gpio_to_controller(gpio);
-		mask = __gpio_mask(gpio);
-		if (value)
-			__raw_writel(mask, ctlr->set_data);
-		else
-			__raw_writel(mask, ctlr->clr_data);
-		return;
+
+		if (ctlr->set_data != ctlr->clr_data) {
+			mask = __gpio_mask(gpio);
+			if (value)
+				__raw_writel(mask, ctlr->set_data);
+			else
+				__raw_writel(mask, ctlr->clr_data);
+			return;
+		}
 	}
 
 	__gpio_set_value(gpio, value);
-- 
1.7.0.4


From cyril at ti.com  Tue May 18 11:51:19 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Tue, 18 May 2010 12:51:19 -0400
Subject: [PATCH v7 3/6] Davinci: tnetv107x soc support
In-Reply-To: <1274201482-15994-1-git-send-email-cyril@ti.com>
References: <1274201482-15994-1-git-send-email-cyril@ti.com>
Message-ID: <1274201482-15994-4-git-send-email-cyril@ti.com>

TNETV107X is a Texas Instruments SOC that shares a number of common features
with the Davinci architecture.  Some of the key differences between
traditional Davincis and this new SOC are as follow:

1. The SOCs clock architecture includes a new spread-spectrum PLL.  Some
elements of the clock architecture are reused from Davinci (e.g. LPSC), but
the PLL related code is overridden using existing interfaces in "struct clk".

2. The MMR layout on this SOC is substantially different from Davinci.
Consequently, the fixed I/O map is a whole lot more convoluted (more so than
DA8xx).  The net impact here is that IO_ADDRESS() will not work on this SoC,
and therefore all mappings have to be through ioremap().

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v7: removed unnecessary PINMUX macro definition
v6: unchanged from v5
v5: simplified watchdog reset code
v5: removed edma iotable entry
v5: updated soc_info interface according to ioremap patch series
v5: reuse davinci serial init code, now that it is generalized enough
v5: allow boards to use nand device on any emif chip select
v5: sorted base address definitions
v4: macroized clock definitions to reduce code volume
v4: moved to new davinci_io_init() mechanism (earlier in this series)
v4: squashed tnetv107x.h header and watchdog reset patches into this
v4: moved all platform_device definitions into soc code, accessible to board
    specific code via tnetv107x_devices_init()
v3: eliminated recalc routines for pll and leaf clocks
v3: stripped "clk_" prefix from clock names
v3: use newly added div_ratio_mask functionality (earlier in this series)
v3: move from fixed_ioremap to __davinci_ioremap() implementation (earlier in
    this series

 arch/arm/mach-davinci/Kconfig                  |    5 +
 arch/arm/mach-davinci/Makefile                 |    1 +
 arch/arm/mach-davinci/devices-tnetv107x.c      |  318 ++++++++++
 arch/arm/mach-davinci/include/mach/tnetv107x.h |   55 ++
 arch/arm/mach-davinci/tnetv107x.c              |  753 ++++++++++++++++++++++++
 5 files changed, 1132 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-davinci/devices-tnetv107x.c
 create mode 100644 arch/arm/mach-davinci/include/mach/tnetv107x.h
 create mode 100644 arch/arm/mach-davinci/tnetv107x.c

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0316e20..a67b47b 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -50,6 +50,11 @@ config ARCH_DAVINCI_DM365
 	select AINTC
 	select ARCH_DAVINCI_DMx
 
+config ARCH_DAVINCI_TNETV107X
+	select CPU_V6
+	select CP_INTC
+	bool "TNETV107X based system"
+
 comment "DaVinci Board Type"
 
 config MACH_DAVINCI_EVM
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 6aac880..1c7bcfe 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= dm365.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o
+obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += tnetv107x.o devices-tnetv107x.o
 
 obj-$(CONFIG_AINTC)			+= irq.o
 obj-$(CONFIG_CP_INTC)			+= cp_intc.o
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
new file mode 100644
index 0000000..4eef6cc
--- /dev/null
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -0,0 +1,318 @@
+/*
+ * Texas Instruments TNETV107X SoC devices
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/edma.h>
+#include <mach/tnetv107x.h>
+
+#include "clock.h"
+
+/* Base addresses for on-chip devices */
+#define TNETV107X_TPCC_BASE			0x01c00000
+#define TNETV107X_TPTC0_BASE			0x01c10000
+#define TNETV107X_TPTC1_BASE			0x01c10400
+#define TNETV107X_WDOG_BASE			0x08086700
+#define TNETV107X_SDIO0_BASE			0x08088700
+#define TNETV107X_SDIO1_BASE			0x08088800
+#define TNETV107X_ASYNC_EMIF_CNTRL_BASE		0x08200000
+#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE	0x30000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE	0x40000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE	0x44000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
+
+/* TNETV107X specific EDMA3 information */
+#define EDMA_TNETV107X_NUM_DMACH	64
+#define EDMA_TNETV107X_NUM_TCC		64
+#define EDMA_TNETV107X_NUM_PARAMENTRY	128
+#define EDMA_TNETV107X_NUM_EVQUE	2
+#define EDMA_TNETV107X_NUM_TC		2
+#define EDMA_TNETV107X_CHMAP_EXIST	0
+#define EDMA_TNETV107X_NUM_REGIONS	4
+#define TNETV107X_DMACH2EVENT_MAP0	0x3C0CE000u
+#define TNETV107X_DMACH2EVENT_MAP1	0x000FFFFFu
+
+#define TNETV107X_DMACH_SDIO0_RX		26
+#define TNETV107X_DMACH_SDIO0_TX		27
+#define TNETV107X_DMACH_SDIO1_RX		28
+#define TNETV107X_DMACH_SDIO1_TX		29
+
+static const s8 edma_tc_mapping[][2] = {
+	/* event queue no	TC no	*/
+	{	 0,		 0	},
+	{	 1,		 1	},
+	{	-1,		-1	}
+};
+
+static const s8 edma_priority_mapping[][2] = {
+	/* event queue no	Prio	*/
+	{	 0,		 3	},
+	{	 1,		 7	},
+	{	-1,		-1	}
+};
+
+static struct edma_soc_info edma_info[] = {
+	{
+		.n_channel		= EDMA_TNETV107X_NUM_DMACH,
+		.n_region		= EDMA_TNETV107X_NUM_REGIONS,
+		.n_slot			= EDMA_TNETV107X_NUM_PARAMENTRY,
+		.n_tc			= EDMA_TNETV107X_NUM_TC,
+		.n_cc			= 1,
+		.queue_tc_mapping	= edma_tc_mapping,
+		.queue_priority_mapping	= edma_priority_mapping,
+	},
+};
+
+static struct resource edma_resources[] = {
+	{
+		.name	= "edma_cc0",
+		.start	= TNETV107X_TPCC_BASE,
+		.end	= TNETV107X_TPCC_BASE + SZ_32K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma_tc0",
+		.start	= TNETV107X_TPTC0_BASE,
+		.end	= TNETV107X_TPTC0_BASE + SZ_1K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma_tc1",
+		.start	= TNETV107X_TPTC1_BASE,
+		.end	= TNETV107X_TPTC1_BASE + SZ_1K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma0",
+		.start	= IRQ_TNETV107X_TPCC,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "edma0_err",
+		.start	= IRQ_TNETV107X_TPCC_ERR,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device edma_device = {
+	.name		= "edma",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(edma_resources),
+	.resource	= edma_resources,
+	.dev.platform_data = edma_info,
+};
+
+static struct plat_serial8250_port serial_data[] = {
+	{
+		.mapbase	= TNETV107X_UART0_BASE,
+		.irq		= IRQ_TNETV107X_UART0,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.mapbase	= TNETV107X_UART1_BASE,
+		.irq		= IRQ_TNETV107X_UART1,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.mapbase	= TNETV107X_UART2_BASE,
+		.irq		= IRQ_TNETV107X_UART2,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.flags	= 0,
+	},
+};
+
+struct platform_device tnetv107x_serial_device = {
+	.name			= "serial8250",
+	.id			= PLAT8250_DEV_PLATFORM,
+	.dev.platform_data	= serial_data,
+};
+
+static struct resource mmc0_resources[] = {
+	{ /* Memory mapped registers */
+		.start	= TNETV107X_SDIO0_BASE,
+		.end	= TNETV107X_SDIO0_BASE + 0x0ff,
+		.flags	= IORESOURCE_MEM
+	},
+	{ /* MMC interrupt */
+		.start	= IRQ_TNETV107X_MMC0,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* SDIO interrupt */
+		.start	= IRQ_TNETV107X_SDIO0,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* DMA RX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX),
+		.flags	= IORESOURCE_DMA
+	},
+	{ /* DMA TX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX),
+		.flags	= IORESOURCE_DMA
+	},
+};
+
+static struct resource mmc1_resources[] = {
+	{ /* Memory mapped registers */
+		.start	= TNETV107X_SDIO1_BASE,
+		.end	= TNETV107X_SDIO1_BASE + 0x0ff,
+		.flags	= IORESOURCE_MEM
+	},
+	{ /* MMC interrupt */
+		.start	= IRQ_TNETV107X_MMC1,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* SDIO interrupt */
+		.start	= IRQ_TNETV107X_SDIO1,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* DMA RX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX),
+		.flags	= IORESOURCE_DMA
+	},
+	{ /* DMA TX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX),
+		.flags	= IORESOURCE_DMA
+	},
+};
+
+static u64 mmc0_dma_mask = DMA_BIT_MASK(32);
+static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device mmc_devices[2] = {
+	{
+		.name		= "davinci_mmc",
+		.id		= 0,
+		.dev		= {
+			.dma_mask		= &mmc0_dma_mask,
+			.coherent_dma_mask	= DMA_BIT_MASK(32),
+		},
+		.num_resources	= ARRAY_SIZE(mmc0_resources),
+		.resource	= mmc0_resources
+	},
+	{
+		.name		= "davinci_mmc",
+		.id		= 1,
+		.dev		= {
+			.dma_mask		= &mmc1_dma_mask,
+			.coherent_dma_mask	= DMA_BIT_MASK(32),
+		},
+		.num_resources	= ARRAY_SIZE(mmc1_resources),
+		.resource	= mmc1_resources
+	},
+};
+
+static const u32 emif_windows[] = {
+	TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE,
+	TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE,
+};
+
+static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M };
+
+static struct resource wdt_resources[] = {
+	{
+		.start	= TNETV107X_WDOG_BASE,
+		.end	= TNETV107X_WDOG_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device tnetv107x_wdt_device = {
+	.name		= "tnetv107x_wdt",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(wdt_resources),
+	.resource	= wdt_resources,
+};
+
+static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
+{
+	struct resource res[2];
+	struct platform_device *pdev;
+	u32	range;
+	int	ret;
+
+	/* Figure out the resource range from the ale/cle masks */
+	range = max(data->mask_cle, data->mask_ale);
+	range = PAGE_ALIGN(range + 4) - 1;
+
+	if (range >= emif_window_sizes[chipsel])
+		return -EINVAL;
+
+	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+	if (!pdev)
+		return -ENOMEM;
+
+	pdev->name		= "davinci_nand";
+	pdev->id		= chipsel;
+	pdev->dev.platform_data	= data;
+
+	memset(res, 0, sizeof(res));
+
+	res[0].start	= emif_windows[chipsel];
+	res[0].end	= res[0].start + range;
+	res[0].flags	= IORESOURCE_MEM;
+
+	res[1].start	= TNETV107X_ASYNC_EMIF_CNTRL_BASE;
+	res[1].end	= res[1].start + SZ_4K - 1;
+	res[1].flags	= IORESOURCE_MEM;
+
+	ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
+	if (ret < 0) {
+		kfree(pdev);
+		return ret;
+	}
+
+	return platform_device_register(pdev);
+}
+
+void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
+{
+	int i;
+
+	platform_device_register(&edma_device);
+	platform_device_register(&tnetv107x_wdt_device);
+
+	if (info->serial_config)
+		davinci_serial_init(info->serial_config);
+
+	for (i = 0; i < 2; i++)
+		if (info->mmc_config[i]) {
+			mmc_devices[i].dev.platform_data = info->mmc_config[i];
+			platform_device_register(&mmc_devices[i]);
+		}
+
+	for (i = 0; i < 4; i++)
+		if (info->nand_config[i])
+			nand_init(i, info->nand_config[i]);
+}
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
new file mode 100644
index 0000000..c720647
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -0,0 +1,55 @@
+/*
+ * Texas Instruments TNETV107X SoC Specific Defines
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
+#define __ASM_ARCH_DAVINCI_TNETV107X_H
+
+#include <asm/sizes.h>
+
+#define TNETV107X_DDR_BASE	0x80000000
+
+/*
+ * Fixed mapping for early init starts here. If low-level debug is enabled,
+ * this area also gets mapped via io_pg_offset and io_phys by the boot code.
+ * To fit in with the io_pg_offset calculation, the io base address selected
+ * here _must_ be a multiple of 2^20.
+ */
+#define TNETV107X_IO_BASE	0x08000000
+#define TNETV107X_IO_VIRT	(IO_VIRT + SZ_1M)
+
+#define TNETV107X_N_GPIO	65
+
+#ifndef __ASSEMBLY__
+
+#include <linux/serial_8250.h>
+#include <mach/mmc.h>
+#include <mach/nand.h>
+#include <mach/serial.h>
+
+struct tnetv107x_device_info {
+	struct davinci_uart_config	*serial_config;
+	struct davinci_mmc_config	*mmc_config[2];  /* 2 controllers */
+	struct davinci_nand_pdata	*nand_config[4]; /* 4 chipsels */
+};
+
+extern struct platform_device tnetv107x_wdt_device;
+extern struct platform_device tnetv107x_serial_device;
+
+extern void __init tnetv107x_init(void);
+extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
+extern void __init tnetv107x_irq_init(void);
+
+#endif
+
+#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
new file mode 100644
index 0000000..864e604
--- /dev/null
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -0,0 +1,753 @@
+/*
+ * Texas Instruments TNETV107X SoC Support
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/common.h>
+#include <mach/time.h>
+#include <mach/cputype.h>
+#include <mach/psc.h>
+#include <mach/cp_intc.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#include <mach/hardware.h>
+#include <mach/tnetv107x.h>
+
+#include "clock.h"
+#include "mux.h"
+
+/* Base addresses for on-chip devices */
+#define TNETV107X_INTC_BASE			0x03000000
+#define TNETV107X_TIMER0_BASE			0x08086500
+#define TNETV107X_TIMER1_BASE			0x08086600
+#define TNETV107X_CHIP_CFG_BASE			0x08087000
+#define TNETV107X_GPIO_BASE			0x08088000
+#define TNETV107X_CLOCK_CONTROL_BASE		0x0808a000
+#define TNETV107X_PSC_BASE			0x0808b000
+
+/* Reference clock frequencies */
+#define OSC_FREQ_ONCHIP		(24000 * 1000)
+#define OSC_FREQ_OFFCHIP_SYS	(25000 * 1000)
+#define OSC_FREQ_OFFCHIP_ETH	(25000 * 1000)
+#define OSC_FREQ_OFFCHIP_TDM	(19200 * 1000)
+
+#define N_PLLS	3
+
+/* Clock Control Registers */
+struct clk_ctrl_regs {
+	u32	pll_bypass;
+	u32	_reserved0;
+	u32	gem_lrst;
+	u32	_reserved1;
+	u32	pll_unlock_stat;
+	u32	sys_unlock;
+	u32	eth_unlock;
+	u32	tdm_unlock;
+};
+
+/* SSPLL Registers */
+struct sspll_regs {
+	u32	modes;
+	u32	post_div;
+	u32	pre_div;
+	u32	mult_factor;
+	u32	divider_range;
+	u32	bw_divider;
+	u32	spr_amount;
+	u32	spr_rate_div;
+	u32	diag;
+};
+
+/* Watchdog Timer Registers */
+struct wdt_regs {
+	u32	kick_lock;
+	u32	kick;
+	u32	change_lock;
+	u32	change ;
+	u32	disable_lock;
+	u32	disable;
+	u32	prescale_lock;
+	u32	prescale;
+};
+
+static struct clk_ctrl_regs __iomem *clk_ctrl_regs;
+
+static struct sspll_regs __iomem *sspll_regs[N_PLLS];
+static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 };
+
+/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */
+static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) };
+
+/* offchip (external) reference clock frequencies */
+static u32 pll_ext_freq[] = {
+	OSC_FREQ_OFFCHIP_SYS,
+	OSC_FREQ_OFFCHIP_TDM,
+	OSC_FREQ_OFFCHIP_ETH
+};
+
+/* PSC control registers */
+static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE };
+
+/* Host map for interrupt controller */
+static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 };
+
+static unsigned long clk_sspll_recalc(struct clk *clk);
+
+/* Level 1 - the PLLs */
+#define define_pll_clk(cname, pll, divmask, base)	\
+	static struct pll_data pll_##cname##_data = {	\
+		.num		= pll,			\
+		.div_ratio_mask	= divmask,		\
+		.phys_base	= base +		\
+			TNETV107X_CLOCK_CONTROL_BASE,	\
+	};						\
+	static struct clk pll_##cname##_clk = {		\
+		.name		= "pll_" #cname "_clk",	\
+		.pll_data	= &pll_##cname##_data,	\
+		.flags		= CLK_PLL,		\
+		.recalc		= clk_sspll_recalc,	\
+	}
+
+define_pll_clk(sys, 0, 0x1ff, 0x600);
+define_pll_clk(tdm, 1, 0x0ff, 0x200);
+define_pll_clk(eth, 2, 0x0ff, 0x400);
+
+/* Level 2 - divided outputs from the PLLs */
+#define define_pll_div_clk(pll, cname, div)		\
+	static struct clk pll##_##cname##_clk = {	\
+		.name		= #pll "_" #cname "_clk",\
+		.parent		= &pll_##pll##_clk,	\
+		.flags		= CLK_PLL,		\
+		.div_reg	= PLLDIV##div,		\
+	}
+
+define_pll_div_clk(sys, arm1176,	1);
+define_pll_div_clk(sys, dsp,		2);
+define_pll_div_clk(sys, ddr,		3);
+define_pll_div_clk(sys, full,		4);
+define_pll_div_clk(sys, lcd,		5);
+define_pll_div_clk(sys, vlynq_ref,	6);
+define_pll_div_clk(sys, tsc,		7);
+define_pll_div_clk(sys, half,		8);
+
+define_pll_div_clk(eth, 5mhz,		1);
+define_pll_div_clk(eth, 50mhz,		2);
+define_pll_div_clk(eth, 125mhz,		3);
+define_pll_div_clk(eth, 250mhz,		4);
+define_pll_div_clk(eth, 25mhz,		5);
+
+define_pll_div_clk(tdm, 0,		1);
+define_pll_div_clk(tdm, extra,		2);
+define_pll_div_clk(tdm, 1,		3);
+
+
+/* Level 3 - LPSC gated clocks */
+#define __lpsc_clk(cname, _parent, mod, flg)		\
+	static struct clk clk_##cname = {		\
+		.name		= #cname,		\
+		.parent		= &_parent,		\
+		.lpsc		= TNETV107X_LPSC_##mod,\
+		.flags		= flg,			\
+	}
+
+#define lpsc_clk_enabled(cname, parent, mod)		\
+	__lpsc_clk(cname, parent, mod, ALWAYS_ENABLED)
+
+#define lpsc_clk(cname, parent, mod)			\
+	__lpsc_clk(cname, parent, mod, 0)
+
+lpsc_clk_enabled(arm,		sys_arm1176_clk, ARM);
+lpsc_clk_enabled(gem,		sys_dsp_clk,	GEM);
+lpsc_clk_enabled(ddr2_phy,	sys_ddr_clk,	DDR2_PHY);
+lpsc_clk_enabled(tpcc,		sys_full_clk,	TPCC);
+lpsc_clk_enabled(tptc0,		sys_full_clk,	TPTC0);
+lpsc_clk_enabled(tptc1,		sys_full_clk,	TPTC1);
+lpsc_clk_enabled(ram,		sys_full_clk,	RAM);
+lpsc_clk_enabled(aemif,		sys_full_clk,	AEMIF);
+lpsc_clk_enabled(chipcfg,	sys_half_clk,	CHIP_CFG);
+lpsc_clk_enabled(rom,		sys_half_clk,	ROM);
+lpsc_clk_enabled(secctl,	sys_half_clk,	SECCTL);
+lpsc_clk_enabled(keymgr,	sys_half_clk,	KEYMGR);
+lpsc_clk_enabled(gpio,		sys_half_clk,	GPIO);
+lpsc_clk_enabled(debugss,	sys_half_clk,	DEBUGSS);
+lpsc_clk_enabled(system,	sys_half_clk,	SYSTEM);
+lpsc_clk_enabled(ddr2_vrst,	sys_ddr_clk,	DDR2_EMIF1_VRST);
+lpsc_clk_enabled(ddr2_vctl_rst,	sys_ddr_clk,	DDR2_EMIF2_VCTL_RST);
+lpsc_clk_enabled(wdt_arm,	sys_half_clk,	WDT_ARM);
+
+lpsc_clk(mbx_lite,	sys_arm1176_clk,	MBX_LITE);
+lpsc_clk(ethss,		eth_125mhz_clk,		ETHSS);
+lpsc_clk(tsc,		sys_tsc_clk,		TSC);
+lpsc_clk(uart0,		sys_half_clk,		UART0);
+lpsc_clk(uart1,		sys_half_clk,		UART1);
+lpsc_clk(uart2,		sys_half_clk,		UART2);
+lpsc_clk(pktsec,	sys_half_clk,		PKTSEC);
+lpsc_clk(keypad,	sys_half_clk,		KEYPAD);
+lpsc_clk(mdio,		sys_half_clk,		MDIO);
+lpsc_clk(sdio0,		sys_half_clk,		SDIO0);
+lpsc_clk(sdio1,		sys_half_clk,		SDIO1);
+lpsc_clk(timer0,	sys_half_clk,		TIMER0);
+lpsc_clk(timer1,	sys_half_clk,		TIMER1);
+lpsc_clk(wdt_dsp,	sys_half_clk,		WDT_DSP);
+lpsc_clk(ssp,		sys_half_clk,		SSP);
+lpsc_clk(tdm0,		tdm_0_clk,		TDM0);
+lpsc_clk(tdm1,		tdm_1_clk,		TDM1);
+lpsc_clk(vlynq,		sys_vlynq_ref_clk,	VLYNQ);
+lpsc_clk(mcdma,		sys_half_clk,		MCDMA);
+lpsc_clk(usb0,		sys_half_clk,		USB0);
+lpsc_clk(usb1,		sys_half_clk,		USB1);
+lpsc_clk(usbss,		sys_half_clk,		USBSS);
+lpsc_clk(ethss_rgmii,	eth_250mhz_clk,		ETHSS_RGMII);
+lpsc_clk(imcop,		sys_dsp_clk,		IMCOP);
+lpsc_clk(spare,		sys_half_clk,		SPARE);
+
+/* LCD needs a full power down to clear controller state */
+__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE);
+
+
+/* Level 4 - leaf clocks for LPSC modules shared across drivers */
+static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec };
+static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec };
+
+static struct clk_lookup clks[] = {
+	CLK(NULL,		"pll_sys_clk",		&pll_sys_clk),
+	CLK(NULL,		"pll_eth_clk",		&pll_eth_clk),
+	CLK(NULL,		"pll_tdm_clk",		&pll_tdm_clk),
+	CLK(NULL,		"sys_arm1176_clk",	&sys_arm1176_clk),
+	CLK(NULL,		"sys_dsp_clk",		&sys_dsp_clk),
+	CLK(NULL,		"sys_ddr_clk",		&sys_ddr_clk),
+	CLK(NULL,		"sys_full_clk",		&sys_full_clk),
+	CLK(NULL,		"sys_lcd_clk",		&sys_lcd_clk),
+	CLK(NULL,		"sys_vlynq_ref_clk",	&sys_vlynq_ref_clk),
+	CLK(NULL,		"sys_tsc_clk",		&sys_tsc_clk),
+	CLK(NULL,		"sys_half_clk",		&sys_half_clk),
+	CLK(NULL,		"eth_5mhz_clk",		&eth_5mhz_clk),
+	CLK(NULL,		"eth_50mhz_clk",	&eth_50mhz_clk),
+	CLK(NULL,		"eth_125mhz_clk",	&eth_125mhz_clk),
+	CLK(NULL,		"eth_250mhz_clk",	&eth_250mhz_clk),
+	CLK(NULL,		"eth_25mhz_clk",	&eth_25mhz_clk),
+	CLK(NULL,		"tdm_0_clk",		&tdm_0_clk),
+	CLK(NULL,		"tdm_extra_clk",	&tdm_extra_clk),
+	CLK(NULL,		"tdm_1_clk",		&tdm_1_clk),
+	CLK(NULL,		"clk_arm",		&clk_arm),
+	CLK(NULL,		"clk_gem",		&clk_gem),
+	CLK(NULL,		"clk_ddr2_phy",		&clk_ddr2_phy),
+	CLK(NULL,		"clk_tpcc",		&clk_tpcc),
+	CLK(NULL,		"clk_tptc0",		&clk_tptc0),
+	CLK(NULL,		"clk_tptc1",		&clk_tptc1),
+	CLK(NULL,		"clk_ram",		&clk_ram),
+	CLK(NULL,		"clk_mbx_lite",		&clk_mbx_lite),
+	CLK("tnetv107x-fb.0",	NULL,			&clk_lcd),
+	CLK(NULL,		"clk_ethss",		&clk_ethss),
+	CLK(NULL,		"aemif",		&clk_aemif),
+	CLK(NULL,		"clk_chipcfg",		&clk_chipcfg),
+	CLK("tnetv107x-ts.0",	NULL,			&clk_tsc),
+	CLK(NULL,		"clk_rom",		&clk_rom),
+	CLK(NULL,		"uart2",		&clk_uart2),
+	CLK(NULL,		"clk_pktsec",		&clk_pktsec),
+	CLK("tnetv107x-rng.0",	NULL,			&clk_rng),
+	CLK("tnetv107x-pka.0",	NULL,			&clk_pka),
+	CLK(NULL,		"clk_secctl",		&clk_secctl),
+	CLK(NULL,		"clk_keymgr",		&clk_keymgr),
+	CLK("tnetv107x-keypad.0", NULL,			&clk_keypad),
+	CLK(NULL,		"clk_gpio",		&clk_gpio),
+	CLK(NULL,		"clk_mdio",		&clk_mdio),
+	CLK("davinci_mmc.0",	NULL,			&clk_sdio0),
+	CLK(NULL,		"uart0",		&clk_uart0),
+	CLK(NULL,		"uart1",		&clk_uart1),
+	CLK(NULL,		"timer0",		&clk_timer0),
+	CLK(NULL,		"timer1",		&clk_timer1),
+	CLK("tnetv107x_wdt.0",	NULL,			&clk_wdt_arm),
+	CLK(NULL,		"clk_wdt_dsp",		&clk_wdt_dsp),
+	CLK("ti-ssp.0",		NULL,			&clk_ssp),
+	CLK(NULL,		"clk_tdm0",		&clk_tdm0),
+	CLK(NULL,		"clk_vlynq",		&clk_vlynq),
+	CLK(NULL,		"clk_mcdma",		&clk_mcdma),
+	CLK(NULL,		"clk_usb0",		&clk_usb0),
+	CLK(NULL,		"clk_tdm1",		&clk_tdm1),
+	CLK(NULL,		"clk_debugss",		&clk_debugss),
+	CLK(NULL,		"clk_ethss_rgmii",	&clk_ethss_rgmii),
+	CLK(NULL,		"clk_system",		&clk_system),
+	CLK(NULL,		"clk_imcop",		&clk_imcop),
+	CLK(NULL,		"clk_spare",		&clk_spare),
+	CLK("davinci_mmc.1",	NULL,			&clk_sdio1),
+	CLK(NULL,		"clk_usb1",		&clk_usb1),
+	CLK(NULL,		"clk_usbss",		&clk_usbss),
+	CLK(NULL,		"clk_ddr2_vrst",	&clk_ddr2_vrst),
+	CLK(NULL,		"clk_ddr2_vctl_rst",	&clk_ddr2_vctl_rst),
+	CLK(NULL,		NULL,			NULL),
+};
+
+static const struct mux_config pins[] = {
+#ifdef CONFIG_DAVINCI_MUX
+	MUX_CFG(TNETV107X, ASR_A00,		0, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO32,		0, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A01,		0, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO33,		0, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A02,		0, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO34,		0, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A03,		0, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO35,		0, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A04,		0, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO36,		0, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A05,		0, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO37,		0, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A06,		1, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO38,		1, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A07,		1, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO39,		1, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A08,		1, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO40,		1, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A09,		1, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO41,		1, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A10,		1, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO42,		1, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A11,		1, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_0,		1, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A12,		2, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_1,		2, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A13,		2, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO43,		2, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A14,		2, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO44,		2, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A15,		2, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO45,		2, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A16,		2, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO46,		2, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A17,		2, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO47,		2, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A18,		3, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO48,		3, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA3_0,	3, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A19,		3, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO49,		3, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA2_0,	3, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A20,		3, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO50,		3, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA1_0,	3, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A21,		3, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO51,		3, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA0_0,	3, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A22,		3, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO52,		3, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_CMD_0,		3, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A23,		3, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO53,		3, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_CLK_0,		3, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_BA_1,		4, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO54,		4, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SYS_PLL_CLK,		4, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_CS0,		4, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_CS1,		4, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_CS2,		4, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM_PLL_CLK,		4, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_CS3,		4, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ETH_PHY_CLK,		4, 20, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, ASR_D00,		4, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO55,		4, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D01,		5, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO56,		5, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D02,		5, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO57,		5, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D03,		5, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO58,		5, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D04,		5, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO59_0,		5, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D05,		5, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO60_0,		5, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D06,		5, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO61_0,		5, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D07,		6, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO62_0,		6, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D08,		6, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO63_0,		6, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D09,		6, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO64_0,		6, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D10,		6, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA3_1,	6, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D11,		6, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA2_1,	6, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D12,		6, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA1_1,	6, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D13,		7, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA0_1,	7, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D14,		7, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_CMD_1,		7, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D15,		7, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_CLK_1,		7, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_OE,		7, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_2,		7, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_RNW,		7, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO29_0,		7, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_WAIT,		7, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO30_0,		7, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_WE,		8, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_3,		8, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_WE_DQM0,		8, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO31,		8, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD17_0,		8, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_WE_DQM1,		8, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_BA0_0,		8, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, VLYNQ_CLK,		9, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO14,		9, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD19_0,		9, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_RXD0,		9, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO15,		9, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD20_0,		9, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_RXD1,		9, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO16,		9, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD21_0,		9, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_TXD0,		9, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO17,		9, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD22_0,		9, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_TXD1,		9, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO18,		9, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD23_0,		9, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, SDIO0_CLK,		10, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO19,		10, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_CMD,		10, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO20,		10, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA0,		10, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO21,		10, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA1,		10, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO22,		10, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA2,		10, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO23,		10, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA3,		10, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO24,		10, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, EMU0,		11, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, EMU1,		11, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, RTCK,		12, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TRST_N,		12, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TCK,			12, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDI,			12, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDO,			12, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TMS,			12, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_CLK,		13, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_RX,		13, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_TX,		13, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_FS,		13, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R0,		14, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R1,		14, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R2,		14, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R3,		14, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R4,		14, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R5,		14, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R6,		15, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO12,		15, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, KEYPAD_R7,		15, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO10,		15, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, KEYPAD_C0,		15, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C1,		15, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C2,		15, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C3,		15, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C4,		16, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C5,		16, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C6,		16, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO13,		16, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, TEST_CLK_IN,		16, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, KEYPAD_C7,		16, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO11,		16, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SSP0_0,		17, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_DCLK,		17, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD20_1,		17, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP0_1,		17, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_CS_N,		17, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD21_1,		17, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP0_2,		17, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_D,		17, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD22_1,		17, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP0_3,		17, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_RESETN,		17, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD23_1,		17, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_0,		18, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO25,		18, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_CTS,		18, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_1,		18, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO26,		18, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_RD,		18, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_2,		18, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO27,		18, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_RTS,		18, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_3,		18, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO28,		18, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_TD,		18, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, UART0_CTS,		19, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART0_RD,		19, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART0_RTS,		19, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART0_TD,		19, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART1_RD,		19, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART1_TD,		19, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_AC_NCS,		20, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_HSYNC_RNW,	20, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_VSYNC_A0,	20, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_MCLK,		20, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD16_0,		20, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PCLK_E,		20, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD00,		20, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD01,		21, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD02,		21, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD03,		21, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD04,		21, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD05,		21, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD06,		21, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD07,		22, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD08,		22, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO59_1,		22, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD09,		22, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO60_1,		22, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD10,		22, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_BA0_1,		22, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO61_1,		22, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD11,		22, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO62_1,		22, 20, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD12,		22, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO63_1,		22, 25, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD13,		23, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO64_1,		23, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD14,		23, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO29_1,		23, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD15,		23, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO30_1,		23, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, EINT0,		24, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO08,		24, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, EINT1,		24, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO09,		24, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO00,		24, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD20_2,		24, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, TDM_CLK_IN_2,	24, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO01,		24, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD21_2,		24, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, 24M_CLK_OUT_1,	24, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO02,		24, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD22_2,		24, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO03,		24, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD23_2,		24, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO04,		25, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD16_1,		25, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, USB0_RXERR,		25, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO05,		25, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD17_1,		25, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, TDM_CLK_IN_1,	25, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO06,		25, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD18,		25, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, 24M_CLK_OUT_2,	25, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO07,		25, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD19_1,		25, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, USB1_RXERR,		25, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, ETH_PLL_CLK,		25, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, MDIO,		26, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, MDC,			26, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, AIC_MUTE_STAT_N,	26, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_CLK,		26, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, AIC_HNS_EN_N,	26, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_FS,		26, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N,	26, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_TX,		26, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N,	26, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_RX,		26, 25, 0x1f, 0x04, false)
+#endif
+};
+
+/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
+static u8 irq_prios[TNETV107X_N_CP_INTC_IRQ] = {
+	/* fill in default priority 7 */
+	[0 ... (TNETV107X_N_CP_INTC_IRQ - 1)]	= 7,
+	/* now override as needed, e.g. [xxx] = 5 */
+};
+
+/* Contents of JTAG ID register used to identify exact cpu type */
+static struct davinci_id ids[] = {
+	{
+		.variant	= 0x0,
+		.part_no	= 0xb8a1,
+		.manufacturer	= 0x017,
+		.cpu_id		= DAVINCI_CPU_ID_TNETV107X,
+		.name		= "tnetv107x rev1.0",
+	},
+};
+
+static struct davinci_timer_instance timer_instance[2] = {
+	{
+		.base		= TNETV107X_TIMER0_BASE,
+		.bottom_irq	= IRQ_TNETV107X_TIMER_0_TINT12,
+		.top_irq	= IRQ_TNETV107X_TIMER_0_TINT34,
+	},
+	{
+		.base		= TNETV107X_TIMER1_BASE,
+		.bottom_irq	= IRQ_TNETV107X_TIMER_1_TINT12,
+		.top_irq	= IRQ_TNETV107X_TIMER_1_TINT34,
+	},
+};
+
+static struct davinci_timer_info timer_info = {
+	.timers		= timer_instance,
+	.clockevent_id	= T0_BOT,
+	.clocksource_id	= T0_TOP,
+};
+
+/*
+ * TNETV107X platforms do not use the static mappings from Davinci
+ * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses,
+ * and changing IO_PHYS would break away from existing Davinci SOCs.
+ *
+ * The primary impact of the current model is that IO_ADDRESS() is not to be
+ * used to map registers on TNETV107X.
+ *
+ * 1.	The first chunk is for INTC:  This needs to be mapped in via iotable
+ *	because ioremap() does not seem to be operational at the time when
+ *	irqs are initialized.  Without this, consistent dma init bombs.
+ *
+ * 2.	The second chunk maps in register areas that need to be populated into
+ *	davinci_soc_info.  Note that alignment restrictions come into play if
+ *	low-level debug is enabled (see note in <mach/tnetv107x.h>).
+ */
+static struct map_desc io_desc[] = {
+	{	/* INTC */
+		.virtual	= IO_VIRT,
+		.pfn		= __phys_to_pfn(TNETV107X_INTC_BASE),
+		.length		= SZ_16K,
+		.type		= MT_DEVICE
+	},
+	{	/* Most of the rest */
+		.virtual	= TNETV107X_IO_VIRT,
+		.pfn		= __phys_to_pfn(TNETV107X_IO_BASE),
+		.length		= IO_SIZE - SZ_1M,
+		.type		= MT_DEVICE
+	},
+};
+
+static unsigned long clk_sspll_recalc(struct clk *clk)
+{
+	int		pll;
+	unsigned long	mult = 0, prediv = 1, postdiv = 1;
+	unsigned long	ref = OSC_FREQ_ONCHIP, ret;
+	u32		tmp;
+
+	if (WARN_ON(!clk->pll_data))
+		return clk->rate;
+
+	if (!clk_ctrl_regs) {
+		void __iomem *tmp;
+
+		tmp = ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K);
+
+		if (WARN(!tmp, "failed ioremap for clock control regs\n"))
+			return clk->parent ? clk->parent->rate : 0;
+
+		for (pll = 0; pll < N_PLLS; pll++)
+			sspll_regs[pll] = tmp + sspll_regs_base[pll];
+
+		clk_ctrl_regs = tmp;
+	}
+
+	pll = clk->pll_data->num;
+
+	tmp = __raw_readl(&clk_ctrl_regs->pll_bypass);
+	if (!(tmp & bypass_mask[pll])) {
+		mult	= __raw_readl(&sspll_regs[pll]->mult_factor);
+		prediv	= __raw_readl(&sspll_regs[pll]->pre_div) + 1;
+		postdiv	= __raw_readl(&sspll_regs[pll]->post_div) + 1;
+	}
+
+	tmp = __raw_readl(clk->pll_data->base + PLLCTL);
+	if (tmp & PLLCTL_CLKMODE)
+		ref = pll_ext_freq[pll];
+
+	clk->pll_data->input_rate = ref;
+
+	tmp = __raw_readl(clk->pll_data->base + PLLCTL);
+	if (!(tmp & PLLCTL_PLLEN))
+		return ref;
+
+	ret = ref;
+	if (mult)
+		ret += ((unsigned long long)ref * mult) / 256;
+
+	ret /= (prediv * postdiv);
+
+	return ret;
+}
+
+static void tnetv107x_watchdog_reset(struct platform_device *pdev)
+{
+	struct wdt_regs __iomem *regs;
+
+	regs = ioremap(pdev->resource[0].start, SZ_4K);
+
+	/* disable watchdog */
+	__raw_writel(0x7777, &regs->disable_lock);
+	__raw_writel(0xcccc, &regs->disable_lock);
+	__raw_writel(0xdddd, &regs->disable_lock);
+	__raw_writel(0, &regs->disable);
+
+	/* program prescale */
+	__raw_writel(0x5a5a, &regs->prescale_lock);
+	__raw_writel(0xa5a5, &regs->prescale_lock);
+	__raw_writel(0, &regs->prescale);
+
+	/* program countdown */
+	__raw_writel(0x6666, &regs->change_lock);
+	__raw_writel(0xbbbb, &regs->change_lock);
+	__raw_writel(1, &regs->change);
+
+	/* enable watchdog */
+	__raw_writel(0x7777, &regs->disable_lock);
+	__raw_writel(0xcccc, &regs->disable_lock);
+	__raw_writel(0xdddd, &regs->disable_lock);
+	__raw_writel(1, &regs->disable);
+
+	/* kick */
+	__raw_writel(0x5555, &regs->kick_lock);
+	__raw_writel(0xaaaa, &regs->kick_lock);
+	__raw_writel(1, &regs->kick);
+}
+
+static struct davinci_soc_info tnetv107x_soc_info = {
+	.io_desc		= io_desc,
+	.io_desc_num		= ARRAY_SIZE(io_desc),
+	.ids			= ids,
+	.ids_num		= ARRAY_SIZE(ids),
+	.jtag_id_reg		= TNETV107X_CHIP_CFG_BASE + 0x018,
+	.cpu_clks		= clks,
+	.psc_bases		= psc_regs,
+	.psc_bases_num		= ARRAY_SIZE(psc_regs),
+	.pinmux_base		= TNETV107X_CHIP_CFG_BASE + 0x150,
+	.pinmux_pins		= pins,
+	.pinmux_pins_num	= ARRAY_SIZE(pins),
+	.intc_type		= DAVINCI_INTC_TYPE_CP_INTC,
+	.intc_base		= TNETV107X_INTC_BASE,
+	.intc_irq_prios		= irq_prios,
+	.intc_irq_num		= TNETV107X_N_CP_INTC_IRQ,
+	.intc_host_map		= intc_host_map,
+	.gpio_base		= TNETV107X_GPIO_BASE,
+	.gpio_type		= GPIO_TYPE_TNETV107X,
+	.gpio_num		= TNETV107X_N_GPIO,
+	.timer_info		= &timer_info,
+	.serial_dev		= &tnetv107x_serial_device,
+	.reset			= tnetv107x_watchdog_reset,
+	.reset_device		= &tnetv107x_wdt_device,
+};
+
+void __init tnetv107x_init(void)
+{
+	davinci_common_init(&tnetv107x_soc_info);
+}
-- 
1.7.0.4


From cyril at ti.com  Tue May 18 11:51:21 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Tue, 18 May 2010 12:51:21 -0400
Subject: [PATCH v7 5/6] Davinci: tnetv107x evm board initial support
In-Reply-To: <1274201482-15994-1-git-send-email-cyril@ti.com>
References: <1274201482-15994-1-git-send-email-cyril@ti.com>
Message-ID: <1274201482-15994-6-git-send-email-cyril@ti.com>

Added support for tnetv107x evaluation module.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v7: unchanged from v6
v6: unchanged from v5
v5: modifications as per ioremap patch series for cpintc
v5: add comments to clarify nand chipselect and mmc controller instance
v5: enable nand bad block table
v4: updated copyrights
v4: squashed relevant gpio pins into sdio1 pin list
v4: eliminated platform device definitions, moved to tnetv107x_devices_init()
    implementation instead
v4: platform devices moved out to devices-tnetv107x.c
v3: moved some base address and edma channel definitions here
v3: minor formatting changes

 arch/arm/mach-davinci/Kconfig               |    7 +
 arch/arm/mach-davinci/Makefile              |    1 +
 arch/arm/mach-davinci/board-tnetv107x-evm.c |  174 +++++++++++++++++++++++++++
 3 files changed, 182 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-davinci/board-tnetv107x-evm.c

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a67b47b..71f90f8 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -178,6 +178,13 @@ config DA850_UI_RMII
 
 endchoice
 
+config MACH_TNETV107X
+	bool "TI TNETV107X Reference Platform"
+	default ARCH_DAVINCI_TNETV107X
+	depends on ARCH_DAVINCI_TNETV107X
+	help
+	  Say Y here to select the TI TNETV107X Evaluation Module.
+
 config DAVINCI_MUX
 	bool "DAVINCI multiplexing support"
 	depends on ARCH_DAVINCI
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 62c5116..eab4c0f 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)	+= board-dm646x-evm.o cdce949.o
 obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)	+= board-dm365-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)	+= board-da830-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= board-da850-evm.o
+obj-$(CONFIG_MACH_TNETV107X)		+= board-tnetv107x-evm.o
 
 # Power Management
 obj-$(CONFIG_CPU_FREQ)			+= cpufreq.o
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
new file mode 100644
index 0000000..fe2a9d9
--- /dev/null
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -0,0 +1,174 @@
+/*
+ * Texas Instruments TNETV107X EVM Board Support
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/ratelimit.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/irqs.h>
+#include <mach/edma.h>
+#include <mach/mux.h>
+#include <mach/cp_intc.h>
+#include <mach/tnetv107x.h>
+
+#define EVM_MMC_WP_GPIO		21
+#define EVM_MMC_CD_GPIO		24
+
+static int initialize_gpio(int gpio, char *desc)
+{
+	int ret;
+
+	ret = gpio_request(gpio, desc);
+	if (ret < 0) {
+		pr_err_ratelimited("cannot open %s gpio\n", desc);
+		return -ENOSYS;
+	}
+	gpio_direction_input(gpio);
+	return gpio;
+}
+
+static int mmc_get_cd(int index)
+{
+	static int gpio;
+
+	if (!gpio)
+		gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect");
+
+	if (gpio < 0)
+		return gpio;
+
+	return gpio_get_value(gpio) ? 0 : 1;
+}
+
+static int mmc_get_ro(int index)
+{
+	static int gpio;
+
+	if (!gpio)
+		gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect");
+
+	if (gpio < 0)
+		return gpio;
+
+	return gpio_get_value(gpio) ? 1 : 0;
+}
+
+static struct davinci_mmc_config mmc_config = {
+	.get_cd		= mmc_get_cd,
+	.get_ro		= mmc_get_ro,
+	.wires		= 4,
+	.max_freq	= 50000000,
+	.caps		= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+	.version	= MMC_CTLR_VERSION_1,
+};
+
+static const short sdio1_pins[] __initdata = {
+	TNETV107X_SDIO1_CLK_1,		TNETV107X_SDIO1_CMD_1,
+	TNETV107X_SDIO1_DATA0_1,	TNETV107X_SDIO1_DATA1_1,
+	TNETV107X_SDIO1_DATA2_1,	TNETV107X_SDIO1_DATA3_1,
+	TNETV107X_GPIO21,		TNETV107X_GPIO24,
+	-1
+};
+
+static const short uart1_pins[] __initdata = {
+	TNETV107X_UART1_RD,		TNETV107X_UART1_TD,
+	-1
+};
+
+static struct mtd_partition nand_partitions[] = {
+	/* bootloader (U-Boot, etc) in first 12 sectors */
+	{
+		.name		= "bootloader",
+		.offset		= 0,
+		.size		= (12*SZ_128K),
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	/* bootloader params in the next sector */
+	{
+		.name		= "params",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	/* kernel */
+	{
+		.name		= "kernel",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= SZ_4M,
+		.mask_flags	= 0,
+	},
+	/* file system */
+	{
+		.name		= "filesystem",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= MTDPART_SIZ_FULL,
+		.mask_flags	= 0,
+	}
+};
+
+static struct davinci_nand_pdata nand_config = {
+	.mask_cle	= 0x4000,
+	.mask_ale	= 0x2000,
+	.parts		= nand_partitions,
+	.nr_parts	= ARRAY_SIZE(nand_partitions),
+	.ecc_mode	= NAND_ECC_HW,
+	.options	= NAND_USE_FLASH_BBT,
+	.ecc_bits	= 1,
+};
+
+static struct davinci_uart_config serial_config __initconst = {
+	.enabled_uarts	= BIT(1),
+};
+
+static struct tnetv107x_device_info evm_device_info __initconst = {
+	.serial_config		= &serial_config,
+	.mmc_config[1]		= &mmc_config,	/* controller 1 */
+	.nand_config[0]		= &nand_config,	/* chip select 0 */
+};
+
+static __init void tnetv107x_evm_board_init(void)
+{
+	davinci_cfg_reg_list(sdio1_pins);
+	davinci_cfg_reg_list(uart1_pins);
+
+	tnetv107x_devices_init(&evm_device_info);
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+static int __init tnetv107x_evm_console_init(void)
+{
+	return add_preferred_console("ttyS", 0, "115200");
+}
+console_initcall(tnetv107x_evm_console_init);
+#endif
+
+MACHINE_START(TNETV107X, "TNETV107X EVM")
+	.phys_io	= TNETV107X_IO_BASE,
+	.io_pg_offst	= (TNETV107X_IO_VIRT >> 18) & 0xfffc,
+	.boot_params	= (TNETV107X_DDR_BASE + 0x100),
+	.map_io		= tnetv107x_init,
+	.init_irq	= cp_intc_init,
+	.timer		= &davinci_timer,
+	.init_machine	= tnetv107x_evm_board_init,
+MACHINE_END
-- 
1.7.0.4


From cyril at ti.com  Tue May 18 11:51:22 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Tue, 18 May 2010 12:51:22 -0400
Subject: [PATCH v7 6/6] Davinci: tnetv107x default configuration
In-Reply-To: <1274201482-15994-1-git-send-email-cyril@ti.com>
References: <1274201482-15994-1-git-send-email-cyril@ti.com>
Message-ID: <1274201482-15994-7-git-send-email-cyril@ti.com>

Added default configuration for tnetv107x platforms.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
v7: unchanged from v6
v6: unchanged from v5

 arch/arm/configs/tnetv107x_defconfig | 1741 ++++++++++++++++++++++++++++++++++
 1 files changed, 1741 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/configs/tnetv107x_defconfig

diff --git a/arch/arm/configs/tnetv107x_defconfig b/arch/arm/configs/tnetv107x_defconfig
new file mode 100644
index 0000000..efc101f
--- /dev/null
+++ b/arch/arm/configs/tnetv107x_defconfig
@@ -0,0 +1,1741 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.34-rc5
+# Sun May  2 15:05:52 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+CONFIG_ARCH_DAVINCI=y
+# CONFIG_ARCH_OMAP is not set
+CONFIG_CP_INTC=y
+
+#
+# TI DaVinci Implementations
+#
+
+#
+# DaVinci Core Type
+#
+# CONFIG_ARCH_DAVINCI_DM644x is not set
+# CONFIG_ARCH_DAVINCI_DM355 is not set
+# CONFIG_ARCH_DAVINCI_DM646x is not set
+# CONFIG_ARCH_DAVINCI_DA830 is not set
+# CONFIG_ARCH_DAVINCI_DA850 is not set
+# CONFIG_ARCH_DAVINCI_DM365 is not set
+CONFIG_ARCH_DAVINCI_TNETV107X=y
+
+#
+# DaVinci Board Type
+#
+CONFIG_MACH_TNETV107X=y
+CONFIG_DAVINCI_MUX=y
+CONFIG_DAVINCI_MUX_DEBUG=y
+CONFIG_DAVINCI_MUX_WARNINGS=y
+CONFIG_DAVINCI_RESET_CLOCKS=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_V6=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_ARM_ERRATA_411920 is not set
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_LEDS=y
+# CONFIG_LEDS_CPU is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=m
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=m
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI_AMDSTD=m
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=m
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=m
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_DAVINCI=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IWMC3200TOP is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=m
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_TI_DAVINCI_EMAC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+CONFIG_INPUT_SPARSEKMAP=m
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVBUG=m
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=m
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+CONFIG_KEYBOARD_XTKBD=m
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+# CONFIG_VT_CONSOLE is not set
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_DAVINCI_WATCHDOG=m
+# CONFIG_MAX63XX_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=m
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_DAVINCI_SOC=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_3M_PCT is not set
+CONFIG_HID_A4TECH=m
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+# CONFIG_HID_DRAGONRISE is not set
+CONFIG_HID_EZKEY=m
+# CONFIG_HID_KYE is not set
+CONFIG_HID_GYRATION=m
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+CONFIG_HID_LOGITECH=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGIG940_FF is not set
+CONFIG_HID_MICROSOFT=m
+# CONFIG_HID_MOSART is not set
+CONFIG_HID_MONTEREY=m
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+CONFIG_HID_PANTHERLORD=m
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=m
+# CONFIG_HID_QUANTA is not set
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+# CONFIG_HID_STANTUM is not set
+CONFIG_HID_SUNPLUS=m
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=m
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_SOC=y
+
+#
+# DaVinci 35x and 644x USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+CONFIG_USB_MUSB_PERIPHERAL=y
+# CONFIG_USB_MUSB_OTG is not set
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_MUSB_PIO_ONLY=y
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_MASS_STORAGE is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+# CONFIG_USB_G_NOKIA is not set
+# CONFIG_USB_G_MULTI is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+CONFIG_NOP_USB_XCEIV=m
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_DAVINCI=y
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=m
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=m
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=m
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
-- 
1.7.0.4


From raghu_ramaraj at mindtree.com  Wed May 19 00:30:10 2010
From: raghu_ramaraj at mindtree.com (Raghu Ramaraj)
Date: Wed, 19 May 2010 11:00:10 +0530
Subject: Unable to run 1080P in Ramdisk
Message-ID: <DE1563FF5EF45A4794D1220EF0363CB411CF0532DF@MTW02MSG02.mindtree.com>

Hi,
            Details of the environment ...

Plateform          : DM6467T
Kernel               : 2.6.18
DVSDK             :2.00.00.22
RAM                 :256/512MB

-----------------------------------------------------
Kernel MEM      :120
FileSystem        : Ramdisk -> 40MB
Cmem               :66 MB
DDRALGHEAP  :64 MB
DDR2                :4MB
DSPLINKMEM   :1M
RESET V          :80B

insmod cmemk.ko phys_start=0x87800000 phys_end=0x8ba00000 pools=10x4177920,4x3458400,0x3250944,0x663552,2x60000

We can able to run the 720P in Ramdisk. But we couldn't run the 1080P(Able to run both in NFS). With the DVSDK, we have received 256MB Memory map based configuration.

But we require more Cmem,Heap memoery .

Could you please give us for 512MB based Memory map configuration..? Or what are the changes have to do for running the 1080P?



Thanks & Regards,
Raghu Ramaraj


________________________________
http://www.mindtree.com/email/disclaimer.html
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From jaya.krishnan at samsung.com  Wed May 19 00:52:52 2010
From: jaya.krishnan at samsung.com (Jaya krishnan)
Date: Wed, 19 May 2010 05:52:52 +0000 (GMT)
Subject: Unable to run 1080P in Ramdisk
Message-ID: <30685858.205001274248372000.JavaMail.weblogic@epml16>

pls  look  at the  following  document
http://processors.wiki.ti.com/index.php/Changing_the_DVEVM_memory_map
regards
JK

 
 

------- Original Message-------
Sender: Raghu Ramaraj<raghu_ramaraj at mindtree.com>
Date: May 19, 2010 14:30 (GMT+09:00)
Title: Unable to run 1080P in Ramdisk

Hi,            Details of the environment ? Plateform          : DM6467TKernel               : 2.6.18 DVSDK             :2.00.00.22RAM                 :256/512MB -----------------------------------------------------Kernel MEM      :120FileSystem        : Ramdisk -> 40MBCmem               :66 MBDDRALGHEAP  :64 MBDDR2                :4MBDSPLINKMEM   :1MRESET V          :80B insmod cmemk.ko phys_start=0x87800000 phys_end=0x8ba00000 pools=10x4177920,4x3458400,0x3250944,0x663552,2x60000  We can able to run the 720P in Ramdisk. But we couldn?t run the 1080P(Able to run both in NFS). With the DVSDK, we have received 256MB Memory map based configuration. But we require more Cmem,Heap memoery .  Could you please give us for 512MB based Memory map configuration..? Or what are the changes have to do for running the 1080P?   Thanks & Regards,Raghu Ramaraj 
http://www.mindtree.com/email/disclaimer.html

 
    
Jayakrishnan M M
Research Engineer
R&D Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krishnan at samsung.com
 
  
 
 

From padmanabha.s at fossilshale.com  Wed May 19 02:18:50 2010
From: padmanabha.s at fossilshale.com (Padmanabha.S)
Date: Wed, 19 May 2010 12:48:50 +0530
Subject: [dm6467]: ImageMagick cross compilation
Message-ID: <000301caf723$8a730430$9f590c90$@s@fossilshale.com>

Hello All,

 

I am using dm6467 EVM (with Montavista toolchain). I am failing to cross
compile ImageMagick (ImageMagick-6.6.1-8), with following error.

 

Configuration parameters used:

 

[ ./configure CC=arm_v5t_le-gcc CXX=arm_v5t_le-c++
CPPFLAGS="-I/opt/mv_pro_5.0.0/montavista/pro/devkit/arm/v5t_le/target/usr/in
clude \

"
LDFLAGS="-L/opt/mv_pro_5.0.0/montavista/pro/devkit/arm/v5t_le/target/usr/lib
" \

 --host=arm --without-x --without-gs-font-dir --without-perl --without-zlib
--prefix=/tmp ]

 

Cross Compilation error:

 

----------------------------------------------------------------------------
----------------------------------------------------------------------------
-----------

libtool: link: warning: library
`/opt/mv_pro_5.0.0/montavista/pro/devkit/arm/v5t_le/target/usr/lib/libgomp.l
a' was moved.

libtool: link: warning: library
`/opt/mv_pro_5.0.0/montavista/pro/devkit/arm/v5t_le/target/usr/lib/libgomp.l
a' was moved.

/usr/lib/libtiff.so: could not read symbols: File in wrong format

collect2: ld returned 1 exit status

make[1]: *** [utilities/animate] Error 1

make[1]: Leaving directory
`/home/padmanabha/Linux/packages/ImageMagick-6.6.1-8'

make: *** [all] Error 2

----------------------------------------------------------------------------
----------------------------------------------------------------------------
--------------

 

 

 

When I tried to compile ImageMagick on target I got following error,

 

#./configure --without-x --without-gs-font-dir --without-perl --without-zlib

:

#make

--------------------------------------------------------------------

gcc: Internal error: Killed (program cc1)

Please submit a full bug report.

See <URL:http://www.mvista.com/support> for instructions.

make[1]: *** [coders/coders_png_la-png.lo] Error 1

make[1]: *** Waiting for unfinished jobs....

make[1]: *** Waiting for unfinished jobs....

make[1]: Leaving directory `/root/ImageMagick-6.5.6-6'

make: *** [all] Error 2

 

--------------------------------------------------------------------

 

Please help me in this regard.

 

Thanks & Regards,

Padmanabha.S

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From sshtylyov at mvista.com  Wed May 19 04:46:45 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Wed, 19 May 2010 13:46:45 +0400
Subject: [PATCH v7 2/6] Davinci: tnetv107x decompresser uart definitions
In-Reply-To: <1274201482-15994-3-git-send-email-cyril@ti.com>
References: <1274201482-15994-1-git-send-email-cyril@ti.com>
	<1274201482-15994-3-git-send-email-cyril@ti.com>
Message-ID: <4BF3B385.4050200@mvista.com>

Hello.

Cyril Chemparathy wrote:

> Added definitions for tnetv107x uart base addresses, and modified base address
> selection for kernel decompressor to check for tnetv107x machine type.

> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> ---
> v7: unchanged from v6
> v6: unchanged from v5
> v5: unchanged from v4
> v4: unchanged from v3
> v3: migrated to uncompress.h based implementation added earlier in this series

>  arch/arm/mach-davinci/include/mach/serial.h     |    8 ++++++++
>  arch/arm/mach-davinci/include/mach/uncompress.h |    7 +++++++
>  2 files changed, 15 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
> index b21ec22..56cc338 100644
> --- a/arch/arm/mach-davinci/include/mach/serial.h
> +++ b/arch/arm/mach-davinci/include/mach/serial.h
> @@ -32,6 +32,14 @@
>  #define DA8XX_UART1_BASE	(IO_PHYS + 0x10c000)
>  #define DA8XX_UART2_BASE	(IO_PHYS + 0x10d000)
>  
> +#define TNETV107X_UART0_BASE	(0x08108100)
> +#define TNETV107X_UART1_BASE	(0x08088400)
> +#define TNETV107X_UART2_BASE	(0x08108300)

    Why parens here?

WBR, Sergei


From nsekhar at ti.com  Wed May 19 08:27:23 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Wed, 19 May 2010 18:57:23 +0530
Subject: [RFC 1/4] Davinci: mdio - separate out mdio controller code
In-Reply-To: <4BF29D04.4010500@ti.com>
References: <1273876947-30711-1-git-send-email-cyril@ti.com>
	<1273876947-30711-2-git-send-email-cyril@ti.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E6F97620@dbde02.ent.ti.com>
	<4BF29D04.4010500@ti.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E7045AD5@dbde02.ent.ti.com>

Hi Cyril,

On Tue, May 18, 2010 at 19:28:28, Chemparathy, Cyril wrote:
> Hi Sekhar,
>
> Thanks for looking at this.
>
> [...]
> >> +#define MDIO_OUT_FREQ                1100000         /* 2.2 MHz */
> >
> > The comment says 2.2 MHz, but the value is 1.1 MHz?
>
> Thanks.
>
> > Also, can you keep this as a platform variable (with
> > a 2.2 MHz default)? The frequency depends on the board,
> > and although most boards work at 2.2 MHz, not having it
> > as a platform variable will make adding a board with a
> > different frequency requirement difficult.
>
> I am not quite convinced that you'll have too many boards deviate from
> the 2MHz ballpark.  That seems to be a nice and safe frequency that
> works well across phys, socs, and boards.
>
> That said, if we see the need to override the bus frequency in future, I
> am all for a patch at that time.  As it stands, I don't see the value in
> adding platform data definitions for a capability that is not going to
> be used at present.

Okay, but why regress on existing functionality? That frequency
is a function of board design anyway so having the driver hardcode
that would not be correct.

>
> [...]
> >> +     struct {
> >> +             u32     access;
> >> +#define USERACCESS_GO                BIT(31)
> >> +#define USERACCESS_WRITE     BIT(30)
> >> +#define USERACCESS_ACK               BIT(29)
> >> +#define USERACCESS_READ              (0)
> >> +#define USERACCESS_DATA              (0xffff)
> >> +
> >> +             u32     physel;
> >> +     }       user[0];
> >> +};
> >
> > Structure overlays are usually not preferred and
> > is difficult to debug. Can you please keep the
> > direct register access method that was being
> > followed in the original driver?
>
> Agreed, will change since the multiple user modules are not being used
> anyway.

Hmm, just curious how is this related to 'multiple user (mdio?) modules'?

[...]
>
> >> +     data->bus->phy_mask = phy_mask;
> >
> > Looks like phy_mask local variable can be eliminated?
>
> Not at the expense of readability.  I'd rather not have
> data->bus->phy_mask references all over.

Your call.

Thanks,
Sekhar


From sshtylyov at ru.mvista.com  Wed May 19 09:11:36 2010
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Wed, 19 May 2010 18:11:36 +0400
Subject: [PATCH] MUSB: make non-OMAP platforms build with CONFIG_PM=y
Message-ID: <201005191811.36433.sshtylyov@ru.mvista.com>

Attempt to build MUSB driver with CONFIG_PM=y (e.g. in the OTG mode) on DaVinci
results in these link errors:

drivers/built-in.o: In function `musb_restore_context':
led-triggers.c:(.text+0x714d8): undefined reference to
`musb_platform_restore_context'
drivers/built-in.o: In function `musb_save_context':
led-triggers.c:(.text+0x71788): undefined reference to
`musb_platform_save_context'

This turned out to be caused by commit 9957dd97ec5e98dd334f87ade1d9a0b24d1f86eb
(usb: musb: Fix compile error for omaps for musb_hdrc). Revert it, taking into
account the rename of CONFIG_ARCH_OMAP34XX into CONFIG_ARCH_OMAP3 (which that
commit fixed in a completely inappropriate way).

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
Cc: stable at kernel.org

---
The first -stable patch I guess...

 drivers/usb/musb/musb_core.h |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Index: linux-2.6/drivers/usb/musb/musb_core.h
===================================================================
--- linux-2.6.orig/drivers/usb/musb/musb_core.h
+++ linux-2.6/drivers/usb/musb/musb_core.h
@@ -469,7 +469,7 @@ struct musb_csr_regs {
 
 struct musb_context_registers {
 
-#ifdef CONFIG_PM
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
 	u32 otg_sysconfig, otg_forcestandby;
 #endif
 	u8 power;
@@ -483,7 +483,7 @@ struct musb_context_registers {
 	struct musb_csr_regs index_regs[MUSB_C_NUM_EPS];
 };
 
-#ifdef CONFIG_PM
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
 extern void musb_platform_save_context(struct musb *musb,
 		struct musb_context_registers *musb_context);
 extern void musb_platform_restore_context(struct musb *musb,

From nsekhar at ti.com  Wed May 19 09:49:28 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Wed, 19 May 2010 20:19:28 +0530
Subject: [PATCH 0/4] Assorted davinci fixes.
In-Reply-To: <4BF28E20.3070701@nexvision.fr>
References: <4BF28E20.3070701@nexvision.fr>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E7045B6E@dbde02.ent.ti.com>


Hi Gilles,

On Tue, May 18, 2010 at 18:24:56, Gilles Chanteperdrix wrote:
>
> Hi,
>
> while experimenting with a davinci DM368, I had a few issues which the
> following patches serie try and fix.
>
> Thanks in advance for your review.

It seems these patches apply to the arago-project.org hosted davinci-staging
tree and not to upstream v4l2 tree or Kevin's davinci tree.

In such cases, please note this fact in the patch 0/N and/or below the ---
in patch description so that folks interested in upstream development only
can ignore these patches.

DaVinci display is still not upstream yet. We are working on cleaning up the
code and preparing the code for upstream submissions. Fixes like these will
surely help the process. Thanks for the work!

Regards,
Sekhar

From cyril at ti.com  Wed May 19 10:05:58 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Wed, 19 May 2010 11:05:58 -0400
Subject: [RFC 1/4] Davinci: mdio - separate out mdio controller code
In-Reply-To: <B85A65D85D7EB246BE421B3FB0FBB59301E7045AD5@dbde02.ent.ti.com>
References: <1273876947-30711-1-git-send-email-cyril@ti.com>
	<1273876947-30711-2-git-send-email-cyril@ti.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E6F97620@dbde02.ent.ti.com>
	<4BF29D04.4010500@ti.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E7045AD5@dbde02.ent.ti.com>
Message-ID: <4BF3FE56.90303@ti.com>

Hi Sekhar,

[...]
>>> Also, can you keep this as a platform variable (with
>>> a 2.2 MHz default)? The frequency depends on the board,
>>> and although most boards work at 2.2 MHz, not having it
>>> as a platform variable will make adding a board with a
>>> different frequency requirement difficult.
>>
>> I am not quite convinced that you'll have too many boards deviate from
>> the 2MHz ballpark.  That seems to be a nice and safe frequency that
>> works well across phys, socs, and boards.
>>
>> That said, if we see the need to override the bus frequency in future, I
>> am all for a patch at that time.  As it stands, I don't see the value in
>> adding platform data definitions for a capability that is not going to
>> be used at present.
> 
> Okay, but why regress on existing functionality?

I don't quite think that the prior existence of a "knob" is reason
enough to keep it around, considering that the knob is essentially
unused (below).

> That frequency is a function of board design anyway so having the
> driver hardcode that would not be correct.

The frequency _limit_ is a function of board design.  However, if these
effects were being factored in, we would have had the mdio bus operating
at different frequencies on different boards.

This is clearly not the case at present.  Every board defines the same
magic 2.2 MHz frequency - a "safe" relatively low frequency that works
well across boards.

In short, we currently have a knob for frequency control, but we don't
use board-specific numbers from characterization data (if available).
That said, what good is the knob?  All that it does at present, is muddy
up the code with identical definitions on every board.

If anyone (in future) were to take up the effort of analytically
determining frequencies based on characterization data, adding a
minuscule piece of platform data code would likely be the very least of
his worries :-)

[...]
>>>> +     struct {
>>>> +             u32     access;
>>>> +#define USERACCESS_GO                BIT(31)
>>>> +#define USERACCESS_WRITE     BIT(30)
>>>> +#define USERACCESS_ACK               BIT(29)
>>>> +#define USERACCESS_READ              (0)
>>>> +#define USERACCESS_DATA              (0xffff)
>>>> +
>>>> +             u32     physel;
>>>> +     }       user[0];
>>>> +};
>>>
>>> Structure overlays are usually not preferred and
>>> is difficult to debug. Can you please keep the
>>> direct register access method that was being
>>> followed in the original driver?
>>
>> Agreed, will change since the multiple user modules are not being used
>> anyway.
> 
> Hmm, just curious how is this related to 'multiple user (mdio?) modules'?

Initially, I considered the option of having the MDIO hardware monitor
the link status for "attached" phys, by programming the physel
registers.  For this, the mdio control register's highest-user-channel
field defines the number of user channels available.  Therefore, the
number of user channels could vary across socs - leading to this kind of
a data structure.

This whole approach turned out to be a bit of a problem because the
phydev layer needs raw mdio interrupts and not "link state change"
interrupts.  Further, the mdio module interrupts are not necessarily
hooked up (on at least some socs).

Regards
Cyril.

From khilman at deeprootsystems.com  Wed May 19 14:00:44 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Wed, 19 May 2010 12:00:44 -0700
Subject: [GIT PULL] davinci platform updates for 2.6.35
Message-ID: <87r5l7k97n.fsf@deeprootsystems.com>

Linus,

Please pull the following davinci platform updates for 2.6.35.

Sorry for the last-minute revert, but realized that one RTC patch had
not recieved the proper signoffs from RTC maintainers, and I figured a
revert would be preferred over a rebase at this point.

Thanks,

Kevin



The following changes since commit 66f41d4c5c8a5deed66fdcc84509376c9a0bf9d8:
  Linus Torvalds (1):
        Linux 2.6.34-rc6

are available in the git repository at:

  ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git davinci-for-linus

Anuj Aggarwal (1):
      davinci: edma: clear interrupt status for interrupt enabled channels only

Cyril Chemparathy (28):
      Davinci: allow SOCs based on other ARM CPUs
      Davinci: enable timer clock before use
      Davinci: cpintc host map configuration
      Davinci: support LPSC SwRstDisable state
      Davinci: promote da8xx_pinmux_setup()
      Davinci: tnetv107x pin list
      Davinci: tnetv107x LPSC modules
      Davinci: tnetv107x IRQ definitions
      Davinci: tnetv107x cpu types
      Davinci: configurable pll divider mask
      Davinci: gpio - minor cleanup
      Davinci: gpio - structs and functions renamed
      Davinci: gpio - register layout invariant inlines
      Davinci: gpio - controller type support
      Davinci: gpio - fine grained locking
      Davinci: eliminate pinmux offset verbosity
      Davinci: watchdog reset separation across socs
      Davinci: serial - remove unnecessary define
      Davinci: serial - use ioremap()
      Davinci: serial - conditional reset via pwremu
      Davinci: gpio - use ioremap()
      Davinci: da8xx: rtc - use ioremap
      Davinci: jtag_id - use ioremap()
      Davinci: timer - use ioremap()
      Davinci: psc - use ioremap()
      Davinci: aintc/cpintc - use ioremap()
      Davinci: pinmux - use ioremap()
      Davinci: iotable based ioremap() interception

Kevin Hilman (3):
      davinci: misc cleanups from sparse
      davinci: sparse: gpio: void casting
      Revert "rtc: omap: let device wakeup capability be configured from chip init logic"

Miguel Aguilar (1):
      RTC: DaVinci RTC driver

Sekhar Nori (5):
      rtc: omap: let device wakeup capability be configured from chip init logic
      davinci: edma: use a more intuitive name for edma_info
      davinci: edma: fix coding style issue related to usage of braces
      davinci: edma: use BIT() wherever possible
      davinci: edma: fix coding style issue related to breaking lines

Sergei Shtylyov (3):
      DaVinci: move AEMIF #define's to the proper headers
      DA830 EVM: use DA8XX_AEMIF_*_BASE #define's
      DaVinci: move IDE platform device to its proper place

Thomas Koeller (5):
      davinci: DM365: Allow use of GPIO64_57
      davinci: mach/common.h: add missing includes
      DM365: Added PINMUX definitions for GPIO30..32
      DM365: Make CLKOUTx available
      DM365: Added more PINMUX configurations for AEMIF

Vipin Bhandari (2):
      davinci: da830/omap-l137 evm: add support for GPIO based MMC/SD card detection
      davinci: da830/omap-l137 evm: use 8-wire MMC/SD card support

 arch/arm/Kconfig                             |    1 -
 arch/arm/mach-davinci/Kconfig                |    2 +
 arch/arm/mach-davinci/board-da830-evm.c      |   52 ++-
 arch/arm/mach-davinci/board-da850-evm.c      |   28 +-
 arch/arm/mach-davinci/board-dm355-evm.c      |   18 +-
 arch/arm/mach-davinci/board-dm355-leopard.c  |   18 +-
 arch/arm/mach-davinci/board-dm365-evm.c      |   12 +-
 arch/arm/mach-davinci/board-dm644x-evm.c     |   60 +--
 arch/arm/mach-davinci/board-dm646x-evm.c     |   22 +-
 arch/arm/mach-davinci/board-neuros-osd2.c    |   54 +--
 arch/arm/mach-davinci/board-sffsdr.c         |   20 +-
 arch/arm/mach-davinci/cdce949.c              |    1 +
 arch/arm/mach-davinci/clock.c                |   32 +-
 arch/arm/mach-davinci/clock.h                |    9 +-
 arch/arm/mach-davinci/common.c               |   57 ++-
 arch/arm/mach-davinci/cp_intc.c              |   22 +-
 arch/arm/mach-davinci/da830.c                |   29 +-
 arch/arm/mach-davinci/da850.c                |   30 +-
 arch/arm/mach-davinci/devices-da8xx.c        |   15 +-
 arch/arm/mach-davinci/devices.c              |   50 ++-
 arch/arm/mach-davinci/dm355.c                |   21 +-
 arch/arm/mach-davinci/dm365.c                |   34 +-
 arch/arm/mach-davinci/dm644x.c               |   21 +-
 arch/arm/mach-davinci/dm646x.c               |   53 +--
 arch/arm/mach-davinci/dma.c                  |  234 +++++-----
 arch/arm/mach-davinci/gpio.c                 |  160 ++++---
 arch/arm/mach-davinci/include/mach/common.h  |   32 +-
 arch/arm/mach-davinci/include/mach/cp_intc.h |    3 +-
 arch/arm/mach-davinci/include/mach/cputype.h |    8 +
 arch/arm/mach-davinci/include/mach/da8xx.h   |   29 +-
 arch/arm/mach-davinci/include/mach/dm355.h   |    3 +
 arch/arm/mach-davinci/include/mach/dm365.h   |    4 +
 arch/arm/mach-davinci/include/mach/dm644x.h  |    6 +
 arch/arm/mach-davinci/include/mach/dm646x.h  |    4 +-
 arch/arm/mach-davinci/include/mach/gpio.h    |   72 ++--
 arch/arm/mach-davinci/include/mach/irqs.h    |   97 ++++
 arch/arm/mach-davinci/include/mach/mux.h     |  290 +++++++++++-
 arch/arm/mach-davinci/include/mach/psc.h     |   55 ++-
 arch/arm/mach-davinci/include/mach/serial.h  |    1 -
 arch/arm/mach-davinci/include/mach/system.h  |    5 +-
 arch/arm/mach-davinci/io.c                   |   20 +-
 arch/arm/mach-davinci/irq.c                  |    7 +-
 arch/arm/mach-davinci/mux.c                  |   19 +-
 arch/arm/mach-davinci/mux.h                  |    2 +-
 arch/arm/mach-davinci/psc.c                  |   10 +-
 arch/arm/mach-davinci/serial.c               |   34 +-
 arch/arm/mach-davinci/time.c                 |   37 +-
 drivers/rtc/Kconfig                          |   10 +
 drivers/rtc/Makefile                         |    1 +
 drivers/rtc/rtc-davinci.c                    |  673 ++++++++++++++++++++++++++
 50 files changed, 1813 insertions(+), 664 deletions(-)
 create mode 100644 drivers/rtc/rtc-davinci.c

From juha.kuikka at gmail.com  Wed May 19 19:38:41 2010
From: juha.kuikka at gmail.com (Juha Kuikka)
Date: Wed, 19 May 2010 17:38:41 -0700
Subject: DA850 and MMCSD1 EDMA
Message-ID: <AANLkTildlmf7ApQoolU7KJLlxC8Hi4NC7vmRyF4MvYUA@mail.gmail.com>

Hi,

I am working with a HW that has an SDIO device on the second
MMC/SD/SDIO controller (mmcsd1).

As the current Davinci-kernel does not have a platform device for the
second controller I have added my own.

It works for probing the device but fails on first CMD53. More
specifically the mmcd process freezes waiting for a response to the
command. This happens because the MMC controller does not have a
timeout for write but instead it relies on the interrupt from EDMA to
terminate writes.

If I disable the dma support in the MMC host driver the device works
without issues.

My mmcsd1 resources look like this:

static struct resource da8xx_mmcsd1_resources[] = {
        {               /* registers */
                .start  = DA8XX_MMCSD1_BASE,
                .end    = DA8XX_MMCSD1_BASE + SZ_4K - 1,
                .flags  = IORESOURCE_MEM,
        },
        {               /* interrupt */
                .start  = IRQ_DA850_MMCSDINT0_1,
                .end    = IRQ_DA850_MMCSDINT0_1,
                .flags  = IORESOURCE_IRQ,
        },
        {               /* DMA RX */
                .start  = EDMA_CTLR_CHAN(1, 28),
                .end    = EDMA_CTLR_CHAN(1, 28),
                .flags  = IORESOURCE_DMA,
        },
        {               /* DMA TX */
                .start  = EDMA_CTLR_CHAN(1, 29),
                .end    = EDMA_CTLR_CHAN(1, 29),
                .flags  = IORESOURCE_DMA,
        },
};

I suspect the DMA channel numbers are wrong or for some reason the
second EDMA controller has issues.

Looking at the OMAP-L138 datasheet table 6-13 "EDMA Synchronization
events" on page 98 I see that MMCSD1 does not have any events listed
but I suspected the 28 and 29 on the second controller to be the ones
to use. Maybe someone from TI could chime in on this?

 - Juha

From liuyue18301 at 163.com  Wed May 19 21:31:40 2010
From: liuyue18301 at 163.com (liuyue18301)
Date: Thu, 20 May 2010 10:31:40 +0800 (CST)
Subject: davinci gpio interrupt
Message-ID: <114919e.d21f.128b38d46eb.Coremail.liuyue18301@163.com>

hello everybody:
         i want to take gpio1 in dm6446 as inpterrupt source, now  i have configure the gpio register.but i have some questions 
         first, in my driver i take a test.read the gpio interrupt status register all the time, but when i press the button,it has make a interrupt input,i have validated it  by the Oscilloscope.but the status is 0  not changed, i do not know the reason.
         second. i have write my interrupt rountie,if i registe the isr by request_irq successfully,if there is a interrupt input,my isr can be called automaticlly

                                                            thank you
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From liuyue18301 at 163.com  Wed May 19 21:51:15 2010
From: liuyue18301 at 163.com (liuyue18301)
Date: Thu, 20 May 2010 10:51:15 +0800 (CST)
Subject: davinci gpio interrupt
Message-ID: <1245dcc.d745.128b39f351a.Coremail.liuyue18301@163.com>

hello everybody:
         i want to take gpio1 in dm6446 as inpterrupt source, now  i have configure the gpio register.but i have some questions 
         first, in my driver i take a test.read the gpio interrupt status register all the time, but when i press the button,it has make a interrupt input,i have validated it  by the Oscilloscope.but the status is 0  not changed, i do not know the reason.
         second. i have write my interrupt rountie,if i registe the isr by request_irq successfully,if there is a interrupt input,my isr can be called automaticlly

                                                            thank you
-------------- next part --------------
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From sudhakar.raj at ti.com  Wed May 19 23:05:24 2010
From: sudhakar.raj at ti.com (Sudhakar Rajashekhara)
Date: Thu, 20 May 2010 09:35:24 +0530
Subject: DA850 and MMCSD1 EDMA
In-Reply-To: <AANLkTildlmf7ApQoolU7KJLlxC8Hi4NC7vmRyF4MvYUA@mail.gmail.com>
References: <AANLkTildlmf7ApQoolU7KJLlxC8Hi4NC7vmRyF4MvYUA@mail.gmail.com>
Message-ID: <032401caf7d1$ac6b9e40$0542dac0$@raj@ti.com>

Hi Juha,

On Thu, May 20, 2010 at 06:08:41, Juha Kuikka wrote:
> Hi,
> 
> I am working with a HW that has an SDIO device on the second
> MMC/SD/SDIO controller (mmcsd1).
> 
> As the current Davinci-kernel does not have a platform device for the
> second controller I have added my own.
> 
> It works for probing the device but fails on first CMD53. More
> specifically the mmcd process freezes waiting for a response to the
> command. This happens because the MMC controller does not have a
> timeout for write but instead it relies on the interrupt from EDMA to
> terminate writes.
> 
> If I disable the dma support in the MMC host driver the device works
> without issues.
> 
> My mmcsd1 resources look like this:
> 
> static struct resource da8xx_mmcsd1_resources[] = {
>         {               /* registers */
>                 .start  = DA8XX_MMCSD1_BASE,
>                 .end    = DA8XX_MMCSD1_BASE + SZ_4K - 1,
>                 .flags  = IORESOURCE_MEM,
>         },
>         {               /* interrupt */
>                 .start  = IRQ_DA850_MMCSDINT0_1,
>                 .end    = IRQ_DA850_MMCSDINT0_1,
>                 .flags  = IORESOURCE_IRQ,
>         },
>         {               /* DMA RX */
>                 .start  = EDMA_CTLR_CHAN(1, 28),
>                 .end    = EDMA_CTLR_CHAN(1, 28),
>                 .flags  = IORESOURCE_DMA,
>         },
>         {               /* DMA TX */
>                 .start  = EDMA_CTLR_CHAN(1, 29),
>                 .end    = EDMA_CTLR_CHAN(1, 29),
>                 .flags  = IORESOURCE_DMA,
>         },
> };
> 
> I suspect the DMA channel numbers are wrong or for some reason the
> second EDMA controller has issues.
> 
> Looking at the OMAP-L138 datasheet table 6-13 "EDMA Synchronization
> events" on page 98 I see that MMCSD1 does not have any events listed
> but I suspected the 28 and 29 on the second controller to be the ones
> to use. Maybe someone from TI could chime in on this?
> 

The EDMA event numbers you are using are correct. Which kernel you are using
for testing this? If you are using a package from TI, then that package contains
an example for EDMA which you can execute and find out whether the second EDMA
instance is working or not.

Regards,
Sudhakar



From nsekhar at ti.com  Thu May 20 03:43:13 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Thu, 20 May 2010 14:13:13 +0530
Subject: [PATCH v2] rtc: omap: let device wakeup capability be
	configured from chip init logic
In-Reply-To: <1267965354-16805-1-git-send-email-nsekhar@ti.com>
References: <1267965354-16805-1-git-send-email-nsekhar@ti.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E704604B@dbde02.ent.ti.com>

Hi Dave,

On Sun, Mar 07, 2010 at 18:05:54, Nori, Sekhar wrote:
> The rtc-omap driver currently hardcodes the RTC wakeup capability
> to be "not capable". While this seems to be true for existing OMAP1
> boards which are not wired for this, the DA850/OMAP-L138 SoC, the
> RTC can always be wake up source from its "deep sleep" mode.
>
> This patch lets the wakeup capability to be set from platform data and
> does not override the setting from the driver. For DA850/OMAP-L138, this
> is done from arch/arm/mach-davinci/devices-da8xx.c:da8xx_register_rtc()
>
> Note that this patch does not change the behavior on any existing OMAP1
> board since the platform device registration sets the wakeup capability
> to 0 by default.
>
> Signed-off-by: Sekhar Nori <nsekhar at ti.com>
> Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
> ---
>
> Dave, would you please ack this patch if you are satisfied?

Can you please ack this patch if it looks good (or suggest
any other changes you would like to see)?

Thanks,
Sekhar

>
>  drivers/rtc/rtc-omap.c |   12 +++++++-----
>  1 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
> index 64d9727..73377b0 100644
> --- a/drivers/rtc/rtc-omap.c
> +++ b/drivers/rtc/rtc-omap.c
> @@ -34,7 +34,8 @@
>   * Board-specific wiring options include using split power mode with
>   * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
>   * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
> - * low power modes).  See the BOARD-SPECIFIC CUSTOMIZATION comment.
> + * low power modes) for OMAP1 boards (OMAP-L138 has this built into
> + * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
>   */
>
>  #define OMAP_RTC_BASE                        0xfffb4800
> @@ -401,16 +402,17 @@ static int __init omap_rtc_probe(struct platform_device *pdev)
>
>       /* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
>        *
> -      *  - Boards wired so that RTC_WAKE_INT does something, and muxed
> -      *    right (W13_1610_RTC_WAKE_INT is the default after chip reset),
> -      *    should initialize the device wakeup flag appropriately.
> +      *  - Device wake-up capability setting should come through chip
> +      *    init logic. OMAP1 boards should initialize the "wakeup capable"
> +      *    flag in the platform device if the board is wired right for
> +      *    being woken up by RTC alarm. For OMAP-L138, this capability
> +      *    is built into the SoC by the "Deep Sleep" capability.
>        *
>        *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
>        *    rather than nPWRON_RESET, should forcibly enable split
>        *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
>        *    is write-only, and always reads as zero...)
>        */
> -     device_init_wakeup(&pdev->dev, 0);
>
>       if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT)
>               pr_info("%s: split power mode\n", pdev->name);
> --
> 1.6.2.4
>
>


From spoulsen at css-design.com  Thu May 20 09:21:27 2010
From: spoulsen at css-design.com (Steve Poulsen)
Date: Thu, 20 May 2010 09:21:27 -0500
Subject: davinci gpio interrupt
In-Reply-To: <1245dcc.d745.128b39f351a.Coremail.liuyue18301@163.com>
References: <1245dcc.d745.128b39f351a.Coremail.liuyue18301@163.com>
Message-ID: <4BF54567.4000404@css-design.com>

I'm not sure which kernel you use, but for some time there has been GPIO 
interrupt support that hides most of the lower level register accessing. 
You should setup the PINMUXing to make sure your pin is GPIO mapped. You 
can then use gpio_to_irq function to convert a GPIO number to an IRQ. 
Afterwards, you request the irq normally.

Sorry, but I have difficutly in understanding everything below. It 
sounds like you are trying to read the GPIO input and it doesn't change. 
Check PINMUX and also make sure you call gpio_direction_input();.

Steve

On 05/19/2010 09:51 PM, liuyue18301 wrote:
> hello everybody:
> i want to take gpio1 in dm6446 as inpterrupt source, now i have 
> configure the gpio register.but i have some questions
> first, in my driver i take a test.read the gpio interrupt status 
> register all the time, but when i press the button,it has make a 
> interrupt input,i have validated it by the Oscilloscope.but the status 
> is 0 not changed, i do not know the reason.
> second. i have write my interrupt rountie,if i registe the isr by 
> request_irq successfully,if there is a interrupt input,my isr can be 
> called automaticlly
>
> thank you
>
>
>
> ------------------------------------------------------------------------
> ?????????????????????????????????????????? <http://ym.163.com/?from=od3>
> -- 
> This message has been scanned for viruses and
> dangerous content by *MailScanner* <http://www.mailscanner.info/>, and is
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>
> _______________________________________________
> Davinci-linux-open-source mailing list
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> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>    


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From david-b at pacbell.net  Thu May 20 11:51:59 2010
From: david-b at pacbell.net (David Brownell)
Date: Thu, 20 May 2010 09:51:59 -0700 (PDT)
Subject: [PATCH v2] rtc: omap: let device wakeup capability be configured
	from chip init logic
In-Reply-To: <B85A65D85D7EB246BE421B3FB0FBB59301E704604B@dbde02.ent.ti.com>
Message-ID: <565797.30510.qm@web180301.mail.gq1.yahoo.com>


> On Sun, Mar 07, 2010 at 18:05:54, Nori, Sekhar wrote:
> > The rtc-omap driver currently hardcodes the RTC wakeup
> capability
> > to be "not capable". While this seems to be true for
> existing OMAP1
> > boards which are not wired for this, the
> DA850/OMAP-L138 SoC, the
> > RTC can always be wake up source from its "deep sleep"
> mode.

Good.  Linux has work to do yet getting wake events to behave,
and I keep thinking that RTC support is the best place for such
work to start ... (since most RTCs seem to issue wake events,
even on ACPI/PC hardware).

So having RTCs do this right is forward motion, and will help
(I'd hope!) get other wake event sources working too.


That driver, as you know, started with OMAP1 where few boards were
actually wired so the RTC would wake.  Which is why it ignored the
wake events ... :(



> >
> > This patch lets the wakeup capability to be set from
> platform data and
> > does not override the setting from the driver. For
> DA850/OMAP-L138, this
> > is done from
> arch/arm/mach-davinci/devices-da8xx.c:da8xx_register_rtc()
> >
> > Note that this patch does not change the behavior on
> any existing OMAP1
> > board since the platform device registration sets the
> wakeup capability
> > to 0 by default.
> > Dave, would you please ack this patch if you are
> satisfied?

I don't see how it could work, since it always sets the
wake capability to the default of "can't wake"...  Even if
the board *can* wake...

The model I've worked with is that for devices which can issue
wake events, the board init code sets that flag, and the driver
responds appropriately.  Presumably that could work here too...


> Can you please ack this patch if it looks good (or suggest
> any other changes you would like to see)?
> 
> ???device_init_wakeup(&pdev->dev, 0);

Having that line seems to defeat the purpose...



From sshtylyov at ru.mvista.com  Thu May 20 12:32:02 2010
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Thu, 20 May 2010 21:32:02 +0400
Subject: [PATCH] musb_core: make
Message-ID: <201005202132.03147.sshtylyov@ru.mvista.com>

Commit 1c25fda4a09e8229800979986ef399401053b46e (usb: musb: handle irqs in the
order dictated by programming guide) forgot to get rid of the old 'STAGE0_MASK'
filter for calling musb_stage_orq(), so now disconnect and suspend interrupts
are effectively ignored...

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
Cc: stable at kernel.org

---
The patch is against the recent Linus' tree.
Should be applied to 2.6.34.y as well...

 drivers/usb/musb/musb_core.c |    6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

Index: linux-2.6/drivers/usb/musb/musb_core.c
===================================================================
--- linux-2.6.orig/drivers/usb/musb/musb_core.c
+++ linux-2.6/drivers/usb/musb/musb_core.c
@@ -371,10 +371,6 @@ void musb_hnp_stop(struct musb *musb)
  * @param power
  */
 
-#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
-		| MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
-		| MUSB_INTR_RESET)
-
 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
 				u8 devctl, u8 power)
 {
@@ -1519,7 +1515,7 @@ irqreturn_t musb_interrupt(struct musb *
 	/* the core can interrupt us for multiple reasons; docs have
 	 * a generic interrupt flowchart to follow
 	 */
-	if (musb->int_usb & STAGE0_MASK)
+	if (musb->int_usb)
 		retval |= musb_stage0_irq(musb, musb->int_usb,
 				devctl, power);
 

From sshtylyov at ru.mvista.com  Thu May 20 12:33:12 2010
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Thu, 20 May 2010 21:33:12 +0400
Subject: [PATCH resend] musb_core: make disconnect and suspend interrupts work
	again
Message-ID: <201005202133.12497.sshtylyov@ru.mvista.com>

Commit 1c25fda4a09e8229800979986ef399401053b46e (usb: musb: handle irqs in the
order dictated by programming guide) forgot to get rid of the old 'STAGE0_MASK'
filter for calling musb_stage_orq(), so now disconnect and suspend interrupts
are effectively ignored...

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
Cc: stable at kernel.org

---
The patch is against the recent Linus' tree.
Should be applied to 2.6.34.y as well...
Resending with the correct subject. :-/

 drivers/usb/musb/musb_core.c |    6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

Index: linux-2.6/drivers/usb/musb/musb_core.c
===================================================================
--- linux-2.6.orig/drivers/usb/musb/musb_core.c
+++ linux-2.6/drivers/usb/musb/musb_core.c
@@ -371,10 +371,6 @@ void musb_hnp_stop(struct musb *musb)
  * @param power
  */
 
-#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
-		| MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
-		| MUSB_INTR_RESET)
-
 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
 				u8 devctl, u8 power)
 {
@@ -1519,7 +1515,7 @@ irqreturn_t musb_interrupt(struct musb *
 	/* the core can interrupt us for multiple reasons; docs have
 	 * a generic interrupt flowchart to follow
 	 */
-	if (musb->int_usb & STAGE0_MASK)
+	if (musb->int_usb)
 		retval |= musb_stage0_irq(musb, musb->int_usb,
 				devctl, power);
 

From blueskyjb at roadrunner.com  Thu May 20 15:07:35 2010
From: blueskyjb at roadrunner.com (Jimmy Blair)
Date: Thu, 20 May 2010 13:07:35 -0700
Subject: vpbe_encoder.c
In-Reply-To: <mailman.2213.1274345001.11996.davinci-linux-open-source@linux.davincidsp.com>
References: <mailman.2213.1274345001.11996.davinci-linux-open-source@linux.davincidsp.com>
Message-ID: <4BF59687.3040407@roadrunner.com>

I've been working from an older version of the kernel (2.6.32-rc2).
It has code to set up the video encoder on the DM365 in
media/video/davinci/vpbe_encoder.c.  That file is gone in the
kernel that I pulled today. Can someone tell me where the
video encoder setup code has been moved to??  Thanks!

From m-karicheri2 at ti.com  Thu May 20 15:52:09 2010
From: m-karicheri2 at ti.com (Karicheri, Muralidharan)
Date: Thu, 20 May 2010 15:52:09 -0500
Subject: vpbe_encoder.c
In-Reply-To: <4BF59687.3040407@roadrunner.com>
References: <mailman.2213.1274345001.11996.davinci-linux-open-source@linux.davincidsp.com>
	<4BF59687.3040407@roadrunner.com>
Message-ID: <A69FA2915331DC488A831521EAE36FE4016AFDE531@dlee06.ent.ti.com>

If you had pulled the kernel from kernel.org or from davinci tree, you
will not be seeing those files since the drivers are not submitted to
upstream yet. It is only available in the Arago tree at

http://arago-project.org/git/people/?p=sneha/linux-davinci-staging.git;a=summary


Murali Karicheri
Software Design Engineer
Texas Instruments Inc.
Germantown, MD 20874
phone: 301-407-9583
email: m-karicheri2 at ti.com

>-----Original Message-----
>From: davinci-linux-open-source-bounces+m-
>karicheri2=ti.com at linux.davincidsp.com [mailto:davinci-linux-open-source-
>bounces+m-karicheri2=ti.com at linux.davincidsp.com] On Behalf Of Jimmy Blair
>Sent: Thursday, May 20, 2010 4:08 PM
>To: davinci-linux-open-source at linux.davincidsp.com
>Subject: vpbe_encoder.c
>
>I've been working from an older version of the kernel (2.6.32-rc2).
>It has code to set up the video encoder on the DM365 in
>media/video/davinci/vpbe_encoder.c.  That file is gone in the
>kernel that I pulled today. Can someone tell me where the
>video encoder setup code has been moved to??  Thanks!
>_______________________________________________
>Davinci-linux-open-source mailing list
>Davinci-linux-open-source at linux.davincidsp.com
>http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source

From ipcevm at gmail.com  Fri May 21 03:14:09 2010
From: ipcevm at gmail.com (shaofeng zhang)
Date: Fri, 21 May 2010 16:14:09 +0800
Subject: How to use VPFE as YUV interface in DM6446?
Message-ID: <AANLkTilw0xTTgfeyCNzcOk9rSw6Bk7Iaxu5tCj3xMzGA@mail.gmail.com>

Hi, all,

I want to use the VPFE as generic YUV configration format in DM6446, and my
program is running in Linux,
So could anyone tell me how to append the davinci_vpfe.c or other files in
Linux driver?
Thank you~~
-- 
Best Regards!                   zhangshaofeng
       @Xi'an JiaoTong University
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From brijesh.j at ti.com  Fri May 21 03:41:27 2010
From: brijesh.j at ti.com (Jadav, Brijesh R)
Date: Fri, 21 May 2010 14:11:27 +0530
Subject: How to use VPFE as YUV interface in DM6446?
In-Reply-To: <AANLkTilw0xTTgfeyCNzcOk9rSw6Bk7Iaxu5tCj3xMzGA@mail.gmail.com>
References: <AANLkTilw0xTTgfeyCNzcOk9rSw6Bk7Iaxu5tCj3xMzGA@mail.gmail.com>
Message-ID: <19F8576C6E063C45BE387C64729E7394044E535F69@dbde02.ent.ti.com>

Hi,

VPFE supports YUV422 format. What do you mean by generic YUV format?

Thx,
Brijesh

________________________________
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of shaofeng zhang
Sent: Friday, May 21, 2010 1:44 PM
To: davinci-linux-open-source at linux.davincidsp.com
Subject: How to use VPFE as YUV interface in DM6446?


Hi, all,

I want to use the VPFE as generic YUV configration format in DM6446, and my program is running in Linux,
So could anyone tell me how to append the davinci_vpfe.c or other files in Linux driver?
Thank you~~
--
Best Regards!                   zhangshaofeng                                      @Xi'an JiaoTong University
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From kieranbingham at gmail.com  Fri May 21 09:28:10 2010
From: kieranbingham at gmail.com (Kieran Bingham)
Date: Fri, 21 May 2010 15:28:10 +0100
Subject: DM365 DavinciFB Colour Keying Transparency
Message-ID: <4BF6987A.7030206@gmail.com>

Hi Guys,

Does anyone know the correct methods to set up the OSD0 to be 
transparent based on a BLACK colour key ?

We are trying to move to the Arago 2.6.32 kernel, and the methods we 
used on the 2.6.18 kernel no longer work - and everything I've tried 
hasn't worked either.

So rather than continue guessing in the dark - I thought I'd ask you guys :)

--
Hope you can help
Regards
Kieran

From gilles.chanteperdrix at nexvision.fr  Fri May 21 09:47:29 2010
From: gilles.chanteperdrix at nexvision.fr (Gilles Chanteperdrix)
Date: Fri, 21 May 2010 16:47:29 +0200
Subject: DM365 DavinciFB Colour Keying Transparency
In-Reply-To: <4BF6987A.7030206@gmail.com>
References: <4BF6987A.7030206@gmail.com>
Message-ID: <4BF69D01.7050706@nexvision.fr>

Kieran Bingham wrote:
> Hi Guys,
> 
> Does anyone know the correct methods to set up the OSD0 to be 
> transparent based on a BLACK colour key ?
> 
> We are trying to move to the Arago 2.6.32 kernel, and the methods we 
> used on the 2.6.18 kernel no longer work - and everything I've tried 
> hasn't worked either.
> 
> So rather than continue guessing in the dark - I thought I'd ask you guys :)

See:
http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-May/019022.html

-- 
					    Gilles.

From kieranbingham at gmail.com  Fri May 21 12:02:46 2010
From: kieranbingham at gmail.com (Kieran Bingham)
Date: Fri, 21 May 2010 18:02:46 +0100
Subject: Flashing uboot from Uboot
Message-ID: <4BF6BCB6.6070707@gmail.com>

Hi Guys,

As I'm running linux, I can't easily switch to running Windows for CCS.

I've been making changes to UBoot and testing them by setting the 
TEXT_BASE at a different address in RAM, loading via TFTP, and calling 
go $(loadaddr)

Now I would like to write this uboot binary to flash, so I've recompiled 
it with the original TEXT_BASE, but I can't figure out where I need to 
flash it in the NAND.

Is it possible to reflash uboot from within Uboot?

--
Regards
Kieran

From spoulsen at css-design.com  Fri May 21 12:13:52 2010
From: spoulsen at css-design.com (Steve Poulsen)
Date: Fri, 21 May 2010 12:13:52 -0500
Subject: Flashing uboot from Uboot
In-Reply-To: <4BF6BCB6.6070707@gmail.com>
References: <4BF6BCB6.6070707@gmail.com>
Message-ID: <F0896752-3B93-4804-8139-F39EA57EA232@css-design.com>

Kieran

It is very possible to do what you want.  Be prepared for a possible  
failure as you figure it out.  The address to write to should b  
determied from the product documentation.  What product are you  
using?  Also, you can read NAND and display to try and match up the  
header and verify it is the correct address.

On a side note, VirtualBox with Windows XP and CCS 3.3 works well with  
the SD emulators.  You may need that if you brick a unit.

Steve

On May 21, 2010, at 12:02 PM, Kieran Bingham <kieranbingham at gmail.com>  
wrote:

> Hi Guys,
>
> As I'm running linux, I can't easily switch to running Windows for  
> CCS.
>
> I've been making changes to UBoot and testing them by setting the  
> TEXT_BASE at a different address in RAM, loading via TFTP, and  
> calling go $(loadaddr)
>
> Now I would like to write this uboot binary to flash, so I've  
> recompiled it with the original TEXT_BASE, but I can't figure out  
> where I need to flash it in the NAND.
>
> Is it possible to reflash uboot from within Uboot?
>
> --
> Regards
> Kieran
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>
> -- 
> This message has been scanned for viruses and
> dangerous content by MailScanner, and is
> believed to be clean.
>

From yan-liu at ti.com  Fri May 21 13:50:50 2010
From: yan-liu at ti.com (Liu, Yan)
Date: Fri, 21 May 2010 13:50:50 -0500
Subject: Flashing uboot from Uboot
In-Reply-To: <4BF6BCB6.6070707@gmail.com>
References: <4BF6BCB6.6070707@gmail.com>
Message-ID: <A69FA2915331DC488A831521EAE36FE4016AFDE960@dlee06.ent.ti.com>

I don't know which product you are using. But, there is a way to write uboot from uboot. Here is the sample command:

tftp 0x80000000 u-boot.bin
nand erase <starting_address_uboot_partition> 0x1C0000
nandecc sw
nand write.i 0x80000000 <starting_address_uboot_partition> 0x1C0000

The <starting_address_uboot_partition> can be found in booting log. Typically, you will find the following part:

0x000000000000-0x000000080000 : "xloader-nand"
0x000000080000-0x000000240000 : "uboot-nand"
0x000000240000-0x000000280000 : "params-nand"
0x000000280000-0x000000780000 : "linux-nand"
0x000000780000-0x000020000000 : "jffs2-nand"

In my case, I use 0x80000 as <starting_address_uboot_partition>.

Hope this helps.

Regards,
Yan

-----Original Message-----
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Kieran Bingham
Sent: Friday, May 21, 2010 1:03 PM
To: davinci-linux-open-source at linux.davincidsp.com
Subject: Flashing uboot from Uboot

Hi Guys,

As I'm running linux, I can't easily switch to running Windows for CCS.

I've been making changes to UBoot and testing them by setting the 
TEXT_BASE at a different address in RAM, loading via TFTP, and calling 
go $(loadaddr)

Now I would like to write this uboot binary to flash, so I've recompiled 
it with the original TEXT_BASE, but I can't figure out where I need to 
flash it in the NAND.

Is it possible to reflash uboot from within Uboot?

--
Regards
Kieran
_______________________________________________
Davinci-linux-open-source mailing list
Davinci-linux-open-source at linux.davincidsp.com
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source

From david-b at pacbell.net  Fri May 21 19:07:53 2010
From: david-b at pacbell.net (David Brownell)
Date: Fri, 21 May 2010 17:07:53 -0700 (PDT)
Subject: DM355+MSP430+push buttons
In-Reply-To: <p2g90d17c5d1005040701p627d41ddmb39b63a14f81ec97@mail.gmail.com>
Message-ID: <661011.93446.qm@web180303.mail.gq1.yahoo.com>

In case the answer didn't get posted (vs. being buried in my mailbox):

--- On Tue, 5/4/10, Idriss Ghodhbane <idriss.ghodhbane at gmail.com> wrote:

From: Idriss Ghodhbane <idriss.ghodhbane at gmail.com>
Subject: DM355+MSP430+push buttons
I am stuck at the level of controlling the push buttons of my EVM DM355(SW10/11/12/13/14).After searching on the net, I had discovered that I haven't the nexassary libraries for the microcontroller MSP430 neither integrated in my DVSDK_2_00_00_22 nor in the LSP "linux-2.6.18_pro500" which is the kernel.
Have you a solution for this issue?
The mainline kernel driver for this is drivers/input/misc/dm355evm_keys.c
It handles the IR remote control and LEDs too.



??? 
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From padmanabha.s at fossilshale.com  Wed May 19 06:56:00 2010
From: padmanabha.s at fossilshale.com (padmanabha srinivasaiah)
Date: Wed, 19 May 2010 06:56:00 (GMT)
Subject: my.TI Support and Feedback
Message-ID: <201005190656.o4J6u0fm013793@comal.ext.ti.com>

This Email Sent From: my.TI Support and Feedback Form


DATE / TIME (UTC): Wed, 19 May 2010 06:55:57 UTC
CUSTOMER'S REGIONAL LOCAL TIME: 19 May 2010 12:25:57

NAME : padmanabha  srinivasaiah

                FIRST NAME: padmanabha
                 LAST NAME: srinivasaiah
                     TITLE: engineer - software
                   COMPANY: FossilShale Embedded Technologies
                     EMAIL: padmanabha.s at fossilshale.com
                     PHONE: 9880762916
                       FAX: 
                 ADDRESS 1: 
                 ADDRESS 2: 
                      CITY: 
                     STATE: 
               POSTAL CODE: 
                   COUNTRY: India


PROBLEM: 
Hi,

I am using Davinci dm6467 EVM (with montavista toolchain), I am unable to cross compile ImageMagick ( ImageMagick-6.6.1-8) package for my target (dm6467 evm).

Can you help me in this regard?

Thank & Regards,
Padmanabha.S

Was there a specific URL that will help illustrate that?


From Ian.Guest at vigilent-tek.com  Wed May 19 15:36:56 2010
From: Ian.Guest at vigilent-tek.com (Ian Guest)
Date: Wed, 19 May 2010 22:36:56 +0200
Subject: OMAPL138 Multiple SPI Chip selects
Message-ID: <AIECJBDDABKLHKAFKNFHGENNEEAA.Ian.Guest@vigilent-tek.com>

Good day

I would like to know if there has been any progress on supporting multiple
chip selects on the SPI of the L138? There was activity:

[PATCH 0/2] overhaul davinci spi driver to fix multiple errors
Brian Niebuhr
Fri, 12 Mar 2010 06:22:18 -0800

but this seems to have stopped as the overhaul was extensive.

Regards
Ian Guest
Tel: +27 12 4601793 (O/S) 012 4601793 (Local)
Cel: +27 84 8532671 (O/S) 084 8532671 (Local)
Fax: +27 88 12 9913491 (O/S) 088 012 9913491 (Local)


From nsekhar at ti.com  Mon May 24 01:06:45 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Mon, 24 May 2010 11:36:45 +0530
Subject: [PATCH v2] rtc: omap: let device wakeup capability be
	configured from chip init logic
In-Reply-To: <565797.30510.qm@web180301.mail.gq1.yahoo.com>
References: <B85A65D85D7EB246BE421B3FB0FBB59301E704604B@dbde02.ent.ti.com>
	<565797.30510.qm@web180301.mail.gq1.yahoo.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E70D2E2C@dbde02.ent.ti.com>

Hi Dave,

On Thu, May 20, 2010 at 22:21:59, David Brownell wrote:
>
> > > This patch lets the wakeup capability to be set from
> > platform data and
> > > does not override the setting from the driver. For
> > DA850/OMAP-L138, this
> > > is done from
> > arch/arm/mach-davinci/devices-da8xx.c:da8xx_register_rtc()
> > >
> > > Note that this patch does not change the behavior on
> > any existing OMAP1
> > > board since the platform device registration sets the
> > wakeup capability
> > > to 0 by default.

Just to be clear, I was actually referring to the fact
that the device_initialize() in drivers/base/core.c is
already clearing the 'can wake-up' flag to 0, so there
should be no need to do so again in the driver.

> > > Dave, would you please ack this patch if you are
> > satisfied?
>
> I don't see how it could work, since it always sets the
> wake capability to the default of "can't wake"...  Even if
> the board *can* wake...

Are you referring to da8xx_register_rtc() here? It sets the
'can wake' flag to true.

        ret = platform_device_register(&da8xx_rtc_device);
        if (!ret)
                /* Atleast on DA850, RTC is a wakeup source */
                device_init_wakeup(&da8xx_rtc_device.dev, true);

>
> The model I've worked with is that for devices which can issue
> wake events, the board init code sets that flag, and the driver
> responds appropriately.  Presumably that could work here too...

Yes, except that the response to the wakeup event is really specific
to DaVinci/DA850 and is handled in arch/arm/mach-davinci/sleep.S, not
in the RTC driver.

>
>
> > Can you please ack this patch if it looks good (or suggest
> > any other changes you would like to see)?
> >
> >    device_init_wakeup(&pdev->dev, 0);
>
> Having that line seems to defeat the purpose...

Agreed, and the patch removes it for that reason.

Thanks,
Sekhar

From nsekhar at ti.com  Mon May 24 01:16:22 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Mon, 24 May 2010 11:46:22 +0530
Subject: [RFC 1/4] Davinci: mdio - separate out mdio controller code
In-Reply-To: <4BF3FE56.90303@ti.com>
References: <1273876947-30711-1-git-send-email-cyril@ti.com>
	<1273876947-30711-2-git-send-email-cyril@ti.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E6F97620@dbde02.ent.ti.com>
	<4BF29D04.4010500@ti.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E7045AD5@dbde02.ent.ti.com>
	<4BF3FE56.90303@ti.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E70D2E44@dbde02.ent.ti.com>


Hi Cyril,

On Wed, May 19, 2010 at 20:35:58, Chemparathy, Cyril wrote:
> Hi Sekhar,
>
> [...]
> >>> Also, can you keep this as a platform variable (with
> >>> a 2.2 MHz default)? The frequency depends on the board,
> >>> and although most boards work at 2.2 MHz, not having it
> >>> as a platform variable will make adding a board with a
> >>> different frequency requirement difficult.
> >>
> >> I am not quite convinced that you'll have too many boards deviate from
> >> the 2MHz ballpark.  That seems to be a nice and safe frequency that
> >> works well across phys, socs, and boards.
> >>
> >> That said, if we see the need to override the bus frequency in future, I
> >> am all for a patch at that time.  As it stands, I don't see the value in
> >> adding platform data definitions for a capability that is not going to
> >> be used at present.
> >
> > Okay, but why regress on existing functionality?
>
> I don't quite think that the prior existence of a "knob" is reason
> enough to keep it around, considering that the knob is essentially
> unused (below).

AFAIR, some boards in mach-omap2 use this driver as well. Hope
you searched them as well before concluding that it is unused.

> In short, we currently have a knob for frequency control, but we don't
> use board-specific numbers from characterization data (if available).
> That said, what good is the knob?  All that it does at present, is muddy
> up the code with identical definitions on every board.

You can decide to default to 2.2 MHz if there is no platform data
that way there wouldn't be any additional code in any of the board
files.

Thanks,
Sekhar

From Jon.Povey at racelogic.co.uk  Mon May 24 01:50:19 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Mon, 24 May 2010 07:50:19 +0100
Subject: Inspiration needed to track down early kernel startup crash
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08E03D096D@Cloud.RL.local>

Trying to get the git kernel running on our in-house board and have an unpleasant crash somewhere between kernel start and console output, with code jumping off to 0xffff000c.

This is using u-boot v2010.03 and kernel based on davinci master at 5954dd1d2cab4b378e22256edbfe132bf4f82f22

Sympoms are; this is the last output I get on the console:

  Starting kernel ...

  Uncompressing Linux... done, booting the kernel.

If I now halt the CPU over JTAG it tells me:

 target halted in ARM state due to debug-request, current mode: Abort
 cpsr: 0x200000d7 pc: 0xffff000c
 MMU: enabled, D-Cache: enabled, I-Cache: enabled

I tried both the vanilla EVM versions of bootloader and kernel, and in-house modified (for different pinmuxing, board file etc). Both combinations boot OK on the DM355EVM, both crash in the same way on our in-house board.
This in-house board and many like it were previously running a MontaVista (DM355 Beta SDK) based setup, so is capable of running linux and the board design should be sound.

There is no UBL on the board at present: I am doing initial setup and loading u-boot over JTAG with OpenOCD.

I stepped through the code enough to determine that the uncompress, relocate and jump to kernel (and several instructions after) seems OK.

I am looking into the ARM ETM/ETB + OpenOCD hoping that could give me a trace of how I end up at 0xffff000c but not having any joy with that so far.

Inspiration for approaches to debugging this problem would be much appreciated, running low on ideas.

Thanks,

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network



From caglarakyuz at gmail.com  Mon May 24 02:10:42 2010
From: caglarakyuz at gmail.com (Caglar Akyuz)
Date: Mon, 24 May 2010 10:10:42 +0300
Subject: Inspiration needed to track down early kernel startup crash
In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE08E03D096D@Cloud.RL.local>
References: <70E876B0EA86DD4BAF101844BC814DFE08E03D096D@Cloud.RL.local>
Message-ID: <201005241010.42626.caglarakyuz@gmail.com>

On Monday 24 May 2010 09:50:19 am Jon Povey wrote:
> Trying to get the git kernel running on our in-house board and have an
>  unpleasant crash somewhere between kernel start and console output, with
>  code jumping off to 0xffff000c.
> 
> This is using u-boot v2010.03 and kernel based on davinci master at
>  5954dd1d2cab4b378e22256edbfe132bf4f82f22
> 
> Sympoms are; this is the last output I get on the console:
> 
>   Starting kernel ...
> 
>   Uncompressing Linux... done, booting the kernel.
> 

Maybe you can use earlyprintk for getting more info from the kernel. i.e. 
earlyprintk=serial,ttyS0,115200 ...

Regards,
Caglar

> If I now halt the CPU over JTAG it tells me:
> 
>  target halted in ARM state due to debug-request, current mode: Abort
>  cpsr: 0x200000d7 pc: 0xffff000c
>  MMU: enabled, D-Cache: enabled, I-Cache: enabled
> 
> I tried both the vanilla EVM versions of bootloader and kernel, and
>  in-house modified (for different pinmuxing, board file etc). Both
>  combinations boot OK on the DM355EVM, both crash in the same way on our
>  in-house board. This in-house board and many like it were previously
>  running a MontaVista (DM355 Beta SDK) based setup, so is capable of
>  running linux and the board design should be sound.
> 
> There is no UBL on the board at present: I am doing initial setup and
>  loading u-boot over JTAG with OpenOCD.
> 
> I stepped through the code enough to determine that the uncompress,
>  relocate and jump to kernel (and several instructions after) seems OK.
> 
> I am looking into the ARM ETM/ETB + OpenOCD hoping that could give me a
>  trace of how I end up at 0xffff000c but not having any joy with that so
>  far.
> 
> Inspiration for approaches to debugging this problem would be much
>  appreciated, running low on ideas.
> 
> Thanks,
> 
> --
> Jon Povey
> jon.povey at racelogic.co.uk
> 
> Racelogic is a limited company registered in England. Registered number
>  2743719 . Registered Office Unit 10, Swan Business Centre, Osier Way,
>  Buckingham, Bucks, MK18 1TB .
> 
> The information contained in this electronic mail transmission is intended
>  by Racelogic Ltd for the use of the named individual or entity to which it
>  is directed and may contain information that is confidential or
>  privileged. If you have received this electronic mail transmission in
>  error, please delete it from your system without copying or forwarding it,
>  and notify the sender of the error by reply email so that the sender's
>  address records can be corrected. The views expressed by the sender of
>  this communication do not necessarily represent those of Racelogic Ltd.
>  Please note that Racelogic reserves the right to monitor e-mail
>  communications passing through its network
> 
> 
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> 

From gasparini at imavis.com  Mon May 24 04:05:25 2010
From: gasparini at imavis.com (Andrea Gasparini)
Date: Mon, 24 May 2010 11:05:25 +0200
Subject: sdio on 2.6.18?
Message-ID: <201005241105.25603.gasparini@imavis.com>

Hi,
someone has ever successfully used SDIO on 2.6.18 for DM355 ?

Thanks, bye.
-- 
Andrea Gasparini 
---- ImaVis S.r.l. ----
web: www.imavis.com

From liuyue18301 at 163.com  Mon May 24 04:36:01 2010
From: liuyue18301 at 163.com (liuyue18301)
Date: Mon, 24 May 2010 17:36:01 +0800 (CST)
Subject: uart interrupt
Message-ID: <7145011e.15395.128c9ab3b28.Coremail.liuyue18301@163.com>

hi,all:
   there are three uart in dm6446,i want to read and write by uart-1 the irq number is 41,but i can not rececive data,i think if i have register the uart-1 to the linux kernel,the irq number can be found in /proc/interrupts but there is only 40 which is uart-0's irq number,if the uart driver register the uart-1 failed but in the /dev, the device file is exiseted. why there is no data can be recieved 
   thank you 


 
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From stanley.miao at windriver.com  Mon May 24 06:59:30 2010
From: stanley.miao at windriver.com (stanley.miao)
Date: Mon, 24 May 2010 19:59:30 +0800
Subject: [PATCH 3/6] davinci: edma: clear events in edma_start()
In-Reply-To: <1268841163-5868-4-git-send-email-khilman@deeprootsystems.com>
References: <1268841163-5868-1-git-send-email-khilman@deeprootsystems.com>
	<1268841163-5868-4-git-send-email-khilman@deeprootsystems.com>
Message-ID: <4BFA6A22.1000006@windriver.com>

This patch causes that the sound can not work normally on OMAP_L138.

Stanley.

Kevin Hilman wrote:
> From: Brian Niebuhr <bniebuhr3 at gmail.com>
>
> This patch fixes an issue where a DMA channel can erroneously process an
> event generated by a previous transfer.  A failure case is where DMA is
> being used for SPI transmit and receive channels on OMAP L138.  In this
> case there is a single bit that controls all event generation from the
> SPI peripheral.  Therefore it is possible that between when edma_stop()
> has been called for the transmit channel on a previous transfer and
> edma_start() is called for the transmit channel on a subsequent transfer,
> that a transmit event has been generated.
>
> The fix is to clear events in edma_start().  This prevents false events
> from being processed when events are enabled for that channel.
>
> Signed-off-by: Brian Niebuhr <bniebuhr at efjohnson.com>
> Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
> ---
>  arch/arm/mach-davinci/dma.c |    3 ++-
>  1 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
> index 15dd886..260485c 100644
> --- a/arch/arm/mach-davinci/dma.c
> +++ b/arch/arm/mach-davinci/dma.c
> @@ -1266,7 +1266,8 @@ int edma_start(unsigned channel)
>  		/* EDMA channel with event association */
>  		pr_debug("EDMA: ER%d %08x\n", j,
>  			edma_shadow0_read_array(ctlr, SH_ER, j));
> -		/* Clear any pending error */
> +		/* Clear any pending event or error */
> +		edma_write_array(ctlr, EDMA_ECR, j, mask);
>  		edma_write_array(ctlr, EDMA_EMCR, j, mask);
>  		/* Clear any SER */
>  		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
>   


From sshtylyov at ru.mvista.com  Mon May 24 08:17:18 2010
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Mon, 24 May 2010 17:17:18 +0400
Subject: [PATCH v2] MUSB: make non-OMAP platforms build with CONFIG_PM=y
Message-ID: <201005241717.19146.sshtylyov@ru.mvista.com>

Attempt to build MUSB driver with CONFIG_PM=y (e.g. in the OTG mode) on DaVinci
results in these link errors:

drivers/built-in.o: In function `musb_restore_context':
led-triggers.c:(.text+0x714d8): undefined reference to
`musb_platform_restore_context'
drivers/built-in.o: In function `musb_save_context':
led-triggers.c:(.text+0x71788): undefined reference to
`musb_platform_save_context'

This turned out to be caused by commit 9957dd97ec5e98dd334f87ade1d9a0b24d1f86eb
(usb: musb: Fix compile error for omaps for musb_hdrc). Revert it, taking into
account the rename of CONFIG_ARCH_OMAP34XX into CONFIG_ARCH_OMAP3 (which that
commit fixed in a completely inappropriate way) and the recent addition of
OMAP4 support.

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>

---
This version of patch should be applied to 2.6.35, while the previous one
should be applied to 2.6.34.y...

 drivers/usb/musb/musb_core.h |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Index: linux-2.6/drivers/usb/musb/musb_core.h
===================================================================
--- linux-2.6.orig/drivers/usb/musb/musb_core.h
+++ linux-2.6/drivers/usb/musb/musb_core.h
@@ -470,7 +470,8 @@ struct musb_csr_regs {
 
 struct musb_context_registers {
 
-#ifdef CONFIG_PM
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
+    defined(CONFIG_ARCH_OMAP4)
 	u32 otg_sysconfig, otg_forcestandby;
 #endif
 	u8 power;
@@ -484,7 +485,8 @@ struct musb_context_registers {
 	struct musb_csr_regs index_regs[MUSB_C_NUM_EPS];
 };
 
-#ifdef CONFIG_PM
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
+    defined(CONFIG_ARCH_OMAP4)
 extern void musb_platform_save_context(struct musb *musb,
 		struct musb_context_registers *musb_context);
 extern void musb_platform_restore_context(struct musb *musb,

From kieranbingham at gmail.com  Mon May 24 11:02:25 2010
From: kieranbingham at gmail.com (Kieran Bingham)
Date: Mon, 24 May 2010 17:02:25 +0100
Subject: Flashing uboot from Uboot
In-Reply-To: <A69FA2915331DC488A831521EAE36FE4016AFDE960@dlee06.ent.ti.com>
References: <4BF6BCB6.6070707@gmail.com>
	<A69FA2915331DC488A831521EAE36FE4016AFDE960@dlee06.ent.ti.com>
Message-ID: <4BFAA311.9030608@gmail.com>

Hi Guys,

Thanks - and yes I'm prepared to use CCS if necesarry - but UBoot 
upgrades will be much easier from a running system :)

I'm on the DM365, but I can't determine the load address...

My nand mappings are :
[    2.250000] Creating 4 MTD partitions on 
"nand_davinci.0":                                                                                                                      

[    2.260000] 0x00000000-0x00660000 : 
"bootloader"                                                                                                                                

[    2.270000] 0x00660000-0x00680000 : 
"params"                                                                                                                                    

[    2.270000] 0x00680000-0x00a80000 : 
"kernel"                                                                                                                                    

[    2.280000] 0x00a80000-0x20000000 : "filesystem"  

And I've tried poking around the nand to look at where I might find the 
UBoot source - but can't "find" it manually.

setenv a 0x80000
nand read.i 0x80700000 $(a) 0x1000; md 0x80700000

80700000: a1aced00 00000100 00000007 00000004    ................
80700010: 00000001 00000020 ffffffff ffffffff    .... ...........
80700020: ffffffff ffffffff ffffffff ffffffff    ................
80700030: ffffffff ffffffff ffffffff ffffffff    ................
80700040: ffffffff ffffffff ffffffff ffffffff    ................
80700050: ffffffff ffffffff ffffffff ffffffff    ................


Anyone got any clues as the correct address?

Regards
--
Kieran

Liu, Yan wrote:
> I don't know which product you are using. But, there is a way to write uboot from uboot. Here is the sample command:
>
> tftp 0x80000000 u-boot.bin
> nand erase <starting_address_uboot_partition> 0x1C0000
> nandecc sw
> nand write.i 0x80000000 <starting_address_uboot_partition> 0x1C0000
>
> The <starting_address_uboot_partition> can be found in booting log. Typically, you will find the following part:
>
> 0x000000000000-0x000000080000 : "xloader-nand"
> 0x000000080000-0x000000240000 : "uboot-nand"
> 0x000000240000-0x000000280000 : "params-nand"
> 0x000000280000-0x000000780000 : "linux-nand"
> 0x000000780000-0x000020000000 : "jffs2-nand"
>
> In my case, I use 0x80000 as <starting_address_uboot_partition>.
>
> Hope this helps.
>
> Regards,
> Yan
>
> -----Original Message-----
> From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Kieran Bingham
> Sent: Friday, May 21, 2010 1:03 PM
> To: davinci-linux-open-source at linux.davincidsp.com
> Subject: Flashing uboot from Uboot
>
> Hi Guys,
>
> As I'm running linux, I can't easily switch to running Windows for CCS.
>
> I've been making changes to UBoot and testing them by setting the 
> TEXT_BASE at a different address in RAM, loading via TFTP, and calling 
> go $(loadaddr)
>
> Now I would like to write this uboot binary to flash, so I've recompiled 
> it with the original TEXT_BASE, but I can't figure out where I need to 
> flash it in the NAND.
>
> Is it possible to reflash uboot from within Uboot?
>
> --
> Regards
> Kieran
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>
>   


From spoulsen at css-design.com  Mon May 24 11:46:11 2010
From: spoulsen at css-design.com (Steve Poulsen)
Date: Mon, 24 May 2010 11:46:11 -0500
Subject: Flashing uboot from Uboot
In-Reply-To: <4BFAA311.9030608@gmail.com>
References: <4BF6BCB6.6070707@gmail.com>
	<A69FA2915331DC488A831521EAE36FE4016AFDE960@dlee06.ent.ti.com>
	<4BFAA311.9030608@gmail.com>
Message-ID: <4BFAAD53.10208@css-design.com>

On 05/24/2010 11:02 AM, Kieran Bingham wrote:
> Hi Guys,
>
> Thanks - and yes I'm prepared to use CCS if necesarry - but UBoot 
> upgrades will be much easier from a running system :)
>
> I'm on the DM365, but I can't determine the load address...
>
> My nand mappings are :
> [    2.250000] Creating 4 MTD partitions on "nand_davinci.0":
> [    2.260000] 0x00000000-0x00660000 : "bootloader"
> [    2.270000] 0x00660000-0x00680000 : "params"
> [    2.270000] 0x00680000-0x00a80000 : "kernel"
> [    2.280000] 0x00a80000-0x20000000 : "filesystem"
> And I've tried poking around the nand to look at where I might find 
> the UBoot source - but can't "find" it manually.
>
> setenv a 0x80000
> nand read.i 0x80700000 $(a) 0x1000; md 0x80700000
>
> 80700000: a1aced00 00000100 00000007 00000004    ................
> 80700010: 00000001 00000020 ffffffff ffffffff    .... ...........
> 80700020: ffffffff ffffffff ffffffff ffffffff    ................
> 80700030: ffffffff ffffffff ffffffff ffffffff    ................
> 80700040: ffffffff ffffffff ffffffff ffffffff    ................
> 80700050: ffffffff ffffffff ffffffff ffffffff    ................
>
>
> Anyone got any clues as the correct address?
>
> Regards
> -- 
> Kieran
>
> Liu, Yan wrote:
>> I don't know which product you are using. But, there is a way to 
>> write uboot from uboot. Here is the sample command:
>>
>> tftp 0x80000000 u-boot.bin
>> nand erase <starting_address_uboot_partition> 0x1C0000
>> nandecc sw
>> nand write.i 0x80000000 <starting_address_uboot_partition> 0x1C0000
>>
>> The <starting_address_uboot_partition> can be found in booting log. 
>> Typically, you will find the following part:
>>
>> 0x000000000000-0x000000080000 : "xloader-nand"
>> 0x000000080000-0x000000240000 : "uboot-nand"
>> 0x000000240000-0x000000280000 : "params-nand"
>> 0x000000280000-0x000000780000 : "linux-nand"
>> 0x000000780000-0x000020000000 : "jffs2-nand"
>>
>> In my case, I use 0x80000 as <starting_address_uboot_partition>.
>>
>> Hope this helps.
>>
>> Regards,
>> Yan
>>
>> -----Original Message-----
>> From: davinci-linux-open-source-bounces at linux.davincidsp.com 
>> [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On 
>> Behalf Of Kieran Bingham
>> Sent: Friday, May 21, 2010 1:03 PM
>> To: davinci-linux-open-source at linux.davincidsp.com
>> Subject: Flashing uboot from Uboot
>>
>> Hi Guys,
>>
>> As I'm running linux, I can't easily switch to running Windows for CCS.
>>
>> I've been making changes to UBoot and testing them by setting the 
>> TEXT_BASE at a different address in RAM, loading via TFTP, and 
>> calling go $(loadaddr)
>>
>> Now I would like to write this uboot binary to flash, so I've 
>> recompiled it with the original TEXT_BASE, but I can't figure out 
>> where I need to flash it in the NAND.
>>
>> Is it possible to reflash uboot from within Uboot?
>>
>> -- 
>> Regards
>> Kieran
>> _______________________________________________
>> Davinci-linux-open-source mailing list
>> Davinci-linux-open-source at linux.davincidsp.com
>> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>>
>
>

Kieran,

In the UBL source, I have bootloader.h which defines 
APP_DESC_START_BLOCK_NUM to be 8.  Block 8 of my NAND is supposed to 
have the start of U-boot.   Check your UBL source and you should be able 
to find the starting block.  Use U-boot's nand dump to view the nand 
without copying to RAM.  According to UBL, the data stored should 
contain the APP_BOOT structure.  You can examine it to make sure this is 
correct.

To be honest, I haven't done this in a long time, I generally have setup 
SD card booting or USB booting for reflashing boards.

My comment about CCS loading was only for emergency loading.  It is not 
desirable but sometimes necessary.

Steve



-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.


From khilman at deeprootsystems.com  Mon May 24 11:52:49 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 24 May 2010 09:52:49 -0700
Subject: [RFC 1/4] Davinci: mdio - separate out mdio controller code
In-Reply-To: <B85A65D85D7EB246BE421B3FB0FBB59301E70D2E44@dbde02.ent.ti.com>
	(Sekhar Nori's message of "Mon\, 24 May 2010 11\:46\:22 +0530")
References: <1273876947-30711-1-git-send-email-cyril@ti.com>
	<1273876947-30711-2-git-send-email-cyril@ti.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E6F97620@dbde02.ent.ti.com>
	<4BF29D04.4010500@ti.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E7045AD5@dbde02.ent.ti.com>
	<4BF3FE56.90303@ti.com>
	<B85A65D85D7EB246BE421B3FB0FBB59301E70D2E44@dbde02.ent.ti.com>
Message-ID: <87bpc58cny.fsf@deeprootsystems.com>

"Nori, Sekhar" <nsekhar at ti.com> writes:

> Hi Cyril,
>
> On Wed, May 19, 2010 at 20:35:58, Chemparathy, Cyril wrote:
>> Hi Sekhar,
>>
>> [...]
>> >>> Also, can you keep this as a platform variable (with
>> >>> a 2.2 MHz default)? The frequency depends on the board,
>> >>> and although most boards work at 2.2 MHz, not having it
>> >>> as a platform variable will make adding a board with a
>> >>> different frequency requirement difficult.
>> >>
>> >> I am not quite convinced that you'll have too many boards deviate from
>> >> the 2MHz ballpark.  That seems to be a nice and safe frequency that
>> >> works well across phys, socs, and boards.
>> >>
>> >> That said, if we see the need to override the bus frequency in future, I
>> >> am all for a patch at that time.  As it stands, I don't see the value in
>> >> adding platform data definitions for a capability that is not going to
>> >> be used at present.
>> >
>> > Okay, but why regress on existing functionality?
>>
>> I don't quite think that the prior existence of a "knob" is reason
>> enough to keep it around, considering that the knob is essentially
>> unused (below).
>
> AFAIR, some boards in mach-omap2 use this driver as well. Hope
> you searched them as well before concluding that it is unused.

Also, there are many, many boards out there that have not been
submitted upstream (and whose maintainers do not read this list.)
While that is a problem in and of itself, I do not want to break those
boards on the assumption that some board-specific knob is unused.

>> In short, we currently have a knob for frequency control, but we don't
>> use board-specific numbers from characterization data (if available).
>> That said, what good is the knob?  All that it does at present, is muddy
>> up the code with identical definitions on every board.
>
> You can decide to default to 2.2 MHz if there is no platform data
> that way there wouldn't be any additional code in any of the board
> files.

Agreed.  

Feel free to drop the setting in the board files if it is just using
the default.  That will help avoid duplicating the redundant code when
board files are copy-pasted to create new boards.

Kevin


From khilman at deeprootsystems.com  Mon May 24 11:54:31 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 24 May 2010 09:54:31 -0700
Subject: [RFC 2/4] Davinci: mdio - add clock lookups for mdio
In-Reply-To: <1273876947-30711-3-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Fri\, 14 May 2010 18\:42\:25 -0400")
References: <1273876947-30711-1-git-send-email-cyril@ti.com>
	<1273876947-30711-3-git-send-email-cyril@ti.com>
Message-ID: <874ohx8cl4.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> The standalone davinci mdio drivers acquires its own (possible separate)
> clock. On existing architectures where MDIO is built into the EMAC subsystem,
> the same underlying clock is used by both mdio and emac.
>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

The preferred method for this is to use clk_add_alias().

Kevin

> ---
>  arch/arm/mach-davinci/da830.c  |    1 +
>  arch/arm/mach-davinci/da850.c  |    1 +
>  arch/arm/mach-davinci/dm365.c  |    1 +
>  arch/arm/mach-davinci/dm644x.c |    1 +
>  arch/arm/mach-davinci/dm646x.c |    1 +
>  5 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
> index 3a7a96f..8fe0292 100644
> --- a/arch/arm/mach-davinci/da830.c
> +++ b/arch/arm/mach-davinci/da830.c
> @@ -416,6 +416,7 @@ static struct clk_lookup da830_clks[] = {
>  	CLK(NULL,		"aintc",	&aintc_clk),
>  	CLK(NULL,		"secu_mgr",	&secu_mgr_clk),
>  	CLK("davinci_emac.1",	NULL,		&emac_clk),
> +	CLK("davinci_mdio.0",	NULL,		&emac_clk),
>  	CLK(NULL,		"gpio",		&gpio_clk),
>  	CLK("i2c_davinci.2",	NULL,		&i2c1_clk),
>  	CLK(NULL,		"usb11",	&usb11_clk),
> diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
> index 6b8331b..5cb8a92 100644
> --- a/arch/arm/mach-davinci/da850.c
> +++ b/arch/arm/mach-davinci/da850.c
> @@ -373,6 +373,7 @@ static struct clk_lookup da850_clks[] = {
>  	CLK(NULL,		"arm",		&arm_clk),
>  	CLK(NULL,		"rmii",		&rmii_clk),
>  	CLK("davinci_emac.1",	NULL,		&emac_clk),
> +	CLK("davinci_mdio.0",	NULL,		&emac_clk),
>  	CLK("davinci-mcasp.0",	NULL,		&mcasp_clk),
>  	CLK("da8xx_lcdc.0",	NULL,		&lcdc_clk),
>  	CLK("davinci_mmc.0",	NULL,		&mmcsd_clk),
> diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
> index e5e3dce..a2c832f 100644
> --- a/arch/arm/mach-davinci/dm365.c
> +++ b/arch/arm/mach-davinci/dm365.c
> @@ -458,6 +458,7 @@ static struct clk_lookup dm365_clks[] = {
>  	CLK(NULL, "timer3", &timer3_clk),
>  	CLK(NULL, "usb", &usb_clk),
>  	CLK("davinci_emac.1", NULL, &emac_clk),
> +	CLK("davinci_mdio.0", NULL, &emac_clk),
>  	CLK("davinci_voicecodec", NULL, &voicecodec_clk),
>  	CLK("davinci-asp.0", NULL, &asp0_clk),
>  	CLK(NULL, "rto", &rto_clk),
> diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
> index 7ad1520..001b9a1 100644
> --- a/arch/arm/mach-davinci/dm644x.c
> +++ b/arch/arm/mach-davinci/dm644x.c
> @@ -300,6 +300,7 @@ static struct clk_lookup dm644x_clks[] = {
>  	CLK(NULL, "uart1", &uart1_clk),
>  	CLK(NULL, "uart2", &uart2_clk),
>  	CLK("davinci_emac.1", NULL, &emac_clk),
> +	CLK("davinci_mdio.0", NULL, &emac_clk),
>  	CLK("i2c_davinci.1", NULL, &i2c_clk),
>  	CLK("palm_bk3710", NULL, &ide_clk),
>  	CLK("davinci-asp", NULL, &asp_clk),
> diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
> index 9404565..60b7a8a 100644
> --- a/arch/arm/mach-davinci/dm646x.c
> +++ b/arch/arm/mach-davinci/dm646x.c
> @@ -343,6 +343,7 @@ static struct clk_lookup dm646x_clks[] = {
>  	CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
>  	CLK(NULL, "aemif", &aemif_clk),
>  	CLK("davinci_emac.1", NULL, &emac_clk),
> +	CLK("davinci_mdio.0", NULL, &emac_clk),
>  	CLK(NULL, "pwm0", &pwm0_clk),
>  	CLK(NULL, "pwm1", &pwm1_clk),
>  	CLK(NULL, "timer0", &timer0_clk),
> -- 
> 1.7.0.4
>
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source

From khilman at deeprootsystems.com  Mon May 24 12:08:14 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 24 May 2010 10:08:14 -0700
Subject: [PATCH 4/4] davinci: Fix transparency handling with dm365.
In-Reply-To: <4BF2A5A7.1060002@ti.com> (Cyril Chemparathy's message of "Tue\,
	18 May 2010 10\:35\:19 -0400")
References: <4BF28E20.3070701@nexvision.fr>
	<1274187385-10969-1-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<1274187385-10969-2-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<1274187385-10969-3-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<1274187385-10969-4-git-send-email-gilles.chanteperdrix@nexvision.fr>
	<4BF2A5A7.1060002@ti.com>
Message-ID: <87wrut6xdt.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> Hi,
>
> [...]
>> -		if (cpu_is_davinci_dm355()) {
>> +		if (cpu_is_davinci_dm355() || cpu_is_davinci_dm365()) {
>
> Why does this driver have cpu_is_ macros all over the place?

Because this driver has not yet been submitted for review. ;) I
believe it is only in the Arago tree at the moment.

> Isn't there a way to pass in the device capabilities via pdata?

Hopefully there is when it is posted.

Kevin

From khilman at deeprootsystems.com  Mon May 24 12:09:56 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 24 May 2010 10:09:56 -0700
Subject: [PATCH 0/4] Assorted davinci fixes.
In-Reply-To: <B85A65D85D7EB246BE421B3FB0FBB59301E7045B6E@dbde02.ent.ti.com>
	(Sekhar Nori's message of "Wed\, 19 May 2010 20\:19\:28 +0530")
References: <4BF28E20.3070701@nexvision.fr>
	<B85A65D85D7EB246BE421B3FB0FBB59301E7045B6E@dbde02.ent.ti.com>
Message-ID: <87pr0l6xaz.fsf@deeprootsystems.com>

"Nori, Sekhar" <nsekhar at ti.com> writes:

> Hi Gilles,
>
> On Tue, May 18, 2010 at 18:24:56, Gilles Chanteperdrix wrote:
>>
>> Hi,
>>
>> while experimenting with a davinci DM368, I had a few issues which the
>> following patches serie try and fix.
>>
>> Thanks in advance for your review.
>
> It seems these patches apply to the arago-project.org hosted davinci-staging
> tree and not to upstream v4l2 tree or Kevin's davinci tree.
>
> In such cases, please note this fact in the patch 0/N and/or below the ---
> in patch description so that folks interested in upstream development only
> can ignore these patches.
>
> DaVinci display is still not upstream yet. We are working on cleaning up the
> code and preparing the code for upstream submissions. Fixes like these will
> surely help the process. Thanks for the work!

In addition to Sekhar's comments, please include a more descriptive
changelog in your patches.  The subject typically summarizes _what_ is
being done, and the changelog should go into more detail to answer
_what_, but also answer _why_.

Thanks,

Kevin

From khilman at deeprootsystems.com  Mon May 24 12:22:34 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 24 May 2010 10:22:34 -0700
Subject: Inspiration needed to track down early kernel startup crash
In-Reply-To: <201005241010.42626.caglarakyuz@gmail.com> (Caglar Akyuz's
	message of "Mon\, 24 May 2010 10\:10\:42 +0300")
References: <70E876B0EA86DD4BAF101844BC814DFE08E03D096D@Cloud.RL.local>
	<201005241010.42626.caglarakyuz@gmail.com>
Message-ID: <87fx1h6wpx.fsf@deeprootsystems.com>

Caglar Akyuz <caglarakyuz at gmail.com> writes:

> On Monday 24 May 2010 09:50:19 am Jon Povey wrote:
>> Trying to get the git kernel running on our in-house board and have an
>>  unpleasant crash somewhere between kernel start and console output, with
>>  code jumping off to 0xffff000c.
>> 
>> This is using u-boot v2010.03 and kernel based on davinci master at
>>  5954dd1d2cab4b378e22256edbfe132bf4f82f22
>> 
>> Sympoms are; this is the last output I get on the console:
>> 
>>   Starting kernel ...
>> 
>>   Uncompressing Linux... done, booting the kernel.
>> 
>
> Maybe you can use earlyprintk for getting more info from the kernel. i.e. 
> earlyprintk=serial,ttyS0,115200 ...

Don't forget to enable early printk support in Kconfig either.

Another trick to get early printk output using JTAG:

Look for the address of __log_buf in System.map, then use your
debugger to dump that region in ASCII format.  This is the printk
buffer, so you can any printk output there, including the kernel crash
dump.

Kevin


From khilman at deeprootsystems.com  Mon May 24 12:27:07 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 24 May 2010 10:27:07 -0700
Subject: [PATCH 3/6] davinci: edma: clear events in edma_start()
In-Reply-To: <4BFA6A22.1000006@windriver.com> (stanley miao's message of "Mon\,
	24 May 2010 19\:59\:30 +0800")
References: <1268841163-5868-1-git-send-email-khilman@deeprootsystems.com>
	<1268841163-5868-4-git-send-email-khilman@deeprootsystems.com>
	<4BFA6A22.1000006@windriver.com>
Message-ID: <871vd16wic.fsf@deeprootsystems.com>

[please don't top post, moved your reply below original...]

"stanley.miao" <stanley.miao at windriver.com> writes:

> Kevin Hilman wrote:
>> From: Brian Niebuhr <bniebuhr3 at gmail.com>
>>
>> This patch fixes an issue where a DMA channel can erroneously process an
>> event generated by a previous transfer.  A failure case is where DMA is
>> being used for SPI transmit and receive channels on OMAP L138.  In this
>> case there is a single bit that controls all event generation from the
>> SPI peripheral.  Therefore it is possible that between when edma_stop()
>> has been called for the transmit channel on a previous transfer and
>> edma_start() is called for the transmit channel on a subsequent transfer,
>> that a transmit event has been generated.
>>
>> The fix is to clear events in edma_start().  This prevents false events
>> from being processed when events are enabled for that channel.
>>
>
> This patch causes that the sound can not work normally on OMAP_L138.
>

Can you describe "can not work normally"?  Does that mean simply does
not work, or works with pops & clicks etc.?

Just to clarify... how did you isolate it to this patch.

If you revert just this patch on current davinci git, do you have
working sound as you expect again?

Kevin

From khilman at deeprootsystems.com  Mon May 24 18:32:03 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 24 May 2010 16:32:03 -0700
Subject: [PATCH v7 0/6] Davinci: initial tnetv107x patch series
In-Reply-To: <1274201482-15994-1-git-send-email-cyril@ti.com> (Cyril
	Chemparathy's message of "Tue\, 18 May 2010 12\:51\:16 -0400")
References: <1274201482-15994-1-git-send-email-cyril@ti.com>
Message-ID: <87pr0kvpu4.fsf@deeprootsystems.com>

Cyril Chemparathy <cyril at ti.com> writes:

> This patch series adds support for TNETV107X - a Texas Instruments SOC that
> shares a number of common features with the Davinci architecture.
>
> This version includes two minor fixes over the v6 series posted earlier.
>
> Cyril Chemparathy (6):
>   Davinci: generalized debug macros
>   Davinci: tnetv107x decompresser uart definitions
>   Davinci: tnetv107x soc support
>   Davinci: tnetv107x initial gpio support
>   Davinci: tnetv107x evm board initial support
>   Davinci: tnetv107x default configuration

Thanks, applying (after dropping parens pointed out be Sergei.)

Will queue for 2.6.36.

Kevin

From e-eo at qq.com  Mon May 24 22:54:42 2010
From: e-eo at qq.com (e-eo)
Date: Tue, 25 May 2010 11:54:42 +0800
Subject: toolchain for davinci kernel
Message-ID: <201005251154403430059@qq.com>

hi,
Where I can download the toolchain to compile the laster davinci linux kernel?

Best Regards!

2010-05-25 



e-eo 
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From bjorn.forsman at gmail.com  Tue May 25 01:06:22 2010
From: bjorn.forsman at gmail.com (=?UTF-8?Q?Bj=C3=B8rn_Forsman?=)
Date: Tue, 25 May 2010 08:06:22 +0200
Subject: toolchain for davinci kernel
In-Reply-To: <201005251154403430059@qq.com>
References: <201005251154403430059@qq.com>
Message-ID: <AANLkTilOOGr_6a15cad-lQmxBaZzjzGrzMkLhXvd10N3@mail.gmail.com>

On 25 May 2010 05:54, e-eo <e-eo at qq.com> wrote:
> hi,
> Where I can download the toolchain to compile the laster davinci linux
> kernel?

CodeSourcery has prebuilt ARM toolchains that you can use:

http://www.codesourcery.com/sgpp/datasheet?target_arch=ARM&target_os=GNU%2FLinux

Best regards,
Bj?rn Forsman

From jp.francois at cynove.com  Tue May 25 01:55:33 2010
From: jp.francois at cynove.com (=?ISO-8859-1?Q?Jean-Philippe_Fran=E7ois?=)
Date: Tue, 25 May 2010 08:55:33 +0200
Subject: DM365 DavinciFB Colour Keying Transparency
In-Reply-To: <4BF69D01.7050706@nexvision.fr>
References: <4BF6987A.7030206@gmail.com> <4BF69D01.7050706@nexvision.fr>
Message-ID: <4BFB7465.6060604@cynove.com>

Gilles Chanteperdrix a ?crit :
> Kieran Bingham wrote:
>> Hi Guys,
>>
>> Does anyone know the correct methods to set up the OSD0 to be 
>> transparent based on a BLACK colour key ?
>>
>> We are trying to move to the Arago 2.6.32 kernel, and the methods we 
>> used on the 2.6.18 kernel no longer work - and everything I've tried 
>> hasn't worked either.
>>
>> So rather than continue guessing in the dark - I thought I'd ask you guys :)
> 
> See:
> http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-May/019022.html
> 
You also need to disable OSD1. If OSD1 is enabled, it is used to set transparency.
You can try above patch, and use the following kernel command line parameter :

video=davincifb:vid0=off:vid1=off:osd1=0x0x8


From rsanchezs at infoglobal.es  Tue May 25 02:26:08 2010
From: rsanchezs at infoglobal.es (=?utf-8?q?Ra=C3=BAl_S=C3=A1nchez_Siles?=)
Date: Tue, 25 May 2010 09:26:08 +0200
Subject: toolchain for davinci kernel
In-Reply-To: <201005251154403430059@qq.com>
References: <201005251154403430059@qq.com>
Message-ID: <201005250926.08728.rsanchezs@infoglobal.es>

  Hi:

El Martes, 25 de Mayo de 2010 05:54:42 e-eo escribi?:
> hi,
> Where I can download the toolchain to compile the laster davinci linux
> kernel?
> 
> Best Regards!
> 
> 
> e-eo

  There's a number of options, if you are in Debian you can also use the one I 
use: http://wiki.debian.org/EmdebianToolchain

  I'm not sure how usable testing or unstable versions are, but here stable 
(Lenny) works fine.

  Regards,

-- 
Ra?l S?nchez Siles

Departamento de Montaje

INFOGLOBAL, S. A.

* C/ Virgilio, 2. Ciudad de la Imagen.
28223 Pozuelo de Alarc?n (Madrid), Espa?a
* T: +34 91 506 40 00
* F: +34 91 506 40 01


From sshtylyov at mvista.com  Tue May 25 04:15:12 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Tue, 25 May 2010 13:15:12 +0400
Subject: [PATCH v7 0/6] Davinci: initial tnetv107x patch series
In-Reply-To: <87pr0kvpu4.fsf@deeprootsystems.com>
References: <1274201482-15994-1-git-send-email-cyril@ti.com>
	<87pr0kvpu4.fsf@deeprootsystems.com>
Message-ID: <4BFB9520.1000607@mvista.com>

Hello.

Kevin Hilman wrote:

>> This patch series adds support for TNETV107X - a Texas Instruments SOC that
>> shares a number of common features with the Davinci architecture.

>> This version includes two minor fixes over the v6 series posted earlier.

>> Cyril Chemparathy (6):
>>   Davinci: generalized debug macros
>>   Davinci: tnetv107x decompresser uart definitions
>>   Davinci: tnetv107x soc support
>>   Davinci: tnetv107x initial gpio support
>>   Davinci: tnetv107x evm board initial support
>>   Davinci: tnetv107x default configuration

> Thanks, applying (after dropping parens pointed out be Sergei.)

> Will queue for 2.6.36.

    But 2.6.35 merge window is still open, isn't it?

> Kevin

WBR, Sergei

From stanley.miao at windriver.com  Tue May 25 05:05:52 2010
From: stanley.miao at windriver.com (stanley.miao)
Date: Tue, 25 May 2010 18:05:52 +0800
Subject: [PATCH 3/6] davinci: edma: clear events in edma_start()
In-Reply-To: <871vd16wic.fsf@deeprootsystems.com>
References: <1268841163-5868-1-git-send-email-khilman@deeprootsystems.com>	<1268841163-5868-4-git-send-email-khilman@deeprootsystems.com>	<4BFA6A22.1000006@windriver.com>
	<871vd16wic.fsf@deeprootsystems.com>
Message-ID: <4BFBA100.4020805@windriver.com>

Kevin Hilman wrote:
> <snip>
>>>
>>>       
>> This patch causes that the sound can not work normally on OMAP_L138.
>>
>>     
>
> Can you describe "can not work normally"?  Does that mean simply does
> not work, or works with pops & clicks etc.?
>
> Just to clarify... how did you isolate it to this patch.
>
> If you revert just this patch on current davinci git, do you have
> working sound as you expect again?
>   
Below is the test result:

$/root> aplay audiodump.wav
Playing WAVE 'audiodump.wav' : Signed 16 bit Little Endian, Rate 44100 
Hz, Stereo
aplay: pcm_write:1269: write error: Input/output error
$/root>

After revert it, the audio works fine.

Hi, Brian,

For the SPI issue, try this patch:
----------------------------------------
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -359,8 +359,10 @@ static void davinci_spi_dma_rx_callback(unsigned 
lch, u16 ch_status, void *data)
 
        if (ch_status == DMA_COMPLETE)
                edma_stop(davinci_spi_dma->dma_rx_channel);
-       else
+       else {
+               edma_stop(davinci_spi_dma->dma_rx_channel);
                edma_clean_channel(davinci_spi_dma->dma_rx_channel);
+       }
 
        complete(&davinci_spi_dma->dma_rx_completion);
        /* We must disable the DMA RX request */
@@ -380,8 +382,10 @@ static void davinci_spi_dma_tx_callback(unsigned 
lch, u16 ch_status, void *data)
 
        if (ch_status == DMA_COMPLETE)
                edma_stop(davinci_spi_dma->dma_tx_channel);
-       else
+       else {
+               edma_stop(davinci_spi_dma->dma_tx_channel);
                edma_clean_channel(davinci_spi_dma->dma_tx_channel);
+       }
 
        complete(&davinci_spi_dma->dma_tx_completion);
-------------------------------------------------

Stanley.

> Kevin
>
>   


From stanley.miao at windriver.com  Tue May 25 05:08:20 2010
From: stanley.miao at windriver.com (Stanley.Miao)
Date: Tue, 25 May 2010 18:08:20 +0800
Subject: [PATCH] davinci: revert a edma patch
Message-ID: <1274782100-15210-1-git-send-email-stanley.miao@windriver.com>

Revert the commit bb17ef102b72e38557bfa829511e06c4bd3bb972.
It caused the sound can not work. Below is the test result: 

$/root> aplay audiodump.wav 
Playing WAVE 'audiodump.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo
aplay: pcm_write:1269: write error: Input/output error
$/root> 

After revert it, the audio works fine.

Signed-off-by: Stanley.Miao <stanley.miao at windriver.com>
---
 arch/arm/mach-davinci/dma.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 5313738..02d9398 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -1267,8 +1267,7 @@ int edma_start(unsigned channel)
 		/* EDMA channel with event association */
 		pr_debug("EDMA: ER%d %08x\n", j,
 			edma_shadow0_read_array(ctlr, SH_ER, j));
-		/* Clear any pending event or error */
-		edma_write_array(ctlr, EDMA_ECR, j, mask);
+		/* Clear any pending error */
 		edma_write_array(ctlr, EDMA_EMCR, j, mask);
 		/* Clear any SER */
 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
-- 
1.5.4.3


From raghu_ramaraj at mindtree.com  Tue May 25 07:26:59 2010
From: raghu_ramaraj at mindtree.com (Raghu Ramaraj)
Date: Tue, 25 May 2010 17:56:59 +0530
Subject: ARM9-PCI-WLAN Card
Message-ID: <DE1563FF5EF45A4794D1220EF0363CB411DD10C575@MTW02MSG02.mindtree.com>

Hi,
            We are trying to bring out Athoers WLAN card with DM6467T and we are facing some communication issue between host & device.

            Has anybody tested any TI Platform (ARM9) with any PCI based WLAN card?


Thanks & Regards,
Raghu Ramaraj


________________________________
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From Jon.Povey at racelogic.co.uk  Tue May 25 07:27:20 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Tue, 25 May 2010 13:27:20 +0100
Subject: Inspiration needed to track down early kernel startup crash
In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE08E03D096D@Cloud.RL.local>
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08E055C3FC@Cloud.RL.local>

Jon Povey wrote:
> Trying to get the git kernel running on our in-house board and have
> an unpleasant crash somewhere between kernel start and console
> output, with code jumping off to 0xffff000c.

In case my experience is useful to anyone else, it seems this is what was happening:

- RBL was enabling Timer0 and its FIQ - perhaps to flash an LED warning that I have no valid UBL on my NAND
- My JTAG connector lacks SRST so the board was not getting fully reset
- u-boot was loaded and run over JTAG (ignoring Timer0 + FIQ?)
- Linux starts, enables FIQ in boot_cpu_init() and crashes because it has not setup the interrupt vector tables yet.

I added a software disable and clear of interrupts over JTAG to my "reset" handler, and now I can boot.

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network



From swami.iyer at ti.com  Tue May 25 07:31:45 2010
From: swami.iyer at ti.com (Subbrathnam, Swaminathan)
Date: Tue, 25 May 2010 18:01:45 +0530
Subject: ARM9-PCI-WLAN Card
In-Reply-To: <DE1563FF5EF45A4794D1220EF0363CB411DD10C575@MTW02MSG02.mindtree.com>
References: <DE1563FF5EF45A4794D1220EF0363CB411DD10C575@MTW02MSG02.mindtree.com>
Message-ID: <FCCFB4CDC6E5564B9182F639FC356087030533753D@dbde02.ent.ti.com>

Raghu,
            Can you not consider over USB?  It is much simpler as compared to PCI.

Regards
swami

________________________________
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Raghu Ramaraj
Sent: Tuesday, May 25, 2010 5:57 PM
To: davinci-linux-open-source at linux.davincidsp.com
Subject: ARM9-PCI-WLAN Card

Hi,
            We are trying to bring out Athoers WLAN card with DM6467T and we are facing some communication issue between host & device.

            Has anybody tested any TI Platform (ARM9) with any PCI based WLAN card?


Thanks & Regards,
Raghu Ramaraj


________________________________
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From sudhakar.raj at ti.com  Tue May 25 08:28:19 2010
From: sudhakar.raj at ti.com (Sudhakar Rajashekhara)
Date: Tue, 25 May 2010 18:58:19 +0530
Subject: [PATCH 3/6] davinci: edma: clear events in edma_start()
In-Reply-To: <4BFBA100.4020805@windriver.com>
References: <1268841163-5868-1-git-send-email-khilman@deeprootsystems.com>	<1268841163-5868-4-git-send-email-khilman@deeprootsystems.com>	<4BFA6A22.1000006@windriver.com>	<871vd16wic.fsf@deeprootsystems.com>
	<4BFBA100.4020805@windriver.com>
Message-ID: <00f701cafc0e$23dedbf0$6b9c93d0$@raj@ti.com>

Hi Stanley,

On Tue, May 25, 2010 at 15:35:52, stanley.miao wrote:
> Kevin Hilman wrote:
> > <snip>
> >>>
> >>>       
> >> This patch causes that the sound can not work normally on OMAP_L138.
> >>
> >>     
> >
> > Can you describe "can not work normally"?  Does that mean simply does
> > not work, or works with pops & clicks etc.?
> >
> > Just to clarify... how did you isolate it to this patch.
> >
> > If you revert just this patch on current davinci git, do you have
> > working sound as you expect again?
> >   
> Below is the test result:
> 
> $/root> aplay audiodump.wav
> Playing WAVE 'audiodump.wav' : Signed 16 bit Little Endian, Rate 44100 
> Hz, Stereo
> aplay: pcm_write:1269: write error: Input/output error
> $/root>
> 
> After revert it, the audio works fine.
> 

This patch works fine on DM644x which has McBSP but breaks audio on OMAP L138
(as you had mentioned) which has McASP. Ideally McBSP/McASP should start after
EDMA is started. If not then this patch clears the EDMA event which is actually
set by McBSP/McASP. As this patch is working fine on DM644x, I think there is
some issue in the audio driver which needs to be debugged.

Regards,
Sudhakar



From khilman at deeprootsystems.com  Tue May 25 10:04:18 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Tue, 25 May 2010 08:04:18 -0700
Subject: [PATCH v7 0/6] Davinci: initial tnetv107x patch series
In-Reply-To: <4BFB9520.1000607@mvista.com> (Sergei Shtylyov's message of "Tue\,
	25 May 2010 13\:15\:12 +0400")
References: <1274201482-15994-1-git-send-email-cyril@ti.com>
	<87pr0kvpu4.fsf@deeprootsystems.com> <4BFB9520.1000607@mvista.com>
Message-ID: <87typwowel.fsf@deeprootsystems.com>

Sergei Shtylyov <sshtylyov at mvista.com> writes:

> Hello.
>
> Kevin Hilman wrote:
>
>>> This patch series adds support for TNETV107X - a Texas Instruments SOC that
>>> shares a number of common features with the Davinci architecture.
>
>>> This version includes two minor fixes over the v6 series posted earlier.
>
>>> Cyril Chemparathy (6):
>>>   Davinci: generalized debug macros
>>>   Davinci: tnetv107x decompresser uart definitions
>>>   Davinci: tnetv107x soc support
>>>   Davinci: tnetv107x initial gpio support
>>>   Davinci: tnetv107x evm board initial support
>>>   Davinci: tnetv107x default configuration
>
>> Thanks, applying (after dropping parens pointed out be Sergei.)
>
>> Will queue for 2.6.36.
>
>    But 2.6.35 merge window is still open, isn't it?
>

Yes, but not for davinci.  

If I haven't merged the code by the time the merge window opens, it will
not go into that merge window, but will have to wait for the next.

Kevin


From khilman at deeprootsystems.com  Tue May 25 10:30:28 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Tue, 25 May 2010 08:30:28 -0700
Subject: [PATCH 3/6] davinci: edma: clear events in edma_start()
In-Reply-To: <4BFBA100.4020805@windriver.com> (stanley miao's message of "Tue\,
	25 May 2010 18\:05\:52 +0800")
References: <1268841163-5868-1-git-send-email-khilman@deeprootsystems.com>
	<1268841163-5868-4-git-send-email-khilman@deeprootsystems.com>
	<4BFA6A22.1000006@windriver.com> <871vd16wic.fsf@deeprootsystems.com>
	<4BFBA100.4020805@windriver.com>
Message-ID: <87fx1gov6z.fsf@deeprootsystems.com>

"stanley.miao" <stanley.miao at windriver.com> writes:

> Kevin Hilman wrote:
>> <snip>
>>>>
>>>>       
>>> This patch causes that the sound can not work normally on OMAP_L138.
>>>
>>>     
>>
>> Can you describe "can not work normally"?  Does that mean simply does
>> not work, or works with pops & clicks etc.?
>>
>> Just to clarify... how did you isolate it to this patch.
>>
>> If you revert just this patch on current davinci git, do you have
>> working sound as you expect again?
>>   
> Below is the test result:
>
> $/root> aplay audiodump.wav
> Playing WAVE 'audiodump.wav' : Signed 16 bit Little Endian, Rate 44100
> Hz, Stereo
> aplay: pcm_write:1269: write error: Input/output error
> $/root>
>
> After revert it, the audio works fine.

Thanks for clarifying.

Kevin

From khilman at deeprootsystems.com  Tue May 25 10:31:00 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Tue, 25 May 2010 08:31:00 -0700
Subject: [PATCH 3/6] davinci: edma: clear events in edma_start()
In-Reply-To: <00f701cafc0e$23dedbf0$6b9c93d0$@raj@ti.com> (Sudhakar
	Rajashekhara's message of "Tue\, 25 May 2010 18\:58\:19 +0530")
References: <1268841163-5868-1-git-send-email-khilman@deeprootsystems.com>
	<1268841163-5868-4-git-send-email-khilman@deeprootsystems.com>
	<4BFA6A22.1000006@windriver.com> <871vd16wic.fsf@deeprootsystems.com>
	<4BFBA100.4020805@windriver.com>
	<00f701cafc0e$23dedbf0$6b9c93d0$@raj@ti.com>
Message-ID: <87d3wkov63.fsf@deeprootsystems.com>

"Sudhakar Rajashekhara" <sudhakar.raj at ti.com> writes:

> Hi Stanley,
>
> On Tue, May 25, 2010 at 15:35:52, stanley.miao wrote:
>> Kevin Hilman wrote:
>> > <snip>
>> >>>
>> >>>       
>> >> This patch causes that the sound can not work normally on OMAP_L138.
>> >>
>> >>     
>> >
>> > Can you describe "can not work normally"?  Does that mean simply does
>> > not work, or works with pops & clicks etc.?
>> >
>> > Just to clarify... how did you isolate it to this patch.
>> >
>> > If you revert just this patch on current davinci git, do you have
>> > working sound as you expect again?
>> >   
>> Below is the test result:
>> 
>> $/root> aplay audiodump.wav
>> Playing WAVE 'audiodump.wav' : Signed 16 bit Little Endian, Rate 44100 
>> Hz, Stereo
>> aplay: pcm_write:1269: write error: Input/output error
>> $/root>
>> 
>> After revert it, the audio works fine.
>> 
>
> This patch works fine on DM644x which has McBSP but breaks audio on OMAP L138
> (as you had mentioned) which has McASP. Ideally McBSP/McASP should start after
> EDMA is started. If not then this patch clears the EDMA event which is actually
> set by McBSP/McASP. As this patch is working fine on DM644x, I think there is
> some issue in the audio driver which needs to be debugged.

In the mean time, I think it makes sense to revert $SUBJECT patch in
davinci git until the audio driver is debugged.

Kevin

From kieranbingham at gmail.com  Wed May 26 03:44:06 2010
From: kieranbingham at gmail.com (Kieran Bingham)
Date: Wed, 26 May 2010 09:44:06 +0100
Subject: DM365 DavinciFB Colour Keying Transparency
In-Reply-To: <4BFB7465.6060604@cynove.com>
References: <4BF6987A.7030206@gmail.com> <4BF69D01.7050706@nexvision.fr>
	<4BFB7465.6060604@cynove.com>
Message-ID: <4BFCDF56.5020907@gmail.com>

Thanks Guys,

We've got it working now :)

--
Regards
Kieran Bingham

Jean-Philippe Fran?ois wrote:
> Gilles Chanteperdrix a ?crit :
>> Kieran Bingham wrote:
>>> Hi Guys,
>>>
>>> Does anyone know the correct methods to set up the OSD0 to be 
>>> transparent based on a BLACK colour key ?
>>>
>>> We are trying to move to the Arago 2.6.32 kernel, and the methods we 
>>> used on the 2.6.18 kernel no longer work - and everything I've tried 
>>> hasn't worked either.
>>>
>>> So rather than continue guessing in the dark - I thought I'd ask you 
>>> guys :)
>>
>> See:
>> http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-May/019022.html 
>>
>>
> You also need to disable OSD1. If OSD1 is enabled, it is used to set 
> transparency.
> You can try above patch, and use the following kernel command line 
> parameter :
>
> video=davincifb:vid0=off:vid1=off:osd1=0x0x8
>
>


From thomas at corelatus.se  Wed May 26 08:34:40 2010
From: thomas at corelatus.se (Thomas Lange)
Date: Wed, 26 May 2010 15:34:40 +0200
Subject: mmap broken on DM644x?
Message-ID: <4BFD2370.9070402@corelatus.se>

Short version:
mmap does not work for me. I don't think data cache is flushed
before and after user space process runs which makes kernel and
user space see different data due to dirty cache lines.

Long version:
I could not get mmap to work properly on my davinci board.
I have narrowed the problem down to a simple test case that
fails every time on my EVM6446 board.

Test code attached along with console test logs.
I would be happy to get confirmation that I have implemented
the mmap driver correctly and that the problem really is with
the kernel itself.

Test description
----------------
1) Kernel module sets a variable in mmap:ed structure.
2) Module awakens user space process.
3) User space sees the _old_ data in mmap:ed structure.
4) User space calls a system function (syslog).
5) Now user space see the updated data.

My interpretation is that in 3), the kernel cache line is still dirty
and has not been flushed. User space uses a different cache line and
does not see the dirty data.

The system call in 4) makes the kernel cache line be flushed.
Thus, user space now see the updated data.

Test rig
--------
Kernel: v2.6.34-davinci1

Hardware: DVEVM6446

Bootloader: U-Boot 2010.03

Compiler: gcc version 4.2.2 (ELDK 4.2)

Rootfs: ELDK 4.2 (except busybox)

/Thomas
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From raghu_ramaraj at mindtree.com  Wed May 26 23:19:20 2010
From: raghu_ramaraj at mindtree.com (Raghu Ramaraj)
Date: Thu, 27 May 2010 09:49:20 +0530
Subject: ARM9-PCI-WLAN Card
In-Reply-To: <FCCFB4CDC6E5564B9182F639FC356087030533753D@dbde02.ent.ti.com>
References: <DE1563FF5EF45A4794D1220EF0363CB411DD10C575@MTW02MSG02.mindtree.com>
	<FCCFB4CDC6E5564B9182F639FC356087030533753D@dbde02.ent.ti.com>
Message-ID: <DE1563FF5EF45A4794D1220EF0363CB411DD395C71@MTW02MSG02.mindtree.com>

Hi Swami,
             Have you tested any USB-WLAN Card with DM6467T?

Could please give us the details of the Card & data rate of the card?



Thanks & Regards,
Raghu Ramaraj

________________________________
From: Subbrathnam, Swaminathan [mailto:swami.iyer at ti.com]
Sent: Tuesday, May 25, 2010 6:02 PM
To: Raghu Ramaraj; davinci-linux-open-source at linux.davincidsp.com
Subject: RE: ARM9-PCI-WLAN Card

Raghu,
            Can you not consider over USB?  It is much simpler as compared to PCI.

Regards
swami

________________________________
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Raghu Ramaraj
Sent: Tuesday, May 25, 2010 5:57 PM
To: davinci-linux-open-source at linux.davincidsp.com
Subject: ARM9-PCI-WLAN Card

Hi,
            We are trying to bring out Athoers WLAN card with DM6467T and we are facing some communication issue between host & device.

            Has anybody tested any TI Platform (ARM9) with any PCI based WLAN card?


Thanks & Regards,
Raghu Ramaraj


________________________________
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From e-eo at qq.com  Wed May 26 23:40:25 2010
From: e-eo at qq.com (=?ISO-8859-1?B?dGFjbw==?=)
Date: Thu, 27 May 2010 12:40:25 +0800
Subject: ARM9-PCI-WLAN Card
Message-ID: <tencent_203B3E5D0B9B77807C07AB54@qq.com>

now I am working on zd1211b , but there are some things wrong, I don't know how to fix it.
 
 
------------------ Original ------------------
From:  "Raghu Ramaraj"<raghu_ramaraj at mindtree.com>;
Date:  Thu, May 27, 2010 12:49 PM
To:  "Subbrathnam, Swaminathan"<swami.iyer at ti.com>; "davinci-linux-open-source at linux.davincidsp.com"<davinci-linux-open-source at linux.davincidsp.com>; 

Subject:  RE: ARM9-PCI-WLAN Card

 
    Hi Swami,
    Have you tested any USB-WLAN Card with DM6467T? 
Could please give us the details of the Card & data rate of the card?
Thanks & Regards,
Raghu Ramaraj
From: Subbrathnam, Swaminathan [mailto:swami.iyer at ti.com] 
 Sent: Tuesday, May 25, 2010 6:02 PM
 To: RaghuRamaraj; davinci-linux-open-source at linux.davincidsp.com
 Subject: RE: ARM9-PCI-WLAN Card
Raghu,
Can you not consider over USB?  It is much simpler as compared to PCI.
Regards
swami
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of RaghuRamaraj
 Sent: Tuesday, May 25, 2010 5:57 PM
 To: davinci-linux-open-source at linux.davincidsp.com
 Subject: ARM9-PCI-WLAN Card
Hi,
We are trying to bring out Athoers WLAN card with DM6467T and we are facing some communication issue between host & device.
Has anybody tested any TI Platform (ARM9) with any PCI based WLAN card?
Thanks & Regards,
Raghu Ramaraj
http://www.mindtree.com/email/disclaimer.html
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From swami.iyer at ti.com  Thu May 27 00:21:09 2010
From: swami.iyer at ti.com (Subbrathnam, Swaminathan)
Date: Thu, 27 May 2010 10:51:09 +0530
Subject: ARM9-PCI-WLAN Card
In-Reply-To: <DE1563FF5EF45A4794D1220EF0363CB411DD395C71@MTW02MSG02.mindtree.com>
References: <DE1563FF5EF45A4794D1220EF0363CB411DD10C575@MTW02MSG02.mindtree.com>
	<FCCFB4CDC6E5564B9182F639FC356087030533753D@dbde02.ent.ti.com>
	<DE1563FF5EF45A4794D1220EF0363CB411DD395C71@MTW02MSG02.mindtree.com>
Message-ID: <FCCFB4CDC6E5564B9182F639FC35608703053F8F41@dbde02.ent.ti.com>

Raghu,
            Any commercially available usbwifi card that has Linux drivers would work just fine on DM6467T.

Regards
swami

________________________________
From: Raghu Ramaraj [mailto:raghu_ramaraj at mindtree.com]
Sent: Thursday, May 27, 2010 9:49 AM
To: Subbrathnam, Swaminathan; davinci-linux-open-source at linux.davincidsp.com
Subject: RE: ARM9-PCI-WLAN Card

Hi Swami,
             Have you tested any USB-WLAN Card with DM6467T?

Could please give us the details of the Card & data rate of the card?



Thanks & Regards,
Raghu Ramaraj

________________________________
From: Subbrathnam, Swaminathan [mailto:swami.iyer at ti.com]
Sent: Tuesday, May 25, 2010 6:02 PM
To: Raghu Ramaraj; davinci-linux-open-source at linux.davincidsp.com
Subject: RE: ARM9-PCI-WLAN Card

Raghu,
            Can you not consider over USB?  It is much simpler as compared to PCI.

Regards
swami

________________________________
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Raghu Ramaraj
Sent: Tuesday, May 25, 2010 5:57 PM
To: davinci-linux-open-source at linux.davincidsp.com
Subject: ARM9-PCI-WLAN Card

Hi,
            We are trying to bring out Athoers WLAN card with DM6467T and we are facing some communication issue between host & device.

            Has anybody tested any TI Platform (ARM9) with any PCI based WLAN card?


Thanks & Regards,
Raghu Ramaraj


________________________________
http://www.mindtree.com/email/disclaimer.html
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From Jon.Povey at racelogic.co.uk  Thu May 27 02:43:03 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Thu, 27 May 2010 08:43:03 +0100
Subject: MUSB Kconfig bugs?
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08E055C6B1@Cloud.RL.local>

I am seeing some weirdness trying to configure MUSB for Gadget mode; I deleted all USB lines from .config and ran "make oldconfig" hoping to be prompted for things. Perhaps that approach is wrong?

Such odd things happened as getting the peripheral controller automatically selected, and not having an option for the Inventra controller; a snippet from "make oldconfig" which automatically selected 1:

USB Peripheral Controller
 > 1. Renesas R8A66597 USB Peripheral Controller (USB_GADGET_R8A66597) (NEW)
   2. Renesas M66592 USB Peripheral Controller (USB_GADGET_M66592) (NEW)
 choice[1-2?]: 1

I had to make two passes and do a few hand-edits to sort things out. Things worked fine once I did.

One thing that jumps out at me is that there are
  config USB_GADGET_MUSB_HDRC
lines in both usb/gadget/Kconfig and usb/musb/Kconfig, ie the same variable in two places. I'm not a Kconfig expert but that seems wrong.

The dependencies seem a bit mixed up and maybe a little circular, I don't know how kconfig resolves such things but USB_MUSB_PERIPHERAL in musb/Kconfig depends on USB_GADGET which doesn't appear until gadget/Kconfig which is sourced later.

I am not quite sure what is wrong or how to fix it, but thought it was worth bringing up.

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network



From sshtylyov at ru.mvista.com  Thu May 27 07:37:31 2010
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Thu, 27 May 2010 16:37:31 +0400
Subject: [PATCH v2] musb_core: make disconnect and suspend interrupts work
	again
Message-ID: <201005271637.32161.sshtylyov@ru.mvista.com>

Commit 1c25fda4a09e8229800979986ef399401053b46e (usb: musb: handle irqs in the
order dictated by programming guide) forgot to get rid of the old 'STAGE0_MASK'
filter for calling musb_stage0_irq(), so now disconnect and suspend interrupts
are effectively ignored...

Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
Cc: stable at kernel.org

---
The patch is against the recent Linus' tree.
Should be applied to 2.6.34.y as well...

Changes since previous version:
- corrected typos in the description...

 drivers/usb/musb/musb_core.c |    6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

Index: linux-2.6/drivers/usb/musb/musb_core.c
===================================================================
--- linux-2.6.orig/drivers/usb/musb/musb_core.c
+++ linux-2.6/drivers/usb/musb/musb_core.c
@@ -371,10 +371,6 @@ void musb_hnp_stop(struct musb *musb)
  * @param power
  */
 
-#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
-		| MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
-		| MUSB_INTR_RESET)
-
 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
 				u8 devctl, u8 power)
 {
@@ -1519,7 +1515,7 @@ irqreturn_t musb_interrupt(struct musb *
 	/* the core can interrupt us for multiple reasons; docs have
 	 * a generic interrupt flowchart to follow
 	 */
-	if (musb->int_usb & STAGE0_MASK)
+	if (musb->int_usb)
 		retval |= musb_stage0_irq(musb, musb->int_usb,
 				devctl, power);
 

From gadiyar at ti.com  Thu May 27 01:17:09 2010
From: gadiyar at ti.com (Gadiyar, Anand)
Date: Thu, 27 May 2010 11:47:09 +0530
Subject: [PATCH resend] musb_core: make disconnect and suspend
	interrupts work again
In-Reply-To: <201005202133.12497.sshtylyov@ru.mvista.com>
References: <201005202133.12497.sshtylyov@ru.mvista.com>
Message-ID: <5A47E75E594F054BAF48C5E4FC4B92AB03230B1C25@dbde02.ent.ti.com>

Sergei Shtylyov wrote:
> Sent: Thursday, May 20, 2010 11:03 PM
> To: linux-usb at vger.kernel.org; felipe.balbi at nokia.com
> Cc: gregkh at suse.de; davinci-linux-open-source at linux.davincidsp.com; stable at kernel.org
> Subject: [PATCH resend] musb_core: make disconnect and suspend interrupts work again
> 
> Commit 1c25fda4a09e8229800979986ef399401053b46e (usb: musb: handle irqs in the
> order dictated by programming guide) forgot to get rid of the old 'STAGE0_MASK'
> filter for calling musb_stage_orq(), so now disconnect and suspend interrupts
> are effectively ignored...
> 
> Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
> Cc: stable at kernel.org
> 

Thanks for fixing this. I see the behavior with current mainline
on my OMAP3 boards.

Acked-by: Anand Gadiyar <gadiyar at ti.com>


> ---
> The patch is against the recent Linus' tree.
> Should be applied to 2.6.34.y as well...
> Resending with the correct subject. :-/
> 
>  drivers/usb/musb/musb_core.c |    6 +-----
>  1 file changed, 1 insertion(+), 5 deletions(-)
> 
> Index: linux-2.6/drivers/usb/musb/musb_core.c
> ===================================================================
> --- linux-2.6.orig/drivers/usb/musb/musb_core.c
> +++ linux-2.6/drivers/usb/musb/musb_core.c
> @@ -371,10 +371,6 @@ void musb_hnp_stop(struct musb *musb)
>   * @param power
>   */
>  
> -#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
> -		| MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
> -		| MUSB_INTR_RESET)
> -
>  static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
>  				u8 devctl, u8 power)
>  {
> @@ -1519,7 +1515,7 @@ irqreturn_t musb_interrupt(struct musb *
>  	/* the core can interrupt us for multiple reasons; docs have
>  	 * a generic interrupt flowchart to follow
>  	 */
> -	if (musb->int_usb & STAGE0_MASK)
> +	if (musb->int_usb)
>  		retval |= musb_stage0_irq(musb, musb->int_usb,
>  				devctl, power);
>  

From Jon.Povey at racelogic.co.uk  Fri May 28 06:00:26 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Fri, 28 May 2010 12:00:26 +0100
Subject: The state of MUSB OTG + CPPI DMA..?
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08E055C93A@Cloud.RL.local>

Hi all,

I'm playing around trying to get MUSB OTG working on DM355, for mass storage (memory sticks) and gadget serial. We had similar functionality in MV 2.6.10 via some hacks involving a GPIO to monitor USB_ID, and a script to reload USB driver modules.. but it would be nice to do it Right(tm) or at least Better.

OTG sort-of works for me after playing with it today, but having some problems with it not finding memory sticks in host mode after connecting as a gadget, and a few weird error messages.

Would anyone like to comment on the status of MUSB OTG (for DM355) in the current git version? And/or on the TI CPPI DMA option?

I note that OTG depends on EXPERIMENTAL and the CPPI driver has a lot of discouraging comments and REVISITs throughout it.

Thought it was worth posting in case someone wanted to say "OTG and CPPI are both (buggy|slow) for DaVinci, don't try and use them", that would save me some time and frustration and I can reimplement the old hacks.

Thanks,

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network



From swami.iyer at ti.com  Fri May 28 06:45:02 2010
From: swami.iyer at ti.com (Subbrathnam, Swaminathan)
Date: Fri, 28 May 2010 17:15:02 +0530
Subject: The state of MUSB OTG + CPPI DMA..?
In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE08E055C93A@Cloud.RL.local>
References: <70E876B0EA86DD4BAF101844BC814DFE08E055C93A@Cloud.RL.local>
Message-ID: <FCCFB4CDC6E5564B9182F639FC35608703053F9709@dbde02.ent.ti.com>

Jon,
	Pl. refer to the Aarago GIT tree for DaVinci.
Regards
swami

> -----Original Message-----
> From: davinci-linux-open-source-bounces at linux.davincidsp.com
> [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf
> Of Jon Povey
> Sent: Friday, May 28, 2010 4:30 PM
> To: davinci-linux-open-source at linux.davincidsp.com
> Subject: The state of MUSB OTG + CPPI DMA..?
> 
> Hi all,
> 
> I'm playing around trying to get MUSB OTG working on DM355, for mass
> storage (memory sticks) and gadget serial. We had similar functionality in
> MV 2.6.10 via some hacks involving a GPIO to monitor USB_ID, and a script
> to reload USB driver modules.. but it would be nice to do it Right(tm) or
> at least Better.
> 
> OTG sort-of works for me after playing with it today, but having some
> problems with it not finding memory sticks in host mode after connecting
> as a gadget, and a few weird error messages.
> 
> Would anyone like to comment on the status of MUSB OTG (for DM355) in the
> current git version? And/or on the TI CPPI DMA option?
> 
> I note that OTG depends on EXPERIMENTAL and the CPPI driver has a lot of
> discouraging comments and REVISITs throughout it.
> 
> Thought it was worth posting in case someone wanted to say "OTG and CPPI
> are both (buggy|slow) for DaVinci, don't try and use them", that would
> save me some time and frustration and I can reimplement the old hacks.
> 
> Thanks,
> 
> --
> Jon Povey
> jon.povey at racelogic.co.uk
> 
> Racelogic is a limited company registered in England. Registered number
> 2743719 .
> Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham,
> Bucks, MK18 1TB .
> 
> The information contained in this electronic mail transmission is intended
> by Racelogic Ltd for the use of the named individual or entity to which it
> is directed and may contain information that is confidential or
> privileged. If you have received this electronic mail transmission in
> error, please delete it from your system without copying or forwarding it,
> and notify the sender of the error by reply email so that the sender's
> address records can be corrected. The views expressed by the sender of
> this communication do not necessarily represent those of Racelogic Ltd.
> Please note that Racelogic reserves the right to monitor e-mail
> communications passing through its network
> 
> 
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source

From mcuos.com at gmail.com  Fri May 28 00:26:55 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Fri, 28 May 2010 13:26:55 +0800
Subject: [PATCH] ALSA/davinci: Use the resource_size , __devinit and __devexit.
Message-ID: <4BFF541F.2080209@gmail.com>

Dear all,

Use the resource_size function instead of manually calculating the
resource size.  This reduces the chance of introducing off-by-one
errors.

In addition, to use __devinit and __devexit is good too.

Signed-off-by:Wan ZongShun<mcuos.com at gmail.com>

>From 6e492675606a92bcf9e1719c37219dfc5d11e6ca Mon Sep 17 00:00:00 2001
From: zswan <zswan at zswan-marvell.(none)>
Date: Fri, 28 May 2010 13:18:40 +0800
Subject: [PATCH 5/5] fix davinci resource size

---
 sound/soc/davinci/davinci-i2s.c   |   12 ++++++------
 sound/soc/davinci/davinci-mcasp.c |   12 ++++++------
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index adadcd3..763ba73 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -521,7 +521,7 @@ struct snd_soc_dai davinci_i2s_dai = {
 };
 EXPORT_SYMBOL_GPL(davinci_i2s_dai);

-static int davinci_i2s_probe(struct platform_device *pdev)
+static int __devinit davinci_i2s_probe(struct platform_device *pdev)
 {
 	struct snd_platform_data *pdata = pdev->dev.platform_data;
 	struct davinci_mcbsp_dev *dev;
@@ -534,7 +534,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}

-	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
+	ioarea = request_mem_region(mem->start, resource_size(mem),
 				    pdev->name);
 	if (!ioarea) {
 		dev_err(&pdev->dev, "McBSP region already claimed\n");
@@ -597,12 +597,12 @@ static int davinci_i2s_probe(struct platform_device *pdev)
 err_free_mem:
 	kfree(dev);
 err_release_region:
-	release_mem_region(mem->start, (mem->end - mem->start) + 1);
+	release_mem_region(mem->start, resource_size(mem));

 	return ret;
 }

-static int davinci_i2s_remove(struct platform_device *pdev)
+static int __devexit davinci_i2s_remove(struct platform_device *pdev)
 {
 	struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data;
 	struct resource *mem;
@@ -613,14 +613,14 @@ static int davinci_i2s_remove(struct platform_device *pdev)
 	dev->clk = NULL;
 	kfree(dev);
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	release_mem_region(mem->start, (mem->end - mem->start) + 1);
+	release_mem_region(mem->start, resource_size(mem));

 	return 0;
 }

 static struct platform_driver davinci_mcbsp_driver = {
 	.probe		= davinci_i2s_probe,
-	.remove		= davinci_i2s_remove,
+	.remove		= __devexit_p(davinci_i2s_remove),
 	.driver		= {
 		.name	= "davinci-asp",
 		.owner	= THIS_MODULE,
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index 79f0f4a..bd328d6 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -844,7 +844,7 @@ struct snd_soc_dai davinci_mcasp_dai[] = {
 };
 EXPORT_SYMBOL_GPL(davinci_mcasp_dai);

-static int davinci_mcasp_probe(struct platform_device *pdev)
+static int __devinit davinci_mcasp_probe(struct platform_device *pdev)
 {
 	struct davinci_pcm_dma_params *dma_data;
 	struct resource *mem, *ioarea, *res;
@@ -864,7 +864,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
 	}

 	ioarea = request_mem_region(mem->start,
-			(mem->end - mem->start) + 1, pdev->name);
+			resource_size(mem), pdev->name);
 	if (!ioarea) {
 		dev_err(&pdev->dev, "Audio region already claimed\n");
 		ret = -EBUSY;
@@ -928,14 +928,14 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
 	return 0;

 err_release_region:
-	release_mem_region(mem->start, (mem->end - mem->start) + 1);
+	release_mem_region(mem->start, resource_size(mem));
 err_release_data:
 	kfree(dev);

 	return ret;
 }

-static int davinci_mcasp_remove(struct platform_device *pdev)
+static int __devexit davinci_mcasp_remove(struct platform_device *pdev)
 {
 	struct snd_platform_data *pdata = pdev->dev.platform_data;
 	struct davinci_audio_dev *dev;
@@ -948,7 +948,7 @@ static int davinci_mcasp_remove(struct platform_device *pdev)
 	dev->clk = NULL;

 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	release_mem_region(mem->start, (mem->end - mem->start) + 1);
+	release_mem_region(mem->start, resource_size(mem));

 	kfree(dev);

@@ -957,7 +957,7 @@ static int davinci_mcasp_remove(struct platform_device *pdev)

 static struct platform_driver davinci_mcasp_driver = {
 	.probe		= davinci_mcasp_probe,
-	.remove		= davinci_mcasp_remove,
+	.remove		= __devexit_p(davinci_mcasp_remove),
 	.driver		= {
 		.name	= "davinci-mcasp",
 		.owner	= THIS_MODULE,
-- 
1.6.3.3

From sshtylyov at mvista.com  Fri May 28 08:33:15 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 28 May 2010 17:33:15 +0400
Subject: [PATCH] ALSA/davinci: Use the resource_size ,
	__devinit and __devexit.
In-Reply-To: <4BFF541F.2080209@gmail.com>
References: <4BFF541F.2080209@gmail.com>
Message-ID: <4BFFC61B.7050402@mvista.com>

Hello.

Wan ZongShun wrote:

> Dear all,

> Use the resource_size function instead of manually calculating the
> resource size.  This reduces the chance of introducing off-by-one
> errors.

> In addition, to use __devinit and __devexit is good too.

    "Good" isn't a good justification I think.
    Also, this just asks to be put into two patches instead of one as 
the patch does two completely different things.

> Signed-off-by:Wan ZongShun<mcuos.com at gmail.com>

WBR, Sergei

From michael.williamson at criticallink.com  Fri May 28 08:46:24 2010
From: michael.williamson at criticallink.com (Mike Williamson)
Date: Fri, 28 May 2010 09:46:24 -0400
Subject: CMEM module build with recent kernel drop.
Message-ID: <AANLkTimHfwL3hyxYXAolSgQtPT1gAf2HU77wQUMbwu9D@mail.gmail.com>

Not sure if this is the right place for this...

It looks like the latest version of the linux utilities (specifically CMEM
for the OMAP-L138) no longer build with kernel Revs >= 2.6.34.? This
is due to the change in the dma-api (e.g., the dmac_inv_range and
clean functions have gone away).? I tried to replace the dmac_* calls
with dmac_map_area as suggested in another thread I stumbled upon,
but the module failed to load as the underlying __glue'd symbols
(arm926_dma_map_area) are not exported.

Has anyone else run into this?  Am I missing something?  My
understanding is CMEM is required in order to use DSPLink.
Is this not the case?

I'm trying to build linuxutils_2.25.02.08 from TI.  I'm tempted to simply
export the needed symbols, but that sort of flies in the face of the
new DMA-API architecture.  Is there a patch to CMEM out there?

Thanks for any insight.

-Mike

--
Michael Williamson
315-425-4045x230
www.criticallink.com

From sshtylyov at mvista.com  Fri May 28 08:49:10 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 28 May 2010 17:49:10 +0400
Subject: The state of MUSB OTG + CPPI DMA..?
In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE08E055C93A@Cloud.RL.local>
References: <70E876B0EA86DD4BAF101844BC814DFE08E055C93A@Cloud.RL.local>
Message-ID: <4BFFC9D6.5040803@mvista.com>

Hello.

Jon Povey wrote:

> Hi all,

> OTG sort-of works for me after playing with it today,

    You're lucky. :-)
    Last I tried, I couldn't get a USB stick recognized in OTG mode on 
DA830 EVM.

> but having some problems with it not finding memory sticks in host mode after connecting as a gadget,

    IIRC, that should be cured by adding musb_platfrom_try_idle() to 
drivers/usb/musb/davinci.c. I'm not sure why it lacks this function, 
while it's been proven that DA830 needs it. You can try copying the code 
from omap2430.c (you'll also have to modify the #ifdef'ery around the 
declaration in musb_core.h). My memory may be wrong though...

> and a few weird error messages.

    Like?

> Would anyone like to comment on the status of MUSB OTG (for DM355) in the current git version?

    Haven't tried...

> And/or on the TI CPPI DMA option?

    Should basically work.

> I note that OTG depends on EXPERIMENTAL and the CPPI driver has a lot of discouraging comments and REVISITs throughout it.

    Well, the whole MUSB driver has a lot of REVISITs. :-)

> Thanks,

WBR, Sergei


From david-b at pacbell.net  Fri May 28 10:16:01 2010
From: david-b at pacbell.net (David Brownell)
Date: Fri, 28 May 2010 08:16:01 -0700 (PDT)
Subject: The state of MUSB OTG + CPPI DMA..?
In-Reply-To: <4BFFC9D6.5040803@mvista.com>
Message-ID: <850744.20234.qm@web180315.mail.gq1.yahoo.com>

--- On Fri, 5/28/10, Sergei Shtylyov <sshtylyov at mvista.com> wrote:


> 
> > Would anyone like to comment on the status of MUSB OTG
> (for DM355) in the current git version?
> 
> ???Haven't tried...

As of something like 18 months ago, two key mechanisms
mostly worked when I tested against (a) OMAP3, and
(b) the fullspeed OTG tester.  The two mechanisms were

  (i) cable based role switch:  ID pin sensing, etc,
      during link setup.  (This was working before, but
I found a few bugs to fix.)

  (ii) basic HNP behavior, although some of the timings
      were out of spec, and some other minor non-compliance
      situations existed too.

ISTR that SRP worked in some cases too, but that was rather
awkward to test with the current PM framework.

Haven't tried recently.  My box that had the fullspeed
OTG tester died (sigh), so I'll not be able to retest that
any time soon.


Those code paths were kind of fragile, so it would not
surprise me to learn that someone patched something and
(accidentally) broke some of them.


> > And/or on the TI CPPI DMA option?
> 
> ???Should basically work...

.. Within limits of its design flaws, ISTR it was more or
less behaving.  Read the comments; "RX woes" explains
some of how the original design was USB-antagonistic,
TX was less so.  Later CPPI (4.1) addressed at least
some of the issues.  I never trusted the code to abort
transactions (TI never documented how to do that stuff
so that code was always iffy).

Since I last touched that code, I believe various folk
have not just worked on it, but have successfully made
it work better (yay!).  Fixed corner cases and patched
over undocumented bhaviors, and so on.


> > I note that OTG depends on EXPERIMENTAL and the CPPI
> driver has a lot of discouraging comments and REVISITs
> throughout it.
> 
> ???Well, the whole MUSB driver has a lot of
> REVISITs. :-)

Coming from odd hardware design artifacts, both from
Mentor (the "M" in MUSB) and from how various teams
at TI integrated that IP with DMA.

- Dave

> > Thanks,
> 
> WBR, Sergei
> 
> ______________________________________________


From cyril at ti.com  Fri May 28 14:24:43 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 28 May 2010 15:24:43 -0400
Subject: [RFC 0/2] Davinci: emac cpdma separation series
Message-ID: <1275074685-10614-1-git-send-email-cyril@ti.com>

In addition to being embedded into the EMAC controller, the CPDMA hardware
block is used in TI's CPSW switch controller.  Fortunately, the programming
interface to this hardware block remains somewhat consistent across these
devices.

This series contains a new reusable cpdma implementation, as well as
corresponding changes to plug unto the current emac driver.

This code has been very briefly tested on DM365.  Performance and stability
tests have not yet been run.  Further, this code does not handle
transmit/receive errors properly.  In short, this code is still pretty raw,
and is being posted here for some early feedback on the overall approach.


Cyril Chemparathy (2):
  Davinci: emac: separate out cpdma for reuse
  Davinci: emac: use new cpdma in emac driver

 drivers/net/Makefile        |    4 +-
 drivers/net/davinci_cpdma.c |  676 ++++++++++++++++++++++++++
 drivers/net/davinci_cpdma.h |   60 +++
 drivers/net/davinci_emac.c  | 1119 +++++--------------------------------------
 4 files changed, 865 insertions(+), 994 deletions(-)
 create mode 100644 drivers/net/davinci_cpdma.c
 create mode 100644 drivers/net/davinci_cpdma.h


From cyril at ti.com  Fri May 28 14:24:44 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 28 May 2010 15:24:44 -0400
Subject: [RFC 1/2] Davinci: emac: separate out cpdma for reuse
In-Reply-To: <1275074685-10614-1-git-send-email-cyril@ti.com>
References: <1275074685-10614-1-git-send-email-cyril@ti.com>
Message-ID: <1275074685-10614-2-git-send-email-cyril@ti.com>

In addition to being embedded into the EMAC controller, the CPDMA hardware
block is used in TI's CPSW switch controller.  Fortunately, the programming
interface to this hardware block remains pretty nicely consistent across these
devices.

This patch adds a new CPDMA services layer, which can then be reused across
EMAC and CPSW drivers.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 drivers/net/Makefile        |    4 +-
 drivers/net/davinci_cpdma.c |  676 +++++++++++++++++++++++++++++++++++++++++++
 drivers/net/davinci_cpdma.h |   60 ++++
 3 files changed, 739 insertions(+), 1 deletions(-)
 create mode 100644 drivers/net/davinci_cpdma.c
 create mode 100644 drivers/net/davinci_cpdma.h

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 57d45fd..4b8e81d 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -2,11 +2,13 @@
 # Makefile for the Linux network (ethercard) device drivers.
 #
 
 obj-$(CONFIG_MII) += mii.o
 obj-$(CONFIG_MDIO) += mdio.o
 obj-$(CONFIG_PHYLIB) += phy/
 
-obj-$(CONFIG_TI_DAVINCI_EMAC) += davinci_emac.o
+obj-$(CONFIG_TI_DAVINCI_EMAC) += davinci_emac.o davinci_cpdma.o
 obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o
 
 obj-$(CONFIG_E1000) += e1000/
diff --git a/drivers/net/davinci_cpdma.c b/drivers/net/davinci_cpdma.c
new file mode 100644
index 0000000..0db9938
--- /dev/null
+++ b/drivers/net/davinci_cpdma.c
@@ -0,0 +1,676 @@
+
+#define DEBUG
+
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+
+#include "davinci_cpdma.h"
+
+/* DMA Registers */
+#define CPDMA_TXIDVER		0x00
+#define CPDMA_TXCONTROL		0x04
+#define CPDMA_TXTEARDOWN	0x08
+#define CPDMA_RXIDVER		0x10
+#define CPDMA_RXCONTROL		0x14
+#define CPDMA_SOFTRESET		0x1c
+#define CPDMA_RXTEARDOWN	0x18
+#define CPDMA_TXINTSTATRAW	0x80
+#define CPDMA_TXINTSTATMASKED	0x84
+#define CPDMA_TXINTMASKSET	0x88
+#define CPDMA_TXINTMASKCLEAR	0x8c
+#define CPDMA_MACINVECTOR	0x90
+#define CPDMA_RXINTSTATRAW	0xa0
+#define CPDMA_RXINTSTATMASKED	0xa4
+#define CPDMA_RXINTMASKSET	0xa8
+#define CPDMA_RXINTMASKCLEAR	0xac
+
+/* Descriptor mode bits */
+#define CPDMA_DESC_SOP		BIT(31)
+#define CPDMA_DESC_EOP		BIT(30)
+#define CPDMA_DESC_OWNER	BIT(29)
+#define CPDMA_DESC_EOQ		BIT(28)
+#define CPDMA_DESC_TD_COMPLETE	BIT(27)
+#define CPDMA_DESC_PASS_CRC	BIT(26)
+
+#define CPDMA_TEARDOWN_VALUE	0xfffffffc
+
+struct cpdma_desc {
+	/* hardware fields */
+	u32			hw_next;
+	u32			hw_buffer;
+	u32			hw_len;
+	u32			hw_mode;
+	/* software fields */
+	void			*sw_token;
+	void			*sw_pad;
+	u32			sw_buffer;
+	u32			sw_len;
+};
+
+struct cpdma_desc_pool {
+	u32			phys;
+	void __iomem		*iomap;		/* ioremap map */
+	void			*cpumap;	/* dma_alloc map */
+	int			desc_size, mem_size;
+	int			num_desc, used_desc;
+	unsigned long		*bitmap;
+	struct device		*dev;
+	spinlock_t		lock;
+};
+
+enum cpdma_state {
+	CPDMA_STATE_IDLE,
+	CPDMA_STATE_ACTIVE,
+	CPDMA_STATE_TEARDOWN,
+};
+
+struct cpdma_ctlr {
+	enum cpdma_state	state;
+	struct cpdma_params	params;
+	struct device		*dev;
+	struct cpdma_desc_pool	*pool;
+	spinlock_t		lock;
+	struct cpdma_chan	*channels[2 * CPDMA_MAX_CHANNELS];
+};
+
+struct cpdma_chan {
+	enum cpdma_state		state;
+	struct cpdma_ctlr		*ctlr;
+	int				chan_num;
+	spinlock_t			lock;
+	struct cpdma_desc __iomem	*head, *tail;
+	int				count;
+	void __iomem			*hdp, *cp, *rxfree;
+	u32				mask;
+	cpdma_handler_fn		handler;
+	enum dma_data_direction		dir;
+	struct cpdma_chan_stats		stats;
+	/* offsets into dmaregs */
+	int	int_set, int_clear, td;
+};
+
+/* The following make access to common cpdma_ctlr params more readable */
+#define dmaregs		params.dmaregs
+#define num_chan	params.num_chan
+
+/* various accessors */
+#define dma_reg_read(ctlr, ofs)		__raw_readl((ctlr)->dmaregs + ofs)
+#define chan_read(chan, fld)		__raw_readl((chan)->fld)
+#define desc_read(desc, fld)		__raw_readl(&(desc)->fld)
+#define dma_reg_write(ctlr, ofs, v)	__raw_writel(v, (ctlr)->dmaregs + ofs)
+#define chan_write(chan, fld, val)	__raw_writel(val, (chan)->fld)
+#define desc_write(desc, fld, v)	__raw_writel((u32)(v), &(desc)->fld)
+
+/*
+ * Utility constructs for a cpdma descriptor pool.  Some devices (e.g. davinci
+ * emac) have dedicated on-chip memory for these descriptors.  Some other
+ * devices (e.g. cpsw switches) use plain old memory.  Descriptor pools
+ * abstract out these details
+ */
+static struct cpdma_desc_pool *
+cpdma_desc_pool_create(struct device *dev, u32 phys, int size, int align)
+{
+	int bitmap_size;
+	struct cpdma_desc_pool *pool;
+
+	pool = kzalloc(sizeof(*pool), GFP_KERNEL);
+	if (!pool)
+		return NULL;
+
+	spin_lock_init(&pool->lock);
+
+	pool->dev	= dev;
+	pool->mem_size	= size;
+	pool->desc_size	= ALIGN(sizeof(struct cpdma_desc), align);
+	pool->num_desc	= size / pool->desc_size;
+
+	bitmap_size  = (pool->num_desc / BITS_PER_LONG) * sizeof(long);
+	pool->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
+	if (!pool->bitmap)
+		goto fail;
+
+	if (phys) {
+		pool->phys  = phys;
+		pool->iomap = ioremap(phys, size);
+	} else {
+		pool->cpumap = dma_alloc_coherent(dev, size, &pool->phys,
+						  GFP_KERNEL);
+		pool->phys  = (__force u32)pool->cpumap;
+		pool->iomap = (void __force __iomem *)pool->cpumap;
+	}
+
+	if (pool->iomap)
+		return pool;
+
+fail:
+	kfree(pool->bitmap);
+	kfree(pool);
+	return NULL;
+}
+
+static void cpdma_desc_pool_destroy(struct cpdma_desc_pool *pool)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&pool->lock, flags);
+	WARN_ON(pool->used_desc);
+	kfree(pool->bitmap);
+	if (pool->cpumap) {
+		dma_free_coherent(pool->dev, pool->mem_size, pool->cpumap,
+				  pool->phys);
+	} else {
+		iounmap(pool->iomap);
+	}
+	spin_unlock_irqrestore(&pool->lock, flags);
+	kfree(pool);
+}
+
+static inline dma_addr_t desc_phys(struct cpdma_desc_pool *pool,
+		  struct cpdma_desc __iomem *desc)
+{
+	if (!desc)
+		return 0;
+	return pool->phys + (__force dma_addr_t)desc -
+			    (__force dma_addr_t)pool->iomap;
+}
+
+static inline struct cpdma_desc __iomem *
+desc_from_phys(struct cpdma_desc_pool *pool, dma_addr_t dma)
+{
+	return dma ? pool->iomap + dma - pool->phys : NULL;
+}
+
+static struct cpdma_desc __iomem *
+cpdma_desc_alloc(struct cpdma_desc_pool *pool, int num_desc)
+{
+	unsigned long flags;
+	int index;
+	struct cpdma_desc __iomem *desc = NULL;
+
+	spin_lock_irqsave(&pool->lock, flags);
+
+	index = bitmap_find_next_zero_area(pool->bitmap, pool->num_desc, 0,
+					   num_desc, 0);
+	if (index < pool->num_desc) {
+		bitmap_set(pool->bitmap, index, num_desc);
+		desc = pool->iomap + pool->desc_size * index;
+		pool->used_desc++;
+	}
+
+	spin_unlock_irqrestore(&pool->lock, flags);
+	return desc;
+}
+
+static void cpdma_desc_free(struct cpdma_desc_pool *pool,
+			    struct cpdma_desc __iomem *desc, int num_desc)
+{
+	unsigned long flags, index;
+
+	index = ((unsigned long)desc - (unsigned long)pool->iomap) /
+		pool->desc_size;
+	spin_lock_irqsave(&pool->lock, flags);
+	bitmap_clear(pool->bitmap, index, num_desc);
+	pool->used_desc--;
+	spin_unlock_irqrestore(&pool->lock, flags);
+}
+
+struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params)
+{
+	struct cpdma_ctlr *ctlr;
+
+	ctlr = kzalloc(sizeof(*ctlr), GFP_KERNEL);
+	if (!ctlr)
+		return NULL;
+
+	ctlr->state = CPDMA_STATE_IDLE;
+	ctlr->params = *params;
+	ctlr->dev = params->dev;
+	spin_lock_init(&ctlr->lock);
+
+	ctlr->pool = cpdma_desc_pool_create(ctlr->dev,
+					    ctlr->params.desc_mem_phys,
+					    ctlr->params.desc_mem_size,
+					    ctlr->params.desc_align);
+	if (!ctlr->pool) {
+		kfree(ctlr);
+		return NULL;
+	}
+
+	if (WARN_ON(ctlr->num_chan > CPDMA_MAX_CHANNELS))
+		ctlr->num_chan = CPDMA_MAX_CHANNELS;
+	return ctlr;
+}
+
+int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
+{
+	unsigned long flags;
+	int i;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+	if (ctlr->state != CPDMA_STATE_IDLE) {
+		spin_unlock_irqrestore(&ctlr->lock, flags);
+		return -EBUSY;
+	}
+
+	if (ctlr->params.has_soft_reset) {
+		unsigned long timeout = jiffies + HZ/10;
+
+		dma_reg_write(ctlr, CPDMA_SOFTRESET, 1);
+		while (time_before(jiffies, timeout)) {
+			if (dma_reg_read(ctlr, CPDMA_SOFTRESET) == 0)
+				break;
+		}
+		WARN_ON(!time_before(jiffies, timeout));
+	}
+
+	for (i = 0; i < ctlr->num_chan; i++) {
+		__raw_writel(0, ctlr->params.txhdp + 4 * i);
+		__raw_writel(0, ctlr->params.rxhdp + 4 * i);
+		__raw_writel(0, ctlr->params.txcp + 4 * i);
+		__raw_writel(0, ctlr->params.rxcp + 4 * i);
+	}
+
+	dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);
+	dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);
+
+	dma_reg_write(ctlr, CPDMA_TXCONTROL, 1);
+	dma_reg_write(ctlr, CPDMA_RXCONTROL, 1);
+
+	ctlr->state = CPDMA_STATE_ACTIVE;
+
+	for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
+		if (ctlr->channels[i])
+			cpdma_chan_start(ctlr->channels[i]);
+	}
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+	return 0;
+}
+
+int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr)
+{
+	unsigned long flags;
+	int i;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+	if (ctlr->state != CPDMA_STATE_ACTIVE) {
+		spin_unlock_irqrestore(&ctlr->lock, flags);
+		return -EINVAL;
+	}
+
+	ctlr->state = CPDMA_STATE_TEARDOWN;
+
+	for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
+		if (ctlr->channels[i])
+			cpdma_chan_stop(ctlr->channels[i]);
+	}
+
+	dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);
+	dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);
+
+	dma_reg_write(ctlr, CPDMA_TXCONTROL, 0);
+	dma_reg_write(ctlr, CPDMA_RXCONTROL, 0);
+
+	ctlr->state = CPDMA_STATE_IDLE;
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+	return 0;
+}
+
+int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr)
+{
+	unsigned long flags;
+	int ret = 0, i;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+	if (ctlr->state != CPDMA_STATE_IDLE)
+		cpdma_ctlr_stop(ctlr);
+
+	for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
+		if (ctlr->channels[i])
+			cpdma_chan_destroy(ctlr->channels[i]);
+	}
+
+	cpdma_desc_pool_destroy(ctlr->pool);
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+	kfree(ctlr);
+	return ret;
+}
+
+struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
+				     cpdma_handler_fn handler)
+{
+	struct cpdma_chan *chan;
+	int ret, offset = (chan_num % CPDMA_MAX_CHANNELS) * 4;
+	unsigned long flags;
+
+	if (__chan_linear(chan_num) >= ctlr->num_chan)
+		return NULL;
+
+	ret = -ENOMEM;
+	chan = kzalloc(sizeof(*chan), GFP_KERNEL);
+	if (!chan)
+		goto err_chan_alloc;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+	ret = -EBUSY;
+	if (ctlr->channels[chan_num])
+		goto err_chan_busy;
+
+	chan->ctlr	= ctlr;
+	chan->state	= CPDMA_STATE_IDLE;
+	chan->chan_num	= chan_num;
+	chan->handler	= handler;
+
+	if (is_rx_chan(chan)) {
+		chan->hdp	= ctlr->params.rxhdp + offset;
+		chan->cp	= ctlr->params.rxcp + offset;
+		chan->rxfree	= ctlr->params.rxfree + offset;
+		chan->int_set	= CPDMA_RXINTMASKSET;
+		chan->int_clear	= CPDMA_RXINTMASKCLEAR;
+		chan->td	= CPDMA_RXTEARDOWN;
+		chan->dir	= DMA_FROM_DEVICE;
+	} else {
+		chan->hdp	= ctlr->params.txhdp + offset;
+		chan->cp	= ctlr->params.txcp + offset;
+		chan->int_set	= CPDMA_TXINTMASKSET;
+		chan->int_clear	= CPDMA_TXINTMASKCLEAR;
+		chan->td	= CPDMA_TXTEARDOWN;
+		chan->dir	= DMA_TO_DEVICE;
+	}
+	chan->mask = BIT(chan_num % CPDMA_MAX_CHANNELS);
+
+	spin_lock_init(&chan->lock);
+
+	ctlr->channels[chan_num] = chan;
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+	return chan;
+
+err_chan_busy:
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+err_chan_alloc:
+	return ERR_PTR(ret);
+}
+
+int cpdma_chan_destroy(struct cpdma_chan *chan)
+{
+	struct cpdma_ctlr *ctlr = chan->ctlr;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+	if (chan->state != CPDMA_STATE_IDLE)
+		cpdma_chan_stop(chan);
+	ctlr->channels[chan->chan_num] = NULL;
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+	kfree(chan);
+	return 0;
+}
+
+static void __cpdma_chan_submit(struct cpdma_chan *chan,
+				struct cpdma_desc __iomem *desc)
+{
+	struct cpdma_ctlr		*ctlr = chan->ctlr;
+	struct cpdma_desc __iomem	*prev = chan->tail;
+	struct cpdma_desc_pool		*pool = ctlr->pool;
+	dma_addr_t			desc_dma;
+
+	desc_dma = desc_phys(pool, desc);
+
+	/* simple case - idle channel */
+	if (!chan->head) {
+		chan->stats.head_enqueue++;
+		chan->head = desc;
+		chan->tail = desc;
+		if (chan->state == CPDMA_STATE_ACTIVE)
+			chan_write(chan, hdp, desc_dma);
+		return;
+	}
+
+	/* first chain the descriptor at the tail of the list */
+	desc_write(prev, hw_next, desc_dma);
+	chan->tail = desc;
+	chan->stats.tail_enqueue++;
+
+	/* next check if EOQ has been triggered already */
+	if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ &&
+	    chan->state == CPDMA_STATE_ACTIVE) {
+		chan_write(chan, hdp, desc_dma);
+		chan->stats.misqueued++;
+	}
+}
+
+int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
+		      int len, gfp_t gfp_mask)
+{
+	struct cpdma_ctlr		*ctlr = chan->ctlr;
+	struct cpdma_desc __iomem	*desc;
+	dma_addr_t			buffer;
+	unsigned long			flags;
+	void				*pad = NULL;
+	u32				mode;
+	int				ret = 0;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if (chan->state == CPDMA_STATE_TEARDOWN) {
+		ret = -EINVAL;
+		goto unlock_ret;
+	}
+
+	desc = cpdma_desc_alloc(ctlr->pool, 1);
+	if (!desc) {
+		chan->stats.desc_alloc_fail++;
+		ret = -ENOMEM;
+		goto unlock_ret;
+	}
+
+	if (len < ctlr->params.min_packet_size) {
+		if (WARN_ONCE(is_rx_chan(chan), "runt receive buffer\n")) {
+			cpdma_desc_free(ctlr->pool, desc, 1);
+			chan->stats.runt_receive_buff++;
+			ret = -EINVAL;
+			goto unlock_ret;
+		}
+
+		pad = kzalloc(ctlr->params.min_packet_size, gfp_mask);
+		if (!pad) {
+			cpdma_desc_free(ctlr->pool, desc, 1);
+			chan->stats.pad_alloc_fail++;
+			ret = -ENOMEM;
+			goto unlock_ret;
+		}
+		chan->stats.pad_enqueue++;
+		memcpy(pad, data, len);
+		data = pad;
+		len = ctlr->params.min_packet_size;
+	}
+
+	buffer = dma_map_single(ctlr->dev, data, len, chan->dir);
+	mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
+
+	desc_write(desc, hw_next,   0);
+	desc_write(desc, hw_buffer, buffer);
+	desc_write(desc, hw_len,    len);
+	desc_write(desc, hw_mode,   mode | len);
+	desc_write(desc, sw_token,  token);
+	desc_write(desc, sw_pad,    pad);
+	desc_write(desc, sw_buffer, buffer);
+	desc_write(desc, sw_len,    len);
+
+	__cpdma_chan_submit(chan, desc);
+
+	if (chan->state == CPDMA_STATE_ACTIVE && chan->rxfree)
+		chan_write(chan, rxfree, 1);
+
+	chan->count++;
+
+unlock_ret:
+	spin_unlock_irqrestore(&chan->lock, flags);
+	return ret;
+}
+
+static void __cpdma_chan_free(struct cpdma_chan *chan,
+			      struct cpdma_desc __iomem *desc,
+			      int outlen, int status)
+{
+	struct cpdma_ctlr		*ctlr = chan->ctlr;
+	struct cpdma_desc_pool		*pool = ctlr->pool;
+	dma_addr_t			buff_dma;
+	int				origlen;
+	void				*pad, *token;
+
+	pad	   = (void *)desc_read(desc, sw_pad);
+	token      = (void *)desc_read(desc, sw_token);
+	buff_dma   = desc_read(desc, sw_buffer);
+	origlen    = desc_read(desc, sw_len);
+
+	dma_unmap_single(ctlr->dev, buff_dma, origlen, chan->dir);
+	kfree(pad);
+	cpdma_desc_free(pool, desc, 1);
+	(*chan->handler)(token, outlen, status);
+}
+
+static int __cpdma_chan_process(struct cpdma_chan *chan, bool waitown)
+{
+	struct cpdma_ctlr		*ctlr = chan->ctlr;
+	struct cpdma_desc __iomem	*desc;
+	int				status, outlen;
+	struct cpdma_desc_pool		*pool = ctlr->pool;
+	dma_addr_t			desc_dma;
+	unsigned long			flags;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	desc = chan->head;
+	if (!desc) {
+		chan->stats.empty_dequeue++;
+		status = -ENOENT;
+		goto unlock_ret;
+	}
+	desc_dma = desc_phys(pool, desc);
+
+	status	= __raw_readl(&desc->hw_mode);
+	outlen	= status & 0x7ff;
+	if (status & CPDMA_DESC_OWNER) {
+		chan->stats.busy_dequeue++;
+		status = -EBUSY;
+		goto unlock_ret;
+	}
+	status	= status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE);
+
+	chan->head = desc_from_phys(pool, desc_read(desc, hw_next));
+	chan_write(chan, cp, desc_dma);
+	chan->count--;
+	chan->stats.good_dequeue++;
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	__cpdma_chan_free(chan, desc, outlen, status);
+	return status;
+
+unlock_ret:
+	spin_unlock_irqrestore(&chan->lock, flags);
+	return status;
+}
+
+int cpdma_chan_process(struct cpdma_chan *chan, int quota)
+{
+	int used, ret = 0;
+
+	if (chan->state != CPDMA_STATE_ACTIVE)
+		return -EINVAL;
+
+	for (used = 0; used < quota && ret >= 0; used++)
+		ret = __cpdma_chan_process(chan, false);
+
+	return used;
+}
+
+int cpdma_chan_start(struct cpdma_chan *chan)
+{
+	struct cpdma_ctlr	*ctlr = chan->ctlr;
+	struct cpdma_desc_pool	*pool = ctlr->pool;
+	unsigned long		flags;
+
+	spin_lock_irqsave(&chan->lock, flags);
+	if (chan->state != CPDMA_STATE_IDLE) {
+		spin_unlock_irqrestore(&chan->lock, flags);
+		return -EBUSY;
+	}
+	if (ctlr->state != CPDMA_STATE_ACTIVE) {
+		spin_unlock_irqrestore(&chan->lock, flags);
+		return -EINVAL;
+	}
+	dma_reg_write(ctlr, chan->int_set, chan->mask);
+	chan->state = CPDMA_STATE_ACTIVE;
+	if (chan->head) {
+		chan_write(chan, hdp, desc_phys(pool, chan->head));
+		if (chan->rxfree)
+			chan_write(chan, rxfree, chan->count);
+	}
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+	return 0;
+}
+
+int cpdma_chan_stop(struct cpdma_chan *chan)
+{
+	struct cpdma_ctlr	*ctlr = chan->ctlr;
+	struct cpdma_desc_pool	*pool = ctlr->pool;
+	unsigned long		flags;
+	int			ret;
+	unsigned long		timeout;
+
+	spin_lock_irqsave(&chan->lock, flags);
+	if (chan->state != CPDMA_STATE_ACTIVE) {
+		spin_unlock_irqrestore(&chan->lock, flags);
+		return -EINVAL;
+	}
+
+	chan->state = CPDMA_STATE_TEARDOWN;
+	dma_reg_write(ctlr, chan->int_clear, chan->mask);
+
+	/* trigger teardown */
+	dma_reg_write(ctlr, chan->td, chan->chan_num);
+
+	/* wait for teardown complete */
+	timeout = jiffies + HZ/10;	/* 100 msec */
+	while (time_before(jiffies, timeout)) {
+		u32 cp = chan_read(chan, cp);
+		if ((cp & CPDMA_TEARDOWN_VALUE) == CPDMA_TEARDOWN_VALUE)
+			break;
+		cpu_relax();
+	}
+	WARN_ON(!time_before(jiffies, timeout));
+	chan_write(chan, cp, CPDMA_TEARDOWN_VALUE);
+
+	/* handle completed packets */
+	do {
+		ret = __cpdma_chan_process(chan, true);
+		if (ret < 0)
+			break;
+	} while ((ret & CPDMA_DESC_TD_COMPLETE) == 0);
+
+	/* remaining packets haven't been tx/rx'ed, clean them up */
+	while (chan->head) {
+		struct cpdma_desc __iomem *desc = chan->head;
+		dma_addr_t next_dma;
+
+		next_dma = desc_read(desc, hw_next);
+		chan->head = desc_from_phys(pool, next_dma);
+		chan->stats.teardown_dequeue++;
+
+		/* issue callback without locks held */
+		spin_unlock_irqrestore(&chan->lock, flags);
+		__cpdma_chan_free(chan, desc, 0, -ENOSYS);
+		spin_lock_irqsave(&chan->lock, flags);
+	}
+
+	chan->state = CPDMA_STATE_IDLE;
+	spin_unlock_irqrestore(&chan->lock, flags);
+	return 0;
+}
diff --git a/drivers/net/davinci_cpdma.h b/drivers/net/davinci_cpdma.h
new file mode 100644
index 0000000..896af60
--- /dev/null
+++ b/drivers/net/davinci_cpdma.h
@@ -0,0 +1,60 @@
+#ifndef __DAVINCI_CPDMA_H__
+#define __DAVINCI_CPDMA_H__
+
+#define CPDMA_MAX_CHANNELS	BITS_PER_LONG
+
+#define tx_chan_num(chan)	(chan)
+#define rx_chan_num(chan)	((chan) + CPDMA_MAX_CHANNELS)
+#define is_rx_chan(chan)	((chan)->chan_num >= CPDMA_MAX_CHANNELS)
+#define is_tx_chan(chan)	(!is_rx_chan(chan))
+#define __chan_linear(chan_num)	((chan_num) & (CPDMA_MAX_CHANNELS - 1))
+#define chan_linear(chan)	__chan_linear((chan)->chan_num)
+
+struct cpdma_params {
+	struct device		*dev;
+	void __iomem		*dmaregs;
+	void __iomem		*txhdp, *rxhdp, *txcp, *rxcp;
+	void __iomem		*rxthresh, *rxfree;
+	int			num_chan;
+	bool			has_soft_reset;
+	int			min_packet_size;
+	u32			desc_mem_phys;
+	int			desc_mem_size;
+	int			desc_align;
+};
+
+struct cpdma_chan_stats {
+	u32			head_enqueue;
+	u32			tail_enqueue;
+	u32			pad_enqueue;
+	u32			misqueued;
+	u32			desc_alloc_fail;
+	u32			pad_alloc_fail;
+	u32			runt_receive_buff;
+	u32			empty_dequeue;
+	u32			busy_dequeue;
+	u32			good_dequeue;
+	u32			teardown_dequeue;
+};
+
+struct cpdma_ctlr;
+struct cpdma_chan;
+
+typedef void (*cpdma_handler_fn)(void *token, int len, int status);
+
+struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
+int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
+int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
+int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
+
+struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
+				     cpdma_handler_fn handler);
+int cpdma_chan_destroy(struct cpdma_chan *chan);
+int cpdma_chan_start(struct cpdma_chan *chan);
+int cpdma_chan_stop(struct cpdma_chan *chan);
+
+int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
+		      int len, gfp_t gfp_mask);
+int cpdma_chan_process(struct cpdma_chan *chan, int quota);
+
+#endif
-- 
1.7.0.4


From cyril at ti.com  Fri May 28 14:24:45 2010
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 28 May 2010 15:24:45 -0400
Subject: [RFC 2/2] Davinci: emac: use new cpdma in emac driver
In-Reply-To: <1275074685-10614-1-git-send-email-cyril@ti.com>
References: <1275074685-10614-1-git-send-email-cyril@ti.com>
Message-ID: <1275074685-10614-3-git-send-email-cyril@ti.com>

This patch replaces the EMAC DMA code with equivalent functionality provided
by the newly added CPDMA layer.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 drivers/net/davinci_emac.c | 1119 +++++---------------------------------------
 1 files changed, 126 insertions(+), 993 deletions(-)

diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 18f6cf6..6a9d1de 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -63,6 +63,8 @@
 #include <asm/irq.h>
 #include <asm/page.h>
 
+#include "davinci_cpdma.h"
+
 static int debug_level;
 module_param(debug_level, int, 0);
 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
@@ -113,6 +115,7 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
 #define EMAC_DEF_MAX_FRAME_SIZE		(1500 + 14 + 4 + 4)
 #define EMAC_DEF_TX_CH			(0) /* Default 0th channel */
 #define EMAC_DEF_RX_CH			(0) /* Default 0th channel */
+#define EMAC_DEF_RX_NUM_DESC		(128)
 #define EMAC_DEF_MAX_TX_CH		(1) /* Max TX channels configured */
 #define EMAC_DEF_MAX_RX_CH		(1) /* Max RX channels configured */
 #define EMAC_POLL_WEIGHT		(64) /* Default NAPI poll weight */
@@ -124,7 +127,6 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
 /* EMAC register related defines */
 #define EMAC_ALL_MULTI_REG_VALUE	(0xFFFFFFFF)
 #define EMAC_NUM_MULTICAST_BITS		(64)
-#define EMAC_TEARDOWN_VALUE		(0xFFFFFFFC)
 #define EMAC_TX_CONTROL_TX_ENABLE_VAL	(0x1)
 #define EMAC_RX_CONTROL_RX_ENABLE_VAL	(0x1)
 #define EMAC_MAC_HOST_ERR_INTMASK_VAL	(0x2)
@@ -211,24 +213,10 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
 
 /* EMAC Peripheral Device Register Memory Layout structure */
-#define EMAC_TXIDVER		0x0
-#define EMAC_TXCONTROL		0x4
-#define EMAC_TXTEARDOWN		0x8
-#define EMAC_RXIDVER		0x10
-#define EMAC_RXCONTROL		0x14
-#define EMAC_RXTEARDOWN		0x18
-#define EMAC_TXINTSTATRAW	0x80
-#define EMAC_TXINTSTATMASKED	0x84
-#define EMAC_TXINTMASKSET	0x88
-#define EMAC_TXINTMASKCLEAR	0x8C
 #define EMAC_MACINVECTOR	0x90
 
 #define EMAC_DM646X_MACEOIVECTOR	0x94
 
-#define EMAC_RXINTSTATRAW	0xA0
-#define EMAC_RXINTSTATMASKED	0xA4
-#define EMAC_RXINTMASKSET	0xA8
-#define EMAC_RXINTMASKCLEAR	0xAC
 #define EMAC_MACINTSTATRAW	0xB0
 #define EMAC_MACINTSTATMASKED	0xB4
 #define EMAC_MACINTMASKSET	0xB8
@@ -255,12 +243,6 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
 #define EMAC_MACADDRHI		0x504
 #define EMAC_MACINDEX		0x508
 
-/* EMAC HDP and Completion registors */
-#define EMAC_TXHDP(ch)		(0x600 + (ch * 4))
-#define EMAC_RXHDP(ch)		(0x620 + (ch * 4))
-#define EMAC_TXCP(ch)		(0x640 + (ch * 4))
-#define EMAC_RXCP(ch)		(0x660 + (ch * 4))
-
 /* EMAC statistics registers */
 #define EMAC_RXGOODFRAMES	0x200
 #define EMAC_RXBCASTFRAMES	0x204
@@ -308,120 +290,6 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
 /* EMAC Stats Clear Mask */
 #define EMAC_STATS_CLR_MASK    (0xFFFFFFFF)
 
-/** net_buf_obj: EMAC network bufferdata structure
- *
- * EMAC network buffer data structure
- */
-struct emac_netbufobj {
-	void *buf_token;
-	char *data_ptr;
-	int length;
-};
-
-/** net_pkt_obj: EMAC network packet data structure
- *
- * EMAC network packet data structure - supports buffer list (for future)
- */
-struct emac_netpktobj {
-	void *pkt_token; /* data token may hold tx/rx chan id */
-	struct emac_netbufobj *buf_list; /* array of network buffer objects */
-	int num_bufs;
-	int pkt_length;
-};
-
-/** emac_tx_bd: EMAC TX Buffer descriptor data structure
- *
- * EMAC TX Buffer descriptor data structure
- */
-struct emac_tx_bd {
-	int h_next;
-	int buff_ptr;
-	int off_b_len;
-	int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
-	struct emac_tx_bd __iomem *next;
-	void *buf_token;
-};
-
-/** emac_txch: EMAC TX Channel data structure
- *
- * EMAC TX Channel data structure
- */
-struct emac_txch {
-	/* Config related */
-	u32 num_bd;
-	u32 service_max;
-
-	/* CPPI specific */
-	u32 alloc_size;
-	void __iomem *bd_mem;
-	struct emac_tx_bd __iomem *bd_pool_head;
-	struct emac_tx_bd __iomem *active_queue_head;
-	struct emac_tx_bd __iomem *active_queue_tail;
-	struct emac_tx_bd __iomem *last_hw_bdprocessed;
-	u32 queue_active;
-	u32 teardown_pending;
-	u32 *tx_complete;
-
-	/** statistics */
-	u32 proc_count;     /* TX: # of times emac_tx_bdproc is called */
-	u32 mis_queued_packets;
-	u32 queue_reinit;
-	u32 end_of_queue_add;
-	u32 out_of_tx_bd;
-	u32 no_active_pkts; /* IRQ when there were no packets to process */
-	u32 active_queue_count;
-};
-
-/** emac_rx_bd: EMAC RX Buffer descriptor data structure
- *
- * EMAC RX Buffer descriptor data structure
- */
-struct emac_rx_bd {
-	int h_next;
-	int buff_ptr;
-	int off_b_len;
-	int mode;
-	struct emac_rx_bd __iomem *next;
-	void *data_ptr;
-	void *buf_token;
-};
-
-/** emac_rxch: EMAC RX Channel data structure
- *
- * EMAC RX Channel data structure
- */
-struct emac_rxch {
-	/* configuration info */
-	u32 num_bd;
-	u32 service_max;
-	u32 buf_size;
-	char mac_addr[6];
-
-	/** CPPI specific */
-	u32 alloc_size;
-	void __iomem *bd_mem;
-	struct emac_rx_bd __iomem *bd_pool_head;
-	struct emac_rx_bd __iomem *active_queue_head;
-	struct emac_rx_bd __iomem *active_queue_tail;
-	u32 queue_active;
-	u32 teardown_pending;
-
-	/* packet and buffer objects */
-	struct emac_netpktobj pkt_queue;
-	struct emac_netbufobj buf_queue;
-
-	/** statistics */
-	u32 proc_count; /* number of times emac_rx_bdproc is called */
-	u32 processed_bd;
-	u32 recycled_bd;
-	u32 out_of_rx_bd;
-	u32 out_of_rx_buffers;
-	u32 queue_reinit;
-	u32 end_of_queue_add;
-	u32 end_of_queue;
-	u32 mis_queued_packets;
-};
-
 /* emac_priv: EMAC private data structure
  *
  * EMAC adapter private data structure
@@ -438,11 +306,9 @@ struct emac_priv {
 	u32 emac_base_phys;
 	void __iomem *emac_base;
 	void __iomem *ctrl_base;
-	void __iomem *emac_ctrl_ram;
-	u32 ctrl_ram_size;
-	u32 hw_ram_addr;
-	struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
-	struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
+	struct cpdma_ctlr *dma;
+	struct cpdma_chan *txch;
+	struct cpdma_chan *rxch;
 	u32 link; /* 1=link on, 0=link off */
 	u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
 	u32 duplex; /* Link duplex: 0=Half, 1=Full */
@@ -467,18 +333,6 @@ struct emac_priv {
 static struct clk *emac_clk;
 static unsigned long emac_bus_frequency;
 
-#define emac_virt_to_phys(addr, priv) \
-	(((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \
-	+ priv->hw_ram_addr)
-
-/* Cache macros - Packet buffers would be from skb pool which is cached */
-#define EMAC_VIRT_NOCACHE(addr) (addr)
-
-/* DM644x does not have BD's in cached memory - so no cache functions */
-#define BD_CACHE_INVALIDATE(addr, size)
-#define BD_CACHE_WRITEBACK(addr, size)
-#define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
-
 /* EMAC TX Host Error description strings */
 static char *emac_txhost_errcodes[16] = {
 	"No error", "SOP error", "Ownership bit not set in SOP buffer",
@@ -519,20 +373,6 @@ static void emac_dump_regs(struct emac_priv *priv)
 	dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
 		emac_ctrl_read(EMAC_CTRL_EWCTL),
 		emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
-	dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n",
-		emac_read(EMAC_TXIDVER),
-		((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"),
-		emac_read(EMAC_RXIDVER),
-		((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled"));
-	dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\
-		"TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW),
-		emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET));
-	dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\
-		"RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW),
-		emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET));
-	dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\
-		"MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW),
-		emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR));
 	dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
 		emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
 	dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
@@ -541,8 +381,6 @@ static void emac_dump_regs(struct emac_priv *priv)
 	dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
 		"MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
 		emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
-	dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n",
-		emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0)));
 	dev_info(emac_dev, "EMAC Statistics\n");
 	dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
 		emac_read(EMAC_RXGOODFRAMES));
@@ -1021,6 +859,7 @@ static irqreturn_t emac_irq(int irq, void *dev_id)
 	struct net_device *ndev = (struct net_device *)dev_id;
 	struct emac_priv *priv = netdev_priv(ndev);
 
+	dev_info(&ndev->dev, "interrupt!\n");
 	++priv->isr_count;
 	if (likely(netif_running(priv->ndev))) {
 		emac_int_disable(priv);
@@ -1031,370 +870,56 @@ static irqreturn_t emac_irq(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-/** EMAC on-chip buffer descriptor memory
- *
- * WARNING: Please note that the on chip memory is used for both TX and RX
- * buffer descriptor queues and is equally divided between TX and RX desc's
- * If the number of TX or RX descriptors change this memory pointers need
- * to be adjusted. If external memory is allocated then these pointers can
- * pointer to the memory
- *
- */
-#define EMAC_TX_BD_MEM(priv)	((priv)->emac_ctrl_ram)
-#define EMAC_RX_BD_MEM(priv)	((priv)->emac_ctrl_ram + \
-				(((priv)->ctrl_ram_size) >> 1))
-
-/**
- * emac_init_txch: TX channel initialization
- * @priv: The DaVinci EMAC private adapter structure
- * @ch: RX channel number
- *
- * Called during device init to setup a TX channel (allocate buffer desc
- * create free pool and keep ready for transmission
- *
- * Returns success(0) or mem alloc failures error code
- */
-static int emac_init_txch(struct emac_priv *priv, u32 ch)
-{
-	struct device *emac_dev = &priv->ndev->dev;
-	u32 cnt, bd_size;
-	void __iomem *mem;
-	struct emac_tx_bd __iomem *curr_bd;
-	struct emac_txch *txch = NULL;
-
-	txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL);
-	if (NULL == txch) {
-		dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed");
-		return -ENOMEM;
-	}
-	priv->txch[ch] = txch;
-	txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
-	txch->active_queue_head = NULL;
-	txch->active_queue_tail = NULL;
-	txch->queue_active = 0;
-	txch->teardown_pending = 0;
-
-	/* allocate memory for TX CPPI channel on a 4 byte boundry */
-	txch->tx_complete = kzalloc(txch->service_max * sizeof(u32),
-				    GFP_KERNEL);
-	if (NULL == txch->tx_complete) {
-		dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed");
-		kfree(txch);
-		return -ENOMEM;
-	}
-
-	/* allocate buffer descriptor pool align every BD on four word
-	 * boundry for future requirements */
-	bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
-	txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
-	txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
-
-	/* alloc TX BD memory */
-	txch->bd_mem = EMAC_TX_BD_MEM(priv);
-	__memzero((void __force *)txch->bd_mem, txch->alloc_size);
-
-	/* initialize the BD linked list */
-	mem = (void __force __iomem *)
-			(((u32 __force) txch->bd_mem + 0xF) & ~0xF);
-	txch->bd_pool_head = NULL;
-	for (cnt = 0; cnt < txch->num_bd; cnt++) {
-		curr_bd = mem + (cnt * bd_size);
-		curr_bd->next = txch->bd_pool_head;
-		txch->bd_pool_head = curr_bd;
-	}
-
-	/* reset statistics counters */
-	txch->out_of_tx_bd = 0;
-	txch->no_active_pkts = 0;
-	txch->active_queue_count = 0;
-
-	return 0;
-}
-
-/**
- * emac_cleanup_txch: Book-keep function to clean TX channel resources
- * @priv: The DaVinci EMAC private adapter structure
- * @ch: TX channel number
- *
- * Called to clean up TX channel resources
- *
- */
-static void emac_cleanup_txch(struct emac_priv *priv, u32 ch)
+static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
 {
-	struct emac_txch *txch = priv->txch[ch];
-
-	if (txch) {
-		if (txch->bd_mem)
-			txch->bd_mem = NULL;
-		kfree(txch->tx_complete);
-		kfree(txch);
-		priv->txch[ch] = NULL;
-	}
-}
-
-/**
- * emac_net_tx_complete: TX packet completion function
- * @priv: The DaVinci EMAC private adapter structure
- * @net_data_tokens: packet token - skb pointer
- * @num_tokens: number of skb's to free
- * @ch: TX channel number
- *
- * Frees the skb once packet is transmitted
- *
- */
-static int emac_net_tx_complete(struct emac_priv *priv,
-				void **net_data_tokens,
-				int num_tokens, u32 ch)
-{
-	u32 cnt;
-
-	if (unlikely(num_tokens && netif_queue_stopped(priv->ndev)))
-		netif_start_queue(priv->ndev);
-	for (cnt = 0; cnt < num_tokens; cnt++) {
-		struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt];
-		if (skb == NULL)
-			continue;
-		priv->net_dev_stats.tx_packets++;
-		priv->net_dev_stats.tx_bytes += skb->len;
-		dev_kfree_skb_any(skb);
-	}
-	return 0;
+	struct sk_buff *skb = dev_alloc_skb(priv->rx_buf_size);
+	if (WARN_ON(!skb))
+		return NULL;
+	skb->dev = priv->ndev;
+	skb_reserve(skb, NET_IP_ALIGN);
+	return skb;
 }
 
-/**
- * emac_txch_teardown: TX channel teardown
- * @priv: The DaVinci EMAC private adapter structure
- * @ch: TX channel number
- *
- * Called to teardown TX channel
- *
- */
-static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
+static void emac_rx_handler(void *token, int len, int status)
 {
-	struct device *emac_dev = &priv->ndev->dev;
-	u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
-	struct emac_txch *txch = priv->txch[ch];
-	struct emac_tx_bd __iomem *curr_bd;
-
-	while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
-	       EMAC_TEARDOWN_VALUE) {
-		/* wait till tx teardown complete */
-		cpu_relax(); /* TODO: check if this helps ... */
-		--teardown_cnt;
-		if (0 == teardown_cnt) {
-			dev_err(emac_dev, "EMAC: TX teardown aborted\n");
-			break;
-		}
-	}
-	emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
-
-	/* process sent packets and return skb's to upper layer */
-	if (1 == txch->queue_active) {
-		curr_bd = txch->active_queue_head;
-		while (curr_bd != NULL) {
-			dma_unmap_single(emac_dev, curr_bd->buff_ptr,
-				curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
-				DMA_TO_DEVICE);
-
-			emac_net_tx_complete(priv, (void __force *)
-					&curr_bd->buf_token, 1, ch);
-			if (curr_bd != txch->active_queue_tail)
-				curr_bd = curr_bd->next;
-			else
-				break;
-		}
-		txch->bd_pool_head = txch->active_queue_head;
-		txch->active_queue_head =
-		txch->active_queue_tail = NULL;
+	struct sk_buff		*skb = token;
+	struct net_device	*ndev = skb->dev;
+	struct emac_priv	*priv = netdev_priv(ndev);
+	int			ret;
+
+	if (status < 0) {
+		/* error */
+		goto recycle;
 	}
-}
 
-/**
- * emac_stop_txch: Stop TX channel operation
- * @priv: The DaVinci EMAC private adapter structure
- * @ch: TX channel number
- *
- * Called to stop TX channel operation
- *
- */
-static void emac_stop_txch(struct emac_priv *priv, u32 ch)
-{
-	struct emac_txch *txch = priv->txch[ch];
-
-	if (txch) {
-		txch->teardown_pending = 1;
-		emac_write(EMAC_TXTEARDOWN, 0);
-		emac_txch_teardown(priv, ch);
-		txch->teardown_pending = 0;
-		emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
-	}
-}
+	skb_put(skb, len);
+	skb->protocol = eth_type_trans(skb, ndev);
+	netif_receive_skb(skb);
+	priv->net_dev_stats.rx_bytes += len;
+	priv->net_dev_stats.rx_packets++;
 
-/**
- * emac_tx_bdproc: TX buffer descriptor (packet) processing
- * @priv: The DaVinci EMAC private adapter structure
- * @ch: TX channel number to process buffer descriptors for
- * @budget: number of packets allowed to process
- * @pending: indication to caller that packets are pending to process
- *
- * Processes TX buffer descriptors after packets are transmitted - checks
- * ownership bit on the TX * descriptor and requeues it to free pool & frees
- * the SKB buffer. Only "budget" number of packets are processed and
- * indication of pending packets provided to the caller
- *
- * Returns number of packets processed
- */
-static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
-{
-	struct device *emac_dev = &priv->ndev->dev;
-	unsigned long flags;
-	u32 frame_status;
-	u32 pkts_processed = 0;
-	u32 tx_complete_cnt = 0;
-	struct emac_tx_bd __iomem *curr_bd;
-	struct emac_txch *txch = priv->txch[ch];
-	u32 *tx_complete_ptr = txch->tx_complete;
-
-	if (unlikely(1 == txch->teardown_pending)) {
-		if (netif_msg_tx_err(priv) && net_ratelimit()) {
-			dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\
-				"teardown pending\n");
-		}
-		return 0;  /* dont handle any pkt completions */
-	}
+	/* alloc a new packet for receive */
+	skb = emac_rx_alloc(priv);
 
-	++txch->proc_count;
-	spin_lock_irqsave(&priv->tx_lock, flags);
-	curr_bd = txch->active_queue_head;
-	if (NULL == curr_bd) {
-		emac_write(EMAC_TXCP(ch),
-			   emac_virt_to_phys(txch->last_hw_bdprocessed, priv));
-		txch->no_active_pkts++;
-		spin_unlock_irqrestore(&priv->tx_lock, flags);
-		return 0;
+recycle:
+	if (skb) {
+		ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
+					skb_tailroom(skb), GFP_KERNEL);
+		WARN_ON(ret < 0);
 	}
-	BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
-	frame_status = curr_bd->mode;
-	while ((curr_bd) &&
-	      ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
-	      (pkts_processed < budget)) {
-		emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd, priv));
-		txch->active_queue_head = curr_bd->next;
-		if (frame_status & EMAC_CPPI_EOQ_BIT) {
-			if (curr_bd->next) {	/* misqueued packet */
-				emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
-				++txch->mis_queued_packets;
-			} else {
-				txch->queue_active = 0; /* end of queue */
-			}
-		}
-
-		dma_unmap_single(emac_dev, curr_bd->buff_ptr,
-				curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
-				DMA_TO_DEVICE);
-
-		*tx_complete_ptr = (u32) curr_bd->buf_token;
-		++tx_complete_ptr;
-		++tx_complete_cnt;
-		curr_bd->next = txch->bd_pool_head;
-		txch->bd_pool_head = curr_bd;
-		--txch->active_queue_count;
-		pkts_processed++;
-		txch->last_hw_bdprocessed = curr_bd;
-		curr_bd = txch->active_queue_head;
-		if (curr_bd) {
-			BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
-			frame_status = curr_bd->mode;
-		}
-	} /* end of pkt processing loop */
-
-	emac_net_tx_complete(priv,
-			     (void *)&txch->tx_complete[0],
-			     tx_complete_cnt, ch);
-	spin_unlock_irqrestore(&priv->tx_lock, flags);
-	return pkts_processed;
 }
 
-#define EMAC_ERR_TX_OUT_OF_BD -1
-
-/**
- * emac_send: EMAC Transmit function (internal)
- * @priv: The DaVinci EMAC private adapter structure
- * @pkt: packet pointer (contains skb ptr)
- * @ch: TX channel number
- *
- * Called by the transmit function to queue the packet in EMAC hardware queue
- *
- * Returns success(0) or error code (typically out of desc's)
- */
-static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
+static void emac_tx_handler(void *token, int len, int status)
 {
-	unsigned long flags;
-	struct emac_tx_bd __iomem *curr_bd;
-	struct emac_txch *txch;
-	struct emac_netbufobj *buf_list;
-
-	txch = priv->txch[ch];
-	buf_list = pkt->buf_list;   /* get handle to the buffer array */
-
-	/* check packet size and pad if short */
-	if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
-		buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
-		pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
-	}
-
-	spin_lock_irqsave(&priv->tx_lock, flags);
-	curr_bd = txch->bd_pool_head;
-	if (curr_bd == NULL) {
-		txch->out_of_tx_bd++;
-		spin_unlock_irqrestore(&priv->tx_lock, flags);
-		return EMAC_ERR_TX_OUT_OF_BD;
-	}
-
-	txch->bd_pool_head = curr_bd->next;
-	curr_bd->buf_token = buf_list->buf_token;
-	curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buf_list->data_ptr,
-			buf_list->length, DMA_TO_DEVICE);
-	curr_bd->off_b_len = buf_list->length;
-	curr_bd->h_next = 0;
-	curr_bd->next = NULL;
-	curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
-			 EMAC_CPPI_EOP_BIT | pkt->pkt_length);
-
-	/* flush the packet from cache if write back cache is present */
-	BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
-
-	/* send the packet */
-	if (txch->active_queue_head == NULL) {
-		txch->active_queue_head = curr_bd;
-		txch->active_queue_tail = curr_bd;
-		if (1 != txch->queue_active) {
-			emac_write(EMAC_TXHDP(ch),
-					emac_virt_to_phys(curr_bd, priv));
-			txch->queue_active = 1;
-		}
-		++txch->queue_reinit;
-	} else {
-		register struct emac_tx_bd __iomem *tail_bd;
-		register u32 frame_status;
-
-		tail_bd = txch->active_queue_tail;
-		tail_bd->next = curr_bd;
-		txch->active_queue_tail = curr_bd;
-		tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
-		tail_bd->h_next = (int)emac_virt_to_phys(curr_bd, priv);
-		frame_status = tail_bd->mode;
-		if (frame_status & EMAC_CPPI_EOQ_BIT) {
-			emac_write(EMAC_TXHDP(ch),
-				emac_virt_to_phys(curr_bd, priv));
-			frame_status &= ~(EMAC_CPPI_EOQ_BIT);
-			tail_bd->mode = frame_status;
-			++txch->end_of_queue_add;
-		}
-	}
-	txch->active_queue_count++;
-	spin_unlock_irqrestore(&priv->tx_lock, flags);
-	return 0;
+	struct sk_buff		*skb = token;
+	struct net_device	*ndev = skb->dev;
+	struct emac_priv	*priv = netdev_priv(ndev);
+
+	if (unlikely(netif_queue_stopped(ndev)))
+		netif_start_queue(ndev);
+	priv->net_dev_stats.tx_packets++;
+	priv->net_dev_stats.tx_bytes += len;
+	dev_kfree_skb_any(skb);
 }
 
 /**
@@ -1411,8 +936,6 @@ static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
 {
 	struct device *emac_dev = &ndev->dev;
 	int ret_code;
-	struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
-	struct emac_netpktobj tx_packet;  /* packet object */
 	struct emac_priv *priv = netdev_priv(ndev);
 
 	/* If no link, return */
@@ -1422,25 +945,14 @@ static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
 		return NETDEV_TX_BUSY;
 	}
 
-	/* Build the buffer and packet objects - Since only single fragment is
-	 * supported, need not set length and token in both packet & object.
-	 * Doing so for completeness sake & to show that this needs to be done
-	 * in multifragment case
-	 */
-	tx_packet.buf_list = &tx_buf;
-	tx_packet.num_bufs = 1; /* only single fragment supported */
-	tx_packet.pkt_length = skb->len;
-	tx_packet.pkt_token = (void *)skb;
-	tx_buf.length = skb->len;
-	tx_buf.buf_token = (void *)skb;
-	tx_buf.data_ptr = skb->data;
 	ndev->trans_start = jiffies;
-	ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
+	ret_code = cpdma_chan_submit(priv->txch, skb, skb->data, skb->len,
+				     GFP_KERNEL);
 	if (unlikely(ret_code != 0)) {
-		if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
+		if (ret_code == -ENOMEM) {
 			if (netif_msg_tx_err(priv) && net_ratelimit())
-				dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\
-					" err. Out of TX BD's");
+				dev_err(emac_dev,
+					"DaVinci EMAC: tx out of memory\n");
 			netif_stop_queue(priv->ndev);
 		}
 		priv->net_dev_stats.tx_dropped++;
@@ -1470,216 +982,12 @@ static void emac_dev_tx_timeout(struct net_device *ndev)
 
 	priv->net_dev_stats.tx_errors++;
 	emac_int_disable(priv);
-	emac_stop_txch(priv, EMAC_DEF_TX_CH);
-	emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
-	emac_init_txch(priv, EMAC_DEF_TX_CH);
-	emac_write(EMAC_TXHDP(0), 0);
-	emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
+	cpdma_chan_stop(priv->txch);
+	cpdma_chan_start(priv->txch);
 	emac_int_enable(priv);
 }
 
 /**
- * emac_net_alloc_rx_buf: Allocate a skb for RX
- * @priv: The DaVinci EMAC private adapter structure
- * @buf_size: size of SKB data buffer to allocate
- * @data_token: data token returned (skb handle for storing in buffer desc)
- * @ch: RX channel number
- *
- * Called during RX channel setup - allocates skb buffer of required size
- * and provides the skb handle and allocated buffer data pointer to caller
- *
- * Returns skb data pointer or 0 on failure to alloc skb
- */
-static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
-		void **data_token, u32 ch)
-{
-	struct net_device *ndev = priv->ndev;
-	struct device *emac_dev = &ndev->dev;
-	struct sk_buff *p_skb;
-
-	p_skb = dev_alloc_skb(buf_size);
-	if (unlikely(NULL == p_skb)) {
-		if (netif_msg_rx_err(priv) && net_ratelimit())
-			dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb");
-		return NULL;
-	}
-
-	/* set device pointer in skb and reserve space for extra bytes */
-	p_skb->dev = ndev;
-	skb_reserve(p_skb, NET_IP_ALIGN);
-	*data_token = (void *) p_skb;
-	return p_skb->data;
-}
-
-/**
- * emac_init_rxch: RX channel initialization
- * @priv: The DaVinci EMAC private adapter structure
- * @ch: RX channel number
- * @param: mac address for RX channel
- *
- * Called during device init to setup a RX channel (allocate buffers and
- * buffer descriptors, create queue and keep ready for reception
- *
- * Returns success(0) or mem alloc failures error code
- */
-static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
-{
-	struct device *emac_dev = &priv->ndev->dev;
-	u32 cnt, bd_size;
-	void __iomem *mem;
-	struct emac_rx_bd __iomem *curr_bd;
-	struct emac_rxch *rxch = NULL;
-
-	rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL);
-	if (NULL == rxch) {
-		dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed");
-		return -ENOMEM;
-	}
-	priv->rxch[ch] = rxch;
-	rxch->buf_size = priv->rx_buf_size;
-	rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
-	rxch->queue_active = 0;
-	rxch->teardown_pending = 0;
-
-	/* save mac address */
-	for (cnt = 0; cnt < 6; cnt++)
-		rxch->mac_addr[cnt] = param[cnt];
-
-	/* allocate buffer descriptor pool align every BD on four word
-	 * boundry for future requirements */
-	bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
-	rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
-	rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
-	rxch->bd_mem = EMAC_RX_BD_MEM(priv);
-	__memzero((void __force *)rxch->bd_mem, rxch->alloc_size);
-	rxch->pkt_queue.buf_list = &rxch->buf_queue;
-
-	/* allocate RX buffer and initialize the BD linked list */
-	mem = (void __force __iomem *)
-			(((u32 __force) rxch->bd_mem + 0xF) & ~0xF);
-	rxch->active_queue_head = NULL;
-	rxch->active_queue_tail = mem;
-	for (cnt = 0; cnt < rxch->num_bd; cnt++) {
-		curr_bd = mem + (cnt * bd_size);
-		/* for future use the last parameter contains the BD ptr */
-		curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
-				    rxch->buf_size,
-				    (void __force **)&curr_bd->buf_token,
-				    EMAC_DEF_RX_CH);
-		if (curr_bd->data_ptr == NULL) {
-			dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \
-				"failed for ch %d\n", ch);
-			kfree(rxch);
-			return -ENOMEM;
-		}
-
-		/* populate the hardware descriptor */
-		curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head,
-				priv);
-		curr_bd->buff_ptr = dma_map_single(emac_dev, curr_bd->data_ptr,
-				rxch->buf_size, DMA_FROM_DEVICE);
-		curr_bd->off_b_len = rxch->buf_size;
-		curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
-
-		/* write back to hardware memory */
-		BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd,
-					      EMAC_BD_LENGTH_FOR_CACHE);
-		curr_bd->next = rxch->active_queue_head;
-		rxch->active_queue_head = curr_bd;
-	}
-
-	/* At this point rxCppi->activeQueueHead points to the first
-	   RX BD ready to be given to RX HDP and rxch->active_queue_tail
-	   points to the last RX BD
-	 */
-	return 0;
-}
-
-/**
- * emac_rxch_teardown: RX channel teardown
- * @priv: The DaVinci EMAC private adapter structure
- * @ch: RX channel number
- *
- * Called during device stop to teardown RX channel
- *
- */
-static void emac_rxch_teardown(struct emac_priv *priv, u32 ch)
-{
-	struct device *emac_dev = &priv->ndev->dev;
-	u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
-
-	while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
-	       EMAC_TEARDOWN_VALUE) {
-		/* wait till tx teardown complete */
-		cpu_relax(); /* TODO: check if this helps ... */
-		--teardown_cnt;
-		if (0 == teardown_cnt) {
-			dev_err(emac_dev, "EMAC: RX teardown aborted\n");
-			break;
-		}
-	}
-	emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE);
-}
-
-/**
- * emac_stop_rxch: Stop RX channel operation
- * @priv: The DaVinci EMAC private adapter structure
- * @ch: RX channel number
- *
- * Called during device stop to stop RX channel operation
- *
- */
-static void emac_stop_rxch(struct emac_priv *priv, u32 ch)
-{
-	struct emac_rxch *rxch = priv->rxch[ch];
-
-	if (rxch) {
-		rxch->teardown_pending = 1;
-		emac_write(EMAC_RXTEARDOWN, ch);
-		/* wait for teardown complete */
-		emac_rxch_teardown(priv, ch);
-		rxch->teardown_pending = 0;
-		emac_write(EMAC_RXINTMASKCLEAR, BIT(ch));
-	}
-}
-
-/**
- * emac_cleanup_rxch: Book-keep function to clean RX channel resources
- * @priv: The DaVinci EMAC private adapter structure
- * @ch: RX channel number
- *
- * Called during device stop to clean up RX channel resources
- *
- */
-static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
-{
-	struct emac_rxch *rxch = priv->rxch[ch];
-	struct emac_rx_bd __iomem *curr_bd;
-
-	if (rxch) {
-		/* free the receive buffers previously allocated */
-		curr_bd = rxch->active_queue_head;
-		while (curr_bd) {
-			if (curr_bd->buf_token) {
-				dma_unmap_single(&priv->ndev->dev,
-					curr_bd->buff_ptr,
-					curr_bd->off_b_len
-						& EMAC_RX_BD_BUF_SIZE,
-					DMA_FROM_DEVICE);
-
-				dev_kfree_skb_any((struct sk_buff *)\
-						  curr_bd->buf_token);
-			}
-			curr_bd = curr_bd->next;
-		}
-		if (rxch->bd_mem)
-			rxch->bd_mem = NULL;
-		kfree(rxch);
-		priv->rxch[ch] = NULL;
-	}
-}
-
-/**
  * emac_set_type0addr: Set EMAC Type0 mac address
  * @priv: The DaVinci EMAC private adapter structure
  * @ch: RX channel number
@@ -1795,7 +1103,6 @@ static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
 {
 	struct emac_priv *priv = netdev_priv(ndev);
-	struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH];
 	struct device *emac_dev = &priv->ndev->dev;
 	struct sockaddr *sa = addr;
 
@@ -1806,11 +1113,10 @@ static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
 	memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
 	memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
 
-	/* If the interface is down - rxch is NULL. */
 	/* MAC address is configured only after the interface is enabled. */
 	if (netif_running(ndev)) {
-		memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
-		emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr);
+		memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
+		emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
 	}
 
 	if (netif_msg_drv(priv))
@@ -1821,194 +1127,6 @@ static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
 }
 
 /**
- * emac_addbd_to_rx_queue: Recycle RX buffer descriptor
- * @priv: The DaVinci EMAC private adapter structure
- * @ch: RX channel number to process buffer descriptors for
- * @curr_bd: current buffer descriptor
- * @buffer: buffer pointer for descriptor
- * @buf_token: buffer token (stores skb information)
- *
- * Prepares the recycled buffer descriptor and addes it to hardware
- * receive queue - if queue empty this descriptor becomes the head
- * else addes the descriptor to end of queue
- *
- */
-static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
-		struct emac_rx_bd __iomem *curr_bd,
-		char *buffer, void *buf_token)
-{
-	struct emac_rxch *rxch = priv->rxch[ch];
-
-	/* populate the hardware descriptor */
-	curr_bd->h_next = 0;
-	curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buffer,
-				rxch->buf_size, DMA_FROM_DEVICE);
-	curr_bd->off_b_len = rxch->buf_size;
-	curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
-	curr_bd->next = NULL;
-	curr_bd->data_ptr = buffer;
-	curr_bd->buf_token = buf_token;
-
-	/* write back  */
-	BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
-	if (rxch->active_queue_head == NULL) {
-		rxch->active_queue_head = curr_bd;
-		rxch->active_queue_tail = curr_bd;
-		if (0 != rxch->queue_active) {
-			emac_write(EMAC_RXHDP(ch),
-			   emac_virt_to_phys(rxch->active_queue_head, priv));
-			rxch->queue_active = 1;
-		}
-	} else {
-		struct emac_rx_bd __iomem *tail_bd;
-		u32 frame_status;
-
-		tail_bd = rxch->active_queue_tail;
-		rxch->active_queue_tail = curr_bd;
-		tail_bd->next = curr_bd;
-		tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
-		tail_bd->h_next = emac_virt_to_phys(curr_bd, priv);
-		frame_status = tail_bd->mode;
-		if (frame_status & EMAC_CPPI_EOQ_BIT) {
-			emac_write(EMAC_RXHDP(ch),
-					emac_virt_to_phys(curr_bd, priv));
-			frame_status &= ~(EMAC_CPPI_EOQ_BIT);
-			tail_bd->mode = frame_status;
-			++rxch->end_of_queue_add;
-		}
-	}
-	++rxch->recycled_bd;
-}
-
-/**
- * emac_net_rx_cb: Prepares packet and sends to upper layer
- * @priv: The DaVinci EMAC private adapter structure
- * @net_pkt_list: Network packet list (received packets)
- *
- * Invalidates packet buffer memory and sends the received packet to upper
- * layer
- *
- * Returns success or appropriate error code (none as of now)
- */
-static int emac_net_rx_cb(struct emac_priv *priv,
-			  struct emac_netpktobj *net_pkt_list)
-{
-	struct sk_buff *p_skb;
-	p_skb = (struct sk_buff *)net_pkt_list->pkt_token;
-	/* set length of packet */
-	skb_put(p_skb, net_pkt_list->pkt_length);
-	p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
-	netif_receive_skb(p_skb);
-	priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length;
-	priv->net_dev_stats.rx_packets++;
-	return 0;
-}
-
-/**
- * emac_rx_bdproc: RX buffer descriptor (packet) processing
- * @priv: The DaVinci EMAC private adapter structure
- * @ch: RX channel number to process buffer descriptors for
- * @budget: number of packets allowed to process
- * @pending: indication to caller that packets are pending to process
- *
- * Processes RX buffer descriptors - checks ownership bit on the RX buffer
- * descriptor, sends the receive packet to upper layer, allocates a new SKB
- * and recycles the buffer descriptor (requeues it in hardware RX queue).
- * Only "budget" number of packets are processed and indication of pending
- * packets provided to the caller.
- *
- * Returns number of packets processed (and indication of pending packets)
- */
-static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
-{
-	unsigned long flags;
-	u32 frame_status;
-	u32 pkts_processed = 0;
-	char *new_buffer;
-	struct emac_rx_bd __iomem *curr_bd;
-	struct emac_rx_bd __iomem *last_bd;
-	struct emac_netpktobj *curr_pkt, pkt_obj;
-	struct emac_netbufobj buf_obj;
-	struct emac_netbufobj *rx_buf_obj;
-	void *new_buf_token;
-	struct emac_rxch *rxch = priv->rxch[ch];
-
-	if (unlikely(1 == rxch->teardown_pending))
-		return 0;
-	++rxch->proc_count;
-	spin_lock_irqsave(&priv->rx_lock, flags);
-	pkt_obj.buf_list = &buf_obj;
-	curr_pkt = &pkt_obj;
-	curr_bd = rxch->active_queue_head;
-	BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
-	frame_status = curr_bd->mode;
-
-	while ((curr_bd) &&
-	       ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
-	       (pkts_processed < budget)) {
-
-		new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
-					&new_buf_token, EMAC_DEF_RX_CH);
-		if (unlikely(NULL == new_buffer)) {
-			++rxch->out_of_rx_buffers;
-			goto end_emac_rx_bdproc;
-		}
-
-		/* populate received packet data structure */
-		rx_buf_obj = &curr_pkt->buf_list[0];
-		rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
-		rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
-		rx_buf_obj->buf_token = curr_bd->buf_token;
-
-		dma_unmap_single(&priv->ndev->dev, curr_bd->buff_ptr,
-				curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
-				DMA_FROM_DEVICE);
-
-		curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
-		curr_pkt->num_bufs = 1;
-		curr_pkt->pkt_length =
-			(frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
-		emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd, priv));
-		++rxch->processed_bd;
-		last_bd = curr_bd;
-		curr_bd = last_bd->next;
-		rxch->active_queue_head = curr_bd;
-
-		/* check if end of RX queue ? */
-		if (frame_status & EMAC_CPPI_EOQ_BIT) {
-			if (curr_bd) {
-				++rxch->mis_queued_packets;
-				emac_write(EMAC_RXHDP(ch),
-					   emac_virt_to_phys(curr_bd, priv));
-			} else {
-				++rxch->end_of_queue;
-				rxch->queue_active = 0;
-			}
-		}
-
-		/* recycle BD */
-		emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
-				       new_buf_token);
-
-		/* return the packet to the user - BD ptr passed in
-		 * last parameter for potential *future* use */
-		spin_unlock_irqrestore(&priv->rx_lock, flags);
-		emac_net_rx_cb(priv, curr_pkt);
-		spin_lock_irqsave(&priv->rx_lock, flags);
-		curr_bd = rxch->active_queue_head;
-		if (curr_bd) {
-			BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
-			frame_status = curr_bd->mode;
-		}
-		++pkts_processed;
-	}
-
-end_emac_rx_bdproc:
-	spin_unlock_irqrestore(&priv->rx_lock, flags);
-	return pkts_processed;
-}
-
-/**
  * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
  * @priv: The DaVinci EMAC private adapter structure
  *
@@ -2019,7 +1137,7 @@ end_emac_rx_bdproc:
  */
 static int emac_hw_enable(struct emac_priv *priv)
 {
-	u32 ch, val, mbp_enable, mac_control;
+	u32 val, mbp_enable, mac_control;
 
 	/* Soft reset */
 	emac_write(EMAC_SOFTRESET, 1);
@@ -2062,26 +1180,9 @@ static int emac_hw_enable(struct emac_priv *priv)
 	emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
 	priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
 
-	val = emac_read(EMAC_TXCONTROL);
-	val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
-	emac_write(EMAC_TXCONTROL, val);
-	val = emac_read(EMAC_RXCONTROL);
-	val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
-	emac_write(EMAC_RXCONTROL, val);
 	emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
 
-	for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
-		emac_write(EMAC_TXHDP(ch), 0);
-		emac_write(EMAC_TXINTMASKSET, BIT(ch));
-	}
-	for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
-		struct emac_rxch *rxch = priv->rxch[ch];
-		emac_setmac(priv, ch, rxch->mac_addr);
-		emac_write(EMAC_RXINTMASKSET, BIT(ch));
-		rxch->queue_active = 1;
-		emac_write(EMAC_RXHDP(ch),
-			   emac_virt_to_phys(rxch->active_queue_head, priv));
-	}
+	emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
 
 	/* Enable MII */
 	val = emac_read(EMAC_MACCONTROL);
@@ -2126,9 +1227,9 @@ static int emac_poll(struct napi_struct *napi, int budget)
 		mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
 
 	if (status & mask) {
-		num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
-					  EMAC_DEF_TX_MAX_SERVICE);
-	} /* TX processing */
+		num_pkts = cpdma_chan_process(priv->txch,
+					      EMAC_DEF_TX_MAX_SERVICE);
+	}
 
 	if (num_pkts)
 		return budget;
@@ -2138,9 +1239,8 @@ static int emac_poll(struct napi_struct *napi, int budget)
 	if (priv->version == EMAC_VERSION_2)
 		mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
 
-	if (status & mask) {
-		num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget);
-	} /* RX processing */
+	if (status & mask)
+		num_pkts = cpdma_chan_process(priv->rxch, budget);
 
 	if (num_pkts < budget) {
 		napi_complete(napi);
@@ -2282,9 +1382,9 @@ static int match_first_device(struct device *dev, void *data)
 static int emac_dev_open(struct net_device *ndev)
 {
 	struct device *emac_dev = &ndev->dev;
-	u32 rc, cnt, ch;
+	u32 cnt;
 	struct resource *res;
-	int q, m;
+	int q, m, ret;
 	int i = 0;
 	int k = 0;
 	struct emac_priv *priv = netdev_priv(ndev);
@@ -2296,31 +1396,25 @@ static int emac_dev_open(struct net_device *ndev)
 	/* Configuration items */
 	priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
 
-	/* Clear basic hardware */
-	for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
-		emac_write(EMAC_TXHDP(ch), 0);
-		emac_write(EMAC_RXHDP(ch), 0);
-		emac_write(EMAC_RXHDP(ch), 0);
-		emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
-		emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
-	}
 	priv->mac_hash1 = 0;
 	priv->mac_hash2 = 0;
 	emac_write(EMAC_MACHASH1, 0);
 	emac_write(EMAC_MACHASH2, 0);
 
-	/* multi ch not supported - open 1 TX, 1RX ch by default */
-	rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
-	if (0 != rc) {
-		dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed");
-		return rc;
-	}
-	rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
-	if (0 != rc) {
-		dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed");
-		return rc;
+	for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
+		struct sk_buff *skb = emac_rx_alloc(priv);
+		
+		if (!skb)
+			break;
+
+		ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
+					skb_tailroom(skb), GFP_KERNEL);
+		if (WARN_ON(ret < 0))
+			break;
 	}
 
+	cpdma_ctlr_start(priv->dma);
+
 	/* Request IRQ */
 
 	while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
@@ -2335,6 +1429,8 @@ static int emac_dev_open(struct net_device *ndev)
 	/* Start/Enable EMAC hardware */
 	emac_hw_enable(priv);
 
+	cpdma_ctlr_start(priv->dma);
+
 	priv->phydev = NULL;
 
 	/* use the first phy on the bus if pdata did not give us a phy id */
@@ -2422,10 +1518,7 @@ static int emac_dev_stop(struct net_device *ndev)
 
 	netif_carrier_off(ndev);
 	emac_int_disable(priv);
-	emac_stop_txch(priv, EMAC_DEF_TX_CH);
-	emac_stop_rxch(priv, EMAC_DEF_RX_CH);
-	emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
-	emac_cleanup_rxch(priv, EMAC_DEF_RX_CH);
+	cpdma_ctlr_stop(priv->dma);
 	emac_write(EMAC_SOFTRESET, 1);
 
 	if (priv->phydev)
@@ -2530,9 +1623,10 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
 	struct resource *res;
 	struct net_device *ndev;
 	struct emac_priv *priv;
-	unsigned long size;
+	unsigned long size, hw_ram_addr;
 	struct emac_platform_data *pdata;
 	struct device *emac_dev;
+	struct cpdma_params dma_params;
 
 	/* obtain emac clock from kernel */
 	emac_clk = clk_get(&pdev->dev, NULL);
@@ -2602,14 +1696,41 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
 	ndev->base_addr = (unsigned long)priv->remap_addr;
 
 	priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
-	priv->ctrl_ram_size = pdata->ctrl_ram_size;
-	priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
 
-	if (pdata->hw_ram_addr)
-		priv->hw_ram_addr = pdata->hw_ram_addr;
-	else
-		priv->hw_ram_addr = (u32 __force)res->start +
-					pdata->ctrl_ram_offset;
+	hw_ram_addr = pdata->hw_ram_addr;
+	if (!hw_ram_addr)
+		hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
+
+	memset(&dma_params, 0, sizeof(dma_params));
+	dma_params.dev			= emac_dev;
+	dma_params.dmaregs		= priv->emac_base;
+	dma_params.rxthresh		= priv->emac_base + 0x120;
+	dma_params.rxfree		= priv->emac_base + 0x140;
+	dma_params.txhdp		= priv->emac_base + 0x600;
+	dma_params.rxhdp		= priv->emac_base + 0x620;
+	dma_params.txcp			= priv->emac_base + 0x640;
+	dma_params.rxcp			= priv->emac_base + 0x660;
+	dma_params.num_chan		= EMAC_MAX_TXRX_CHANNELS;
+	dma_params.min_packet_size	= EMAC_DEF_MIN_ETHPKTSIZE;
+	dma_params.desc_mem_phys	= hw_ram_addr;
+	dma_params.desc_mem_size	= pdata->ctrl_ram_size;
+	dma_params.desc_align		= 16;
+
+	priv->dma = cpdma_ctlr_create(&dma_params);
+	if (!priv->dma) {
+		dev_err(emac_dev, "DaVinci EMAC: Error initializing DMA\n");
+		rc = -ENOMEM;
+		goto no_dma;
+	}
+
+	priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
+				       emac_tx_handler);
+	priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
+				       emac_rx_handler);
+	if (WARN_ON(!priv->txch || !priv->rxch)) {
+		rc = -ENOMEM;
+		goto no_irq_res;
+	}
 
 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 	if (!res) {
@@ -2652,6 +1773,12 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
 netdev_reg_err:
 	clk_disable(emac_clk);
 no_irq_res:
+	if (priv->txch)
+		cpdma_chan_destroy(priv->txch);
+	if (priv->rxch)
+		cpdma_chan_destroy(priv->rxch);
+	cpdma_ctlr_destroy(priv->dma);
+no_dma:
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	release_mem_region(res->start, res->end - res->start + 1);
 	iounmap(priv->remap_addr);
@@ -2680,6 +1807,12 @@ static int __devexit davinci_emac_remove(struct platform_device *pdev)
 	platform_set_drvdata(pdev, NULL);
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
+	if (priv->txch)
+		cpdma_chan_destroy(priv->txch);
+	if (priv->rxch)
+		cpdma_chan_destroy(priv->rxch);
+	cpdma_ctlr_destroy(priv->dma);
+
 	release_mem_region(res->start, res->end - res->start + 1);
 
 	unregister_netdev(ndev);
-- 
1.7.0.4


From sshtylyov at mvista.com  Fri May 28 15:55:37 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Sat, 29 May 2010 00:55:37 +0400
Subject: [PATCH v5 1/3] ARM: add CPPI 4.1 DMA support
In-Reply-To: <201005152214.53993.sshtylyov@ru.mvista.com>
References: <201005152214.53993.sshtylyov@ru.mvista.com>
Message-ID: <4C002DC9.1070905@mvista.com>

Hello.

I wrote:

> Add support for Texas Instuments Communication Port Programming Interface 4.1
> (CPPI 4.1) used on OMAP-L1x/DA8xx and AM35x.
> 
> At this moment, only the DMA controller and queue manager are supported.
> Support for the buffer manager is lacking but these chips don't have it anyway.
> 
> Signed-off-by: Sergei Shtylyov <sshtylyov at ru.mvista.com>
> Signed-off-by: Sekhar Nori <nsekhar at ti.com>
> 
> ---
> Changes since the previous version:
> - moved everything from arch/arm/mach-davinci/ to arch/arm/common/;
> - s/CONFIG_CPPI41/CONFIG_TI_CPPI41/, made that option invisible;
> - added #include <linux/slab.h> for kzalloc();
> - switched alloc_queue() and cppi41_queue_free() to using bit operations;
> - replaced 'static' linking_ram[] by local variable in cppi41_queue_mgr_init();
> - fixed pr_debug() in cppi41_dma_ctrlr_init() to print the real queue manager #.

    I saw no feedback about this patch. Russel, can I put this into your 
patch system?

WBR, Sergei

From nsekhar at ti.com  Mon May 31 07:52:32 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Mon, 31 May 2010 18:22:32 +0530
Subject: mmap broken on DM644x?
In-Reply-To: <4BFD2370.9070402@corelatus.se>
References: <4BFD2370.9070402@corelatus.se>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E728FF75@dbde02.ent.ti.com>

Hi Thomas,

On Wed, May 26, 2010 at 19:04:40, Thomas Lange wrote:
> Short version:
> mmap does not work for me. I don't think data cache is flushed
> before and after user space process runs which makes kernel and
> user space see different data due to dirty cache lines.
>
> Long version:
> I could not get mmap to work properly on my davinci board.
> I have narrowed the problem down to a simple test case that
> fails every time on my EVM6446 board.
>
> Test code attached along with console test logs.
> I would be happy to get confirmation that I have implemented
> the mmap driver correctly and that the problem really is with
> the kernel itself.
>
> Test description
> ----------------
> 1) Kernel module sets a variable in mmap:ed structure.
> 2) Module awakens user space process.
> 3) User space sees the _old_ data in mmap:ed structure.
> 4) User space calls a system function (syslog).
> 5) Now user space see the updated data.
>

What is the reason for exposing the kernel data
structure to userspace though mmap? Typically it
is only used for IO data.

Thanks,
Sekhar

From Jon.Povey at racelogic.co.uk  Mon May 31 08:28:33 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Mon, 31 May 2010 14:28:33 +0100
Subject: Kernel oops when unloading musb module in OTG mode
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08E055CA19@Cloud.RL.local>

In the process of looking into problems with MUSB OTG behaviour here, I tried a rebase to the current master, which has broken module unload of musb_hdrc - it now OOPSes while trying to rmmod (OOPS pasted below).

I reverted two commits in /musb, after reverting the second I could unload musb_hdrc without crash:

        #1 34e2beb2c883e0ea1b6135ad6f7713f7574a01aa
        #2 461972d8a4c94bc44f11a13046041c78a7cf18dd

Note that I am running with two of Sergei's patches in order to be able to use OTG:
http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-May/019078.html
http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-May/019108.html

Some relevant snippets from my .config; note USB_STORAGE is built static but musb_hdrc and g_serial are modules:

CONFIG_USB_MUSB_HDRC=m
CONFIG_USB_MUSB_SOC=y
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_PERIPHERAL is not set
CONFIG_USB_MUSB_OTG=y
CONFIG_USB_GADGET_MUSB_HDRC=y
CONFIG_USB_MUSB_HDRC_HCD=y
# CONFIG_MUSB_PIO_ONLY is not set
# CONFIG_USB_INVENTRA_DMA is not set
CONFIG_USB_TI_CPPI_DMA=y
CONFIG_USB_MUSB_DEBUG=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=m
CONFIG_USB_G_SERIAL=m

The OOPS:

Unable to handle kernel NULL pointer dereference at virtual address 0000002c
pgd = c7df0000
[0000002c] *pgd=87e1b031, *pte=00000000, *ppte=00000000
Internal error: Oops: 17 [#1] PREEMPT
last sysfs file: /sys/devices/platform/musb_hdrc/usb1/product
Modules linked in: musb_hdrc(-) [last unloaded: g_serial]
CPU: 0    Not tainted  (2.6.34-07363-g879b87a #78)
PC is at kobject_put+0x18/0x60
LR is at put_device+0x1c/0x20
pc : [<c012f0b4>]    lr : [<c016c91c>]    psr: 20000013
sp : c7e0be28  ip : c7e0be48  fp : c7e0be44
r10: 00000000  r9 : c7e0a000  r8 : c00260a4
r7 : fec64000  r6 : c030f038  r5 : c7dfd100  r4 : 0000000c
r3 : c7d84360  r2 : c7e0bdf8  r1 : c7db6440  r0 : 0000000c
Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 0005317f  Table: 87df0000  DAC: 00000015
Process rmmod (pid: 1019, stack limit = 0xc7e0a270)
Stack: (0xc7e0be28 to 0xc7e0c000)
be20:                   c7e0be54 c7e0be38 c006a3c0 c7dfd100 c7e0be54 c7e0be48
be40: c016c91c c012f0ac c7e0be6c c7e0be58 bf000920 c016c910 00000000 c7dfd100
be60: c7e0be8c c7e0be70 bf0081fc bf0008d0 c030f040 bf00a530 c030f074 bf00a530
be80: c7e0be9c c7e0be90 c0170f90 bf0081a8 c7e0beb4 c7e0bea0 c016fbe0 c0170f80
bea0: c030f040 c7e0a000 c7e0bed4 c7e0beb8 c016fce8 c016fb60 bf00a530 bf00a530
bec0: c0320588 c7e0bf3c c7e0bef4 c7e0bed8 c016ee78 c016fc3c 00000000 bf00a530
bee0: 00000000 c7e0bf3c c7e0bf14 c7e0bef8 c01702b4 c016edf0 00000000 bf00a5b8
bf00: 00000880 c7e0bf3c c7e0bf24 c7e0bf18 c01711f4 c017025c c7e0bf34 c7e0bf28
bf20: bf008190 c01711f0 c7e0bfa4 c7e0bf38 c0066310 bf00818c c0089088 6273756d
bf40: 7264685f c7e00063 c0132cc0 c0032fec 00000000 c7dd7934 00001000 40020000
bf60: c00260a4 00000000 c7e0bf84 c7e0bf78 c0055934 00132b80 bf00a5b8 00000880
bf80: c7e0bf84 00000000 00090008 00000000 00098028 00000081 00000000 c7e0bfa8
bfa0: c0025f20 c006612c 00090008 00000000 00098028 00000880 00098278 00098278
bfc0: 00090008 00000000 00098028 00000081 00000001 beba8e68 00000000 00000000
bfe0: 00098278 beba8ac8 00014140 400e96dc 20000010 00098028 e9045000 22540000
Backtrace:
[<c012f09c>] (kobject_put+0x0/0x60) from [<c016c91c>] (put_device+0x1c/0x20)
 r4:c7dfd100
[<c016c900>] (put_device+0x0/0x20) from [<bf000920>] (musb_free+0x60/0x70 [musb_hdrc])
[<bf0008c0>] (musb_free+0x0/0x70 [musb_hdrc]) from [<bf0081fc>] (musb_remove+0x64/0x8c [musb_hdrc])
 r5:c7dfd100 r4:00000000
[<bf008198>] (musb_remove+0x0/0x8c [musb_hdrc]) from [<c0170f90>] (platform_drv_remove+0x20/0x24)
 r7:bf00a530 r6:c030f074 r5:bf00a530 r4:c030f040
[<c0170f70>] (platform_drv_remove+0x0/0x24) from [<c016fbe0>] (__device_release_driver+0x90/0xdc)
[<c016fb50>] (__device_release_driver+0x0/0xdc) from [<c016fce8>] (driver_detach+0xbc/0xe4)
 r5:c7e0a000 r4:c030f040
[<c016fc2c>] (driver_detach+0x0/0xe4) from [<c016ee78>] (bus_remove_driver+0x98/0xc0)
 r7:c7e0bf3c r6:c0320588 r5:bf00a530 r4:bf00a530
[<c016ede0>] (bus_remove_driver+0x0/0xc0) from [<c01702b4>] (driver_unregister+0x68/0x78)
 r7:c7e0bf3c r6:00000000 r5:bf00a530 r4:00000000
[<c017024c>] (driver_unregister+0x0/0x78) from [<c01711f4>] (platform_driver_unregister+0x14/0x18)
 r7:c7e0bf3c r6:00000880 r5:bf00a5b8 r4:00000000
[<c01711e0>] (platform_driver_unregister+0x0/0x18) from [<bf008190>] (musb_cleanup+0x14/0x1c [musb_hdrc])
[<bf00817c>] (musb_cleanup+0x0/0x1c [musb_hdrc]) from [<c0066310>] (sys_delete_module+0x1f4/0x268)
[<c006611c>] (sys_delete_module+0x0/0x268) from [<c0025f20>] (ret_fast_syscall+0x0/0x2c)
 r7:00000081 r6:00098028 r5:00000000 r4:00090008
Code: e24cb004 e24dd00c e2504000 0a00000b (e5d43020)

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

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From thomas at corelatus.se  Mon May 31 08:39:41 2010
From: thomas at corelatus.se (Thomas Lange)
Date: Mon, 31 May 2010 15:39:41 +0200
Subject: mmap broken on DM644x?
In-Reply-To: <B85A65D85D7EB246BE421B3FB0FBB59301E728FF75@dbde02.ent.ti.com>
References: <4BFD2370.9070402@corelatus.se>
	<B85A65D85D7EB246BE421B3FB0FBB59301E728FF75@dbde02.ent.ti.com>
Message-ID: <4C03BC1D.4060909@corelatus.se>

On 2010-05-31 14:52, Nori, Sekhar wrote:
> On Wed, May 26, 2010 at 19:04:40, Thomas Lange wrote:
>> Short version:
>> mmap does not work for me. I don't think data cache is flushed
>> before and after user space process runs which makes kernel and
>> user space see different data due to dirty cache lines.
>>
>> Long version:
>> I could not get mmap to work properly on my davinci board.
>> I have narrowed the problem down to a simple test case that
>> fails every time on my EVM6446 board.
>>
>> Test code attached along with console test logs.
>> I would be happy to get confirmation that I have implemented
>> the mmap driver correctly and that the problem really is with
>> the kernel itself.
>>
>> Test description
>> ----------------
>> 1) Kernel module sets a variable in mmap:ed structure.
>> 2) Module awakens user space process.
>> 3) User space sees the _old_ data in mmap:ed structure.
>> 4) User space calls a system function (syslog).
>> 5) Now user space see the updated data.
>>
>
> What is the reason for exposing the kernel data
> structure to userspace though mmap? Typically it
> is only used for IO data.

My original code handles transfer of large amounts of data from DSP to
ethernet. Timing critical stuff is handled in kernel. User space handles
socket setup, supervision, write etc. They need to exchange state information
and other data.

But the relevant question here is why mmap does not work as advertised. It seems
that there are dirty dcache issues with dm644x and mmap.
Perhaps more ARM:s are affected?

/T

From thomas.koeller at baslerweb.com  Mon May 31 09:14:39 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Mon, 31 May 2010 16:14:39 +0200
Subject: [PATCH] Make UART1 work
Message-ID: <1275315280-13094-1-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

Due to a wrong address definition, the second serial port on DaVinci DM365
was unusable. Not knowing whether the original definition was actually
correct for some other SoC I changed it unconditionally.

Patch is agains 'arago' tree.

Thomas Koeller (1):
  DM365: fixed second serial port

 arch/arm/mach-davinci/include/mach/serial.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


From thomas.koeller at baslerweb.com  Mon May 31 09:14:40 2010
From: thomas.koeller at baslerweb.com (thomas.koeller at baslerweb.com)
Date: Mon, 31 May 2010 16:14:40 +0200
Subject: [PATCH] DM365: fixed second serial port
In-Reply-To: <1275315280-13094-1-git-send-email-thomas.koeller@baslerweb.com>
References: <1275315280-13094-1-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <1275315280-13094-2-git-send-email-thomas.koeller@baslerweb.com>

From: Thomas Koeller <thomas.koeller at baslerweb.com>

The register base address for the second serial pot (UART1) was
wrong.

Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
---
 arch/arm/mach-davinci/include/mach/serial.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index a584697..9f5ea76 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -15,7 +15,7 @@
 
 #define DAVINCI_MAX_NR_UARTS	3
 #define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
-#define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
+#define DAVINCI_UART1_BASE	(IO_PHYS + 0x106000)
 #define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
 
 #define DA8XX_UART0_BASE	(IO_PHYS + 0x042000)
-- 
1.7.1


From suhas.jain at mavensystems.com  Mon May 31 09:37:25 2010
From: suhas.jain at mavensystems.com (Suhas Jain)
Date: Mon, 31 May 2010 20:07:25 +0530
Subject: Problem with DM365 boot modes
Message-ID: <003701cb00ce$c9fd1320$5df73960$@jain@mavensystems.com>

Hi All,

We are facing a strange problem with configuring the boot mode for DM365.
Boot mode for DM365 processor is never getting changed from NAND to any
other boot mode. Even if we set the BOOTCFG lines (010) for SD boot mode,
still the processor boots from NAND flash. The only way we have to boot with
SD boot is to erase the NAND flash. Processor always enters NAND boot mode
if there is some bootable image existing on NAND flash irrespective of
BOOTCFG. 

Please let me know what could be the possible reason for this. Your prompt
response would be highly appreciated.

Thanks,
Suhas Jain



From nsekhar at ti.com  Mon May 31 09:47:05 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Mon, 31 May 2010 20:17:05 +0530
Subject: Problem with DM365 boot modes
In-Reply-To: <003701cb00ce$c9fd1320$5df73960$@jain@mavensystems.com>
References: <003701cb00ce$c9fd1320$5df73960$@jain@mavensystems.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E7290000@dbde02.ent.ti.com>

Hi Suhas,

On Mon, May 31, 2010 at 20:07:25, Suhas Jain wrote:
> Hi All,
>
> We are facing a strange problem with configuring the boot mode for DM365.
> Boot mode for DM365 processor is never getting changed from NAND to any
> other boot mode. Even if we set the BOOTCFG lines (010) for SD boot mode,
> still the processor boots from NAND flash. The only way we have to boot with
> SD boot is to erase the NAND flash. Processor always enters NAND boot mode
> if there is some bootable image existing on NAND flash irrespective of
> BOOTCFG.
>
> Please let me know what could be the possible reason for this. Your prompt
> response would be highly appreciated.

Can you post this query on e2e.ti.com? There is a better chance of this
getting addressed there.

Thanks,
Sekhar

From nsekhar at ti.com  Mon May 31 10:07:14 2010
From: nsekhar at ti.com (Nori, Sekhar)
Date: Mon, 31 May 2010 20:37:14 +0530
Subject: [PATCH] DM365: fixed second serial port
In-Reply-To: <1275315280-13094-2-git-send-email-thomas.koeller@baslerweb.com>
References: <1275315280-13094-1-git-send-email-thomas.koeller@baslerweb.com>
	<1275315280-13094-2-git-send-email-thomas.koeller@baslerweb.com>
Message-ID: <B85A65D85D7EB246BE421B3FB0FBB59301E7290014@dbde02.ent.ti.com>

Hi Thomas,

On Mon, May 31, 2010 at 19:44:40, thomas.koeller at baslerweb.com wrote:
> From: Thomas Koeller <thomas.koeller at baslerweb.com>
>
> The register base address for the second serial pot (UART1) was
> wrong.
>
> Signed-off-by: Thomas Koeller <thomas.koeller at baslerweb.com>
> ---
>  arch/arm/mach-davinci/include/mach/serial.h |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
> index a584697..9f5ea76 100644
> --- a/arch/arm/mach-davinci/include/mach/serial.h
> +++ b/arch/arm/mach-davinci/include/mach/serial.h
> @@ -15,7 +15,7 @@
>
>  #define DAVINCI_MAX_NR_UARTS 3
>  #define DAVINCI_UART0_BASE   (IO_PHYS + 0x20000)
> -#define DAVINCI_UART1_BASE   (IO_PHYS + 0x20400)
> +#define DAVINCI_UART1_BASE   (IO_PHYS + 0x106000)
>  #define DAVINCI_UART2_BASE   (IO_PHYS + 0x20800)

The original address is correct for DM644x (and may be
other DaVincis) and wrong for DM365. IMO, the correct
fix would be to leave serial.h as is and #define the
correct address for DM365 before dm365_serial_platform_data
in dm365.c where the address is used.

Also, this bug is present in upstream kernel so can you
please generate a patch against Kevin's tree?

Thanks,
Sekhar